1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Distributed Switch Architecture VSC9953 driver 3 * Copyright (C) 2020, Maxim Kochetkov <fido_max@inbox.ru> 4 */ 5 #include <linux/types.h> 6 #include <soc/mscc/ocelot_vcap.h> 7 #include <soc/mscc/ocelot_sys.h> 8 #include <soc/mscc/ocelot.h> 9 #include <linux/of_platform.h> 10 #include <linux/pcs-lynx.h> 11 #include <linux/packing.h> 12 #include <linux/iopoll.h> 13 #include "felix.h" 14 15 #define VSC9953_VCAP_IS2_CNT 1024 16 #define VSC9953_VCAP_IS2_ENTRY_WIDTH 376 17 #define VSC9953_VCAP_PORT_CNT 10 18 19 #define MSCC_MIIM_CMD_OPR_WRITE BIT(1) 20 #define MSCC_MIIM_CMD_OPR_READ BIT(2) 21 #define MSCC_MIIM_CMD_WRDATA_SHIFT 4 22 #define MSCC_MIIM_CMD_REGAD_SHIFT 20 23 #define MSCC_MIIM_CMD_PHYAD_SHIFT 25 24 #define MSCC_MIIM_CMD_VLD BIT(31) 25 26 static const u32 vsc9953_ana_regmap[] = { 27 REG(ANA_ADVLEARN, 0x00b500), 28 REG(ANA_VLANMASK, 0x00b504), 29 REG_RESERVED(ANA_PORT_B_DOMAIN), 30 REG(ANA_ANAGEFIL, 0x00b50c), 31 REG(ANA_ANEVENTS, 0x00b510), 32 REG(ANA_STORMLIMIT_BURST, 0x00b514), 33 REG(ANA_STORMLIMIT_CFG, 0x00b518), 34 REG(ANA_ISOLATED_PORTS, 0x00b528), 35 REG(ANA_COMMUNITY_PORTS, 0x00b52c), 36 REG(ANA_AUTOAGE, 0x00b530), 37 REG(ANA_MACTOPTIONS, 0x00b534), 38 REG(ANA_LEARNDISC, 0x00b538), 39 REG(ANA_AGENCTRL, 0x00b53c), 40 REG(ANA_MIRRORPORTS, 0x00b540), 41 REG(ANA_EMIRRORPORTS, 0x00b544), 42 REG(ANA_FLOODING, 0x00b548), 43 REG(ANA_FLOODING_IPMC, 0x00b54c), 44 REG(ANA_SFLOW_CFG, 0x00b550), 45 REG(ANA_PORT_MODE, 0x00b57c), 46 REG_RESERVED(ANA_CUT_THRU_CFG), 47 REG(ANA_PGID_PGID, 0x00b600), 48 REG(ANA_TABLES_ANMOVED, 0x00b4ac), 49 REG(ANA_TABLES_MACHDATA, 0x00b4b0), 50 REG(ANA_TABLES_MACLDATA, 0x00b4b4), 51 REG_RESERVED(ANA_TABLES_STREAMDATA), 52 REG(ANA_TABLES_MACACCESS, 0x00b4b8), 53 REG(ANA_TABLES_MACTINDX, 0x00b4bc), 54 REG(ANA_TABLES_VLANACCESS, 0x00b4c0), 55 REG(ANA_TABLES_VLANTIDX, 0x00b4c4), 56 REG_RESERVED(ANA_TABLES_ISDXACCESS), 57 REG_RESERVED(ANA_TABLES_ISDXTIDX), 58 REG(ANA_TABLES_ENTRYLIM, 0x00b480), 59 REG_RESERVED(ANA_TABLES_PTP_ID_HIGH), 60 REG_RESERVED(ANA_TABLES_PTP_ID_LOW), 61 REG_RESERVED(ANA_TABLES_STREAMACCESS), 62 REG_RESERVED(ANA_TABLES_STREAMTIDX), 63 REG_RESERVED(ANA_TABLES_SEQ_HISTORY), 64 REG_RESERVED(ANA_TABLES_SEQ_MASK), 65 REG_RESERVED(ANA_TABLES_SFID_MASK), 66 REG_RESERVED(ANA_TABLES_SFIDACCESS), 67 REG_RESERVED(ANA_TABLES_SFIDTIDX), 68 REG_RESERVED(ANA_MSTI_STATE), 69 REG_RESERVED(ANA_OAM_UPM_LM_CNT), 70 REG_RESERVED(ANA_SG_ACCESS_CTRL), 71 REG_RESERVED(ANA_SG_CONFIG_REG_1), 72 REG_RESERVED(ANA_SG_CONFIG_REG_2), 73 REG_RESERVED(ANA_SG_CONFIG_REG_3), 74 REG_RESERVED(ANA_SG_CONFIG_REG_4), 75 REG_RESERVED(ANA_SG_CONFIG_REG_5), 76 REG_RESERVED(ANA_SG_GCL_GS_CONFIG), 77 REG_RESERVED(ANA_SG_GCL_TI_CONFIG), 78 REG_RESERVED(ANA_SG_STATUS_REG_1), 79 REG_RESERVED(ANA_SG_STATUS_REG_2), 80 REG_RESERVED(ANA_SG_STATUS_REG_3), 81 REG(ANA_PORT_VLAN_CFG, 0x000000), 82 REG(ANA_PORT_DROP_CFG, 0x000004), 83 REG(ANA_PORT_QOS_CFG, 0x000008), 84 REG(ANA_PORT_VCAP_CFG, 0x00000c), 85 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x000010), 86 REG(ANA_PORT_VCAP_S2_CFG, 0x00001c), 87 REG(ANA_PORT_PCP_DEI_MAP, 0x000020), 88 REG(ANA_PORT_CPU_FWD_CFG, 0x000060), 89 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x000064), 90 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x000068), 91 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00006c), 92 REG(ANA_PORT_PORT_CFG, 0x000070), 93 REG(ANA_PORT_POL_CFG, 0x000074), 94 REG_RESERVED(ANA_PORT_PTP_CFG), 95 REG_RESERVED(ANA_PORT_PTP_DLY1_CFG), 96 REG_RESERVED(ANA_PORT_PTP_DLY2_CFG), 97 REG_RESERVED(ANA_PORT_SFID_CFG), 98 REG(ANA_PFC_PFC_CFG, 0x00c000), 99 REG_RESERVED(ANA_PFC_PFC_TIMER), 100 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 101 REG_RESERVED(ANA_IPT_IPT), 102 REG_RESERVED(ANA_PPT_PPT), 103 REG_RESERVED(ANA_FID_MAP_FID_MAP), 104 REG(ANA_AGGR_CFG, 0x00c600), 105 REG(ANA_CPUQ_CFG, 0x00c604), 106 REG_RESERVED(ANA_CPUQ_CFG2), 107 REG(ANA_CPUQ_8021_CFG, 0x00c60c), 108 REG(ANA_DSCP_CFG, 0x00c64c), 109 REG(ANA_DSCP_REWR_CFG, 0x00c74c), 110 REG(ANA_VCAP_RNG_TYPE_CFG, 0x00c78c), 111 REG(ANA_VCAP_RNG_VAL_CFG, 0x00c7ac), 112 REG_RESERVED(ANA_VRAP_CFG), 113 REG_RESERVED(ANA_VRAP_HDR_DATA), 114 REG_RESERVED(ANA_VRAP_HDR_MASK), 115 REG(ANA_DISCARD_CFG, 0x00c7d8), 116 REG(ANA_FID_CFG, 0x00c7dc), 117 REG(ANA_POL_PIR_CFG, 0x00a000), 118 REG(ANA_POL_CIR_CFG, 0x00a004), 119 REG(ANA_POL_MODE_CFG, 0x00a008), 120 REG(ANA_POL_PIR_STATE, 0x00a00c), 121 REG(ANA_POL_CIR_STATE, 0x00a010), 122 REG_RESERVED(ANA_POL_STATE), 123 REG(ANA_POL_FLOWC, 0x00c280), 124 REG(ANA_POL_HYST, 0x00c2ec), 125 REG_RESERVED(ANA_POL_MISC_CFG), 126 }; 127 128 static const u32 vsc9953_qs_regmap[] = { 129 REG(QS_XTR_GRP_CFG, 0x000000), 130 REG(QS_XTR_RD, 0x000008), 131 REG(QS_XTR_FRM_PRUNING, 0x000010), 132 REG(QS_XTR_FLUSH, 0x000018), 133 REG(QS_XTR_DATA_PRESENT, 0x00001c), 134 REG(QS_XTR_CFG, 0x000020), 135 REG(QS_INJ_GRP_CFG, 0x000024), 136 REG(QS_INJ_WR, 0x00002c), 137 REG(QS_INJ_CTRL, 0x000034), 138 REG(QS_INJ_STATUS, 0x00003c), 139 REG(QS_INJ_ERR, 0x000040), 140 REG_RESERVED(QS_INH_DBG), 141 }; 142 143 static const u32 vsc9953_s2_regmap[] = { 144 REG(S2_CORE_UPDATE_CTRL, 0x000000), 145 REG(S2_CORE_MV_CFG, 0x000004), 146 REG(S2_CACHE_ENTRY_DAT, 0x000008), 147 REG(S2_CACHE_MASK_DAT, 0x000108), 148 REG(S2_CACHE_ACTION_DAT, 0x000208), 149 REG(S2_CACHE_CNT_DAT, 0x000308), 150 REG(S2_CACHE_TG_DAT, 0x000388), 151 }; 152 153 static const u32 vsc9953_qsys_regmap[] = { 154 REG(QSYS_PORT_MODE, 0x003600), 155 REG(QSYS_SWITCH_PORT_MODE, 0x003630), 156 REG(QSYS_STAT_CNT_CFG, 0x00365c), 157 REG(QSYS_EEE_CFG, 0x003660), 158 REG(QSYS_EEE_THRES, 0x003688), 159 REG(QSYS_IGR_NO_SHARING, 0x00368c), 160 REG(QSYS_EGR_NO_SHARING, 0x003690), 161 REG(QSYS_SW_STATUS, 0x003694), 162 REG(QSYS_EXT_CPU_CFG, 0x0036c0), 163 REG_RESERVED(QSYS_PAD_CFG), 164 REG(QSYS_CPU_GROUP_MAP, 0x0036c8), 165 REG_RESERVED(QSYS_QMAP), 166 REG_RESERVED(QSYS_ISDX_SGRP), 167 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 168 REG_RESERVED(QSYS_TFRM_MISC), 169 REG_RESERVED(QSYS_TFRM_PORT_DLY), 170 REG_RESERVED(QSYS_TFRM_TIMER_CFG_1), 171 REG_RESERVED(QSYS_TFRM_TIMER_CFG_2), 172 REG_RESERVED(QSYS_TFRM_TIMER_CFG_3), 173 REG_RESERVED(QSYS_TFRM_TIMER_CFG_4), 174 REG_RESERVED(QSYS_TFRM_TIMER_CFG_5), 175 REG_RESERVED(QSYS_TFRM_TIMER_CFG_6), 176 REG_RESERVED(QSYS_TFRM_TIMER_CFG_7), 177 REG_RESERVED(QSYS_TFRM_TIMER_CFG_8), 178 REG(QSYS_RED_PROFILE, 0x003724), 179 REG(QSYS_RES_QOS_MODE, 0x003764), 180 REG(QSYS_RES_CFG, 0x004000), 181 REG(QSYS_RES_STAT, 0x004004), 182 REG(QSYS_EGR_DROP_MODE, 0x003768), 183 REG(QSYS_EQ_CTRL, 0x00376c), 184 REG_RESERVED(QSYS_EVENTS_CORE), 185 REG_RESERVED(QSYS_QMAXSDU_CFG_0), 186 REG_RESERVED(QSYS_QMAXSDU_CFG_1), 187 REG_RESERVED(QSYS_QMAXSDU_CFG_2), 188 REG_RESERVED(QSYS_QMAXSDU_CFG_3), 189 REG_RESERVED(QSYS_QMAXSDU_CFG_4), 190 REG_RESERVED(QSYS_QMAXSDU_CFG_5), 191 REG_RESERVED(QSYS_QMAXSDU_CFG_6), 192 REG_RESERVED(QSYS_QMAXSDU_CFG_7), 193 REG_RESERVED(QSYS_PREEMPTION_CFG), 194 REG(QSYS_CIR_CFG, 0x000000), 195 REG_RESERVED(QSYS_EIR_CFG), 196 REG(QSYS_SE_CFG, 0x000008), 197 REG(QSYS_SE_DWRR_CFG, 0x00000c), 198 REG_RESERVED(QSYS_SE_CONNECT), 199 REG_RESERVED(QSYS_SE_DLB_SENSE), 200 REG(QSYS_CIR_STATE, 0x000044), 201 REG_RESERVED(QSYS_EIR_STATE), 202 REG_RESERVED(QSYS_SE_STATE), 203 REG(QSYS_HSCH_MISC_CFG, 0x003774), 204 REG_RESERVED(QSYS_TAG_CONFIG), 205 REG_RESERVED(QSYS_TAS_PARAM_CFG_CTRL), 206 REG_RESERVED(QSYS_PORT_MAX_SDU), 207 REG_RESERVED(QSYS_PARAM_CFG_REG_1), 208 REG_RESERVED(QSYS_PARAM_CFG_REG_2), 209 REG_RESERVED(QSYS_PARAM_CFG_REG_3), 210 REG_RESERVED(QSYS_PARAM_CFG_REG_4), 211 REG_RESERVED(QSYS_PARAM_CFG_REG_5), 212 REG_RESERVED(QSYS_GCL_CFG_REG_1), 213 REG_RESERVED(QSYS_GCL_CFG_REG_2), 214 REG_RESERVED(QSYS_PARAM_STATUS_REG_1), 215 REG_RESERVED(QSYS_PARAM_STATUS_REG_2), 216 REG_RESERVED(QSYS_PARAM_STATUS_REG_3), 217 REG_RESERVED(QSYS_PARAM_STATUS_REG_4), 218 REG_RESERVED(QSYS_PARAM_STATUS_REG_5), 219 REG_RESERVED(QSYS_PARAM_STATUS_REG_6), 220 REG_RESERVED(QSYS_PARAM_STATUS_REG_7), 221 REG_RESERVED(QSYS_PARAM_STATUS_REG_8), 222 REG_RESERVED(QSYS_PARAM_STATUS_REG_9), 223 REG_RESERVED(QSYS_GCL_STATUS_REG_1), 224 REG_RESERVED(QSYS_GCL_STATUS_REG_2), 225 }; 226 227 static const u32 vsc9953_rew_regmap[] = { 228 REG(REW_PORT_VLAN_CFG, 0x000000), 229 REG(REW_TAG_CFG, 0x000004), 230 REG(REW_PORT_CFG, 0x000008), 231 REG(REW_DSCP_CFG, 0x00000c), 232 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 233 REG_RESERVED(REW_PTP_CFG), 234 REG_RESERVED(REW_PTP_DLY1_CFG), 235 REG_RESERVED(REW_RED_TAG_CFG), 236 REG(REW_DSCP_REMAP_DP1_CFG, 0x000610), 237 REG(REW_DSCP_REMAP_CFG, 0x000710), 238 REG_RESERVED(REW_STAT_CFG), 239 REG_RESERVED(REW_REW_STICKY), 240 REG_RESERVED(REW_PPT), 241 }; 242 243 static const u32 vsc9953_sys_regmap[] = { 244 REG(SYS_COUNT_RX_OCTETS, 0x000000), 245 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 246 REG(SYS_COUNT_RX_SHORTS, 0x000010), 247 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 248 REG(SYS_COUNT_RX_JABBERS, 0x000018), 249 REG(SYS_COUNT_RX_64, 0x000024), 250 REG(SYS_COUNT_RX_65_127, 0x000028), 251 REG(SYS_COUNT_RX_128_255, 0x00002c), 252 REG(SYS_COUNT_RX_256_1023, 0x000030), 253 REG(SYS_COUNT_RX_1024_1526, 0x000034), 254 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 255 REG(SYS_COUNT_RX_LONGS, 0x000048), 256 REG(SYS_COUNT_TX_OCTETS, 0x000100), 257 REG(SYS_COUNT_TX_COLLISION, 0x000110), 258 REG(SYS_COUNT_TX_DROPS, 0x000114), 259 REG(SYS_COUNT_TX_64, 0x00011c), 260 REG(SYS_COUNT_TX_65_127, 0x000120), 261 REG(SYS_COUNT_TX_128_511, 0x000124), 262 REG(SYS_COUNT_TX_512_1023, 0x000128), 263 REG(SYS_COUNT_TX_1024_1526, 0x00012c), 264 REG(SYS_COUNT_TX_1527_MAX, 0x000130), 265 REG(SYS_COUNT_TX_AGING, 0x000178), 266 REG(SYS_RESET_CFG, 0x000318), 267 REG_RESERVED(SYS_SR_ETYPE_CFG), 268 REG(SYS_VLAN_ETYPE_CFG, 0x000320), 269 REG(SYS_PORT_MODE, 0x000324), 270 REG(SYS_FRONT_PORT_MODE, 0x000354), 271 REG(SYS_FRM_AGING, 0x00037c), 272 REG(SYS_STAT_CFG, 0x000380), 273 REG_RESERVED(SYS_SW_STATUS), 274 REG_RESERVED(SYS_MISC_CFG), 275 REG_RESERVED(SYS_REW_MAC_HIGH_CFG), 276 REG_RESERVED(SYS_REW_MAC_LOW_CFG), 277 REG_RESERVED(SYS_TIMESTAMP_OFFSET), 278 REG(SYS_PAUSE_CFG, 0x00044c), 279 REG(SYS_PAUSE_TOT_CFG, 0x000478), 280 REG(SYS_ATOP, 0x00047c), 281 REG(SYS_ATOP_TOT_CFG, 0x0004a8), 282 REG(SYS_MAC_FC_CFG, 0x0004ac), 283 REG(SYS_MMGT, 0x0004d4), 284 REG_RESERVED(SYS_MMGT_FAST), 285 REG_RESERVED(SYS_EVENTS_DIF), 286 REG_RESERVED(SYS_EVENTS_CORE), 287 REG_RESERVED(SYS_CNT), 288 REG_RESERVED(SYS_PTP_STATUS), 289 REG_RESERVED(SYS_PTP_TXSTAMP), 290 REG_RESERVED(SYS_PTP_NXT), 291 REG_RESERVED(SYS_PTP_CFG), 292 REG_RESERVED(SYS_RAM_INIT), 293 REG_RESERVED(SYS_CM_ADDR), 294 REG_RESERVED(SYS_CM_DATA_WR), 295 REG_RESERVED(SYS_CM_DATA_RD), 296 REG_RESERVED(SYS_CM_OP), 297 REG_RESERVED(SYS_CM_DATA), 298 }; 299 300 static const u32 vsc9953_gcb_regmap[] = { 301 REG(GCB_SOFT_RST, 0x000008), 302 REG(GCB_MIIM_MII_STATUS, 0x0000ac), 303 REG(GCB_MIIM_MII_CMD, 0x0000b4), 304 REG(GCB_MIIM_MII_DATA, 0x0000b8), 305 }; 306 307 static const u32 vsc9953_dev_gmii_regmap[] = { 308 REG(DEV_CLOCK_CFG, 0x0), 309 REG(DEV_PORT_MISC, 0x4), 310 REG_RESERVED(DEV_EVENTS), 311 REG(DEV_EEE_CFG, 0xc), 312 REG_RESERVED(DEV_RX_PATH_DELAY), 313 REG_RESERVED(DEV_TX_PATH_DELAY), 314 REG_RESERVED(DEV_PTP_PREDICT_CFG), 315 REG(DEV_MAC_ENA_CFG, 0x10), 316 REG(DEV_MAC_MODE_CFG, 0x14), 317 REG(DEV_MAC_MAXLEN_CFG, 0x18), 318 REG(DEV_MAC_TAGS_CFG, 0x1c), 319 REG(DEV_MAC_ADV_CHK_CFG, 0x20), 320 REG(DEV_MAC_IFG_CFG, 0x24), 321 REG(DEV_MAC_HDX_CFG, 0x28), 322 REG_RESERVED(DEV_MAC_DBG_CFG), 323 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x30), 324 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x34), 325 REG(DEV_MAC_STICKY, 0x38), 326 REG_RESERVED(PCS1G_CFG), 327 REG_RESERVED(PCS1G_MODE_CFG), 328 REG_RESERVED(PCS1G_SD_CFG), 329 REG_RESERVED(PCS1G_ANEG_CFG), 330 REG_RESERVED(PCS1G_ANEG_NP_CFG), 331 REG_RESERVED(PCS1G_LB_CFG), 332 REG_RESERVED(PCS1G_DBG_CFG), 333 REG_RESERVED(PCS1G_CDET_CFG), 334 REG_RESERVED(PCS1G_ANEG_STATUS), 335 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 336 REG_RESERVED(PCS1G_LINK_STATUS), 337 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 338 REG_RESERVED(PCS1G_STICKY), 339 REG_RESERVED(PCS1G_DEBUG_STATUS), 340 REG_RESERVED(PCS1G_LPI_CFG), 341 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 342 REG_RESERVED(PCS1G_LPI_STATUS), 343 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 344 REG_RESERVED(PCS1G_TSTPAT_STATUS), 345 REG_RESERVED(DEV_PCS_FX100_CFG), 346 REG_RESERVED(DEV_PCS_FX100_STATUS), 347 }; 348 349 static const u32 *vsc9953_regmap[TARGET_MAX] = { 350 [ANA] = vsc9953_ana_regmap, 351 [QS] = vsc9953_qs_regmap, 352 [QSYS] = vsc9953_qsys_regmap, 353 [REW] = vsc9953_rew_regmap, 354 [SYS] = vsc9953_sys_regmap, 355 [S2] = vsc9953_s2_regmap, 356 [GCB] = vsc9953_gcb_regmap, 357 [DEV_GMII] = vsc9953_dev_gmii_regmap, 358 }; 359 360 /* Addresses are relative to the device's base address */ 361 static const struct resource vsc9953_target_io_res[TARGET_MAX] = { 362 [ANA] = { 363 .start = 0x0280000, 364 .end = 0x028ffff, 365 .name = "ana", 366 }, 367 [QS] = { 368 .start = 0x0080000, 369 .end = 0x00800ff, 370 .name = "qs", 371 }, 372 [QSYS] = { 373 .start = 0x0200000, 374 .end = 0x021ffff, 375 .name = "qsys", 376 }, 377 [REW] = { 378 .start = 0x0030000, 379 .end = 0x003ffff, 380 .name = "rew", 381 }, 382 [SYS] = { 383 .start = 0x0010000, 384 .end = 0x001ffff, 385 .name = "sys", 386 }, 387 [S2] = { 388 .start = 0x0060000, 389 .end = 0x00603ff, 390 .name = "s2", 391 }, 392 [PTP] = { 393 .start = 0x0090000, 394 .end = 0x00900cb, 395 .name = "ptp", 396 }, 397 [GCB] = { 398 .start = 0x0070000, 399 .end = 0x00701ff, 400 .name = "devcpu_gcb", 401 }, 402 }; 403 404 static const struct resource vsc9953_port_io_res[] = { 405 { 406 .start = 0x0100000, 407 .end = 0x010ffff, 408 .name = "port0", 409 }, 410 { 411 .start = 0x0110000, 412 .end = 0x011ffff, 413 .name = "port1", 414 }, 415 { 416 .start = 0x0120000, 417 .end = 0x012ffff, 418 .name = "port2", 419 }, 420 { 421 .start = 0x0130000, 422 .end = 0x013ffff, 423 .name = "port3", 424 }, 425 { 426 .start = 0x0140000, 427 .end = 0x014ffff, 428 .name = "port4", 429 }, 430 { 431 .start = 0x0150000, 432 .end = 0x015ffff, 433 .name = "port5", 434 }, 435 { 436 .start = 0x0160000, 437 .end = 0x016ffff, 438 .name = "port6", 439 }, 440 { 441 .start = 0x0170000, 442 .end = 0x017ffff, 443 .name = "port7", 444 }, 445 { 446 .start = 0x0180000, 447 .end = 0x018ffff, 448 .name = "port8", 449 }, 450 { 451 .start = 0x0190000, 452 .end = 0x019ffff, 453 .name = "port9", 454 }, 455 }; 456 457 static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = { 458 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 10, 10), 459 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 9), 460 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), 461 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), 462 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), 463 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), 464 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), 465 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 466 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), 467 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), 468 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), 469 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), 470 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), 471 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 472 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 473 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), 474 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), 475 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), 476 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 477 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 478 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), 479 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), 480 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), 481 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), 482 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), 483 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 484 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 485 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 486 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 7, 7), 487 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 6, 6), 488 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 5, 5), 489 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 490 [GCB_MIIM_MII_STATUS_PENDING] = REG_FIELD(GCB_MIIM_MII_STATUS, 2, 2), 491 [GCB_MIIM_MII_STATUS_BUSY] = REG_FIELD(GCB_MIIM_MII_STATUS, 3, 3), 492 /* Replicated per number of ports (11), register size 4 per port */ 493 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 13, 13, 11, 4), 494 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 11, 4), 495 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 11, 4), 496 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 11, 4), 497 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 11, 4), 498 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 4, 5, 11, 4), 499 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 2, 3, 11, 4), 500 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 11, 4), 501 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 11, 20, 11, 4), 502 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 10, 11, 4), 503 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 11, 4), 504 }; 505 506 static const struct ocelot_stat_layout vsc9953_stats_layout[] = { 507 { .offset = 0x00, .name = "rx_octets", }, 508 { .offset = 0x01, .name = "rx_unicast", }, 509 { .offset = 0x02, .name = "rx_multicast", }, 510 { .offset = 0x03, .name = "rx_broadcast", }, 511 { .offset = 0x04, .name = "rx_shorts", }, 512 { .offset = 0x05, .name = "rx_fragments", }, 513 { .offset = 0x06, .name = "rx_jabbers", }, 514 { .offset = 0x07, .name = "rx_crc_align_errs", }, 515 { .offset = 0x08, .name = "rx_sym_errs", }, 516 { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 517 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 518 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 519 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 520 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 521 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 522 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 523 { .offset = 0x10, .name = "rx_pause", }, 524 { .offset = 0x11, .name = "rx_control", }, 525 { .offset = 0x12, .name = "rx_longs", }, 526 { .offset = 0x13, .name = "rx_classified_drops", }, 527 { .offset = 0x14, .name = "rx_red_prio_0", }, 528 { .offset = 0x15, .name = "rx_red_prio_1", }, 529 { .offset = 0x16, .name = "rx_red_prio_2", }, 530 { .offset = 0x17, .name = "rx_red_prio_3", }, 531 { .offset = 0x18, .name = "rx_red_prio_4", }, 532 { .offset = 0x19, .name = "rx_red_prio_5", }, 533 { .offset = 0x1A, .name = "rx_red_prio_6", }, 534 { .offset = 0x1B, .name = "rx_red_prio_7", }, 535 { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 536 { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 537 { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 538 { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 539 { .offset = 0x20, .name = "rx_yellow_prio_4", }, 540 { .offset = 0x21, .name = "rx_yellow_prio_5", }, 541 { .offset = 0x22, .name = "rx_yellow_prio_6", }, 542 { .offset = 0x23, .name = "rx_yellow_prio_7", }, 543 { .offset = 0x24, .name = "rx_green_prio_0", }, 544 { .offset = 0x25, .name = "rx_green_prio_1", }, 545 { .offset = 0x26, .name = "rx_green_prio_2", }, 546 { .offset = 0x27, .name = "rx_green_prio_3", }, 547 { .offset = 0x28, .name = "rx_green_prio_4", }, 548 { .offset = 0x29, .name = "rx_green_prio_5", }, 549 { .offset = 0x2A, .name = "rx_green_prio_6", }, 550 { .offset = 0x2B, .name = "rx_green_prio_7", }, 551 { .offset = 0x40, .name = "tx_octets", }, 552 { .offset = 0x41, .name = "tx_unicast", }, 553 { .offset = 0x42, .name = "tx_multicast", }, 554 { .offset = 0x43, .name = "tx_broadcast", }, 555 { .offset = 0x44, .name = "tx_collision", }, 556 { .offset = 0x45, .name = "tx_drops", }, 557 { .offset = 0x46, .name = "tx_pause", }, 558 { .offset = 0x47, .name = "tx_frames_below_65_octets", }, 559 { .offset = 0x48, .name = "tx_frames_65_to_127_octets", }, 560 { .offset = 0x49, .name = "tx_frames_128_255_octets", }, 561 { .offset = 0x4A, .name = "tx_frames_256_511_octets", }, 562 { .offset = 0x4B, .name = "tx_frames_512_1023_octets", }, 563 { .offset = 0x4C, .name = "tx_frames_1024_1526_octets", }, 564 { .offset = 0x4D, .name = "tx_frames_over_1526_octets", }, 565 { .offset = 0x4E, .name = "tx_yellow_prio_0", }, 566 { .offset = 0x4F, .name = "tx_yellow_prio_1", }, 567 { .offset = 0x50, .name = "tx_yellow_prio_2", }, 568 { .offset = 0x51, .name = "tx_yellow_prio_3", }, 569 { .offset = 0x52, .name = "tx_yellow_prio_4", }, 570 { .offset = 0x53, .name = "tx_yellow_prio_5", }, 571 { .offset = 0x54, .name = "tx_yellow_prio_6", }, 572 { .offset = 0x55, .name = "tx_yellow_prio_7", }, 573 { .offset = 0x56, .name = "tx_green_prio_0", }, 574 { .offset = 0x57, .name = "tx_green_prio_1", }, 575 { .offset = 0x58, .name = "tx_green_prio_2", }, 576 { .offset = 0x59, .name = "tx_green_prio_3", }, 577 { .offset = 0x5A, .name = "tx_green_prio_4", }, 578 { .offset = 0x5B, .name = "tx_green_prio_5", }, 579 { .offset = 0x5C, .name = "tx_green_prio_6", }, 580 { .offset = 0x5D, .name = "tx_green_prio_7", }, 581 { .offset = 0x5E, .name = "tx_aged", }, 582 { .offset = 0x80, .name = "drop_local", }, 583 { .offset = 0x81, .name = "drop_tail", }, 584 { .offset = 0x82, .name = "drop_yellow_prio_0", }, 585 { .offset = 0x83, .name = "drop_yellow_prio_1", }, 586 { .offset = 0x84, .name = "drop_yellow_prio_2", }, 587 { .offset = 0x85, .name = "drop_yellow_prio_3", }, 588 { .offset = 0x86, .name = "drop_yellow_prio_4", }, 589 { .offset = 0x87, .name = "drop_yellow_prio_5", }, 590 { .offset = 0x88, .name = "drop_yellow_prio_6", }, 591 { .offset = 0x89, .name = "drop_yellow_prio_7", }, 592 { .offset = 0x8A, .name = "drop_green_prio_0", }, 593 { .offset = 0x8B, .name = "drop_green_prio_1", }, 594 { .offset = 0x8C, .name = "drop_green_prio_2", }, 595 { .offset = 0x8D, .name = "drop_green_prio_3", }, 596 { .offset = 0x8E, .name = "drop_green_prio_4", }, 597 { .offset = 0x8F, .name = "drop_green_prio_5", }, 598 { .offset = 0x90, .name = "drop_green_prio_6", }, 599 { .offset = 0x91, .name = "drop_green_prio_7", }, 600 }; 601 602 static struct vcap_field vsc9953_vcap_is2_keys[] = { 603 /* Common: 41 bits */ 604 [VCAP_IS2_TYPE] = { 0, 4}, 605 [VCAP_IS2_HK_FIRST] = { 4, 1}, 606 [VCAP_IS2_HK_PAG] = { 5, 8}, 607 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 11}, 608 [VCAP_IS2_HK_RSV2] = { 24, 1}, 609 [VCAP_IS2_HK_HOST_MATCH] = { 25, 1}, 610 [VCAP_IS2_HK_L2_MC] = { 26, 1}, 611 [VCAP_IS2_HK_L2_BC] = { 27, 1}, 612 [VCAP_IS2_HK_VLAN_TAGGED] = { 28, 1}, 613 [VCAP_IS2_HK_VID] = { 29, 12}, 614 [VCAP_IS2_HK_DEI] = { 41, 1}, 615 [VCAP_IS2_HK_PCP] = { 42, 3}, 616 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 617 [VCAP_IS2_HK_L2_DMAC] = { 45, 48}, 618 [VCAP_IS2_HK_L2_SMAC] = { 93, 48}, 619 /* MAC_ETYPE (TYPE=000) */ 620 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {141, 16}, 621 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {157, 16}, 622 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {173, 8}, 623 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {181, 3}, 624 /* MAC_LLC (TYPE=001) */ 625 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {141, 40}, 626 /* MAC_SNAP (TYPE=010) */ 627 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {141, 40}, 628 /* MAC_ARP (TYPE=011) */ 629 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 45, 48}, 630 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 93, 1}, 631 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 94, 1}, 632 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 95, 1}, 633 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 96, 1}, 634 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 97, 1}, 635 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 98, 1}, 636 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 99, 2}, 637 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {101, 32}, 638 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {133, 32}, 639 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {165, 1}, 640 /* IP4_TCP_UDP / IP4_OTHER common */ 641 [VCAP_IS2_HK_IP4] = { 45, 1}, 642 [VCAP_IS2_HK_L3_FRAGMENT] = { 46, 1}, 643 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 47, 1}, 644 [VCAP_IS2_HK_L3_OPTIONS] = { 48, 1}, 645 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 49, 1}, 646 [VCAP_IS2_HK_L3_TOS] = { 50, 8}, 647 [VCAP_IS2_HK_L3_IP4_DIP] = { 58, 32}, 648 [VCAP_IS2_HK_L3_IP4_SIP] = { 90, 32}, 649 [VCAP_IS2_HK_DIP_EQ_SIP] = {122, 1}, 650 /* IP4_TCP_UDP (TYPE=100) */ 651 [VCAP_IS2_HK_TCP] = {123, 1}, 652 [VCAP_IS2_HK_L4_DPORT] = {124, 16}, 653 [VCAP_IS2_HK_L4_SPORT] = {140, 16}, 654 [VCAP_IS2_HK_L4_RNG] = {156, 8}, 655 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {164, 1}, 656 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {165, 1}, 657 [VCAP_IS2_HK_L4_FIN] = {166, 1}, 658 [VCAP_IS2_HK_L4_SYN] = {167, 1}, 659 [VCAP_IS2_HK_L4_RST] = {168, 1}, 660 [VCAP_IS2_HK_L4_PSH] = {169, 1}, 661 [VCAP_IS2_HK_L4_ACK] = {170, 1}, 662 [VCAP_IS2_HK_L4_URG] = {171, 1}, 663 /* IP4_OTHER (TYPE=101) */ 664 [VCAP_IS2_HK_IP4_L3_PROTO] = {123, 8}, 665 [VCAP_IS2_HK_L3_PAYLOAD] = {131, 56}, 666 /* IP6_STD (TYPE=110) */ 667 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 45, 1}, 668 [VCAP_IS2_HK_L3_IP6_SIP] = { 46, 128}, 669 [VCAP_IS2_HK_IP6_L3_PROTO] = {174, 8}, 670 }; 671 672 static struct vcap_field vsc9953_vcap_is2_actions[] = { 673 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 674 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 675 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 676 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 677 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 678 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 679 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 680 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 8}, 681 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 21, 1}, 682 [VCAP_IS2_ACT_PORT_MASK] = { 22, 10}, 683 [VCAP_IS2_ACT_ACL_ID] = { 44, 6}, 684 [VCAP_IS2_ACT_HIT_CNT] = { 50, 32}, 685 }; 686 687 static const struct vcap_props vsc9953_vcap_props[] = { 688 [VCAP_IS2] = { 689 .tg_width = 2, 690 .sw_count = 4, 691 .entry_count = VSC9953_VCAP_IS2_CNT, 692 .entry_width = VSC9953_VCAP_IS2_ENTRY_WIDTH, 693 .action_count = VSC9953_VCAP_IS2_CNT + 694 VSC9953_VCAP_PORT_CNT + 2, 695 .action_width = 101, 696 .action_type_width = 1, 697 .action_table = { 698 [IS2_ACTION_TYPE_NORMAL] = { 699 .width = 44, 700 .count = 2 701 }, 702 [IS2_ACTION_TYPE_SMAC_SIP] = { 703 .width = 6, 704 .count = 4 705 }, 706 }, 707 .counter_words = 4, 708 .counter_width = 32, 709 }, 710 }; 711 712 #define VSC9953_INIT_TIMEOUT 50000 713 #define VSC9953_GCB_RST_SLEEP 100 714 #define VSC9953_SYS_RAMINIT_SLEEP 80 715 #define VCS9953_MII_TIMEOUT 10000 716 717 static int vsc9953_gcb_soft_rst_status(struct ocelot *ocelot) 718 { 719 int val; 720 721 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 722 723 return val; 724 } 725 726 static int vsc9953_sys_ram_init_status(struct ocelot *ocelot) 727 { 728 int val; 729 730 ocelot_field_read(ocelot, SYS_RESET_CFG_MEM_INIT, &val); 731 732 return val; 733 } 734 735 static int vsc9953_gcb_miim_pending_status(struct ocelot *ocelot) 736 { 737 int val; 738 739 ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_PENDING, &val); 740 741 return val; 742 } 743 744 static int vsc9953_gcb_miim_busy_status(struct ocelot *ocelot) 745 { 746 int val; 747 748 ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_BUSY, &val); 749 750 return val; 751 } 752 753 static int vsc9953_mdio_write(struct mii_bus *bus, int phy_id, int regnum, 754 u16 value) 755 { 756 struct ocelot *ocelot = bus->priv; 757 int err, cmd, val; 758 759 /* Wait while MIIM controller becomes idle */ 760 err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot, 761 val, !val, 10, VCS9953_MII_TIMEOUT); 762 if (err) { 763 dev_err(ocelot->dev, "MDIO write: pending timeout\n"); 764 goto out; 765 } 766 767 cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) | 768 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | 769 (value << MSCC_MIIM_CMD_WRDATA_SHIFT) | 770 MSCC_MIIM_CMD_OPR_WRITE; 771 772 ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD); 773 774 out: 775 return err; 776 } 777 778 static int vsc9953_mdio_read(struct mii_bus *bus, int phy_id, int regnum) 779 { 780 struct ocelot *ocelot = bus->priv; 781 int err, cmd, val; 782 783 /* Wait until MIIM controller becomes idle */ 784 err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot, 785 val, !val, 10, VCS9953_MII_TIMEOUT); 786 if (err) { 787 dev_err(ocelot->dev, "MDIO read: pending timeout\n"); 788 goto out; 789 } 790 791 /* Write the MIIM COMMAND register */ 792 cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) | 793 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ; 794 795 ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD); 796 797 /* Wait while read operation via the MIIM controller is in progress */ 798 err = readx_poll_timeout(vsc9953_gcb_miim_busy_status, ocelot, 799 val, !val, 10, VCS9953_MII_TIMEOUT); 800 if (err) { 801 dev_err(ocelot->dev, "MDIO read: busy timeout\n"); 802 goto out; 803 } 804 805 val = ocelot_read(ocelot, GCB_MIIM_MII_DATA); 806 807 err = val & 0xFFFF; 808 out: 809 return err; 810 } 811 812 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 813 * MEM_INIT is in SYS:SYSTEM:RESET_CFG 814 * MEM_ENA is in SYS:SYSTEM:RESET_CFG 815 */ 816 static int vsc9953_reset(struct ocelot *ocelot) 817 { 818 int val, err; 819 820 /* soft-reset the switch core */ 821 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 822 823 err = readx_poll_timeout(vsc9953_gcb_soft_rst_status, ocelot, val, !val, 824 VSC9953_GCB_RST_SLEEP, VSC9953_INIT_TIMEOUT); 825 if (err) { 826 dev_err(ocelot->dev, "timeout: switch core reset\n"); 827 return err; 828 } 829 830 /* initialize switch mem ~40us */ 831 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_ENA, 1); 832 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_INIT, 1); 833 834 err = readx_poll_timeout(vsc9953_sys_ram_init_status, ocelot, val, !val, 835 VSC9953_SYS_RAMINIT_SLEEP, 836 VSC9953_INIT_TIMEOUT); 837 if (err) { 838 dev_err(ocelot->dev, "timeout: switch sram init\n"); 839 return err; 840 } 841 842 /* enable switch core */ 843 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 844 845 return 0; 846 } 847 848 static void vsc9953_phylink_validate(struct ocelot *ocelot, int port, 849 unsigned long *supported, 850 struct phylink_link_state *state) 851 { 852 struct ocelot_port *ocelot_port = ocelot->ports[port]; 853 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 854 855 if (state->interface != PHY_INTERFACE_MODE_NA && 856 state->interface != ocelot_port->phy_mode) { 857 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 858 return; 859 } 860 861 phylink_set_port_modes(mask); 862 phylink_set(mask, Autoneg); 863 phylink_set(mask, Pause); 864 phylink_set(mask, Asym_Pause); 865 phylink_set(mask, 10baseT_Full); 866 phylink_set(mask, 10baseT_Half); 867 phylink_set(mask, 100baseT_Full); 868 phylink_set(mask, 100baseT_Half); 869 phylink_set(mask, 1000baseT_Full); 870 871 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) { 872 phylink_set(mask, 2500baseT_Full); 873 phylink_set(mask, 2500baseX_Full); 874 } 875 876 bitmap_and(supported, supported, mask, 877 __ETHTOOL_LINK_MODE_MASK_NBITS); 878 bitmap_and(state->advertising, state->advertising, mask, 879 __ETHTOOL_LINK_MODE_MASK_NBITS); 880 } 881 882 static int vsc9953_prevalidate_phy_mode(struct ocelot *ocelot, int port, 883 phy_interface_t phy_mode) 884 { 885 switch (phy_mode) { 886 case PHY_INTERFACE_MODE_INTERNAL: 887 if (port != 8 && port != 9) 888 return -ENOTSUPP; 889 return 0; 890 case PHY_INTERFACE_MODE_SGMII: 891 case PHY_INTERFACE_MODE_QSGMII: 892 /* Not supported on internal to-CPU ports */ 893 if (port == 8 || port == 9) 894 return -ENOTSUPP; 895 return 0; 896 default: 897 return -ENOTSUPP; 898 } 899 } 900 901 /* Watermark encode 902 * Bit 9: Unit; 0:1, 1:16 903 * Bit 8-0: Value to be multiplied with unit 904 */ 905 static u16 vsc9953_wm_enc(u16 value) 906 { 907 if (value >= BIT(9)) 908 return BIT(9) | (value / 16); 909 910 return value; 911 } 912 913 static const struct ocelot_ops vsc9953_ops = { 914 .reset = vsc9953_reset, 915 .wm_enc = vsc9953_wm_enc, 916 }; 917 918 static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot) 919 { 920 struct felix *felix = ocelot_to_felix(ocelot); 921 struct device *dev = ocelot->dev; 922 struct mii_bus *bus; 923 int port; 924 int rc; 925 926 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 927 sizeof(struct phy_device *), 928 GFP_KERNEL); 929 if (!felix->pcs) { 930 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 931 return -ENOMEM; 932 } 933 934 bus = devm_mdiobus_alloc(dev); 935 if (!bus) 936 return -ENOMEM; 937 938 bus->name = "VSC9953 internal MDIO bus"; 939 bus->read = vsc9953_mdio_read; 940 bus->write = vsc9953_mdio_write; 941 bus->parent = dev; 942 bus->priv = ocelot; 943 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 944 945 /* Needed in order to initialize the bus mutex lock */ 946 rc = mdiobus_register(bus); 947 if (rc < 0) { 948 dev_err(dev, "failed to register MDIO bus\n"); 949 return rc; 950 } 951 952 felix->imdio = bus; 953 954 for (port = 0; port < felix->info->num_ports; port++) { 955 struct ocelot_port *ocelot_port = ocelot->ports[port]; 956 int addr = port + 4; 957 struct mdio_device *pcs; 958 struct lynx_pcs *lynx; 959 960 if (dsa_is_unused_port(felix->ds, port)) 961 continue; 962 963 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 964 continue; 965 966 pcs = mdio_device_create(felix->imdio, addr); 967 if (IS_ERR(pcs)) 968 continue; 969 970 lynx = lynx_pcs_create(pcs); 971 if (!lynx) { 972 mdio_device_free(pcs); 973 continue; 974 } 975 976 felix->pcs[port] = lynx; 977 978 dev_info(dev, "Found PCS at internal MDIO address %d\n", addr); 979 } 980 981 return 0; 982 } 983 984 static void vsc9953_mdio_bus_free(struct ocelot *ocelot) 985 { 986 struct felix *felix = ocelot_to_felix(ocelot); 987 int port; 988 989 for (port = 0; port < ocelot->num_phys_ports; port++) { 990 struct lynx_pcs *pcs = felix->pcs[port]; 991 992 if (!pcs) 993 continue; 994 995 mdio_device_free(pcs->mdio); 996 lynx_pcs_destroy(pcs); 997 } 998 mdiobus_unregister(felix->imdio); 999 } 1000 1001 static void vsc9953_xmit_template_populate(struct ocelot *ocelot, int port) 1002 { 1003 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1004 u8 *template = ocelot_port->xmit_template; 1005 u64 bypass, dest, src; 1006 __be32 *prefix; 1007 u8 *injection; 1008 1009 /* Set the source port as the CPU port module and not the 1010 * NPI port 1011 */ 1012 src = ocelot->num_phys_ports; 1013 dest = BIT(port); 1014 bypass = true; 1015 1016 injection = template + OCELOT_SHORT_PREFIX_LEN; 1017 prefix = (__be32 *)template; 1018 1019 packing(injection, &bypass, 127, 127, OCELOT_TAG_LEN, PACK, 0); 1020 packing(injection, &dest, 67, 57, OCELOT_TAG_LEN, PACK, 0); 1021 packing(injection, &src, 46, 43, OCELOT_TAG_LEN, PACK, 0); 1022 1023 *prefix = cpu_to_be32(0x88800005); 1024 } 1025 1026 static const struct felix_info seville_info_vsc9953 = { 1027 .target_io_res = vsc9953_target_io_res, 1028 .port_io_res = vsc9953_port_io_res, 1029 .regfields = vsc9953_regfields, 1030 .map = vsc9953_regmap, 1031 .ops = &vsc9953_ops, 1032 .stats_layout = vsc9953_stats_layout, 1033 .num_stats = ARRAY_SIZE(vsc9953_stats_layout), 1034 .vcap_is2_keys = vsc9953_vcap_is2_keys, 1035 .vcap_is2_actions = vsc9953_vcap_is2_actions, 1036 .vcap = vsc9953_vcap_props, 1037 .shared_queue_sz = 2048 * 1024, 1038 .num_mact_rows = 2048, 1039 .num_ports = 10, 1040 .mdio_bus_alloc = vsc9953_mdio_bus_alloc, 1041 .mdio_bus_free = vsc9953_mdio_bus_free, 1042 .phylink_validate = vsc9953_phylink_validate, 1043 .prevalidate_phy_mode = vsc9953_prevalidate_phy_mode, 1044 .xmit_template_populate = vsc9953_xmit_template_populate, 1045 }; 1046 1047 static int seville_probe(struct platform_device *pdev) 1048 { 1049 struct dsa_switch *ds; 1050 struct ocelot *ocelot; 1051 struct resource *res; 1052 struct felix *felix; 1053 int err; 1054 1055 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 1056 if (!felix) { 1057 err = -ENOMEM; 1058 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 1059 goto err_alloc_felix; 1060 } 1061 1062 platform_set_drvdata(pdev, felix); 1063 1064 ocelot = &felix->ocelot; 1065 ocelot->dev = &pdev->dev; 1066 felix->info = &seville_info_vsc9953; 1067 1068 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1069 felix->switch_base = res->start; 1070 1071 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 1072 if (!ds) { 1073 err = -ENOMEM; 1074 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 1075 goto err_alloc_ds; 1076 } 1077 1078 ds->dev = &pdev->dev; 1079 ds->num_ports = felix->info->num_ports; 1080 ds->ops = &felix_switch_ops; 1081 ds->priv = ocelot; 1082 felix->ds = ds; 1083 1084 err = dsa_register_switch(ds); 1085 if (err) { 1086 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err); 1087 goto err_register_ds; 1088 } 1089 1090 return 0; 1091 1092 err_register_ds: 1093 kfree(ds); 1094 err_alloc_ds: 1095 err_alloc_felix: 1096 kfree(felix); 1097 return err; 1098 } 1099 1100 static int seville_remove(struct platform_device *pdev) 1101 { 1102 struct felix *felix; 1103 1104 felix = platform_get_drvdata(pdev); 1105 1106 dsa_unregister_switch(felix->ds); 1107 1108 kfree(felix->ds); 1109 kfree(felix); 1110 1111 return 0; 1112 } 1113 1114 static const struct of_device_id seville_of_match[] = { 1115 { .compatible = "mscc,vsc9953-switch" }, 1116 { }, 1117 }; 1118 MODULE_DEVICE_TABLE(of, seville_of_match); 1119 1120 static struct platform_driver seville_vsc9953_driver = { 1121 .probe = seville_probe, 1122 .remove = seville_remove, 1123 .driver = { 1124 .name = "mscc_seville", 1125 .of_match_table = of_match_ptr(seville_of_match), 1126 }, 1127 }; 1128 module_platform_driver(seville_vsc9953_driver); 1129 1130 MODULE_DESCRIPTION("Seville Switch driver"); 1131 MODULE_LICENSE("GPL v2"); 1132