1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Distributed Switch Architecture VSC9953 driver 3 * Copyright (C) 2020, Maxim Kochetkov <fido_max@inbox.ru> 4 */ 5 #include <linux/types.h> 6 #include <soc/mscc/ocelot_vcap.h> 7 #include <soc/mscc/ocelot_sys.h> 8 #include <soc/mscc/ocelot.h> 9 #include <linux/mdio/mdio-mscc-miim.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_platform.h> 12 #include <linux/pcs-lynx.h> 13 #include <linux/dsa/ocelot.h> 14 #include <linux/iopoll.h> 15 #include "felix.h" 16 17 #define VSC9953_NUM_PORTS 10 18 19 #define VSC9953_VCAP_POLICER_BASE 11 20 #define VSC9953_VCAP_POLICER_MAX 31 21 #define VSC9953_VCAP_POLICER_BASE2 120 22 #define VSC9953_VCAP_POLICER_MAX2 161 23 24 #define VSC9953_PORT_MODE_SERDES (OCELOT_PORT_MODE_1000BASEX | \ 25 OCELOT_PORT_MODE_SGMII | \ 26 OCELOT_PORT_MODE_QSGMII) 27 28 static const u32 vsc9953_port_modes[VSC9953_NUM_PORTS] = { 29 VSC9953_PORT_MODE_SERDES, 30 VSC9953_PORT_MODE_SERDES, 31 VSC9953_PORT_MODE_SERDES, 32 VSC9953_PORT_MODE_SERDES, 33 VSC9953_PORT_MODE_SERDES, 34 VSC9953_PORT_MODE_SERDES, 35 VSC9953_PORT_MODE_SERDES, 36 VSC9953_PORT_MODE_SERDES, 37 OCELOT_PORT_MODE_INTERNAL, 38 OCELOT_PORT_MODE_INTERNAL, 39 }; 40 41 static const u32 vsc9953_ana_regmap[] = { 42 REG(ANA_ADVLEARN, 0x00b500), 43 REG(ANA_VLANMASK, 0x00b504), 44 REG_RESERVED(ANA_PORT_B_DOMAIN), 45 REG(ANA_ANAGEFIL, 0x00b50c), 46 REG(ANA_ANEVENTS, 0x00b510), 47 REG(ANA_STORMLIMIT_BURST, 0x00b514), 48 REG(ANA_STORMLIMIT_CFG, 0x00b518), 49 REG(ANA_ISOLATED_PORTS, 0x00b528), 50 REG(ANA_COMMUNITY_PORTS, 0x00b52c), 51 REG(ANA_AUTOAGE, 0x00b530), 52 REG(ANA_MACTOPTIONS, 0x00b534), 53 REG(ANA_LEARNDISC, 0x00b538), 54 REG(ANA_AGENCTRL, 0x00b53c), 55 REG(ANA_MIRRORPORTS, 0x00b540), 56 REG(ANA_EMIRRORPORTS, 0x00b544), 57 REG(ANA_FLOODING, 0x00b548), 58 REG(ANA_FLOODING_IPMC, 0x00b54c), 59 REG(ANA_SFLOW_CFG, 0x00b550), 60 REG(ANA_PORT_MODE, 0x00b57c), 61 REG_RESERVED(ANA_CUT_THRU_CFG), 62 REG(ANA_PGID_PGID, 0x00b600), 63 REG(ANA_TABLES_ANMOVED, 0x00b4ac), 64 REG(ANA_TABLES_MACHDATA, 0x00b4b0), 65 REG(ANA_TABLES_MACLDATA, 0x00b4b4), 66 REG_RESERVED(ANA_TABLES_STREAMDATA), 67 REG(ANA_TABLES_MACACCESS, 0x00b4b8), 68 REG(ANA_TABLES_MACTINDX, 0x00b4bc), 69 REG(ANA_TABLES_VLANACCESS, 0x00b4c0), 70 REG(ANA_TABLES_VLANTIDX, 0x00b4c4), 71 REG_RESERVED(ANA_TABLES_ISDXACCESS), 72 REG_RESERVED(ANA_TABLES_ISDXTIDX), 73 REG(ANA_TABLES_ENTRYLIM, 0x00b480), 74 REG_RESERVED(ANA_TABLES_PTP_ID_HIGH), 75 REG_RESERVED(ANA_TABLES_PTP_ID_LOW), 76 REG_RESERVED(ANA_TABLES_STREAMACCESS), 77 REG_RESERVED(ANA_TABLES_STREAMTIDX), 78 REG_RESERVED(ANA_TABLES_SEQ_HISTORY), 79 REG_RESERVED(ANA_TABLES_SEQ_MASK), 80 REG_RESERVED(ANA_TABLES_SFID_MASK), 81 REG_RESERVED(ANA_TABLES_SFIDACCESS), 82 REG_RESERVED(ANA_TABLES_SFIDTIDX), 83 REG_RESERVED(ANA_MSTI_STATE), 84 REG_RESERVED(ANA_OAM_UPM_LM_CNT), 85 REG_RESERVED(ANA_SG_ACCESS_CTRL), 86 REG_RESERVED(ANA_SG_CONFIG_REG_1), 87 REG_RESERVED(ANA_SG_CONFIG_REG_2), 88 REG_RESERVED(ANA_SG_CONFIG_REG_3), 89 REG_RESERVED(ANA_SG_CONFIG_REG_4), 90 REG_RESERVED(ANA_SG_CONFIG_REG_5), 91 REG_RESERVED(ANA_SG_GCL_GS_CONFIG), 92 REG_RESERVED(ANA_SG_GCL_TI_CONFIG), 93 REG_RESERVED(ANA_SG_STATUS_REG_1), 94 REG_RESERVED(ANA_SG_STATUS_REG_2), 95 REG_RESERVED(ANA_SG_STATUS_REG_3), 96 REG(ANA_PORT_VLAN_CFG, 0x000000), 97 REG(ANA_PORT_DROP_CFG, 0x000004), 98 REG(ANA_PORT_QOS_CFG, 0x000008), 99 REG(ANA_PORT_VCAP_CFG, 0x00000c), 100 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x000010), 101 REG(ANA_PORT_VCAP_S2_CFG, 0x00001c), 102 REG(ANA_PORT_PCP_DEI_MAP, 0x000020), 103 REG(ANA_PORT_CPU_FWD_CFG, 0x000060), 104 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x000064), 105 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x000068), 106 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00006c), 107 REG(ANA_PORT_PORT_CFG, 0x000070), 108 REG(ANA_PORT_POL_CFG, 0x000074), 109 REG_RESERVED(ANA_PORT_PTP_CFG), 110 REG_RESERVED(ANA_PORT_PTP_DLY1_CFG), 111 REG_RESERVED(ANA_PORT_PTP_DLY2_CFG), 112 REG_RESERVED(ANA_PORT_SFID_CFG), 113 REG(ANA_PFC_PFC_CFG, 0x00c000), 114 REG_RESERVED(ANA_PFC_PFC_TIMER), 115 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 116 REG_RESERVED(ANA_IPT_IPT), 117 REG_RESERVED(ANA_PPT_PPT), 118 REG_RESERVED(ANA_FID_MAP_FID_MAP), 119 REG(ANA_AGGR_CFG, 0x00c600), 120 REG(ANA_CPUQ_CFG, 0x00c604), 121 REG_RESERVED(ANA_CPUQ_CFG2), 122 REG(ANA_CPUQ_8021_CFG, 0x00c60c), 123 REG(ANA_DSCP_CFG, 0x00c64c), 124 REG(ANA_DSCP_REWR_CFG, 0x00c74c), 125 REG(ANA_VCAP_RNG_TYPE_CFG, 0x00c78c), 126 REG(ANA_VCAP_RNG_VAL_CFG, 0x00c7ac), 127 REG_RESERVED(ANA_VRAP_CFG), 128 REG_RESERVED(ANA_VRAP_HDR_DATA), 129 REG_RESERVED(ANA_VRAP_HDR_MASK), 130 REG(ANA_DISCARD_CFG, 0x00c7d8), 131 REG(ANA_FID_CFG, 0x00c7dc), 132 REG(ANA_POL_PIR_CFG, 0x00a000), 133 REG(ANA_POL_CIR_CFG, 0x00a004), 134 REG(ANA_POL_MODE_CFG, 0x00a008), 135 REG(ANA_POL_PIR_STATE, 0x00a00c), 136 REG(ANA_POL_CIR_STATE, 0x00a010), 137 REG_RESERVED(ANA_POL_STATE), 138 REG(ANA_POL_FLOWC, 0x00c280), 139 REG(ANA_POL_HYST, 0x00c2ec), 140 REG_RESERVED(ANA_POL_MISC_CFG), 141 }; 142 143 static const u32 vsc9953_qs_regmap[] = { 144 REG(QS_XTR_GRP_CFG, 0x000000), 145 REG(QS_XTR_RD, 0x000008), 146 REG(QS_XTR_FRM_PRUNING, 0x000010), 147 REG(QS_XTR_FLUSH, 0x000018), 148 REG(QS_XTR_DATA_PRESENT, 0x00001c), 149 REG(QS_XTR_CFG, 0x000020), 150 REG(QS_INJ_GRP_CFG, 0x000024), 151 REG(QS_INJ_WR, 0x00002c), 152 REG(QS_INJ_CTRL, 0x000034), 153 REG(QS_INJ_STATUS, 0x00003c), 154 REG(QS_INJ_ERR, 0x000040), 155 REG_RESERVED(QS_INH_DBG), 156 }; 157 158 static const u32 vsc9953_vcap_regmap[] = { 159 /* VCAP_CORE_CFG */ 160 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 161 REG(VCAP_CORE_MV_CFG, 0x000004), 162 /* VCAP_CORE_CACHE */ 163 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 164 REG(VCAP_CACHE_MASK_DAT, 0x000108), 165 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 166 REG(VCAP_CACHE_CNT_DAT, 0x000308), 167 REG(VCAP_CACHE_TG_DAT, 0x000388), 168 /* VCAP_CONST */ 169 REG(VCAP_CONST_VCAP_VER, 0x000398), 170 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 171 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 172 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 173 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 174 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 175 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 176 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 177 REG_RESERVED(VCAP_CONST_CORE_CNT), 178 REG_RESERVED(VCAP_CONST_IF_CNT), 179 }; 180 181 static const u32 vsc9953_qsys_regmap[] = { 182 REG(QSYS_PORT_MODE, 0x003600), 183 REG(QSYS_SWITCH_PORT_MODE, 0x003630), 184 REG(QSYS_STAT_CNT_CFG, 0x00365c), 185 REG(QSYS_EEE_CFG, 0x003660), 186 REG(QSYS_EEE_THRES, 0x003688), 187 REG(QSYS_IGR_NO_SHARING, 0x00368c), 188 REG(QSYS_EGR_NO_SHARING, 0x003690), 189 REG(QSYS_SW_STATUS, 0x003694), 190 REG(QSYS_EXT_CPU_CFG, 0x0036c0), 191 REG_RESERVED(QSYS_PAD_CFG), 192 REG(QSYS_CPU_GROUP_MAP, 0x0036c8), 193 REG_RESERVED(QSYS_QMAP), 194 REG_RESERVED(QSYS_ISDX_SGRP), 195 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 196 REG_RESERVED(QSYS_TFRM_MISC), 197 REG_RESERVED(QSYS_TFRM_PORT_DLY), 198 REG_RESERVED(QSYS_TFRM_TIMER_CFG_1), 199 REG_RESERVED(QSYS_TFRM_TIMER_CFG_2), 200 REG_RESERVED(QSYS_TFRM_TIMER_CFG_3), 201 REG_RESERVED(QSYS_TFRM_TIMER_CFG_4), 202 REG_RESERVED(QSYS_TFRM_TIMER_CFG_5), 203 REG_RESERVED(QSYS_TFRM_TIMER_CFG_6), 204 REG_RESERVED(QSYS_TFRM_TIMER_CFG_7), 205 REG_RESERVED(QSYS_TFRM_TIMER_CFG_8), 206 REG(QSYS_RED_PROFILE, 0x003724), 207 REG(QSYS_RES_QOS_MODE, 0x003764), 208 REG(QSYS_RES_CFG, 0x004000), 209 REG(QSYS_RES_STAT, 0x004004), 210 REG(QSYS_EGR_DROP_MODE, 0x003768), 211 REG(QSYS_EQ_CTRL, 0x00376c), 212 REG_RESERVED(QSYS_EVENTS_CORE), 213 REG_RESERVED(QSYS_QMAXSDU_CFG_0), 214 REG_RESERVED(QSYS_QMAXSDU_CFG_1), 215 REG_RESERVED(QSYS_QMAXSDU_CFG_2), 216 REG_RESERVED(QSYS_QMAXSDU_CFG_3), 217 REG_RESERVED(QSYS_QMAXSDU_CFG_4), 218 REG_RESERVED(QSYS_QMAXSDU_CFG_5), 219 REG_RESERVED(QSYS_QMAXSDU_CFG_6), 220 REG_RESERVED(QSYS_QMAXSDU_CFG_7), 221 REG_RESERVED(QSYS_PREEMPTION_CFG), 222 REG(QSYS_CIR_CFG, 0x000000), 223 REG_RESERVED(QSYS_EIR_CFG), 224 REG(QSYS_SE_CFG, 0x000008), 225 REG(QSYS_SE_DWRR_CFG, 0x00000c), 226 REG_RESERVED(QSYS_SE_CONNECT), 227 REG_RESERVED(QSYS_SE_DLB_SENSE), 228 REG(QSYS_CIR_STATE, 0x000044), 229 REG_RESERVED(QSYS_EIR_STATE), 230 REG_RESERVED(QSYS_SE_STATE), 231 REG(QSYS_HSCH_MISC_CFG, 0x003774), 232 REG_RESERVED(QSYS_TAG_CONFIG), 233 REG_RESERVED(QSYS_TAS_PARAM_CFG_CTRL), 234 REG_RESERVED(QSYS_PORT_MAX_SDU), 235 REG_RESERVED(QSYS_PARAM_CFG_REG_1), 236 REG_RESERVED(QSYS_PARAM_CFG_REG_2), 237 REG_RESERVED(QSYS_PARAM_CFG_REG_3), 238 REG_RESERVED(QSYS_PARAM_CFG_REG_4), 239 REG_RESERVED(QSYS_PARAM_CFG_REG_5), 240 REG_RESERVED(QSYS_GCL_CFG_REG_1), 241 REG_RESERVED(QSYS_GCL_CFG_REG_2), 242 REG_RESERVED(QSYS_PARAM_STATUS_REG_1), 243 REG_RESERVED(QSYS_PARAM_STATUS_REG_2), 244 REG_RESERVED(QSYS_PARAM_STATUS_REG_3), 245 REG_RESERVED(QSYS_PARAM_STATUS_REG_4), 246 REG_RESERVED(QSYS_PARAM_STATUS_REG_5), 247 REG_RESERVED(QSYS_PARAM_STATUS_REG_6), 248 REG_RESERVED(QSYS_PARAM_STATUS_REG_7), 249 REG_RESERVED(QSYS_PARAM_STATUS_REG_8), 250 REG_RESERVED(QSYS_PARAM_STATUS_REG_9), 251 REG_RESERVED(QSYS_GCL_STATUS_REG_1), 252 REG_RESERVED(QSYS_GCL_STATUS_REG_2), 253 }; 254 255 static const u32 vsc9953_rew_regmap[] = { 256 REG(REW_PORT_VLAN_CFG, 0x000000), 257 REG(REW_TAG_CFG, 0x000004), 258 REG(REW_PORT_CFG, 0x000008), 259 REG(REW_DSCP_CFG, 0x00000c), 260 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 261 REG_RESERVED(REW_PTP_CFG), 262 REG_RESERVED(REW_PTP_DLY1_CFG), 263 REG_RESERVED(REW_RED_TAG_CFG), 264 REG(REW_DSCP_REMAP_DP1_CFG, 0x000610), 265 REG(REW_DSCP_REMAP_CFG, 0x000710), 266 REG_RESERVED(REW_STAT_CFG), 267 REG_RESERVED(REW_REW_STICKY), 268 REG_RESERVED(REW_PPT), 269 }; 270 271 static const u32 vsc9953_sys_regmap[] = { 272 REG(SYS_COUNT_RX_OCTETS, 0x000000), 273 REG(SYS_COUNT_RX_UNICAST, 0x000004), 274 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 275 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 276 REG(SYS_COUNT_RX_SHORTS, 0x000010), 277 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 278 REG(SYS_COUNT_RX_JABBERS, 0x000018), 279 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 280 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 281 REG(SYS_COUNT_RX_64, 0x000024), 282 REG(SYS_COUNT_RX_65_127, 0x000028), 283 REG(SYS_COUNT_RX_128_255, 0x00002c), 284 REG(SYS_COUNT_RX_256_511, 0x000030), 285 REG(SYS_COUNT_RX_512_1023, 0x000034), 286 REG(SYS_COUNT_RX_1024_1526, 0x000038), 287 REG(SYS_COUNT_RX_1527_MAX, 0x00003c), 288 REG(SYS_COUNT_RX_PAUSE, 0x000040), 289 REG(SYS_COUNT_RX_CONTROL, 0x000044), 290 REG(SYS_COUNT_RX_LONGS, 0x000048), 291 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), 292 REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), 293 REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), 294 REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), 295 REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), 296 REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), 297 REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), 298 REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), 299 REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), 300 REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), 301 REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), 302 REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), 303 REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), 304 REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), 305 REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), 306 REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), 307 REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), 308 REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), 309 REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), 310 REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), 311 REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), 312 REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), 313 REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), 314 REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), 315 REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), 316 REG(SYS_COUNT_TX_OCTETS, 0x000100), 317 REG(SYS_COUNT_TX_UNICAST, 0x000104), 318 REG(SYS_COUNT_TX_MULTICAST, 0x000108), 319 REG(SYS_COUNT_TX_BROADCAST, 0x00010c), 320 REG(SYS_COUNT_TX_COLLISION, 0x000110), 321 REG(SYS_COUNT_TX_DROPS, 0x000114), 322 REG(SYS_COUNT_TX_PAUSE, 0x000118), 323 REG(SYS_COUNT_TX_64, 0x00011c), 324 REG(SYS_COUNT_TX_65_127, 0x000120), 325 REG(SYS_COUNT_TX_128_255, 0x000124), 326 REG(SYS_COUNT_TX_256_511, 0x000128), 327 REG(SYS_COUNT_TX_512_1023, 0x00012c), 328 REG(SYS_COUNT_TX_1024_1526, 0x000130), 329 REG(SYS_COUNT_TX_1527_MAX, 0x000134), 330 REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000138), 331 REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00013c), 332 REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000140), 333 REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000144), 334 REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000148), 335 REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00014c), 336 REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000150), 337 REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000154), 338 REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000158), 339 REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00015c), 340 REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000160), 341 REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000164), 342 REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000168), 343 REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00016c), 344 REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000170), 345 REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000174), 346 REG(SYS_COUNT_TX_AGED, 0x000178), 347 REG(SYS_COUNT_DROP_LOCAL, 0x000200), 348 REG(SYS_COUNT_DROP_TAIL, 0x000204), 349 REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000208), 350 REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00020c), 351 REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000210), 352 REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000214), 353 REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000218), 354 REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00021c), 355 REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000220), 356 REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000224), 357 REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000228), 358 REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00022c), 359 REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000230), 360 REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000234), 361 REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000238), 362 REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00023c), 363 REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000240), 364 REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000244), 365 REG(SYS_RESET_CFG, 0x000318), 366 REG_RESERVED(SYS_SR_ETYPE_CFG), 367 REG(SYS_VLAN_ETYPE_CFG, 0x000320), 368 REG(SYS_PORT_MODE, 0x000324), 369 REG(SYS_FRONT_PORT_MODE, 0x000354), 370 REG(SYS_FRM_AGING, 0x00037c), 371 REG(SYS_STAT_CFG, 0x000380), 372 REG_RESERVED(SYS_SW_STATUS), 373 REG_RESERVED(SYS_MISC_CFG), 374 REG_RESERVED(SYS_REW_MAC_HIGH_CFG), 375 REG_RESERVED(SYS_REW_MAC_LOW_CFG), 376 REG_RESERVED(SYS_TIMESTAMP_OFFSET), 377 REG(SYS_PAUSE_CFG, 0x00044c), 378 REG(SYS_PAUSE_TOT_CFG, 0x000478), 379 REG(SYS_ATOP, 0x00047c), 380 REG(SYS_ATOP_TOT_CFG, 0x0004a8), 381 REG(SYS_MAC_FC_CFG, 0x0004ac), 382 REG(SYS_MMGT, 0x0004d4), 383 REG_RESERVED(SYS_MMGT_FAST), 384 REG_RESERVED(SYS_EVENTS_DIF), 385 REG_RESERVED(SYS_EVENTS_CORE), 386 REG_RESERVED(SYS_PTP_STATUS), 387 REG_RESERVED(SYS_PTP_TXSTAMP), 388 REG_RESERVED(SYS_PTP_NXT), 389 REG_RESERVED(SYS_PTP_CFG), 390 REG_RESERVED(SYS_RAM_INIT), 391 REG_RESERVED(SYS_CM_ADDR), 392 REG_RESERVED(SYS_CM_DATA_WR), 393 REG_RESERVED(SYS_CM_DATA_RD), 394 REG_RESERVED(SYS_CM_OP), 395 REG_RESERVED(SYS_CM_DATA), 396 }; 397 398 static const u32 vsc9953_gcb_regmap[] = { 399 REG(GCB_SOFT_RST, 0x000008), 400 REG(GCB_MIIM_MII_STATUS, 0x0000ac), 401 REG(GCB_MIIM_MII_CMD, 0x0000b4), 402 REG(GCB_MIIM_MII_DATA, 0x0000b8), 403 }; 404 405 static const u32 vsc9953_dev_gmii_regmap[] = { 406 REG(DEV_CLOCK_CFG, 0x0), 407 REG(DEV_PORT_MISC, 0x4), 408 REG_RESERVED(DEV_EVENTS), 409 REG(DEV_EEE_CFG, 0xc), 410 REG_RESERVED(DEV_RX_PATH_DELAY), 411 REG_RESERVED(DEV_TX_PATH_DELAY), 412 REG_RESERVED(DEV_PTP_PREDICT_CFG), 413 REG(DEV_MAC_ENA_CFG, 0x10), 414 REG(DEV_MAC_MODE_CFG, 0x14), 415 REG(DEV_MAC_MAXLEN_CFG, 0x18), 416 REG(DEV_MAC_TAGS_CFG, 0x1c), 417 REG(DEV_MAC_ADV_CHK_CFG, 0x20), 418 REG(DEV_MAC_IFG_CFG, 0x24), 419 REG(DEV_MAC_HDX_CFG, 0x28), 420 REG_RESERVED(DEV_MAC_DBG_CFG), 421 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x30), 422 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x34), 423 REG(DEV_MAC_STICKY, 0x38), 424 REG_RESERVED(PCS1G_CFG), 425 REG_RESERVED(PCS1G_MODE_CFG), 426 REG_RESERVED(PCS1G_SD_CFG), 427 REG_RESERVED(PCS1G_ANEG_CFG), 428 REG_RESERVED(PCS1G_ANEG_NP_CFG), 429 REG_RESERVED(PCS1G_LB_CFG), 430 REG_RESERVED(PCS1G_DBG_CFG), 431 REG_RESERVED(PCS1G_CDET_CFG), 432 REG_RESERVED(PCS1G_ANEG_STATUS), 433 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 434 REG_RESERVED(PCS1G_LINK_STATUS), 435 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 436 REG_RESERVED(PCS1G_STICKY), 437 REG_RESERVED(PCS1G_DEBUG_STATUS), 438 REG_RESERVED(PCS1G_LPI_CFG), 439 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 440 REG_RESERVED(PCS1G_LPI_STATUS), 441 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 442 REG_RESERVED(PCS1G_TSTPAT_STATUS), 443 REG_RESERVED(DEV_PCS_FX100_CFG), 444 REG_RESERVED(DEV_PCS_FX100_STATUS), 445 }; 446 447 static const u32 *vsc9953_regmap[TARGET_MAX] = { 448 [ANA] = vsc9953_ana_regmap, 449 [QS] = vsc9953_qs_regmap, 450 [QSYS] = vsc9953_qsys_regmap, 451 [REW] = vsc9953_rew_regmap, 452 [SYS] = vsc9953_sys_regmap, 453 [S0] = vsc9953_vcap_regmap, 454 [S1] = vsc9953_vcap_regmap, 455 [S2] = vsc9953_vcap_regmap, 456 [GCB] = vsc9953_gcb_regmap, 457 [DEV_GMII] = vsc9953_dev_gmii_regmap, 458 }; 459 460 /* Addresses are relative to the device's base address */ 461 static const struct resource vsc9953_target_io_res[TARGET_MAX] = { 462 [ANA] = { 463 .start = 0x0280000, 464 .end = 0x028ffff, 465 .name = "ana", 466 }, 467 [QS] = { 468 .start = 0x0080000, 469 .end = 0x00800ff, 470 .name = "qs", 471 }, 472 [QSYS] = { 473 .start = 0x0200000, 474 .end = 0x021ffff, 475 .name = "qsys", 476 }, 477 [REW] = { 478 .start = 0x0030000, 479 .end = 0x003ffff, 480 .name = "rew", 481 }, 482 [SYS] = { 483 .start = 0x0010000, 484 .end = 0x001ffff, 485 .name = "sys", 486 }, 487 [S0] = { 488 .start = 0x0040000, 489 .end = 0x00403ff, 490 .name = "s0", 491 }, 492 [S1] = { 493 .start = 0x0050000, 494 .end = 0x00503ff, 495 .name = "s1", 496 }, 497 [S2] = { 498 .start = 0x0060000, 499 .end = 0x00603ff, 500 .name = "s2", 501 }, 502 [PTP] = { 503 .start = 0x0090000, 504 .end = 0x00900cb, 505 .name = "ptp", 506 }, 507 [GCB] = { 508 .start = 0x0070000, 509 .end = 0x00701ff, 510 .name = "devcpu_gcb", 511 }, 512 }; 513 514 static const struct resource vsc9953_port_io_res[] = { 515 { 516 .start = 0x0100000, 517 .end = 0x010ffff, 518 .name = "port0", 519 }, 520 { 521 .start = 0x0110000, 522 .end = 0x011ffff, 523 .name = "port1", 524 }, 525 { 526 .start = 0x0120000, 527 .end = 0x012ffff, 528 .name = "port2", 529 }, 530 { 531 .start = 0x0130000, 532 .end = 0x013ffff, 533 .name = "port3", 534 }, 535 { 536 .start = 0x0140000, 537 .end = 0x014ffff, 538 .name = "port4", 539 }, 540 { 541 .start = 0x0150000, 542 .end = 0x015ffff, 543 .name = "port5", 544 }, 545 { 546 .start = 0x0160000, 547 .end = 0x016ffff, 548 .name = "port6", 549 }, 550 { 551 .start = 0x0170000, 552 .end = 0x017ffff, 553 .name = "port7", 554 }, 555 { 556 .start = 0x0180000, 557 .end = 0x018ffff, 558 .name = "port8", 559 }, 560 { 561 .start = 0x0190000, 562 .end = 0x019ffff, 563 .name = "port9", 564 }, 565 }; 566 567 static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = { 568 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 10, 10), 569 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 9), 570 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), 571 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), 572 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), 573 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), 574 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), 575 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 576 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), 577 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), 578 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), 579 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), 580 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), 581 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 582 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 583 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), 584 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), 585 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), 586 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 587 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 588 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), 589 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), 590 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), 591 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), 592 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), 593 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 594 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 595 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 596 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 7, 7), 597 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 6, 6), 598 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 5, 5), 599 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 600 [GCB_MIIM_MII_STATUS_PENDING] = REG_FIELD(GCB_MIIM_MII_STATUS, 2, 2), 601 [GCB_MIIM_MII_STATUS_BUSY] = REG_FIELD(GCB_MIIM_MII_STATUS, 3, 3), 602 /* Replicated per number of ports (11), register size 4 per port */ 603 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 13, 13, 11, 4), 604 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 11, 4), 605 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 11, 4), 606 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 11, 4), 607 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 11, 4), 608 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 4, 5, 11, 4), 609 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 2, 3, 11, 4), 610 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 11, 4), 611 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 11, 20, 11, 4), 612 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 10, 11, 4), 613 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 11, 4), 614 }; 615 616 static const struct ocelot_stat_layout vsc9953_stats_layout[OCELOT_NUM_STATS] = { 617 OCELOT_COMMON_STATS, 618 }; 619 620 static const struct vcap_field vsc9953_vcap_es0_keys[] = { 621 [VCAP_ES0_EGR_PORT] = { 0, 4}, 622 [VCAP_ES0_IGR_PORT] = { 4, 4}, 623 [VCAP_ES0_RSV] = { 8, 2}, 624 [VCAP_ES0_L2_MC] = { 10, 1}, 625 [VCAP_ES0_L2_BC] = { 11, 1}, 626 [VCAP_ES0_VID] = { 12, 12}, 627 [VCAP_ES0_DP] = { 24, 1}, 628 [VCAP_ES0_PCP] = { 25, 3}, 629 }; 630 631 static const struct vcap_field vsc9953_vcap_es0_actions[] = { 632 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 633 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 634 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 635 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 636 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 637 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 638 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 639 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 640 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 641 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 642 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 643 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 644 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 645 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 646 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 647 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 648 [VCAP_ES0_ACT_RSV] = { 49, 24}, 649 [VCAP_ES0_ACT_HIT_STICKY] = { 73, 1}, 650 }; 651 652 static const struct vcap_field vsc9953_vcap_is1_keys[] = { 653 [VCAP_IS1_HK_TYPE] = { 0, 1}, 654 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 655 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 11}, 656 [VCAP_IS1_HK_RSV] = { 14, 10}, 657 /* VCAP_IS1_HK_OAM_Y1731 not supported */ 658 [VCAP_IS1_HK_L2_MC] = { 24, 1}, 659 [VCAP_IS1_HK_L2_BC] = { 25, 1}, 660 [VCAP_IS1_HK_IP_MC] = { 26, 1}, 661 [VCAP_IS1_HK_VLAN_TAGGED] = { 27, 1}, 662 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 28, 1}, 663 [VCAP_IS1_HK_TPID] = { 29, 1}, 664 [VCAP_IS1_HK_VID] = { 30, 12}, 665 [VCAP_IS1_HK_DEI] = { 42, 1}, 666 [VCAP_IS1_HK_PCP] = { 43, 3}, 667 /* Specific Fields for IS1 Half Key S1_NORMAL */ 668 [VCAP_IS1_HK_L2_SMAC] = { 46, 48}, 669 [VCAP_IS1_HK_ETYPE_LEN] = { 94, 1}, 670 [VCAP_IS1_HK_ETYPE] = { 95, 16}, 671 [VCAP_IS1_HK_IP_SNAP] = {111, 1}, 672 [VCAP_IS1_HK_IP4] = {112, 1}, 673 /* Layer-3 Information */ 674 [VCAP_IS1_HK_L3_FRAGMENT] = {113, 1}, 675 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {114, 1}, 676 [VCAP_IS1_HK_L3_OPTIONS] = {115, 1}, 677 [VCAP_IS1_HK_L3_DSCP] = {116, 6}, 678 [VCAP_IS1_HK_L3_IP4_SIP] = {122, 32}, 679 /* Layer-4 Information */ 680 [VCAP_IS1_HK_TCP_UDP] = {154, 1}, 681 [VCAP_IS1_HK_TCP] = {155, 1}, 682 [VCAP_IS1_HK_L4_SPORT] = {156, 16}, 683 [VCAP_IS1_HK_L4_RNG] = {172, 8}, 684 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 685 [VCAP_IS1_HK_IP4_INNER_TPID] = { 46, 1}, 686 [VCAP_IS1_HK_IP4_INNER_VID] = { 47, 12}, 687 [VCAP_IS1_HK_IP4_INNER_DEI] = { 59, 1}, 688 [VCAP_IS1_HK_IP4_INNER_PCP] = { 60, 3}, 689 [VCAP_IS1_HK_IP4_IP4] = { 63, 1}, 690 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 64, 1}, 691 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 65, 1}, 692 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 66, 1}, 693 [VCAP_IS1_HK_IP4_L3_DSCP] = { 67, 6}, 694 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 73, 32}, 695 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {105, 32}, 696 [VCAP_IS1_HK_IP4_L3_PROTO] = {137, 8}, 697 [VCAP_IS1_HK_IP4_TCP_UDP] = {145, 1}, 698 [VCAP_IS1_HK_IP4_TCP] = {146, 1}, 699 [VCAP_IS1_HK_IP4_L4_RNG] = {147, 8}, 700 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {155, 32}, 701 }; 702 703 static const struct vcap_field vsc9953_vcap_is1_actions[] = { 704 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 705 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 706 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 707 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 708 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 709 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 710 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 711 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 712 [VCAP_IS1_ACT_RSV] = { 29, 11}, 713 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 40, 1}, 714 [VCAP_IS1_ACT_VID_ADD_VAL] = { 41, 12}, 715 [VCAP_IS1_ACT_FID_SEL] = { 53, 2}, 716 [VCAP_IS1_ACT_FID_VAL] = { 55, 13}, 717 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 68, 1}, 718 [VCAP_IS1_ACT_PCP_VAL] = { 69, 3}, 719 [VCAP_IS1_ACT_DEI_VAL] = { 72, 1}, 720 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 73, 1}, 721 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 74, 2}, 722 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 76, 4}, 723 [VCAP_IS1_ACT_HIT_STICKY] = { 80, 1}, 724 }; 725 726 static struct vcap_field vsc9953_vcap_is2_keys[] = { 727 /* Common: 41 bits */ 728 [VCAP_IS2_TYPE] = { 0, 4}, 729 [VCAP_IS2_HK_FIRST] = { 4, 1}, 730 [VCAP_IS2_HK_PAG] = { 5, 8}, 731 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 11}, 732 [VCAP_IS2_HK_RSV2] = { 24, 1}, 733 [VCAP_IS2_HK_HOST_MATCH] = { 25, 1}, 734 [VCAP_IS2_HK_L2_MC] = { 26, 1}, 735 [VCAP_IS2_HK_L2_BC] = { 27, 1}, 736 [VCAP_IS2_HK_VLAN_TAGGED] = { 28, 1}, 737 [VCAP_IS2_HK_VID] = { 29, 12}, 738 [VCAP_IS2_HK_DEI] = { 41, 1}, 739 [VCAP_IS2_HK_PCP] = { 42, 3}, 740 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 741 [VCAP_IS2_HK_L2_DMAC] = { 45, 48}, 742 [VCAP_IS2_HK_L2_SMAC] = { 93, 48}, 743 /* MAC_ETYPE (TYPE=000) */ 744 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {141, 16}, 745 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {157, 16}, 746 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {173, 8}, 747 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {181, 3}, 748 /* MAC_LLC (TYPE=001) */ 749 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {141, 40}, 750 /* MAC_SNAP (TYPE=010) */ 751 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {141, 40}, 752 /* MAC_ARP (TYPE=011) */ 753 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 45, 48}, 754 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 93, 1}, 755 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 94, 1}, 756 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 95, 1}, 757 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 96, 1}, 758 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 97, 1}, 759 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 98, 1}, 760 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 99, 2}, 761 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {101, 32}, 762 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {133, 32}, 763 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {165, 1}, 764 /* IP4_TCP_UDP / IP4_OTHER common */ 765 [VCAP_IS2_HK_IP4] = { 45, 1}, 766 [VCAP_IS2_HK_L3_FRAGMENT] = { 46, 1}, 767 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 47, 1}, 768 [VCAP_IS2_HK_L3_OPTIONS] = { 48, 1}, 769 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 49, 1}, 770 [VCAP_IS2_HK_L3_TOS] = { 50, 8}, 771 [VCAP_IS2_HK_L3_IP4_DIP] = { 58, 32}, 772 [VCAP_IS2_HK_L3_IP4_SIP] = { 90, 32}, 773 [VCAP_IS2_HK_DIP_EQ_SIP] = {122, 1}, 774 /* IP4_TCP_UDP (TYPE=100) */ 775 [VCAP_IS2_HK_TCP] = {123, 1}, 776 [VCAP_IS2_HK_L4_DPORT] = {124, 16}, 777 [VCAP_IS2_HK_L4_SPORT] = {140, 16}, 778 [VCAP_IS2_HK_L4_RNG] = {156, 8}, 779 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {164, 1}, 780 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {165, 1}, 781 [VCAP_IS2_HK_L4_FIN] = {166, 1}, 782 [VCAP_IS2_HK_L4_SYN] = {167, 1}, 783 [VCAP_IS2_HK_L4_RST] = {168, 1}, 784 [VCAP_IS2_HK_L4_PSH] = {169, 1}, 785 [VCAP_IS2_HK_L4_ACK] = {170, 1}, 786 [VCAP_IS2_HK_L4_URG] = {171, 1}, 787 /* IP4_OTHER (TYPE=101) */ 788 [VCAP_IS2_HK_IP4_L3_PROTO] = {123, 8}, 789 [VCAP_IS2_HK_L3_PAYLOAD] = {131, 56}, 790 /* IP6_STD (TYPE=110) */ 791 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 45, 1}, 792 [VCAP_IS2_HK_L3_IP6_SIP] = { 46, 128}, 793 [VCAP_IS2_HK_IP6_L3_PROTO] = {174, 8}, 794 }; 795 796 static struct vcap_field vsc9953_vcap_is2_actions[] = { 797 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 798 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 799 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 800 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 801 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 802 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 803 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 804 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 8}, 805 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 21, 1}, 806 [VCAP_IS2_ACT_PORT_MASK] = { 22, 10}, 807 [VCAP_IS2_ACT_ACL_ID] = { 44, 6}, 808 [VCAP_IS2_ACT_HIT_CNT] = { 50, 32}, 809 }; 810 811 static struct vcap_props vsc9953_vcap_props[] = { 812 [VCAP_ES0] = { 813 .action_type_width = 0, 814 .action_table = { 815 [ES0_ACTION_TYPE_NORMAL] = { 816 .width = 73, /* HIT_STICKY not included */ 817 .count = 1, 818 }, 819 }, 820 .target = S0, 821 .keys = vsc9953_vcap_es0_keys, 822 .actions = vsc9953_vcap_es0_actions, 823 }, 824 [VCAP_IS1] = { 825 .action_type_width = 0, 826 .action_table = { 827 [IS1_ACTION_TYPE_NORMAL] = { 828 .width = 80, /* HIT_STICKY not included */ 829 .count = 4, 830 }, 831 }, 832 .target = S1, 833 .keys = vsc9953_vcap_is1_keys, 834 .actions = vsc9953_vcap_is1_actions, 835 }, 836 [VCAP_IS2] = { 837 .action_type_width = 1, 838 .action_table = { 839 [IS2_ACTION_TYPE_NORMAL] = { 840 .width = 50, /* HIT_CNT not included */ 841 .count = 2 842 }, 843 [IS2_ACTION_TYPE_SMAC_SIP] = { 844 .width = 6, 845 .count = 4 846 }, 847 }, 848 .target = S2, 849 .keys = vsc9953_vcap_is2_keys, 850 .actions = vsc9953_vcap_is2_actions, 851 }, 852 }; 853 854 #define VSC9953_INIT_TIMEOUT 50000 855 #define VSC9953_GCB_RST_SLEEP 100 856 #define VSC9953_SYS_RAMINIT_SLEEP 80 857 858 static int vsc9953_gcb_soft_rst_status(struct ocelot *ocelot) 859 { 860 int val; 861 862 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 863 864 return val; 865 } 866 867 static int vsc9953_sys_ram_init_status(struct ocelot *ocelot) 868 { 869 int val; 870 871 ocelot_field_read(ocelot, SYS_RESET_CFG_MEM_INIT, &val); 872 873 return val; 874 } 875 876 877 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 878 * MEM_INIT is in SYS:SYSTEM:RESET_CFG 879 * MEM_ENA is in SYS:SYSTEM:RESET_CFG 880 */ 881 static int vsc9953_reset(struct ocelot *ocelot) 882 { 883 int val, err; 884 885 /* soft-reset the switch core */ 886 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 887 888 err = readx_poll_timeout(vsc9953_gcb_soft_rst_status, ocelot, val, !val, 889 VSC9953_GCB_RST_SLEEP, VSC9953_INIT_TIMEOUT); 890 if (err) { 891 dev_err(ocelot->dev, "timeout: switch core reset\n"); 892 return err; 893 } 894 895 /* initialize switch mem ~40us */ 896 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_ENA, 1); 897 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_INIT, 1); 898 899 err = readx_poll_timeout(vsc9953_sys_ram_init_status, ocelot, val, !val, 900 VSC9953_SYS_RAMINIT_SLEEP, 901 VSC9953_INIT_TIMEOUT); 902 if (err) { 903 dev_err(ocelot->dev, "timeout: switch sram init\n"); 904 return err; 905 } 906 907 /* enable switch core */ 908 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 909 910 return 0; 911 } 912 913 static void vsc9953_phylink_validate(struct ocelot *ocelot, int port, 914 unsigned long *supported, 915 struct phylink_link_state *state) 916 { 917 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 918 919 phylink_set_port_modes(mask); 920 phylink_set(mask, Autoneg); 921 phylink_set(mask, Pause); 922 phylink_set(mask, Asym_Pause); 923 phylink_set(mask, 10baseT_Full); 924 phylink_set(mask, 10baseT_Half); 925 phylink_set(mask, 100baseT_Full); 926 phylink_set(mask, 100baseT_Half); 927 phylink_set(mask, 1000baseT_Full); 928 phylink_set(mask, 1000baseX_Full); 929 930 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) { 931 phylink_set(mask, 2500baseT_Full); 932 phylink_set(mask, 2500baseX_Full); 933 } 934 935 linkmode_and(supported, supported, mask); 936 linkmode_and(state->advertising, state->advertising, mask); 937 } 938 939 /* Watermark encode 940 * Bit 9: Unit; 0:1, 1:16 941 * Bit 8-0: Value to be multiplied with unit 942 */ 943 static u16 vsc9953_wm_enc(u16 value) 944 { 945 WARN_ON(value >= 16 * BIT(9)); 946 947 if (value >= BIT(9)) 948 return BIT(9) | (value / 16); 949 950 return value; 951 } 952 953 static u16 vsc9953_wm_dec(u16 wm) 954 { 955 WARN_ON(wm & ~GENMASK(9, 0)); 956 957 if (wm & BIT(9)) 958 return (wm & GENMASK(8, 0)) * 16; 959 960 return wm; 961 } 962 963 static void vsc9953_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 964 { 965 *inuse = (val & GENMASK(25, 13)) >> 13; 966 *maxuse = val & GENMASK(12, 0); 967 } 968 969 static const struct ocelot_ops vsc9953_ops = { 970 .reset = vsc9953_reset, 971 .wm_enc = vsc9953_wm_enc, 972 .wm_dec = vsc9953_wm_dec, 973 .wm_stat = vsc9953_wm_stat, 974 .port_to_netdev = felix_port_to_netdev, 975 .netdev_to_port = felix_netdev_to_port, 976 }; 977 978 static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot) 979 { 980 struct felix *felix = ocelot_to_felix(ocelot); 981 struct device *dev = ocelot->dev; 982 struct mii_bus *bus; 983 int port; 984 int rc; 985 986 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 987 sizeof(struct phylink_pcs *), 988 GFP_KERNEL); 989 if (!felix->pcs) { 990 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 991 return -ENOMEM; 992 } 993 994 rc = mscc_miim_setup(dev, &bus, "VSC9953 internal MDIO bus", 995 ocelot->targets[GCB], 996 ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK]); 997 998 if (rc) { 999 dev_err(dev, "failed to setup MDIO bus\n"); 1000 return rc; 1001 } 1002 1003 /* Needed in order to initialize the bus mutex lock */ 1004 rc = devm_of_mdiobus_register(dev, bus, NULL); 1005 if (rc < 0) { 1006 dev_err(dev, "failed to register MDIO bus\n"); 1007 return rc; 1008 } 1009 1010 felix->imdio = bus; 1011 1012 for (port = 0; port < felix->info->num_ports; port++) { 1013 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1014 struct phylink_pcs *phylink_pcs; 1015 struct mdio_device *mdio_device; 1016 int addr = port + 4; 1017 1018 if (dsa_is_unused_port(felix->ds, port)) 1019 continue; 1020 1021 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1022 continue; 1023 1024 mdio_device = mdio_device_create(felix->imdio, addr); 1025 if (IS_ERR(mdio_device)) 1026 continue; 1027 1028 phylink_pcs = lynx_pcs_create(mdio_device); 1029 if (!phylink_pcs) { 1030 mdio_device_free(mdio_device); 1031 continue; 1032 } 1033 1034 felix->pcs[port] = phylink_pcs; 1035 1036 dev_info(dev, "Found PCS at internal MDIO address %d\n", addr); 1037 } 1038 1039 return 0; 1040 } 1041 1042 static void vsc9953_mdio_bus_free(struct ocelot *ocelot) 1043 { 1044 struct felix *felix = ocelot_to_felix(ocelot); 1045 int port; 1046 1047 for (port = 0; port < ocelot->num_phys_ports; port++) { 1048 struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1049 struct mdio_device *mdio_device; 1050 1051 if (!phylink_pcs) 1052 continue; 1053 1054 mdio_device = lynx_get_mdio_device(phylink_pcs); 1055 mdio_device_free(mdio_device); 1056 lynx_pcs_destroy(phylink_pcs); 1057 } 1058 1059 /* mdiobus_unregister and mdiobus_free handled by devres */ 1060 } 1061 1062 static const struct felix_info seville_info_vsc9953 = { 1063 .target_io_res = vsc9953_target_io_res, 1064 .port_io_res = vsc9953_port_io_res, 1065 .regfields = vsc9953_regfields, 1066 .map = vsc9953_regmap, 1067 .ops = &vsc9953_ops, 1068 .stats_layout = vsc9953_stats_layout, 1069 .vcap = vsc9953_vcap_props, 1070 .vcap_pol_base = VSC9953_VCAP_POLICER_BASE, 1071 .vcap_pol_max = VSC9953_VCAP_POLICER_MAX, 1072 .vcap_pol_base2 = VSC9953_VCAP_POLICER_BASE2, 1073 .vcap_pol_max2 = VSC9953_VCAP_POLICER_MAX2, 1074 .num_mact_rows = 2048, 1075 .num_ports = VSC9953_NUM_PORTS, 1076 .num_tx_queues = OCELOT_NUM_TC, 1077 .mdio_bus_alloc = vsc9953_mdio_bus_alloc, 1078 .mdio_bus_free = vsc9953_mdio_bus_free, 1079 .phylink_validate = vsc9953_phylink_validate, 1080 .port_modes = vsc9953_port_modes, 1081 .init_regmap = ocelot_regmap_init, 1082 }; 1083 1084 static int seville_probe(struct platform_device *pdev) 1085 { 1086 struct dsa_switch *ds; 1087 struct ocelot *ocelot; 1088 struct resource *res; 1089 struct felix *felix; 1090 int err; 1091 1092 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 1093 if (!felix) { 1094 err = -ENOMEM; 1095 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 1096 goto err_alloc_felix; 1097 } 1098 1099 platform_set_drvdata(pdev, felix); 1100 1101 ocelot = &felix->ocelot; 1102 ocelot->dev = &pdev->dev; 1103 ocelot->num_flooding_pgids = 1; 1104 felix->info = &seville_info_vsc9953; 1105 1106 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1107 if (!res) { 1108 err = -EINVAL; 1109 dev_err(&pdev->dev, "Invalid resource\n"); 1110 goto err_alloc_felix; 1111 } 1112 felix->switch_base = res->start; 1113 1114 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 1115 if (!ds) { 1116 err = -ENOMEM; 1117 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 1118 goto err_alloc_ds; 1119 } 1120 1121 ds->dev = &pdev->dev; 1122 ds->num_ports = felix->info->num_ports; 1123 ds->ops = &felix_switch_ops; 1124 ds->priv = ocelot; 1125 felix->ds = ds; 1126 felix->tag_proto = DSA_TAG_PROTO_SEVILLE; 1127 1128 err = dsa_register_switch(ds); 1129 if (err) { 1130 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err); 1131 goto err_register_ds; 1132 } 1133 1134 return 0; 1135 1136 err_register_ds: 1137 kfree(ds); 1138 err_alloc_ds: 1139 err_alloc_felix: 1140 kfree(felix); 1141 return err; 1142 } 1143 1144 static int seville_remove(struct platform_device *pdev) 1145 { 1146 struct felix *felix = platform_get_drvdata(pdev); 1147 1148 if (!felix) 1149 return 0; 1150 1151 dsa_unregister_switch(felix->ds); 1152 1153 kfree(felix->ds); 1154 kfree(felix); 1155 1156 platform_set_drvdata(pdev, NULL); 1157 1158 return 0; 1159 } 1160 1161 static void seville_shutdown(struct platform_device *pdev) 1162 { 1163 struct felix *felix = platform_get_drvdata(pdev); 1164 1165 if (!felix) 1166 return; 1167 1168 dsa_switch_shutdown(felix->ds); 1169 1170 platform_set_drvdata(pdev, NULL); 1171 } 1172 1173 static const struct of_device_id seville_of_match[] = { 1174 { .compatible = "mscc,vsc9953-switch" }, 1175 { }, 1176 }; 1177 MODULE_DEVICE_TABLE(of, seville_of_match); 1178 1179 static struct platform_driver seville_vsc9953_driver = { 1180 .probe = seville_probe, 1181 .remove = seville_remove, 1182 .shutdown = seville_shutdown, 1183 .driver = { 1184 .name = "mscc_seville", 1185 .of_match_table = of_match_ptr(seville_of_match), 1186 }, 1187 }; 1188 module_platform_driver(seville_vsc9953_driver); 1189 1190 MODULE_DESCRIPTION("Seville Switch driver"); 1191 MODULE_LICENSE("GPL v2"); 1192