1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright 2017 Microsemi Corporation 3 * Copyright 2018-2019 NXP 4 */ 5 #include <linux/fsl/enetc_mdio.h> 6 #include <soc/mscc/ocelot_qsys.h> 7 #include <soc/mscc/ocelot_vcap.h> 8 #include <soc/mscc/ocelot_ana.h> 9 #include <soc/mscc/ocelot_dev.h> 10 #include <soc/mscc/ocelot_ptp.h> 11 #include <soc/mscc/ocelot_sys.h> 12 #include <net/tc_act/tc_gate.h> 13 #include <soc/mscc/ocelot.h> 14 #include <linux/dsa/ocelot.h> 15 #include <linux/pcs-lynx.h> 16 #include <net/pkt_sched.h> 17 #include <linux/iopoll.h> 18 #include <linux/mdio.h> 19 #include <linux/pci.h> 20 #include <linux/time.h> 21 #include "felix.h" 22 23 #define VSC9959_NUM_PORTS 6 24 25 #define VSC9959_TAS_GCL_ENTRY_MAX 63 26 #define VSC9959_TAS_MIN_GATE_LEN_NS 33 27 #define VSC9959_VCAP_POLICER_BASE 63 28 #define VSC9959_VCAP_POLICER_MAX 383 29 #define VSC9959_SWITCH_PCI_BAR 4 30 #define VSC9959_IMDIO_PCI_BAR 0 31 32 #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ 33 OCELOT_PORT_MODE_QSGMII | \ 34 OCELOT_PORT_MODE_1000BASEX | \ 35 OCELOT_PORT_MODE_2500BASEX | \ 36 OCELOT_PORT_MODE_USXGMII) 37 38 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { 39 VSC9959_PORT_MODE_SERDES, 40 VSC9959_PORT_MODE_SERDES, 41 VSC9959_PORT_MODE_SERDES, 42 VSC9959_PORT_MODE_SERDES, 43 OCELOT_PORT_MODE_INTERNAL, 44 OCELOT_PORT_MODE_INTERNAL, 45 }; 46 47 static const u32 vsc9959_ana_regmap[] = { 48 REG(ANA_ADVLEARN, 0x0089a0), 49 REG(ANA_VLANMASK, 0x0089a4), 50 REG_RESERVED(ANA_PORT_B_DOMAIN), 51 REG(ANA_ANAGEFIL, 0x0089ac), 52 REG(ANA_ANEVENTS, 0x0089b0), 53 REG(ANA_STORMLIMIT_BURST, 0x0089b4), 54 REG(ANA_STORMLIMIT_CFG, 0x0089b8), 55 REG(ANA_ISOLATED_PORTS, 0x0089c8), 56 REG(ANA_COMMUNITY_PORTS, 0x0089cc), 57 REG(ANA_AUTOAGE, 0x0089d0), 58 REG(ANA_MACTOPTIONS, 0x0089d4), 59 REG(ANA_LEARNDISC, 0x0089d8), 60 REG(ANA_AGENCTRL, 0x0089dc), 61 REG(ANA_MIRRORPORTS, 0x0089e0), 62 REG(ANA_EMIRRORPORTS, 0x0089e4), 63 REG(ANA_FLOODING, 0x0089e8), 64 REG(ANA_FLOODING_IPMC, 0x008a08), 65 REG(ANA_SFLOW_CFG, 0x008a0c), 66 REG(ANA_PORT_MODE, 0x008a28), 67 REG(ANA_CUT_THRU_CFG, 0x008a48), 68 REG(ANA_PGID_PGID, 0x008400), 69 REG(ANA_TABLES_ANMOVED, 0x007f1c), 70 REG(ANA_TABLES_MACHDATA, 0x007f20), 71 REG(ANA_TABLES_MACLDATA, 0x007f24), 72 REG(ANA_TABLES_STREAMDATA, 0x007f28), 73 REG(ANA_TABLES_MACACCESS, 0x007f2c), 74 REG(ANA_TABLES_MACTINDX, 0x007f30), 75 REG(ANA_TABLES_VLANACCESS, 0x007f34), 76 REG(ANA_TABLES_VLANTIDX, 0x007f38), 77 REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 78 REG(ANA_TABLES_ISDXTIDX, 0x007f40), 79 REG(ANA_TABLES_ENTRYLIM, 0x007f00), 80 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 81 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 82 REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 83 REG(ANA_TABLES_STREAMTIDX, 0x007f50), 84 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 85 REG(ANA_TABLES_SEQ_MASK, 0x007f58), 86 REG(ANA_TABLES_SFID_MASK, 0x007f5c), 87 REG(ANA_TABLES_SFIDACCESS, 0x007f60), 88 REG(ANA_TABLES_SFIDTIDX, 0x007f64), 89 REG(ANA_MSTI_STATE, 0x008600), 90 REG(ANA_OAM_UPM_LM_CNT, 0x008000), 91 REG(ANA_SG_ACCESS_CTRL, 0x008a64), 92 REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 93 REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 94 REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 95 REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 96 REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 97 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 98 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 99 REG(ANA_SG_STATUS_REG_1, 0x008980), 100 REG(ANA_SG_STATUS_REG_2, 0x008984), 101 REG(ANA_SG_STATUS_REG_3, 0x008988), 102 REG(ANA_PORT_VLAN_CFG, 0x007800), 103 REG(ANA_PORT_DROP_CFG, 0x007804), 104 REG(ANA_PORT_QOS_CFG, 0x007808), 105 REG(ANA_PORT_VCAP_CFG, 0x00780c), 106 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 107 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 108 REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 109 REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 110 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 111 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 112 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 113 REG(ANA_PORT_PORT_CFG, 0x007870), 114 REG(ANA_PORT_POL_CFG, 0x007874), 115 REG(ANA_PORT_PTP_CFG, 0x007878), 116 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 117 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 118 REG(ANA_PORT_SFID_CFG, 0x007884), 119 REG(ANA_PFC_PFC_CFG, 0x008800), 120 REG_RESERVED(ANA_PFC_PFC_TIMER), 121 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 122 REG_RESERVED(ANA_IPT_IPT), 123 REG_RESERVED(ANA_PPT_PPT), 124 REG_RESERVED(ANA_FID_MAP_FID_MAP), 125 REG(ANA_AGGR_CFG, 0x008a68), 126 REG(ANA_CPUQ_CFG, 0x008a6c), 127 REG_RESERVED(ANA_CPUQ_CFG2), 128 REG(ANA_CPUQ_8021_CFG, 0x008a74), 129 REG(ANA_DSCP_CFG, 0x008ab4), 130 REG(ANA_DSCP_REWR_CFG, 0x008bb4), 131 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 132 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 133 REG_RESERVED(ANA_VRAP_CFG), 134 REG_RESERVED(ANA_VRAP_HDR_DATA), 135 REG_RESERVED(ANA_VRAP_HDR_MASK), 136 REG(ANA_DISCARD_CFG, 0x008c40), 137 REG(ANA_FID_CFG, 0x008c44), 138 REG(ANA_POL_PIR_CFG, 0x004000), 139 REG(ANA_POL_CIR_CFG, 0x004004), 140 REG(ANA_POL_MODE_CFG, 0x004008), 141 REG(ANA_POL_PIR_STATE, 0x00400c), 142 REG(ANA_POL_CIR_STATE, 0x004010), 143 REG_RESERVED(ANA_POL_STATE), 144 REG(ANA_POL_FLOWC, 0x008c48), 145 REG(ANA_POL_HYST, 0x008cb4), 146 REG_RESERVED(ANA_POL_MISC_CFG), 147 }; 148 149 static const u32 vsc9959_qs_regmap[] = { 150 REG(QS_XTR_GRP_CFG, 0x000000), 151 REG(QS_XTR_RD, 0x000008), 152 REG(QS_XTR_FRM_PRUNING, 0x000010), 153 REG(QS_XTR_FLUSH, 0x000018), 154 REG(QS_XTR_DATA_PRESENT, 0x00001c), 155 REG(QS_XTR_CFG, 0x000020), 156 REG(QS_INJ_GRP_CFG, 0x000024), 157 REG(QS_INJ_WR, 0x00002c), 158 REG(QS_INJ_CTRL, 0x000034), 159 REG(QS_INJ_STATUS, 0x00003c), 160 REG(QS_INJ_ERR, 0x000040), 161 REG_RESERVED(QS_INH_DBG), 162 }; 163 164 static const u32 vsc9959_vcap_regmap[] = { 165 /* VCAP_CORE_CFG */ 166 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 167 REG(VCAP_CORE_MV_CFG, 0x000004), 168 /* VCAP_CORE_CACHE */ 169 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 170 REG(VCAP_CACHE_MASK_DAT, 0x000108), 171 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 172 REG(VCAP_CACHE_CNT_DAT, 0x000308), 173 REG(VCAP_CACHE_TG_DAT, 0x000388), 174 /* VCAP_CONST */ 175 REG(VCAP_CONST_VCAP_VER, 0x000398), 176 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 177 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 178 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 179 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 180 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 181 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 182 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 183 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 184 REG(VCAP_CONST_IF_CNT, 0x0003bc), 185 }; 186 187 static const u32 vsc9959_qsys_regmap[] = { 188 REG(QSYS_PORT_MODE, 0x00f460), 189 REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 190 REG(QSYS_STAT_CNT_CFG, 0x00f49c), 191 REG(QSYS_EEE_CFG, 0x00f4a0), 192 REG(QSYS_EEE_THRES, 0x00f4b8), 193 REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 194 REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 195 REG(QSYS_SW_STATUS, 0x00f4c4), 196 REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 197 REG_RESERVED(QSYS_PAD_CFG), 198 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 199 REG_RESERVED(QSYS_QMAP), 200 REG_RESERVED(QSYS_ISDX_SGRP), 201 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 202 REG(QSYS_TFRM_MISC, 0x00f50c), 203 REG(QSYS_TFRM_PORT_DLY, 0x00f510), 204 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 205 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 206 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 207 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 208 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 209 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 210 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 211 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 212 REG(QSYS_RED_PROFILE, 0x00f534), 213 REG(QSYS_RES_QOS_MODE, 0x00f574), 214 REG(QSYS_RES_CFG, 0x00c000), 215 REG(QSYS_RES_STAT, 0x00c004), 216 REG(QSYS_EGR_DROP_MODE, 0x00f578), 217 REG(QSYS_EQ_CTRL, 0x00f57c), 218 REG_RESERVED(QSYS_EVENTS_CORE), 219 REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 220 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 221 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 222 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 223 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 224 REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 225 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 226 REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 227 REG(QSYS_PREEMPTION_CFG, 0x00f664), 228 REG(QSYS_CIR_CFG, 0x000000), 229 REG(QSYS_EIR_CFG, 0x000004), 230 REG(QSYS_SE_CFG, 0x000008), 231 REG(QSYS_SE_DWRR_CFG, 0x00000c), 232 REG_RESERVED(QSYS_SE_CONNECT), 233 REG(QSYS_SE_DLB_SENSE, 0x000040), 234 REG(QSYS_CIR_STATE, 0x000044), 235 REG(QSYS_EIR_STATE, 0x000048), 236 REG_RESERVED(QSYS_SE_STATE), 237 REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 238 REG(QSYS_TAG_CONFIG, 0x00f680), 239 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 240 REG(QSYS_PORT_MAX_SDU, 0x00f69c), 241 REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 242 REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 243 REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 244 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 245 REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 246 REG(QSYS_GCL_CFG_REG_1, 0x00f454), 247 REG(QSYS_GCL_CFG_REG_2, 0x00f458), 248 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 249 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 250 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 251 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 252 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 253 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 254 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 255 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 256 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 257 REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 258 REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 259 }; 260 261 static const u32 vsc9959_rew_regmap[] = { 262 REG(REW_PORT_VLAN_CFG, 0x000000), 263 REG(REW_TAG_CFG, 0x000004), 264 REG(REW_PORT_CFG, 0x000008), 265 REG(REW_DSCP_CFG, 0x00000c), 266 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 267 REG(REW_PTP_CFG, 0x000050), 268 REG(REW_PTP_DLY1_CFG, 0x000054), 269 REG(REW_RED_TAG_CFG, 0x000058), 270 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 271 REG(REW_DSCP_REMAP_CFG, 0x000510), 272 REG_RESERVED(REW_STAT_CFG), 273 REG_RESERVED(REW_REW_STICKY), 274 REG_RESERVED(REW_PPT), 275 }; 276 277 static const u32 vsc9959_sys_regmap[] = { 278 REG(SYS_COUNT_RX_OCTETS, 0x000000), 279 REG(SYS_COUNT_RX_UNICAST, 0x000004), 280 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 281 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 282 REG(SYS_COUNT_RX_SHORTS, 0x000010), 283 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 284 REG(SYS_COUNT_RX_JABBERS, 0x000018), 285 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 286 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 287 REG(SYS_COUNT_RX_64, 0x000024), 288 REG(SYS_COUNT_RX_65_127, 0x000028), 289 REG(SYS_COUNT_RX_128_255, 0x00002c), 290 REG(SYS_COUNT_RX_256_511, 0x000030), 291 REG(SYS_COUNT_RX_512_1023, 0x000034), 292 REG(SYS_COUNT_RX_1024_1526, 0x000038), 293 REG(SYS_COUNT_RX_1527_MAX, 0x00003c), 294 REG(SYS_COUNT_RX_PAUSE, 0x000040), 295 REG(SYS_COUNT_RX_CONTROL, 0x000044), 296 REG(SYS_COUNT_RX_LONGS, 0x000048), 297 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), 298 REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), 299 REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), 300 REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), 301 REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), 302 REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), 303 REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), 304 REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), 305 REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), 306 REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), 307 REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), 308 REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), 309 REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), 310 REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), 311 REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), 312 REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), 313 REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), 314 REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), 315 REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), 316 REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), 317 REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), 318 REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), 319 REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), 320 REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), 321 REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), 322 REG(SYS_COUNT_RX_ASSEMBLY_ERRS, 0x0000b0), 323 REG(SYS_COUNT_RX_SMD_ERRS, 0x0000b4), 324 REG(SYS_COUNT_RX_ASSEMBLY_OK, 0x0000b8), 325 REG(SYS_COUNT_RX_MERGE_FRAGMENTS, 0x0000bc), 326 REG(SYS_COUNT_RX_PMAC_OCTETS, 0x0000c0), 327 REG(SYS_COUNT_RX_PMAC_UNICAST, 0x0000c4), 328 REG(SYS_COUNT_RX_PMAC_MULTICAST, 0x0000c8), 329 REG(SYS_COUNT_RX_PMAC_BROADCAST, 0x0000cc), 330 REG(SYS_COUNT_RX_PMAC_SHORTS, 0x0000d0), 331 REG(SYS_COUNT_RX_PMAC_FRAGMENTS, 0x0000d4), 332 REG(SYS_COUNT_RX_PMAC_JABBERS, 0x0000d8), 333 REG(SYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS, 0x0000dc), 334 REG(SYS_COUNT_RX_PMAC_SYM_ERRS, 0x0000e0), 335 REG(SYS_COUNT_RX_PMAC_64, 0x0000e4), 336 REG(SYS_COUNT_RX_PMAC_65_127, 0x0000e8), 337 REG(SYS_COUNT_RX_PMAC_128_255, 0x0000ec), 338 REG(SYS_COUNT_RX_PMAC_256_511, 0x0000f0), 339 REG(SYS_COUNT_RX_PMAC_512_1023, 0x0000f4), 340 REG(SYS_COUNT_RX_PMAC_1024_1526, 0x0000f8), 341 REG(SYS_COUNT_RX_PMAC_1527_MAX, 0x0000fc), 342 REG(SYS_COUNT_RX_PMAC_PAUSE, 0x000100), 343 REG(SYS_COUNT_RX_PMAC_CONTROL, 0x000104), 344 REG(SYS_COUNT_RX_PMAC_LONGS, 0x000108), 345 REG(SYS_COUNT_TX_OCTETS, 0x000200), 346 REG(SYS_COUNT_TX_UNICAST, 0x000204), 347 REG(SYS_COUNT_TX_MULTICAST, 0x000208), 348 REG(SYS_COUNT_TX_BROADCAST, 0x00020c), 349 REG(SYS_COUNT_TX_COLLISION, 0x000210), 350 REG(SYS_COUNT_TX_DROPS, 0x000214), 351 REG(SYS_COUNT_TX_PAUSE, 0x000218), 352 REG(SYS_COUNT_TX_64, 0x00021c), 353 REG(SYS_COUNT_TX_65_127, 0x000220), 354 REG(SYS_COUNT_TX_128_255, 0x000224), 355 REG(SYS_COUNT_TX_256_511, 0x000228), 356 REG(SYS_COUNT_TX_512_1023, 0x00022c), 357 REG(SYS_COUNT_TX_1024_1526, 0x000230), 358 REG(SYS_COUNT_TX_1527_MAX, 0x000234), 359 REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238), 360 REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c), 361 REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240), 362 REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244), 363 REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248), 364 REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c), 365 REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250), 366 REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254), 367 REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258), 368 REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c), 369 REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260), 370 REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264), 371 REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268), 372 REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c), 373 REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270), 374 REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274), 375 REG(SYS_COUNT_TX_AGED, 0x000278), 376 REG(SYS_COUNT_TX_MM_HOLD, 0x00027c), 377 REG(SYS_COUNT_TX_MERGE_FRAGMENTS, 0x000280), 378 REG(SYS_COUNT_TX_PMAC_OCTETS, 0x000284), 379 REG(SYS_COUNT_TX_PMAC_UNICAST, 0x000288), 380 REG(SYS_COUNT_TX_PMAC_MULTICAST, 0x00028c), 381 REG(SYS_COUNT_TX_PMAC_BROADCAST, 0x000290), 382 REG(SYS_COUNT_TX_PMAC_PAUSE, 0x000294), 383 REG(SYS_COUNT_TX_PMAC_64, 0x000298), 384 REG(SYS_COUNT_TX_PMAC_65_127, 0x00029c), 385 REG(SYS_COUNT_TX_PMAC_128_255, 0x0002a0), 386 REG(SYS_COUNT_TX_PMAC_256_511, 0x0002a4), 387 REG(SYS_COUNT_TX_PMAC_512_1023, 0x0002a8), 388 REG(SYS_COUNT_TX_PMAC_1024_1526, 0x0002ac), 389 REG(SYS_COUNT_TX_PMAC_1527_MAX, 0x0002b0), 390 REG(SYS_COUNT_DROP_LOCAL, 0x000400), 391 REG(SYS_COUNT_DROP_TAIL, 0x000404), 392 REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408), 393 REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c), 394 REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410), 395 REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414), 396 REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418), 397 REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c), 398 REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420), 399 REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424), 400 REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428), 401 REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c), 402 REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430), 403 REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434), 404 REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438), 405 REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c), 406 REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440), 407 REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444), 408 REG(SYS_COUNT_SF_MATCHING_FRAMES, 0x000800), 409 REG(SYS_COUNT_SF_NOT_PASSING_FRAMES, 0x000804), 410 REG(SYS_COUNT_SF_NOT_PASSING_SDU, 0x000808), 411 REG(SYS_COUNT_SF_RED_FRAMES, 0x00080c), 412 REG(SYS_RESET_CFG, 0x000e00), 413 REG(SYS_SR_ETYPE_CFG, 0x000e04), 414 REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 415 REG(SYS_PORT_MODE, 0x000e0c), 416 REG(SYS_FRONT_PORT_MODE, 0x000e2c), 417 REG(SYS_FRM_AGING, 0x000e44), 418 REG(SYS_STAT_CFG, 0x000e48), 419 REG(SYS_SW_STATUS, 0x000e4c), 420 REG_RESERVED(SYS_MISC_CFG), 421 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 422 REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 423 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 424 REG(SYS_PAUSE_CFG, 0x000ea0), 425 REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 426 REG(SYS_ATOP, 0x000ec0), 427 REG(SYS_ATOP_TOT_CFG, 0x000edc), 428 REG(SYS_MAC_FC_CFG, 0x000ee0), 429 REG(SYS_MMGT, 0x000ef8), 430 REG_RESERVED(SYS_MMGT_FAST), 431 REG_RESERVED(SYS_EVENTS_DIF), 432 REG_RESERVED(SYS_EVENTS_CORE), 433 REG(SYS_PTP_STATUS, 0x000f14), 434 REG(SYS_PTP_TXSTAMP, 0x000f18), 435 REG(SYS_PTP_NXT, 0x000f1c), 436 REG(SYS_PTP_CFG, 0x000f20), 437 REG(SYS_RAM_INIT, 0x000f24), 438 REG_RESERVED(SYS_CM_ADDR), 439 REG_RESERVED(SYS_CM_DATA_WR), 440 REG_RESERVED(SYS_CM_DATA_RD), 441 REG_RESERVED(SYS_CM_OP), 442 REG_RESERVED(SYS_CM_DATA), 443 }; 444 445 static const u32 vsc9959_ptp_regmap[] = { 446 REG(PTP_PIN_CFG, 0x000000), 447 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 448 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 449 REG(PTP_PIN_TOD_NSEC, 0x00000c), 450 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 451 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 452 REG(PTP_CFG_MISC, 0x0000a0), 453 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 454 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 455 }; 456 457 static const u32 vsc9959_gcb_regmap[] = { 458 REG(GCB_SOFT_RST, 0x000004), 459 }; 460 461 static const u32 vsc9959_dev_gmii_regmap[] = { 462 REG(DEV_CLOCK_CFG, 0x0), 463 REG(DEV_PORT_MISC, 0x4), 464 REG(DEV_EVENTS, 0x8), 465 REG(DEV_EEE_CFG, 0xc), 466 REG(DEV_RX_PATH_DELAY, 0x10), 467 REG(DEV_TX_PATH_DELAY, 0x14), 468 REG(DEV_PTP_PREDICT_CFG, 0x18), 469 REG(DEV_MAC_ENA_CFG, 0x1c), 470 REG(DEV_MAC_MODE_CFG, 0x20), 471 REG(DEV_MAC_MAXLEN_CFG, 0x24), 472 REG(DEV_MAC_TAGS_CFG, 0x28), 473 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 474 REG(DEV_MAC_IFG_CFG, 0x30), 475 REG(DEV_MAC_HDX_CFG, 0x34), 476 REG(DEV_MAC_DBG_CFG, 0x38), 477 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 478 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 479 REG(DEV_MAC_STICKY, 0x44), 480 REG(DEV_MM_ENABLE_CONFIG, 0x48), 481 REG(DEV_MM_VERIF_CONFIG, 0x4C), 482 REG(DEV_MM_STATUS, 0x50), 483 REG_RESERVED(PCS1G_CFG), 484 REG_RESERVED(PCS1G_MODE_CFG), 485 REG_RESERVED(PCS1G_SD_CFG), 486 REG_RESERVED(PCS1G_ANEG_CFG), 487 REG_RESERVED(PCS1G_ANEG_NP_CFG), 488 REG_RESERVED(PCS1G_LB_CFG), 489 REG_RESERVED(PCS1G_DBG_CFG), 490 REG_RESERVED(PCS1G_CDET_CFG), 491 REG_RESERVED(PCS1G_ANEG_STATUS), 492 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 493 REG_RESERVED(PCS1G_LINK_STATUS), 494 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 495 REG_RESERVED(PCS1G_STICKY), 496 REG_RESERVED(PCS1G_DEBUG_STATUS), 497 REG_RESERVED(PCS1G_LPI_CFG), 498 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 499 REG_RESERVED(PCS1G_LPI_STATUS), 500 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 501 REG_RESERVED(PCS1G_TSTPAT_STATUS), 502 REG_RESERVED(DEV_PCS_FX100_CFG), 503 REG_RESERVED(DEV_PCS_FX100_STATUS), 504 }; 505 506 static const u32 *vsc9959_regmap[TARGET_MAX] = { 507 [ANA] = vsc9959_ana_regmap, 508 [QS] = vsc9959_qs_regmap, 509 [QSYS] = vsc9959_qsys_regmap, 510 [REW] = vsc9959_rew_regmap, 511 [SYS] = vsc9959_sys_regmap, 512 [S0] = vsc9959_vcap_regmap, 513 [S1] = vsc9959_vcap_regmap, 514 [S2] = vsc9959_vcap_regmap, 515 [PTP] = vsc9959_ptp_regmap, 516 [GCB] = vsc9959_gcb_regmap, 517 [DEV_GMII] = vsc9959_dev_gmii_regmap, 518 }; 519 520 /* Addresses are relative to the PCI device's base address */ 521 static const struct resource vsc9959_resources[] = { 522 DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"), 523 DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"), 524 DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"), 525 DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"), 526 DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"), 527 DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"), 528 DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"), 529 DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"), 530 DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"), 531 DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"), 532 DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"), 533 DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"), 534 DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"), 535 DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"), 536 DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"), 537 DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"), 538 }; 539 540 static const char * const vsc9959_resource_names[TARGET_MAX] = { 541 [SYS] = "sys", 542 [REW] = "rew", 543 [S0] = "s0", 544 [S1] = "s1", 545 [S2] = "s2", 546 [GCB] = "devcpu_gcb", 547 [QS] = "qs", 548 [PTP] = "ptp", 549 [QSYS] = "qsys", 550 [ANA] = "ana", 551 }; 552 553 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 554 * SGMII/QSGMII MAC PCS can be found. 555 */ 556 static const struct resource vsc9959_imdio_res = 557 DEFINE_RES_MEM_NAMED(0x8030, 0x10, "imdio"); 558 559 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 560 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 561 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 562 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 563 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 564 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 565 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 566 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 567 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 568 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 569 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 570 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 571 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 572 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 573 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 574 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 575 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 576 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 577 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 578 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 579 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 580 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 581 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 582 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 583 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 584 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 585 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 586 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 587 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 588 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 589 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 590 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 591 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 592 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 593 /* Replicated per number of ports (7), register size 4 per port */ 594 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 595 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 596 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 597 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 598 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 599 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 600 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 601 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 602 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 603 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 604 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 605 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 606 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 607 }; 608 609 static const struct vcap_field vsc9959_vcap_es0_keys[] = { 610 [VCAP_ES0_EGR_PORT] = { 0, 3}, 611 [VCAP_ES0_IGR_PORT] = { 3, 3}, 612 [VCAP_ES0_RSV] = { 6, 2}, 613 [VCAP_ES0_L2_MC] = { 8, 1}, 614 [VCAP_ES0_L2_BC] = { 9, 1}, 615 [VCAP_ES0_VID] = { 10, 12}, 616 [VCAP_ES0_DP] = { 22, 1}, 617 [VCAP_ES0_PCP] = { 23, 3}, 618 }; 619 620 static const struct vcap_field vsc9959_vcap_es0_actions[] = { 621 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 622 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 623 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 624 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 625 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 626 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 627 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 628 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 629 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 630 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 631 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 632 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 633 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 634 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 635 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 636 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 637 [VCAP_ES0_ACT_RSV] = { 49, 23}, 638 [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 639 }; 640 641 static const struct vcap_field vsc9959_vcap_is1_keys[] = { 642 [VCAP_IS1_HK_TYPE] = { 0, 1}, 643 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 644 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 645 [VCAP_IS1_HK_RSV] = { 10, 9}, 646 [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 647 [VCAP_IS1_HK_L2_MC] = { 20, 1}, 648 [VCAP_IS1_HK_L2_BC] = { 21, 1}, 649 [VCAP_IS1_HK_IP_MC] = { 22, 1}, 650 [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 651 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 652 [VCAP_IS1_HK_TPID] = { 25, 1}, 653 [VCAP_IS1_HK_VID] = { 26, 12}, 654 [VCAP_IS1_HK_DEI] = { 38, 1}, 655 [VCAP_IS1_HK_PCP] = { 39, 3}, 656 /* Specific Fields for IS1 Half Key S1_NORMAL */ 657 [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 658 [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 659 [VCAP_IS1_HK_ETYPE] = { 91, 16}, 660 [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 661 [VCAP_IS1_HK_IP4] = {108, 1}, 662 /* Layer-3 Information */ 663 [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 664 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 665 [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 666 [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 667 [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 668 /* Layer-4 Information */ 669 [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 670 [VCAP_IS1_HK_TCP] = {151, 1}, 671 [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 672 [VCAP_IS1_HK_L4_RNG] = {168, 8}, 673 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 674 [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 675 [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 676 [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 677 [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 678 [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 679 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 680 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 681 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 682 [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 683 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 684 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 685 [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 686 [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 687 [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 688 [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 689 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 690 }; 691 692 static const struct vcap_field vsc9959_vcap_is1_actions[] = { 693 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 694 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 695 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 696 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 697 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 698 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 699 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 700 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 701 [VCAP_IS1_ACT_RSV] = { 29, 9}, 702 /* The fields below are incorrectly shifted by 2 in the manual */ 703 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 704 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 705 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 706 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 707 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 708 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 709 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 710 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 711 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 712 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 713 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 714 }; 715 716 static struct vcap_field vsc9959_vcap_is2_keys[] = { 717 /* Common: 41 bits */ 718 [VCAP_IS2_TYPE] = { 0, 4}, 719 [VCAP_IS2_HK_FIRST] = { 4, 1}, 720 [VCAP_IS2_HK_PAG] = { 5, 8}, 721 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 722 [VCAP_IS2_HK_RSV2] = { 20, 1}, 723 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 724 [VCAP_IS2_HK_L2_MC] = { 22, 1}, 725 [VCAP_IS2_HK_L2_BC] = { 23, 1}, 726 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 727 [VCAP_IS2_HK_VID] = { 25, 12}, 728 [VCAP_IS2_HK_DEI] = { 37, 1}, 729 [VCAP_IS2_HK_PCP] = { 38, 3}, 730 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 731 [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 732 [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 733 /* MAC_ETYPE (TYPE=000) */ 734 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 735 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 736 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 737 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 738 /* MAC_LLC (TYPE=001) */ 739 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 740 /* MAC_SNAP (TYPE=010) */ 741 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 742 /* MAC_ARP (TYPE=011) */ 743 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 744 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 745 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 746 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 747 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 748 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 749 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 750 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 751 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 752 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 753 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 754 /* IP4_TCP_UDP / IP4_OTHER common */ 755 [VCAP_IS2_HK_IP4] = { 41, 1}, 756 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 757 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 758 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 759 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 760 [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 761 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 762 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 763 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 764 /* IP4_TCP_UDP (TYPE=100) */ 765 [VCAP_IS2_HK_TCP] = {119, 1}, 766 [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 767 [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 768 [VCAP_IS2_HK_L4_RNG] = {152, 8}, 769 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 770 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 771 [VCAP_IS2_HK_L4_FIN] = {162, 1}, 772 [VCAP_IS2_HK_L4_SYN] = {163, 1}, 773 [VCAP_IS2_HK_L4_RST] = {164, 1}, 774 [VCAP_IS2_HK_L4_PSH] = {165, 1}, 775 [VCAP_IS2_HK_L4_ACK] = {166, 1}, 776 [VCAP_IS2_HK_L4_URG] = {167, 1}, 777 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 778 [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 779 /* IP4_OTHER (TYPE=101) */ 780 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 781 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 782 /* IP6_STD (TYPE=110) */ 783 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 784 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 785 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 786 /* OAM (TYPE=111) */ 787 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 788 [VCAP_IS2_HK_OAM_VER] = {144, 5}, 789 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 790 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 791 [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 792 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 793 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 794 }; 795 796 static struct vcap_field vsc9959_vcap_is2_actions[] = { 797 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 798 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 799 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 800 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 801 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 802 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 803 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 804 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 805 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 806 [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 807 [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 808 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 809 [VCAP_IS2_ACT_RSV] = { 36, 2}, 810 [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 811 [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 812 }; 813 814 static struct vcap_props vsc9959_vcap_props[] = { 815 [VCAP_ES0] = { 816 .action_type_width = 0, 817 .action_table = { 818 [ES0_ACTION_TYPE_NORMAL] = { 819 .width = 72, /* HIT_STICKY not included */ 820 .count = 1, 821 }, 822 }, 823 .target = S0, 824 .keys = vsc9959_vcap_es0_keys, 825 .actions = vsc9959_vcap_es0_actions, 826 }, 827 [VCAP_IS1] = { 828 .action_type_width = 0, 829 .action_table = { 830 [IS1_ACTION_TYPE_NORMAL] = { 831 .width = 78, /* HIT_STICKY not included */ 832 .count = 4, 833 }, 834 }, 835 .target = S1, 836 .keys = vsc9959_vcap_is1_keys, 837 .actions = vsc9959_vcap_is1_actions, 838 }, 839 [VCAP_IS2] = { 840 .action_type_width = 1, 841 .action_table = { 842 [IS2_ACTION_TYPE_NORMAL] = { 843 .width = 44, 844 .count = 2 845 }, 846 [IS2_ACTION_TYPE_SMAC_SIP] = { 847 .width = 6, 848 .count = 4 849 }, 850 }, 851 .target = S2, 852 .keys = vsc9959_vcap_is2_keys, 853 .actions = vsc9959_vcap_is2_actions, 854 }, 855 }; 856 857 static const struct ptp_clock_info vsc9959_ptp_caps = { 858 .owner = THIS_MODULE, 859 .name = "felix ptp", 860 .max_adj = 0x7fffffff, 861 .n_alarm = 0, 862 .n_ext_ts = 0, 863 .n_per_out = OCELOT_PTP_PINS_NUM, 864 .n_pins = OCELOT_PTP_PINS_NUM, 865 .pps = 0, 866 .gettime64 = ocelot_ptp_gettime64, 867 .settime64 = ocelot_ptp_settime64, 868 .adjtime = ocelot_ptp_adjtime, 869 .adjfine = ocelot_ptp_adjfine, 870 .verify = ocelot_ptp_verify, 871 .enable = ocelot_ptp_enable, 872 }; 873 874 #define VSC9959_INIT_TIMEOUT 50000 875 #define VSC9959_GCB_RST_SLEEP 100 876 #define VSC9959_SYS_RAMINIT_SLEEP 80 877 878 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 879 { 880 int val; 881 882 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 883 884 return val; 885 } 886 887 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 888 { 889 return ocelot_read(ocelot, SYS_RAM_INIT); 890 } 891 892 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 893 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 894 */ 895 static int vsc9959_reset(struct ocelot *ocelot) 896 { 897 int val, err; 898 899 /* soft-reset the switch core */ 900 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 901 902 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 903 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 904 if (err) { 905 dev_err(ocelot->dev, "timeout: switch core reset\n"); 906 return err; 907 } 908 909 /* initialize switch mem ~40us */ 910 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 911 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 912 VSC9959_SYS_RAMINIT_SLEEP, 913 VSC9959_INIT_TIMEOUT); 914 if (err) { 915 dev_err(ocelot->dev, "timeout: switch sram init\n"); 916 return err; 917 } 918 919 /* enable switch core */ 920 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 921 922 return 0; 923 } 924 925 /* Watermark encode 926 * Bit 8: Unit; 0:1, 1:16 927 * Bit 7-0: Value to be multiplied with unit 928 */ 929 static u16 vsc9959_wm_enc(u16 value) 930 { 931 WARN_ON(value >= 16 * BIT(8)); 932 933 if (value >= BIT(8)) 934 return BIT(8) | (value / 16); 935 936 return value; 937 } 938 939 static u16 vsc9959_wm_dec(u16 wm) 940 { 941 WARN_ON(wm & ~GENMASK(8, 0)); 942 943 if (wm & BIT(8)) 944 return (wm & GENMASK(7, 0)) * 16; 945 946 return wm; 947 } 948 949 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 950 { 951 *inuse = (val & GENMASK(23, 12)) >> 12; 952 *maxuse = val & GENMASK(11, 0); 953 } 954 955 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 956 { 957 struct pci_dev *pdev = to_pci_dev(ocelot->dev); 958 struct felix *felix = ocelot_to_felix(ocelot); 959 struct enetc_mdio_priv *mdio_priv; 960 struct device *dev = ocelot->dev; 961 resource_size_t imdio_base; 962 void __iomem *imdio_regs; 963 struct resource res; 964 struct enetc_hw *hw; 965 struct mii_bus *bus; 966 int port; 967 int rc; 968 969 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 970 sizeof(struct phylink_pcs *), 971 GFP_KERNEL); 972 if (!felix->pcs) { 973 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 974 return -ENOMEM; 975 } 976 977 imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); 978 979 memcpy(&res, &vsc9959_imdio_res, sizeof(res)); 980 res.start += imdio_base; 981 res.end += imdio_base; 982 983 imdio_regs = devm_ioremap_resource(dev, &res); 984 if (IS_ERR(imdio_regs)) 985 return PTR_ERR(imdio_regs); 986 987 hw = enetc_hw_alloc(dev, imdio_regs); 988 if (IS_ERR(hw)) { 989 dev_err(dev, "failed to allocate ENETC HW structure\n"); 990 return PTR_ERR(hw); 991 } 992 993 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 994 if (!bus) 995 return -ENOMEM; 996 997 bus->name = "VSC9959 internal MDIO bus"; 998 bus->read = enetc_mdio_read_c22; 999 bus->write = enetc_mdio_write_c22; 1000 bus->read_c45 = enetc_mdio_read_c45; 1001 bus->write_c45 = enetc_mdio_write_c45; 1002 bus->parent = dev; 1003 mdio_priv = bus->priv; 1004 mdio_priv->hw = hw; 1005 /* This gets added to imdio_regs, which already maps addresses 1006 * starting with the proper offset. 1007 */ 1008 mdio_priv->mdio_base = 0; 1009 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1010 1011 /* Needed in order to initialize the bus mutex lock */ 1012 rc = mdiobus_register(bus); 1013 if (rc < 0) { 1014 dev_err(dev, "failed to register MDIO bus\n"); 1015 mdiobus_free(bus); 1016 return rc; 1017 } 1018 1019 felix->imdio = bus; 1020 1021 for (port = 0; port < felix->info->num_ports; port++) { 1022 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1023 struct phylink_pcs *phylink_pcs; 1024 1025 if (dsa_is_unused_port(felix->ds, port)) 1026 continue; 1027 1028 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1029 continue; 1030 1031 phylink_pcs = lynx_pcs_create_mdiodev(felix->imdio, port); 1032 if (IS_ERR(phylink_pcs)) 1033 continue; 1034 1035 felix->pcs[port] = phylink_pcs; 1036 1037 dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1038 } 1039 1040 return 0; 1041 } 1042 1043 static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1044 { 1045 struct felix *felix = ocelot_to_felix(ocelot); 1046 int port; 1047 1048 for (port = 0; port < ocelot->num_phys_ports; port++) { 1049 struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1050 1051 if (phylink_pcs) 1052 lynx_pcs_destroy(phylink_pcs); 1053 } 1054 mdiobus_unregister(felix->imdio); 1055 mdiobus_free(felix->imdio); 1056 } 1057 1058 /* The switch considers any frame (regardless of size) as eligible for 1059 * transmission if the traffic class gate is open for at least 33 ns. 1060 * Overruns are prevented by cropping an interval at the end of the gate time 1061 * slot for which egress scheduling is blocked, but we need to still keep 33 ns 1062 * available for one packet to be transmitted, otherwise the port tc will hang. 1063 * This function returns the size of a gate interval that remains available for 1064 * setting the guard band, after reserving the space for one egress frame. 1065 */ 1066 static u64 vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns) 1067 { 1068 /* Gate always open */ 1069 if (gate_len_ns == U64_MAX) 1070 return U64_MAX; 1071 1072 return (gate_len_ns - VSC9959_TAS_MIN_GATE_LEN_NS) * PSEC_PER_NSEC; 1073 } 1074 1075 /* Extract shortest continuous gate open intervals in ns for each traffic class 1076 * of a cyclic tc-taprio schedule. If a gate is always open, the duration is 1077 * considered U64_MAX. If the gate is always closed, it is considered 0. 1078 */ 1079 static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio, 1080 u64 min_gate_len[OCELOT_NUM_TC]) 1081 { 1082 struct tc_taprio_sched_entry *entry; 1083 u64 gate_len[OCELOT_NUM_TC]; 1084 u8 gates_ever_opened = 0; 1085 int tc, i, n; 1086 1087 /* Initialize arrays */ 1088 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1089 min_gate_len[tc] = U64_MAX; 1090 gate_len[tc] = 0; 1091 } 1092 1093 /* If we don't have taprio, consider all gates as permanently open */ 1094 if (!taprio) 1095 return; 1096 1097 n = taprio->num_entries; 1098 1099 /* Walk through the gate list twice to determine the length 1100 * of consecutively open gates for a traffic class, including 1101 * open gates that wrap around. We are just interested in the 1102 * minimum window size, and this doesn't change what the 1103 * minimum is (if the gate never closes, min_gate_len will 1104 * remain U64_MAX). 1105 */ 1106 for (i = 0; i < 2 * n; i++) { 1107 entry = &taprio->entries[i % n]; 1108 1109 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1110 if (entry->gate_mask & BIT(tc)) { 1111 gate_len[tc] += entry->interval; 1112 gates_ever_opened |= BIT(tc); 1113 } else { 1114 /* Gate closes now, record a potential new 1115 * minimum and reinitialize length 1116 */ 1117 if (min_gate_len[tc] > gate_len[tc] && 1118 gate_len[tc]) 1119 min_gate_len[tc] = gate_len[tc]; 1120 gate_len[tc] = 0; 1121 } 1122 } 1123 } 1124 1125 /* min_gate_len[tc] actually tracks minimum *open* gate time, so for 1126 * permanently closed gates, min_gate_len[tc] will still be U64_MAX. 1127 * Therefore they are currently indistinguishable from permanently 1128 * open gates. Overwrite the gate len with 0 when we know they're 1129 * actually permanently closed, i.e. after the loop above. 1130 */ 1131 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 1132 if (!(gates_ever_opened & BIT(tc))) 1133 min_gate_len[tc] = 0; 1134 } 1135 1136 /* ocelot_write_rix is a macro that concatenates QSYS_MAXSDU_CFG_* with _RSZ, 1137 * so we need to spell out the register access to each traffic class in helper 1138 * functions, to simplify callers 1139 */ 1140 static void vsc9959_port_qmaxsdu_set(struct ocelot *ocelot, int port, int tc, 1141 u32 max_sdu) 1142 { 1143 switch (tc) { 1144 case 0: 1145 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0, 1146 port); 1147 break; 1148 case 1: 1149 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1, 1150 port); 1151 break; 1152 case 2: 1153 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2, 1154 port); 1155 break; 1156 case 3: 1157 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3, 1158 port); 1159 break; 1160 case 4: 1161 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4, 1162 port); 1163 break; 1164 case 5: 1165 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5, 1166 port); 1167 break; 1168 case 6: 1169 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6, 1170 port); 1171 break; 1172 case 7: 1173 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7, 1174 port); 1175 break; 1176 } 1177 } 1178 1179 static u32 vsc9959_port_qmaxsdu_get(struct ocelot *ocelot, int port, int tc) 1180 { 1181 switch (tc) { 1182 case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port); 1183 case 1: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_1, port); 1184 case 2: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_2, port); 1185 case 3: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_3, port); 1186 case 4: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_4, port); 1187 case 5: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_5, port); 1188 case 6: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_6, port); 1189 case 7: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_7, port); 1190 default: 1191 return 0; 1192 } 1193 } 1194 1195 static u32 vsc9959_tas_tc_max_sdu(struct tc_taprio_qopt_offload *taprio, int tc) 1196 { 1197 if (!taprio || !taprio->max_sdu[tc]) 1198 return 0; 1199 1200 return taprio->max_sdu[tc] + ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN; 1201 } 1202 1203 /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the 1204 * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU 1205 * values (the default value is 1518). Also, for traffic class windows smaller 1206 * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame 1207 * dropping, such that these won't hang the port, as they will never be sent. 1208 */ 1209 static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port) 1210 { 1211 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1212 struct tc_taprio_qopt_offload *taprio; 1213 u64 min_gate_len[OCELOT_NUM_TC]; 1214 int speed, picos_per_byte; 1215 u64 needed_bit_time_ps; 1216 u32 val, maxlen; 1217 u8 tas_speed; 1218 int tc; 1219 1220 lockdep_assert_held(&ocelot->tas_lock); 1221 1222 taprio = ocelot_port->taprio; 1223 1224 val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port); 1225 tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val); 1226 1227 switch (tas_speed) { 1228 case OCELOT_SPEED_10: 1229 speed = SPEED_10; 1230 break; 1231 case OCELOT_SPEED_100: 1232 speed = SPEED_100; 1233 break; 1234 case OCELOT_SPEED_1000: 1235 speed = SPEED_1000; 1236 break; 1237 case OCELOT_SPEED_2500: 1238 speed = SPEED_2500; 1239 break; 1240 default: 1241 return; 1242 } 1243 1244 picos_per_byte = (USEC_PER_SEC * 8) / speed; 1245 1246 val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG); 1247 /* MAXLEN_CFG accounts automatically for VLAN. We need to include it 1248 * manually in the bit time calculation, plus the preamble and SFD. 1249 */ 1250 maxlen = val + 2 * VLAN_HLEN; 1251 /* Consider the standard Ethernet overhead of 8 octets preamble+SFD, 1252 * 4 octets FCS, 12 octets IFG. 1253 */ 1254 needed_bit_time_ps = (u64)(maxlen + 24) * picos_per_byte; 1255 1256 dev_dbg(ocelot->dev, 1257 "port %d: max frame size %d needs %llu ps at speed %d\n", 1258 port, maxlen, needed_bit_time_ps, speed); 1259 1260 vsc9959_tas_min_gate_lengths(taprio, min_gate_len); 1261 1262 mutex_lock(&ocelot->fwd_domain_lock); 1263 1264 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1265 u32 requested_max_sdu = vsc9959_tas_tc_max_sdu(taprio, tc); 1266 u64 remaining_gate_len_ps; 1267 u32 max_sdu; 1268 1269 remaining_gate_len_ps = 1270 vsc9959_tas_remaining_gate_len_ps(min_gate_len[tc]); 1271 1272 if (remaining_gate_len_ps > needed_bit_time_ps) { 1273 /* Setting QMAXSDU_CFG to 0 disables oversized frame 1274 * dropping. 1275 */ 1276 max_sdu = requested_max_sdu; 1277 dev_dbg(ocelot->dev, 1278 "port %d tc %d min gate len %llu" 1279 ", sending all frames\n", 1280 port, tc, min_gate_len[tc]); 1281 } else { 1282 /* If traffic class doesn't support a full MTU sized 1283 * frame, make sure to enable oversize frame dropping 1284 * for frames larger than the smallest that would fit. 1285 * 1286 * However, the exact same register, QSYS_QMAXSDU_CFG_*, 1287 * controls not only oversized frame dropping, but also 1288 * per-tc static guard band lengths, so it reduces the 1289 * useful gate interval length. Therefore, be careful 1290 * to calculate a guard band (and therefore max_sdu) 1291 * that still leaves 33 ns available in the time slot. 1292 */ 1293 max_sdu = div_u64(remaining_gate_len_ps, picos_per_byte); 1294 /* A TC gate may be completely closed, which is a 1295 * special case where all packets are oversized. 1296 * Any limit smaller than 64 octets accomplishes this 1297 */ 1298 if (!max_sdu) 1299 max_sdu = 1; 1300 /* Take L1 overhead into account, but just don't allow 1301 * max_sdu to go negative or to 0. Here we use 20 1302 * because QSYS_MAXSDU_CFG_* already counts the 4 FCS 1303 * octets as part of packet size. 1304 */ 1305 if (max_sdu > 20) 1306 max_sdu -= 20; 1307 1308 if (requested_max_sdu && requested_max_sdu < max_sdu) 1309 max_sdu = requested_max_sdu; 1310 1311 dev_info(ocelot->dev, 1312 "port %d tc %d min gate length %llu" 1313 " ns not enough for max frame size %d at %d" 1314 " Mbps, dropping frames over %d" 1315 " octets including FCS\n", 1316 port, tc, min_gate_len[tc], maxlen, speed, 1317 max_sdu); 1318 } 1319 1320 vsc9959_port_qmaxsdu_set(ocelot, port, tc, max_sdu); 1321 } 1322 1323 ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port); 1324 1325 ocelot->ops->cut_through_fwd(ocelot); 1326 1327 mutex_unlock(&ocelot->fwd_domain_lock); 1328 } 1329 1330 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1331 u32 speed) 1332 { 1333 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1334 u8 tas_speed; 1335 1336 switch (speed) { 1337 case SPEED_10: 1338 tas_speed = OCELOT_SPEED_10; 1339 break; 1340 case SPEED_100: 1341 tas_speed = OCELOT_SPEED_100; 1342 break; 1343 case SPEED_1000: 1344 tas_speed = OCELOT_SPEED_1000; 1345 break; 1346 case SPEED_2500: 1347 tas_speed = OCELOT_SPEED_2500; 1348 break; 1349 default: 1350 tas_speed = OCELOT_SPEED_1000; 1351 break; 1352 } 1353 1354 mutex_lock(&ocelot->tas_lock); 1355 1356 ocelot_rmw_rix(ocelot, 1357 QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1358 QSYS_TAG_CONFIG_LINK_SPEED_M, 1359 QSYS_TAG_CONFIG, port); 1360 1361 if (ocelot_port->taprio) 1362 vsc9959_tas_guard_bands_update(ocelot, port); 1363 1364 mutex_unlock(&ocelot->tas_lock); 1365 } 1366 1367 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1368 u64 cycle_time, 1369 struct timespec64 *new_base_ts) 1370 { 1371 struct timespec64 ts; 1372 ktime_t new_base_time; 1373 ktime_t current_time; 1374 1375 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1376 current_time = timespec64_to_ktime(ts); 1377 new_base_time = base_time; 1378 1379 if (base_time < current_time) { 1380 u64 nr_of_cycles = current_time - base_time; 1381 1382 do_div(nr_of_cycles, cycle_time); 1383 new_base_time += cycle_time * (nr_of_cycles + 1); 1384 } 1385 1386 *new_base_ts = ktime_to_timespec64(new_base_time); 1387 } 1388 1389 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1390 { 1391 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1392 } 1393 1394 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1395 struct tc_taprio_sched_entry *entry) 1396 { 1397 ocelot_write(ocelot, 1398 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1399 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1400 QSYS_GCL_CFG_REG_1); 1401 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1402 } 1403 1404 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1405 struct tc_taprio_qopt_offload *taprio) 1406 { 1407 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1408 struct timespec64 base_ts; 1409 int ret, i; 1410 u32 val; 1411 1412 mutex_lock(&ocelot->tas_lock); 1413 1414 if (taprio->cmd == TAPRIO_CMD_DESTROY) { 1415 ocelot_port_mqprio(ocelot, port, &taprio->mqprio); 1416 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1417 QSYS_TAG_CONFIG, port); 1418 1419 taprio_offload_free(ocelot_port->taprio); 1420 ocelot_port->taprio = NULL; 1421 1422 vsc9959_tas_guard_bands_update(ocelot, port); 1423 1424 mutex_unlock(&ocelot->tas_lock); 1425 return 0; 1426 } else if (taprio->cmd != TAPRIO_CMD_REPLACE) { 1427 ret = -EOPNOTSUPP; 1428 goto err_unlock; 1429 } 1430 1431 ret = ocelot_port_mqprio(ocelot, port, &taprio->mqprio); 1432 if (ret) 1433 goto err_unlock; 1434 1435 if (taprio->cycle_time > NSEC_PER_SEC || 1436 taprio->cycle_time_extension >= NSEC_PER_SEC) { 1437 ret = -EINVAL; 1438 goto err_reset_tc; 1439 } 1440 1441 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) { 1442 ret = -ERANGE; 1443 goto err_reset_tc; 1444 } 1445 1446 /* Enable guard band. The switch will schedule frames without taking 1447 * their length into account. Thus we'll always need to enable the 1448 * guard band which reserves the time of a maximum sized frame at the 1449 * end of the time window. 1450 * 1451 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1452 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1453 * operate on the port number. 1454 */ 1455 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1456 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1457 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1458 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1459 QSYS_TAS_PARAM_CFG_CTRL); 1460 1461 /* Hardware errata - Admin config could not be overwritten if 1462 * config is pending, need reset the TAS module 1463 */ 1464 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1465 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) { 1466 ret = -EBUSY; 1467 goto err_reset_tc; 1468 } 1469 1470 ocelot_rmw_rix(ocelot, 1471 QSYS_TAG_CONFIG_ENABLE | 1472 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1473 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1474 QSYS_TAG_CONFIG_ENABLE | 1475 QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1476 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1477 QSYS_TAG_CONFIG, port); 1478 1479 vsc9959_new_base_time(ocelot, taprio->base_time, 1480 taprio->cycle_time, &base_ts); 1481 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1482 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1483 val = upper_32_bits(base_ts.tv_sec); 1484 ocelot_write(ocelot, 1485 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1486 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1487 QSYS_PARAM_CFG_REG_3); 1488 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1489 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1490 1491 for (i = 0; i < taprio->num_entries; i++) 1492 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1493 1494 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1495 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1496 QSYS_TAS_PARAM_CFG_CTRL); 1497 1498 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1499 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1500 10, 100000); 1501 if (ret) 1502 goto err_reset_tc; 1503 1504 ocelot_port->taprio = taprio_offload_get(taprio); 1505 vsc9959_tas_guard_bands_update(ocelot, port); 1506 1507 mutex_unlock(&ocelot->tas_lock); 1508 1509 return 0; 1510 1511 err_reset_tc: 1512 taprio->mqprio.qopt.num_tc = 0; 1513 ocelot_port_mqprio(ocelot, port, &taprio->mqprio); 1514 err_unlock: 1515 mutex_unlock(&ocelot->tas_lock); 1516 1517 return ret; 1518 } 1519 1520 static void vsc9959_tas_clock_adjust(struct ocelot *ocelot) 1521 { 1522 struct tc_taprio_qopt_offload *taprio; 1523 struct ocelot_port *ocelot_port; 1524 struct timespec64 base_ts; 1525 int port; 1526 u32 val; 1527 1528 mutex_lock(&ocelot->tas_lock); 1529 1530 for (port = 0; port < ocelot->num_phys_ports; port++) { 1531 ocelot_port = ocelot->ports[port]; 1532 taprio = ocelot_port->taprio; 1533 if (!taprio) 1534 continue; 1535 1536 ocelot_rmw(ocelot, 1537 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port), 1538 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M, 1539 QSYS_TAS_PARAM_CFG_CTRL); 1540 1541 /* Disable time-aware shaper */ 1542 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1543 QSYS_TAG_CONFIG, port); 1544 1545 vsc9959_new_base_time(ocelot, taprio->base_time, 1546 taprio->cycle_time, &base_ts); 1547 1548 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1549 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), 1550 QSYS_PARAM_CFG_REG_2); 1551 val = upper_32_bits(base_ts.tv_sec); 1552 ocelot_rmw(ocelot, 1553 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val), 1554 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M, 1555 QSYS_PARAM_CFG_REG_3); 1556 1557 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1558 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1559 QSYS_TAS_PARAM_CFG_CTRL); 1560 1561 /* Re-enable time-aware shaper */ 1562 ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE, 1563 QSYS_TAG_CONFIG_ENABLE, 1564 QSYS_TAG_CONFIG, port); 1565 } 1566 mutex_unlock(&ocelot->tas_lock); 1567 } 1568 1569 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 1570 struct tc_cbs_qopt_offload *cbs_qopt) 1571 { 1572 struct ocelot *ocelot = ds->priv; 1573 int port_ix = port * 8 + cbs_qopt->queue; 1574 u32 rate, burst; 1575 1576 if (cbs_qopt->queue >= ds->num_tx_queues) 1577 return -EINVAL; 1578 1579 if (!cbs_qopt->enable) { 1580 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 1581 QSYS_CIR_CFG_CIR_BURST(0), 1582 QSYS_CIR_CFG, port_ix); 1583 1584 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 1585 QSYS_SE_CFG, port_ix); 1586 1587 return 0; 1588 } 1589 1590 /* Rate unit is 100 kbps */ 1591 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 1592 /* Avoid using zero rate */ 1593 rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 1594 /* Burst unit is 4kB */ 1595 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 1596 /* Avoid using zero burst size */ 1597 burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 1598 ocelot_write_gix(ocelot, 1599 QSYS_CIR_CFG_CIR_RATE(rate) | 1600 QSYS_CIR_CFG_CIR_BURST(burst), 1601 QSYS_CIR_CFG, 1602 port_ix); 1603 1604 ocelot_rmw_gix(ocelot, 1605 QSYS_SE_CFG_SE_FRM_MODE(0) | 1606 QSYS_SE_CFG_SE_AVB_ENA, 1607 QSYS_SE_CFG_SE_AVB_ENA | 1608 QSYS_SE_CFG_SE_FRM_MODE_M, 1609 QSYS_SE_CFG, 1610 port_ix); 1611 1612 return 0; 1613 } 1614 1615 static int vsc9959_qos_query_caps(struct tc_query_caps_base *base) 1616 { 1617 switch (base->type) { 1618 case TC_SETUP_QDISC_MQPRIO: { 1619 struct tc_mqprio_caps *caps = base->caps; 1620 1621 caps->validate_queue_counts = true; 1622 1623 return 0; 1624 } 1625 case TC_SETUP_QDISC_TAPRIO: { 1626 struct tc_taprio_caps *caps = base->caps; 1627 1628 caps->supports_queue_max_sdu = true; 1629 1630 return 0; 1631 } 1632 default: 1633 return -EOPNOTSUPP; 1634 } 1635 } 1636 1637 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1638 enum tc_setup_type type, 1639 void *type_data) 1640 { 1641 struct ocelot *ocelot = ds->priv; 1642 1643 switch (type) { 1644 case TC_QUERY_CAPS: 1645 return vsc9959_qos_query_caps(type_data); 1646 case TC_SETUP_QDISC_TAPRIO: 1647 return vsc9959_qos_port_tas_set(ocelot, port, type_data); 1648 case TC_SETUP_QDISC_MQPRIO: 1649 return ocelot_port_mqprio(ocelot, port, type_data); 1650 case TC_SETUP_QDISC_CBS: 1651 return vsc9959_qos_port_cbs_set(ds, port, type_data); 1652 default: 1653 return -EOPNOTSUPP; 1654 } 1655 } 1656 1657 #define VSC9959_PSFP_SFID_MAX 175 1658 #define VSC9959_PSFP_GATE_ID_MAX 183 1659 #define VSC9959_PSFP_POLICER_BASE 63 1660 #define VSC9959_PSFP_POLICER_MAX 383 1661 #define VSC9959_PSFP_GATE_LIST_NUM 4 1662 #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 1663 1664 struct felix_stream { 1665 struct list_head list; 1666 unsigned long id; 1667 bool dummy; 1668 int ports; 1669 int port; 1670 u8 dmac[ETH_ALEN]; 1671 u16 vid; 1672 s8 prio; 1673 u8 sfid_valid; 1674 u8 ssid_valid; 1675 u32 sfid; 1676 u32 ssid; 1677 }; 1678 1679 struct felix_stream_filter_counters { 1680 u64 match; 1681 u64 not_pass_gate; 1682 u64 not_pass_sdu; 1683 u64 red; 1684 }; 1685 1686 struct felix_stream_filter { 1687 struct felix_stream_filter_counters stats; 1688 struct list_head list; 1689 refcount_t refcount; 1690 u32 index; 1691 u8 enable; 1692 int portmask; 1693 u8 sg_valid; 1694 u32 sgid; 1695 u8 fm_valid; 1696 u32 fmid; 1697 u8 prio_valid; 1698 u8 prio; 1699 u32 maxsdu; 1700 }; 1701 1702 struct felix_stream_gate { 1703 u32 index; 1704 u8 enable; 1705 u8 ipv_valid; 1706 u8 init_ipv; 1707 u64 basetime; 1708 u64 cycletime; 1709 u64 cycletime_ext; 1710 u32 num_entries; 1711 struct action_gate_entry entries[]; 1712 }; 1713 1714 struct felix_stream_gate_entry { 1715 struct list_head list; 1716 refcount_t refcount; 1717 u32 index; 1718 }; 1719 1720 static int vsc9959_stream_identify(struct flow_cls_offload *f, 1721 struct felix_stream *stream) 1722 { 1723 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 1724 struct flow_dissector *dissector = rule->match.dissector; 1725 1726 if (dissector->used_keys & 1727 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 1728 BIT(FLOW_DISSECTOR_KEY_BASIC) | 1729 BIT(FLOW_DISSECTOR_KEY_VLAN) | 1730 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 1731 return -EOPNOTSUPP; 1732 1733 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 1734 struct flow_match_eth_addrs match; 1735 1736 flow_rule_match_eth_addrs(rule, &match); 1737 ether_addr_copy(stream->dmac, match.key->dst); 1738 if (!is_zero_ether_addr(match.mask->src)) 1739 return -EOPNOTSUPP; 1740 } else { 1741 return -EOPNOTSUPP; 1742 } 1743 1744 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 1745 struct flow_match_vlan match; 1746 1747 flow_rule_match_vlan(rule, &match); 1748 if (match.mask->vlan_priority) 1749 stream->prio = match.key->vlan_priority; 1750 else 1751 stream->prio = -1; 1752 1753 if (!match.mask->vlan_id) 1754 return -EOPNOTSUPP; 1755 stream->vid = match.key->vlan_id; 1756 } else { 1757 return -EOPNOTSUPP; 1758 } 1759 1760 stream->id = f->cookie; 1761 1762 return 0; 1763 } 1764 1765 static int vsc9959_mact_stream_set(struct ocelot *ocelot, 1766 struct felix_stream *stream, 1767 struct netlink_ext_ack *extack) 1768 { 1769 enum macaccess_entry_type type; 1770 int ret, sfid, ssid; 1771 u32 vid, dst_idx; 1772 u8 mac[ETH_ALEN]; 1773 1774 ether_addr_copy(mac, stream->dmac); 1775 vid = stream->vid; 1776 1777 /* Stream identification desn't support to add a stream with non 1778 * existent MAC (The MAC entry has not been learned in MAC table). 1779 */ 1780 ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 1781 if (ret) { 1782 if (extack) 1783 NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 1784 return -EOPNOTSUPP; 1785 } 1786 1787 if ((stream->sfid_valid || stream->ssid_valid) && 1788 type == ENTRYTYPE_NORMAL) 1789 type = ENTRYTYPE_LOCKED; 1790 1791 sfid = stream->sfid_valid ? stream->sfid : -1; 1792 ssid = stream->ssid_valid ? stream->ssid : -1; 1793 1794 ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 1795 sfid, ssid); 1796 1797 return ret; 1798 } 1799 1800 static struct felix_stream * 1801 vsc9959_stream_table_lookup(struct list_head *stream_list, 1802 struct felix_stream *stream) 1803 { 1804 struct felix_stream *tmp; 1805 1806 list_for_each_entry(tmp, stream_list, list) 1807 if (ether_addr_equal(tmp->dmac, stream->dmac) && 1808 tmp->vid == stream->vid) 1809 return tmp; 1810 1811 return NULL; 1812 } 1813 1814 static int vsc9959_stream_table_add(struct ocelot *ocelot, 1815 struct list_head *stream_list, 1816 struct felix_stream *stream, 1817 struct netlink_ext_ack *extack) 1818 { 1819 struct felix_stream *stream_entry; 1820 int ret; 1821 1822 stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL); 1823 if (!stream_entry) 1824 return -ENOMEM; 1825 1826 if (!stream->dummy) { 1827 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 1828 if (ret) { 1829 kfree(stream_entry); 1830 return ret; 1831 } 1832 } 1833 1834 list_add_tail(&stream_entry->list, stream_list); 1835 1836 return 0; 1837 } 1838 1839 static struct felix_stream * 1840 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 1841 { 1842 struct felix_stream *tmp; 1843 1844 list_for_each_entry(tmp, stream_list, list) 1845 if (tmp->id == id) 1846 return tmp; 1847 1848 return NULL; 1849 } 1850 1851 static void vsc9959_stream_table_del(struct ocelot *ocelot, 1852 struct felix_stream *stream) 1853 { 1854 if (!stream->dummy) 1855 vsc9959_mact_stream_set(ocelot, stream, NULL); 1856 1857 list_del(&stream->list); 1858 kfree(stream); 1859 } 1860 1861 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 1862 { 1863 return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 1864 } 1865 1866 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 1867 struct felix_stream_filter *sfi) 1868 { 1869 u32 val; 1870 1871 if (sfi->index > VSC9959_PSFP_SFID_MAX) 1872 return -EINVAL; 1873 1874 if (!sfi->enable) { 1875 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1876 ANA_TABLES_SFIDTIDX); 1877 1878 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 1879 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 1880 1881 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1882 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1883 10, 100000); 1884 } 1885 1886 if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 1887 sfi->fmid > VSC9959_PSFP_POLICER_MAX) 1888 return -EINVAL; 1889 1890 ocelot_write(ocelot, 1891 (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 1892 ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 1893 (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 1894 ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 1895 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1896 ANA_TABLES_SFIDTIDX); 1897 1898 ocelot_write(ocelot, 1899 (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 1900 ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 1901 ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 1902 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1903 ANA_TABLES_SFIDACCESS); 1904 1905 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1906 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1907 10, 100000); 1908 } 1909 1910 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) 1911 { 1912 u32 val; 1913 1914 ocelot_rmw(ocelot, 1915 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), 1916 ANA_TABLES_SFIDTIDX_SFID_INDEX_M, 1917 ANA_TABLES_SFIDTIDX); 1918 1919 ocelot_write(ocelot, 1920 ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | 1921 ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, 1922 ANA_TABLES_SFID_MASK); 1923 1924 ocelot_rmw(ocelot, 1925 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1926 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, 1927 ANA_TABLES_SFIDACCESS); 1928 1929 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1930 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1931 10, 100000); 1932 } 1933 1934 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, 1935 struct felix_stream_filter *sfi, 1936 struct list_head *pos) 1937 { 1938 struct felix_stream_filter *sfi_entry; 1939 int ret; 1940 1941 sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL); 1942 if (!sfi_entry) 1943 return -ENOMEM; 1944 1945 refcount_set(&sfi_entry->refcount, 1); 1946 1947 ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 1948 if (ret) { 1949 kfree(sfi_entry); 1950 return ret; 1951 } 1952 1953 vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask); 1954 1955 list_add(&sfi_entry->list, pos); 1956 1957 return 0; 1958 } 1959 1960 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 1961 struct felix_stream_filter *sfi) 1962 { 1963 struct list_head *pos, *q, *last; 1964 struct felix_stream_filter *tmp; 1965 struct ocelot_psfp_list *psfp; 1966 u32 insert = 0; 1967 1968 psfp = &ocelot->psfp; 1969 last = &psfp->sfi_list; 1970 1971 list_for_each_safe(pos, q, &psfp->sfi_list) { 1972 tmp = list_entry(pos, struct felix_stream_filter, list); 1973 if (sfi->sg_valid == tmp->sg_valid && 1974 sfi->fm_valid == tmp->fm_valid && 1975 sfi->portmask == tmp->portmask && 1976 tmp->sgid == sfi->sgid && 1977 tmp->fmid == sfi->fmid) { 1978 sfi->index = tmp->index; 1979 refcount_inc(&tmp->refcount); 1980 return 0; 1981 } 1982 /* Make sure that the index is increasing in order. */ 1983 if (tmp->index == insert) { 1984 last = pos; 1985 insert++; 1986 } 1987 } 1988 sfi->index = insert; 1989 1990 return vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1991 } 1992 1993 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, 1994 struct felix_stream_filter *sfi, 1995 struct felix_stream_filter *sfi2) 1996 { 1997 struct felix_stream_filter *tmp; 1998 struct list_head *pos, *q, *last; 1999 struct ocelot_psfp_list *psfp; 2000 u32 insert = 0; 2001 int ret; 2002 2003 psfp = &ocelot->psfp; 2004 last = &psfp->sfi_list; 2005 2006 list_for_each_safe(pos, q, &psfp->sfi_list) { 2007 tmp = list_entry(pos, struct felix_stream_filter, list); 2008 /* Make sure that the index is increasing in order. */ 2009 if (tmp->index >= insert + 2) 2010 break; 2011 2012 insert = tmp->index + 1; 2013 last = pos; 2014 } 2015 sfi->index = insert; 2016 2017 ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 2018 if (ret) 2019 return ret; 2020 2021 sfi2->index = insert + 1; 2022 2023 return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next); 2024 } 2025 2026 static struct felix_stream_filter * 2027 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 2028 { 2029 struct felix_stream_filter *tmp; 2030 2031 list_for_each_entry(tmp, sfi_list, list) 2032 if (tmp->index == index) 2033 return tmp; 2034 2035 return NULL; 2036 } 2037 2038 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 2039 { 2040 struct felix_stream_filter *tmp, *n; 2041 struct ocelot_psfp_list *psfp; 2042 u8 z; 2043 2044 psfp = &ocelot->psfp; 2045 2046 list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 2047 if (tmp->index == index) { 2048 z = refcount_dec_and_test(&tmp->refcount); 2049 if (z) { 2050 tmp->enable = 0; 2051 vsc9959_psfp_sfi_set(ocelot, tmp); 2052 list_del(&tmp->list); 2053 kfree(tmp); 2054 } 2055 break; 2056 } 2057 } 2058 2059 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 2060 struct felix_stream_gate *sgi) 2061 { 2062 sgi->index = entry->hw_index; 2063 sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 2064 sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 2065 sgi->basetime = entry->gate.basetime; 2066 sgi->cycletime = entry->gate.cycletime; 2067 sgi->num_entries = entry->gate.num_entries; 2068 sgi->enable = 1; 2069 2070 memcpy(sgi->entries, entry->gate.entries, 2071 entry->gate.num_entries * sizeof(struct action_gate_entry)); 2072 } 2073 2074 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 2075 { 2076 return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 2077 } 2078 2079 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 2080 struct felix_stream_gate *sgi) 2081 { 2082 struct action_gate_entry *e; 2083 struct timespec64 base_ts; 2084 u32 interval_sum = 0; 2085 u32 val; 2086 int i; 2087 2088 if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 2089 return -EINVAL; 2090 2091 ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 2092 ANA_SG_ACCESS_CTRL); 2093 2094 if (!sgi->enable) { 2095 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 2096 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2097 ANA_SG_CONFIG_REG_3_GATE_ENABLE, 2098 ANA_SG_CONFIG_REG_3); 2099 2100 return 0; 2101 } 2102 2103 if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 2104 sgi->cycletime > NSEC_PER_SEC) 2105 return -EINVAL; 2106 2107 if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 2108 return -EINVAL; 2109 2110 vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 2111 ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 2112 val = lower_32_bits(base_ts.tv_sec); 2113 ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 2114 2115 val = upper_32_bits(base_ts.tv_sec); 2116 ocelot_write(ocelot, 2117 (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 2118 ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 2119 ANA_SG_CONFIG_REG_3_GATE_ENABLE | 2120 ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 2121 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2122 ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 2123 ANA_SG_CONFIG_REG_3); 2124 2125 ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 2126 2127 e = sgi->entries; 2128 for (i = 0; i < sgi->num_entries; i++) { 2129 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 2130 2131 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 2132 (e[i].gate_state ? 2133 ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 2134 ANA_SG_GCL_GS_CONFIG, i); 2135 2136 interval_sum += e[i].interval; 2137 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 2138 } 2139 2140 ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2141 ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2142 ANA_SG_ACCESS_CTRL); 2143 2144 return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 2145 (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 2146 10, 100000); 2147 } 2148 2149 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 2150 struct felix_stream_gate *sgi) 2151 { 2152 struct felix_stream_gate_entry *tmp; 2153 struct ocelot_psfp_list *psfp; 2154 int ret; 2155 2156 psfp = &ocelot->psfp; 2157 2158 list_for_each_entry(tmp, &psfp->sgi_list, list) 2159 if (tmp->index == sgi->index) { 2160 refcount_inc(&tmp->refcount); 2161 return 0; 2162 } 2163 2164 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 2165 if (!tmp) 2166 return -ENOMEM; 2167 2168 ret = vsc9959_psfp_sgi_set(ocelot, sgi); 2169 if (ret) { 2170 kfree(tmp); 2171 return ret; 2172 } 2173 2174 tmp->index = sgi->index; 2175 refcount_set(&tmp->refcount, 1); 2176 list_add_tail(&tmp->list, &psfp->sgi_list); 2177 2178 return 0; 2179 } 2180 2181 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 2182 u32 index) 2183 { 2184 struct felix_stream_gate_entry *tmp, *n; 2185 struct felix_stream_gate sgi = {0}; 2186 struct ocelot_psfp_list *psfp; 2187 u8 z; 2188 2189 psfp = &ocelot->psfp; 2190 2191 list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 2192 if (tmp->index == index) { 2193 z = refcount_dec_and_test(&tmp->refcount); 2194 if (z) { 2195 sgi.index = index; 2196 sgi.enable = 0; 2197 vsc9959_psfp_sgi_set(ocelot, &sgi); 2198 list_del(&tmp->list); 2199 kfree(tmp); 2200 } 2201 break; 2202 } 2203 } 2204 2205 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, 2206 struct flow_cls_offload *f) 2207 { 2208 struct netlink_ext_ack *extack = f->common.extack; 2209 struct felix_stream_filter old_sfi, *sfi_entry; 2210 struct felix_stream_filter sfi = {0}; 2211 const struct flow_action_entry *a; 2212 struct felix_stream *stream_entry; 2213 struct felix_stream stream = {0}; 2214 struct felix_stream_gate *sgi; 2215 struct ocelot_psfp_list *psfp; 2216 struct ocelot_policer pol; 2217 int ret, i, size; 2218 u64 rate, burst; 2219 u32 index; 2220 2221 psfp = &ocelot->psfp; 2222 2223 ret = vsc9959_stream_identify(f, &stream); 2224 if (ret) { 2225 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 2226 return ret; 2227 } 2228 2229 mutex_lock(&psfp->lock); 2230 2231 flow_action_for_each(i, a, &f->rule->action) { 2232 switch (a->id) { 2233 case FLOW_ACTION_GATE: 2234 size = struct_size(sgi, entries, a->gate.num_entries); 2235 sgi = kzalloc(size, GFP_KERNEL); 2236 if (!sgi) { 2237 ret = -ENOMEM; 2238 goto err; 2239 } 2240 vsc9959_psfp_parse_gate(a, sgi); 2241 ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 2242 if (ret) { 2243 kfree(sgi); 2244 goto err; 2245 } 2246 sfi.sg_valid = 1; 2247 sfi.sgid = sgi->index; 2248 kfree(sgi); 2249 break; 2250 case FLOW_ACTION_POLICE: 2251 index = a->hw_index + VSC9959_PSFP_POLICER_BASE; 2252 if (index > VSC9959_PSFP_POLICER_MAX) { 2253 ret = -EINVAL; 2254 goto err; 2255 } 2256 2257 rate = a->police.rate_bytes_ps; 2258 burst = rate * PSCHED_NS2TICKS(a->police.burst); 2259 pol = (struct ocelot_policer) { 2260 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC), 2261 .rate = div_u64(rate, 1000) * 8, 2262 }; 2263 ret = ocelot_vcap_policer_add(ocelot, index, &pol); 2264 if (ret) 2265 goto err; 2266 2267 sfi.fm_valid = 1; 2268 sfi.fmid = index; 2269 sfi.maxsdu = a->police.mtu; 2270 break; 2271 default: 2272 mutex_unlock(&psfp->lock); 2273 return -EOPNOTSUPP; 2274 } 2275 } 2276 2277 stream.ports = BIT(port); 2278 stream.port = port; 2279 2280 sfi.portmask = stream.ports; 2281 sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 2282 sfi.prio = (sfi.prio_valid ? stream.prio : 0); 2283 sfi.enable = 1; 2284 2285 /* Check if stream is set. */ 2286 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 2287 if (stream_entry) { 2288 if (stream_entry->ports & BIT(port)) { 2289 NL_SET_ERR_MSG_MOD(extack, 2290 "The stream is added on this port"); 2291 ret = -EEXIST; 2292 goto err; 2293 } 2294 2295 if (stream_entry->ports != BIT(stream_entry->port)) { 2296 NL_SET_ERR_MSG_MOD(extack, 2297 "The stream is added on two ports"); 2298 ret = -EEXIST; 2299 goto err; 2300 } 2301 2302 stream_entry->ports |= BIT(port); 2303 stream.ports = stream_entry->ports; 2304 2305 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, 2306 stream_entry->sfid); 2307 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); 2308 2309 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid); 2310 2311 old_sfi.portmask = stream_entry->ports; 2312 sfi.portmask = stream.ports; 2313 2314 if (stream_entry->port > port) { 2315 ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi, 2316 &old_sfi); 2317 stream_entry->dummy = true; 2318 } else { 2319 ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi, 2320 &sfi); 2321 stream.dummy = true; 2322 } 2323 if (ret) 2324 goto err; 2325 2326 stream_entry->sfid = old_sfi.index; 2327 } else { 2328 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 2329 if (ret) 2330 goto err; 2331 } 2332 2333 stream.sfid = sfi.index; 2334 stream.sfid_valid = 1; 2335 ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 2336 &stream, extack); 2337 if (ret) { 2338 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 2339 goto err; 2340 } 2341 2342 mutex_unlock(&psfp->lock); 2343 2344 return 0; 2345 2346 err: 2347 if (sfi.sg_valid) 2348 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 2349 2350 if (sfi.fm_valid) 2351 ocelot_vcap_policer_del(ocelot, sfi.fmid); 2352 2353 mutex_unlock(&psfp->lock); 2354 2355 return ret; 2356 } 2357 2358 static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 2359 struct flow_cls_offload *f) 2360 { 2361 struct felix_stream *stream, tmp, *stream_entry; 2362 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2363 static struct felix_stream_filter *sfi; 2364 2365 mutex_lock(&psfp->lock); 2366 2367 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2368 if (!stream) { 2369 mutex_unlock(&psfp->lock); 2370 return -ENOMEM; 2371 } 2372 2373 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2374 if (!sfi) { 2375 mutex_unlock(&psfp->lock); 2376 return -ENOMEM; 2377 } 2378 2379 if (sfi->sg_valid) 2380 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 2381 2382 if (sfi->fm_valid) 2383 ocelot_vcap_policer_del(ocelot, sfi->fmid); 2384 2385 vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 2386 2387 memcpy(&tmp, stream, sizeof(tmp)); 2388 2389 stream->sfid_valid = 0; 2390 vsc9959_stream_table_del(ocelot, stream); 2391 2392 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp); 2393 if (stream_entry) { 2394 stream_entry->ports = BIT(stream_entry->port); 2395 if (stream_entry->dummy) { 2396 stream_entry->dummy = false; 2397 vsc9959_mact_stream_set(ocelot, stream_entry, NULL); 2398 } 2399 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid, 2400 stream_entry->ports); 2401 } 2402 2403 mutex_unlock(&psfp->lock); 2404 2405 return 0; 2406 } 2407 2408 static void vsc9959_update_sfid_stats(struct ocelot *ocelot, 2409 struct felix_stream_filter *sfi) 2410 { 2411 struct felix_stream_filter_counters *s = &sfi->stats; 2412 u32 match, not_pass_gate, not_pass_sdu, red; 2413 u32 sfid = sfi->index; 2414 2415 lockdep_assert_held(&ocelot->stat_view_lock); 2416 2417 ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(sfid), 2418 SYS_STAT_CFG_STAT_VIEW_M, 2419 SYS_STAT_CFG); 2420 2421 match = ocelot_read(ocelot, SYS_COUNT_SF_MATCHING_FRAMES); 2422 not_pass_gate = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_FRAMES); 2423 not_pass_sdu = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_SDU); 2424 red = ocelot_read(ocelot, SYS_COUNT_SF_RED_FRAMES); 2425 2426 /* Clear the PSFP counter. */ 2427 ocelot_write(ocelot, 2428 SYS_STAT_CFG_STAT_VIEW(sfid) | 2429 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 2430 SYS_STAT_CFG); 2431 2432 s->match += match; 2433 s->not_pass_gate += not_pass_gate; 2434 s->not_pass_sdu += not_pass_sdu; 2435 s->red += red; 2436 } 2437 2438 /* Caller must hold &ocelot->stat_view_lock */ 2439 static void vsc9959_update_stats(struct ocelot *ocelot) 2440 { 2441 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2442 struct felix_stream_filter *sfi; 2443 2444 mutex_lock(&psfp->lock); 2445 2446 list_for_each_entry(sfi, &psfp->sfi_list, list) 2447 vsc9959_update_sfid_stats(ocelot, sfi); 2448 2449 mutex_unlock(&psfp->lock); 2450 } 2451 2452 static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 2453 struct flow_cls_offload *f, 2454 struct flow_stats *stats) 2455 { 2456 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2457 struct felix_stream_filter_counters *s; 2458 static struct felix_stream_filter *sfi; 2459 struct felix_stream *stream; 2460 2461 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2462 if (!stream) 2463 return -ENOMEM; 2464 2465 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2466 if (!sfi) 2467 return -EINVAL; 2468 2469 mutex_lock(&ocelot->stat_view_lock); 2470 2471 vsc9959_update_sfid_stats(ocelot, sfi); 2472 2473 s = &sfi->stats; 2474 stats->pkts = s->match; 2475 stats->drops = s->not_pass_gate + s->not_pass_sdu + s->red; 2476 2477 memset(s, 0, sizeof(*s)); 2478 2479 mutex_unlock(&ocelot->stat_view_lock); 2480 2481 return 0; 2482 } 2483 2484 static void vsc9959_psfp_init(struct ocelot *ocelot) 2485 { 2486 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2487 2488 INIT_LIST_HEAD(&psfp->stream_list); 2489 INIT_LIST_HEAD(&psfp->sfi_list); 2490 INIT_LIST_HEAD(&psfp->sgi_list); 2491 mutex_init(&psfp->lock); 2492 } 2493 2494 /* When using cut-through forwarding and the egress port runs at a higher data 2495 * rate than the ingress port, the packet currently under transmission would 2496 * suffer an underrun since it would be transmitted faster than it is received. 2497 * The Felix switch implementation of cut-through forwarding does not check in 2498 * hardware whether this condition is satisfied or not, so we must restrict the 2499 * list of ports that have cut-through forwarding enabled on egress to only be 2500 * the ports operating at the lowest link speed within their respective 2501 * forwarding domain. 2502 */ 2503 static void vsc9959_cut_through_fwd(struct ocelot *ocelot) 2504 { 2505 struct felix *felix = ocelot_to_felix(ocelot); 2506 struct dsa_switch *ds = felix->ds; 2507 int tc, port, other_port; 2508 2509 lockdep_assert_held(&ocelot->fwd_domain_lock); 2510 2511 for (port = 0; port < ocelot->num_phys_ports; port++) { 2512 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2513 struct ocelot_mm_state *mm = &ocelot->mm[port]; 2514 int min_speed = ocelot_port->speed; 2515 unsigned long mask = 0; 2516 u32 tmp, val = 0; 2517 2518 /* Disable cut-through on ports that are down */ 2519 if (ocelot_port->speed <= 0) 2520 goto set; 2521 2522 if (dsa_is_cpu_port(ds, port)) { 2523 /* Ocelot switches forward from the NPI port towards 2524 * any port, regardless of it being in the NPI port's 2525 * forwarding domain or not. 2526 */ 2527 mask = dsa_user_ports(ds); 2528 } else { 2529 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 2530 mask &= ~BIT(port); 2531 if (ocelot->npi >= 0) 2532 mask |= BIT(ocelot->npi); 2533 else 2534 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 2535 port); 2536 } 2537 2538 /* Calculate the minimum link speed, among the ports that are 2539 * up, of this source port's forwarding domain. 2540 */ 2541 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { 2542 struct ocelot_port *other_ocelot_port; 2543 2544 other_ocelot_port = ocelot->ports[other_port]; 2545 if (other_ocelot_port->speed <= 0) 2546 continue; 2547 2548 if (min_speed > other_ocelot_port->speed) 2549 min_speed = other_ocelot_port->speed; 2550 } 2551 2552 /* Enable cut-through forwarding for all traffic classes that 2553 * don't have oversized dropping enabled, since this check is 2554 * bypassed in cut-through mode. Also exclude preemptible 2555 * traffic classes, since these would hang the port for some 2556 * reason, if sent as cut-through. 2557 */ 2558 if (ocelot_port->speed == min_speed) { 2559 val = GENMASK(7, 0) & ~mm->active_preemptible_tcs; 2560 2561 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 2562 if (vsc9959_port_qmaxsdu_get(ocelot, port, tc)) 2563 val &= ~BIT(tc); 2564 } 2565 2566 set: 2567 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); 2568 if (tmp == val) 2569 continue; 2570 2571 dev_dbg(ocelot->dev, 2572 "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding on TC mask 0x%x\n", 2573 port, mask, ocelot_port->speed, min_speed, 2574 val ? "enabling" : "disabling", val); 2575 2576 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); 2577 } 2578 } 2579 2580 static const struct ocelot_ops vsc9959_ops = { 2581 .reset = vsc9959_reset, 2582 .wm_enc = vsc9959_wm_enc, 2583 .wm_dec = vsc9959_wm_dec, 2584 .wm_stat = vsc9959_wm_stat, 2585 .port_to_netdev = felix_port_to_netdev, 2586 .netdev_to_port = felix_netdev_to_port, 2587 .psfp_init = vsc9959_psfp_init, 2588 .psfp_filter_add = vsc9959_psfp_filter_add, 2589 .psfp_filter_del = vsc9959_psfp_filter_del, 2590 .psfp_stats_get = vsc9959_psfp_stats_get, 2591 .cut_through_fwd = vsc9959_cut_through_fwd, 2592 .tas_clock_adjust = vsc9959_tas_clock_adjust, 2593 .update_stats = vsc9959_update_stats, 2594 }; 2595 2596 static const struct felix_info felix_info_vsc9959 = { 2597 .resources = vsc9959_resources, 2598 .num_resources = ARRAY_SIZE(vsc9959_resources), 2599 .resource_names = vsc9959_resource_names, 2600 .regfields = vsc9959_regfields, 2601 .map = vsc9959_regmap, 2602 .ops = &vsc9959_ops, 2603 .vcap = vsc9959_vcap_props, 2604 .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 2605 .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 2606 .vcap_pol_base2 = 0, 2607 .vcap_pol_max2 = 0, 2608 .num_mact_rows = 2048, 2609 .num_ports = VSC9959_NUM_PORTS, 2610 .num_tx_queues = OCELOT_NUM_TC, 2611 .quirks = FELIX_MAC_QUIRKS, 2612 .quirk_no_xtr_irq = true, 2613 .ptp_caps = &vsc9959_ptp_caps, 2614 .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2615 .mdio_bus_free = vsc9959_mdio_bus_free, 2616 .port_modes = vsc9959_port_modes, 2617 .port_setup_tc = vsc9959_port_setup_tc, 2618 .port_sched_speed_set = vsc9959_sched_speed_set, 2619 .tas_guard_bands_update = vsc9959_tas_guard_bands_update, 2620 }; 2621 2622 /* The INTB interrupt is shared between for PTP TX timestamp availability 2623 * notification and MAC Merge status change on each port. 2624 */ 2625 static irqreturn_t felix_irq_handler(int irq, void *data) 2626 { 2627 struct ocelot *ocelot = (struct ocelot *)data; 2628 2629 ocelot_get_txtstamp(ocelot); 2630 ocelot_mm_irq(ocelot); 2631 2632 return IRQ_HANDLED; 2633 } 2634 2635 static int felix_pci_probe(struct pci_dev *pdev, 2636 const struct pci_device_id *id) 2637 { 2638 struct dsa_switch *ds; 2639 struct ocelot *ocelot; 2640 struct felix *felix; 2641 int err; 2642 2643 if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 2644 dev_info(&pdev->dev, "device is disabled, skipping\n"); 2645 return -ENODEV; 2646 } 2647 2648 err = pci_enable_device(pdev); 2649 if (err) { 2650 dev_err(&pdev->dev, "device enable failed\n"); 2651 goto err_pci_enable; 2652 } 2653 2654 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 2655 if (!felix) { 2656 err = -ENOMEM; 2657 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 2658 goto err_alloc_felix; 2659 } 2660 2661 pci_set_drvdata(pdev, felix); 2662 ocelot = &felix->ocelot; 2663 ocelot->dev = &pdev->dev; 2664 ocelot->num_flooding_pgids = OCELOT_NUM_TC; 2665 felix->info = &felix_info_vsc9959; 2666 felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); 2667 2668 pci_set_master(pdev); 2669 2670 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 2671 &felix_irq_handler, IRQF_ONESHOT, 2672 "felix-intb", ocelot); 2673 if (err) { 2674 dev_err(&pdev->dev, "Failed to request irq\n"); 2675 goto err_alloc_irq; 2676 } 2677 2678 ocelot->ptp = 1; 2679 ocelot->mm_supported = true; 2680 2681 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 2682 if (!ds) { 2683 err = -ENOMEM; 2684 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 2685 goto err_alloc_ds; 2686 } 2687 2688 ds->dev = &pdev->dev; 2689 ds->num_ports = felix->info->num_ports; 2690 ds->num_tx_queues = felix->info->num_tx_queues; 2691 ds->ops = &felix_switch_ops; 2692 ds->priv = ocelot; 2693 felix->ds = ds; 2694 felix->tag_proto = DSA_TAG_PROTO_OCELOT; 2695 2696 err = dsa_register_switch(ds); 2697 if (err) { 2698 dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n"); 2699 goto err_register_ds; 2700 } 2701 2702 return 0; 2703 2704 err_register_ds: 2705 kfree(ds); 2706 err_alloc_ds: 2707 err_alloc_irq: 2708 kfree(felix); 2709 err_alloc_felix: 2710 pci_disable_device(pdev); 2711 err_pci_enable: 2712 return err; 2713 } 2714 2715 static void felix_pci_remove(struct pci_dev *pdev) 2716 { 2717 struct felix *felix = pci_get_drvdata(pdev); 2718 2719 if (!felix) 2720 return; 2721 2722 dsa_unregister_switch(felix->ds); 2723 2724 kfree(felix->ds); 2725 kfree(felix); 2726 2727 pci_disable_device(pdev); 2728 } 2729 2730 static void felix_pci_shutdown(struct pci_dev *pdev) 2731 { 2732 struct felix *felix = pci_get_drvdata(pdev); 2733 2734 if (!felix) 2735 return; 2736 2737 dsa_switch_shutdown(felix->ds); 2738 2739 pci_set_drvdata(pdev, NULL); 2740 } 2741 2742 static struct pci_device_id felix_ids[] = { 2743 { 2744 /* NXP LS1028A */ 2745 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 2746 }, 2747 { 0, } 2748 }; 2749 MODULE_DEVICE_TABLE(pci, felix_ids); 2750 2751 static struct pci_driver felix_vsc9959_pci_driver = { 2752 .name = "mscc_felix", 2753 .id_table = felix_ids, 2754 .probe = felix_pci_probe, 2755 .remove = felix_pci_remove, 2756 .shutdown = felix_pci_shutdown, 2757 }; 2758 module_pci_driver(felix_vsc9959_pci_driver); 2759 2760 MODULE_DESCRIPTION("Felix Switch driver"); 2761 MODULE_LICENSE("GPL v2"); 2762