1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright 2017 Microsemi Corporation 3 * Copyright 2018-2019 NXP 4 */ 5 #include <linux/fsl/enetc_mdio.h> 6 #include <soc/mscc/ocelot_qsys.h> 7 #include <soc/mscc/ocelot_vcap.h> 8 #include <soc/mscc/ocelot_ana.h> 9 #include <soc/mscc/ocelot_ptp.h> 10 #include <soc/mscc/ocelot_sys.h> 11 #include <net/tc_act/tc_gate.h> 12 #include <soc/mscc/ocelot.h> 13 #include <linux/dsa/ocelot.h> 14 #include <linux/pcs-lynx.h> 15 #include <net/pkt_sched.h> 16 #include <linux/iopoll.h> 17 #include <linux/mdio.h> 18 #include <linux/pci.h> 19 #include <linux/time.h> 20 #include "felix.h" 21 22 #define VSC9959_NUM_PORTS 6 23 24 #define VSC9959_TAS_GCL_ENTRY_MAX 63 25 #define VSC9959_TAS_MIN_GATE_LEN_NS 33 26 #define VSC9959_VCAP_POLICER_BASE 63 27 #define VSC9959_VCAP_POLICER_MAX 383 28 #define VSC9959_SWITCH_PCI_BAR 4 29 #define VSC9959_IMDIO_PCI_BAR 0 30 31 #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ 32 OCELOT_PORT_MODE_QSGMII | \ 33 OCELOT_PORT_MODE_1000BASEX | \ 34 OCELOT_PORT_MODE_2500BASEX | \ 35 OCELOT_PORT_MODE_USXGMII) 36 37 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { 38 VSC9959_PORT_MODE_SERDES, 39 VSC9959_PORT_MODE_SERDES, 40 VSC9959_PORT_MODE_SERDES, 41 VSC9959_PORT_MODE_SERDES, 42 OCELOT_PORT_MODE_INTERNAL, 43 OCELOT_PORT_MODE_INTERNAL, 44 }; 45 46 static const u32 vsc9959_ana_regmap[] = { 47 REG(ANA_ADVLEARN, 0x0089a0), 48 REG(ANA_VLANMASK, 0x0089a4), 49 REG_RESERVED(ANA_PORT_B_DOMAIN), 50 REG(ANA_ANAGEFIL, 0x0089ac), 51 REG(ANA_ANEVENTS, 0x0089b0), 52 REG(ANA_STORMLIMIT_BURST, 0x0089b4), 53 REG(ANA_STORMLIMIT_CFG, 0x0089b8), 54 REG(ANA_ISOLATED_PORTS, 0x0089c8), 55 REG(ANA_COMMUNITY_PORTS, 0x0089cc), 56 REG(ANA_AUTOAGE, 0x0089d0), 57 REG(ANA_MACTOPTIONS, 0x0089d4), 58 REG(ANA_LEARNDISC, 0x0089d8), 59 REG(ANA_AGENCTRL, 0x0089dc), 60 REG(ANA_MIRRORPORTS, 0x0089e0), 61 REG(ANA_EMIRRORPORTS, 0x0089e4), 62 REG(ANA_FLOODING, 0x0089e8), 63 REG(ANA_FLOODING_IPMC, 0x008a08), 64 REG(ANA_SFLOW_CFG, 0x008a0c), 65 REG(ANA_PORT_MODE, 0x008a28), 66 REG(ANA_CUT_THRU_CFG, 0x008a48), 67 REG(ANA_PGID_PGID, 0x008400), 68 REG(ANA_TABLES_ANMOVED, 0x007f1c), 69 REG(ANA_TABLES_MACHDATA, 0x007f20), 70 REG(ANA_TABLES_MACLDATA, 0x007f24), 71 REG(ANA_TABLES_STREAMDATA, 0x007f28), 72 REG(ANA_TABLES_MACACCESS, 0x007f2c), 73 REG(ANA_TABLES_MACTINDX, 0x007f30), 74 REG(ANA_TABLES_VLANACCESS, 0x007f34), 75 REG(ANA_TABLES_VLANTIDX, 0x007f38), 76 REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 77 REG(ANA_TABLES_ISDXTIDX, 0x007f40), 78 REG(ANA_TABLES_ENTRYLIM, 0x007f00), 79 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 80 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 81 REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 82 REG(ANA_TABLES_STREAMTIDX, 0x007f50), 83 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 84 REG(ANA_TABLES_SEQ_MASK, 0x007f58), 85 REG(ANA_TABLES_SFID_MASK, 0x007f5c), 86 REG(ANA_TABLES_SFIDACCESS, 0x007f60), 87 REG(ANA_TABLES_SFIDTIDX, 0x007f64), 88 REG(ANA_MSTI_STATE, 0x008600), 89 REG(ANA_OAM_UPM_LM_CNT, 0x008000), 90 REG(ANA_SG_ACCESS_CTRL, 0x008a64), 91 REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 92 REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 93 REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 94 REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 95 REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 96 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 97 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 98 REG(ANA_SG_STATUS_REG_1, 0x008980), 99 REG(ANA_SG_STATUS_REG_2, 0x008984), 100 REG(ANA_SG_STATUS_REG_3, 0x008988), 101 REG(ANA_PORT_VLAN_CFG, 0x007800), 102 REG(ANA_PORT_DROP_CFG, 0x007804), 103 REG(ANA_PORT_QOS_CFG, 0x007808), 104 REG(ANA_PORT_VCAP_CFG, 0x00780c), 105 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 106 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 107 REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 108 REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 109 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 110 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 111 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 112 REG(ANA_PORT_PORT_CFG, 0x007870), 113 REG(ANA_PORT_POL_CFG, 0x007874), 114 REG(ANA_PORT_PTP_CFG, 0x007878), 115 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 116 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 117 REG(ANA_PORT_SFID_CFG, 0x007884), 118 REG(ANA_PFC_PFC_CFG, 0x008800), 119 REG_RESERVED(ANA_PFC_PFC_TIMER), 120 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 121 REG_RESERVED(ANA_IPT_IPT), 122 REG_RESERVED(ANA_PPT_PPT), 123 REG_RESERVED(ANA_FID_MAP_FID_MAP), 124 REG(ANA_AGGR_CFG, 0x008a68), 125 REG(ANA_CPUQ_CFG, 0x008a6c), 126 REG_RESERVED(ANA_CPUQ_CFG2), 127 REG(ANA_CPUQ_8021_CFG, 0x008a74), 128 REG(ANA_DSCP_CFG, 0x008ab4), 129 REG(ANA_DSCP_REWR_CFG, 0x008bb4), 130 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 131 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 132 REG_RESERVED(ANA_VRAP_CFG), 133 REG_RESERVED(ANA_VRAP_HDR_DATA), 134 REG_RESERVED(ANA_VRAP_HDR_MASK), 135 REG(ANA_DISCARD_CFG, 0x008c40), 136 REG(ANA_FID_CFG, 0x008c44), 137 REG(ANA_POL_PIR_CFG, 0x004000), 138 REG(ANA_POL_CIR_CFG, 0x004004), 139 REG(ANA_POL_MODE_CFG, 0x004008), 140 REG(ANA_POL_PIR_STATE, 0x00400c), 141 REG(ANA_POL_CIR_STATE, 0x004010), 142 REG_RESERVED(ANA_POL_STATE), 143 REG(ANA_POL_FLOWC, 0x008c48), 144 REG(ANA_POL_HYST, 0x008cb4), 145 REG_RESERVED(ANA_POL_MISC_CFG), 146 }; 147 148 static const u32 vsc9959_qs_regmap[] = { 149 REG(QS_XTR_GRP_CFG, 0x000000), 150 REG(QS_XTR_RD, 0x000008), 151 REG(QS_XTR_FRM_PRUNING, 0x000010), 152 REG(QS_XTR_FLUSH, 0x000018), 153 REG(QS_XTR_DATA_PRESENT, 0x00001c), 154 REG(QS_XTR_CFG, 0x000020), 155 REG(QS_INJ_GRP_CFG, 0x000024), 156 REG(QS_INJ_WR, 0x00002c), 157 REG(QS_INJ_CTRL, 0x000034), 158 REG(QS_INJ_STATUS, 0x00003c), 159 REG(QS_INJ_ERR, 0x000040), 160 REG_RESERVED(QS_INH_DBG), 161 }; 162 163 static const u32 vsc9959_vcap_regmap[] = { 164 /* VCAP_CORE_CFG */ 165 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 166 REG(VCAP_CORE_MV_CFG, 0x000004), 167 /* VCAP_CORE_CACHE */ 168 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 169 REG(VCAP_CACHE_MASK_DAT, 0x000108), 170 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 171 REG(VCAP_CACHE_CNT_DAT, 0x000308), 172 REG(VCAP_CACHE_TG_DAT, 0x000388), 173 /* VCAP_CONST */ 174 REG(VCAP_CONST_VCAP_VER, 0x000398), 175 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 176 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 177 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 178 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 179 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 180 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 181 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 182 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 183 REG(VCAP_CONST_IF_CNT, 0x0003bc), 184 }; 185 186 static const u32 vsc9959_qsys_regmap[] = { 187 REG(QSYS_PORT_MODE, 0x00f460), 188 REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 189 REG(QSYS_STAT_CNT_CFG, 0x00f49c), 190 REG(QSYS_EEE_CFG, 0x00f4a0), 191 REG(QSYS_EEE_THRES, 0x00f4b8), 192 REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 193 REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 194 REG(QSYS_SW_STATUS, 0x00f4c4), 195 REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 196 REG_RESERVED(QSYS_PAD_CFG), 197 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 198 REG_RESERVED(QSYS_QMAP), 199 REG_RESERVED(QSYS_ISDX_SGRP), 200 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 201 REG(QSYS_TFRM_MISC, 0x00f50c), 202 REG(QSYS_TFRM_PORT_DLY, 0x00f510), 203 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 204 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 205 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 206 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 207 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 208 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 209 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 210 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 211 REG(QSYS_RED_PROFILE, 0x00f534), 212 REG(QSYS_RES_QOS_MODE, 0x00f574), 213 REG(QSYS_RES_CFG, 0x00c000), 214 REG(QSYS_RES_STAT, 0x00c004), 215 REG(QSYS_EGR_DROP_MODE, 0x00f578), 216 REG(QSYS_EQ_CTRL, 0x00f57c), 217 REG_RESERVED(QSYS_EVENTS_CORE), 218 REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 219 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 220 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 221 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 222 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 223 REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 224 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 225 REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 226 REG(QSYS_PREEMPTION_CFG, 0x00f664), 227 REG(QSYS_CIR_CFG, 0x000000), 228 REG(QSYS_EIR_CFG, 0x000004), 229 REG(QSYS_SE_CFG, 0x000008), 230 REG(QSYS_SE_DWRR_CFG, 0x00000c), 231 REG_RESERVED(QSYS_SE_CONNECT), 232 REG(QSYS_SE_DLB_SENSE, 0x000040), 233 REG(QSYS_CIR_STATE, 0x000044), 234 REG(QSYS_EIR_STATE, 0x000048), 235 REG_RESERVED(QSYS_SE_STATE), 236 REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 237 REG(QSYS_TAG_CONFIG, 0x00f680), 238 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 239 REG(QSYS_PORT_MAX_SDU, 0x00f69c), 240 REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 241 REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 242 REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 243 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 244 REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 245 REG(QSYS_GCL_CFG_REG_1, 0x00f454), 246 REG(QSYS_GCL_CFG_REG_2, 0x00f458), 247 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 248 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 249 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 250 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 251 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 252 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 253 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 254 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 255 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 256 REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 257 REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 258 }; 259 260 static const u32 vsc9959_rew_regmap[] = { 261 REG(REW_PORT_VLAN_CFG, 0x000000), 262 REG(REW_TAG_CFG, 0x000004), 263 REG(REW_PORT_CFG, 0x000008), 264 REG(REW_DSCP_CFG, 0x00000c), 265 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 266 REG(REW_PTP_CFG, 0x000050), 267 REG(REW_PTP_DLY1_CFG, 0x000054), 268 REG(REW_RED_TAG_CFG, 0x000058), 269 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 270 REG(REW_DSCP_REMAP_CFG, 0x000510), 271 REG_RESERVED(REW_STAT_CFG), 272 REG_RESERVED(REW_REW_STICKY), 273 REG_RESERVED(REW_PPT), 274 }; 275 276 static const u32 vsc9959_sys_regmap[] = { 277 REG(SYS_COUNT_RX_OCTETS, 0x000000), 278 REG(SYS_COUNT_RX_UNICAST, 0x000004), 279 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 280 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 281 REG(SYS_COUNT_RX_SHORTS, 0x000010), 282 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 283 REG(SYS_COUNT_RX_JABBERS, 0x000018), 284 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 285 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 286 REG(SYS_COUNT_RX_64, 0x000024), 287 REG(SYS_COUNT_RX_65_127, 0x000028), 288 REG(SYS_COUNT_RX_128_255, 0x00002c), 289 REG(SYS_COUNT_RX_256_511, 0x000030), 290 REG(SYS_COUNT_RX_512_1023, 0x000034), 291 REG(SYS_COUNT_RX_1024_1526, 0x000038), 292 REG(SYS_COUNT_RX_1527_MAX, 0x00003c), 293 REG(SYS_COUNT_RX_PAUSE, 0x000040), 294 REG(SYS_COUNT_RX_CONTROL, 0x000044), 295 REG(SYS_COUNT_RX_LONGS, 0x000048), 296 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), 297 REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), 298 REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), 299 REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), 300 REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), 301 REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), 302 REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), 303 REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), 304 REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), 305 REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), 306 REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), 307 REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), 308 REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), 309 REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), 310 REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), 311 REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), 312 REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), 313 REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), 314 REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), 315 REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), 316 REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), 317 REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), 318 REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), 319 REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), 320 REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), 321 REG(SYS_COUNT_TX_OCTETS, 0x000200), 322 REG(SYS_COUNT_TX_UNICAST, 0x000204), 323 REG(SYS_COUNT_TX_MULTICAST, 0x000208), 324 REG(SYS_COUNT_TX_BROADCAST, 0x00020c), 325 REG(SYS_COUNT_TX_COLLISION, 0x000210), 326 REG(SYS_COUNT_TX_DROPS, 0x000214), 327 REG(SYS_COUNT_TX_PAUSE, 0x000218), 328 REG(SYS_COUNT_TX_64, 0x00021c), 329 REG(SYS_COUNT_TX_65_127, 0x000220), 330 REG(SYS_COUNT_TX_128_255, 0x000224), 331 REG(SYS_COUNT_TX_256_511, 0x000228), 332 REG(SYS_COUNT_TX_512_1023, 0x00022c), 333 REG(SYS_COUNT_TX_1024_1526, 0x000230), 334 REG(SYS_COUNT_TX_1527_MAX, 0x000234), 335 REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238), 336 REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c), 337 REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240), 338 REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244), 339 REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248), 340 REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c), 341 REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250), 342 REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254), 343 REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258), 344 REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c), 345 REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260), 346 REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264), 347 REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268), 348 REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c), 349 REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270), 350 REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274), 351 REG(SYS_COUNT_TX_AGED, 0x000278), 352 REG(SYS_COUNT_DROP_LOCAL, 0x000400), 353 REG(SYS_COUNT_DROP_TAIL, 0x000404), 354 REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408), 355 REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c), 356 REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410), 357 REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414), 358 REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418), 359 REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c), 360 REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420), 361 REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424), 362 REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428), 363 REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c), 364 REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430), 365 REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434), 366 REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438), 367 REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c), 368 REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440), 369 REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444), 370 REG(SYS_COUNT_SF_MATCHING_FRAMES, 0x000800), 371 REG(SYS_COUNT_SF_NOT_PASSING_FRAMES, 0x000804), 372 REG(SYS_COUNT_SF_NOT_PASSING_SDU, 0x000808), 373 REG(SYS_COUNT_SF_RED_FRAMES, 0x00080c), 374 REG(SYS_RESET_CFG, 0x000e00), 375 REG(SYS_SR_ETYPE_CFG, 0x000e04), 376 REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 377 REG(SYS_PORT_MODE, 0x000e0c), 378 REG(SYS_FRONT_PORT_MODE, 0x000e2c), 379 REG(SYS_FRM_AGING, 0x000e44), 380 REG(SYS_STAT_CFG, 0x000e48), 381 REG(SYS_SW_STATUS, 0x000e4c), 382 REG_RESERVED(SYS_MISC_CFG), 383 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 384 REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 385 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 386 REG(SYS_PAUSE_CFG, 0x000ea0), 387 REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 388 REG(SYS_ATOP, 0x000ec0), 389 REG(SYS_ATOP_TOT_CFG, 0x000edc), 390 REG(SYS_MAC_FC_CFG, 0x000ee0), 391 REG(SYS_MMGT, 0x000ef8), 392 REG_RESERVED(SYS_MMGT_FAST), 393 REG_RESERVED(SYS_EVENTS_DIF), 394 REG_RESERVED(SYS_EVENTS_CORE), 395 REG(SYS_PTP_STATUS, 0x000f14), 396 REG(SYS_PTP_TXSTAMP, 0x000f18), 397 REG(SYS_PTP_NXT, 0x000f1c), 398 REG(SYS_PTP_CFG, 0x000f20), 399 REG(SYS_RAM_INIT, 0x000f24), 400 REG_RESERVED(SYS_CM_ADDR), 401 REG_RESERVED(SYS_CM_DATA_WR), 402 REG_RESERVED(SYS_CM_DATA_RD), 403 REG_RESERVED(SYS_CM_OP), 404 REG_RESERVED(SYS_CM_DATA), 405 }; 406 407 static const u32 vsc9959_ptp_regmap[] = { 408 REG(PTP_PIN_CFG, 0x000000), 409 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 410 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 411 REG(PTP_PIN_TOD_NSEC, 0x00000c), 412 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 413 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 414 REG(PTP_CFG_MISC, 0x0000a0), 415 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 416 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 417 }; 418 419 static const u32 vsc9959_gcb_regmap[] = { 420 REG(GCB_SOFT_RST, 0x000004), 421 }; 422 423 static const u32 vsc9959_dev_gmii_regmap[] = { 424 REG(DEV_CLOCK_CFG, 0x0), 425 REG(DEV_PORT_MISC, 0x4), 426 REG(DEV_EVENTS, 0x8), 427 REG(DEV_EEE_CFG, 0xc), 428 REG(DEV_RX_PATH_DELAY, 0x10), 429 REG(DEV_TX_PATH_DELAY, 0x14), 430 REG(DEV_PTP_PREDICT_CFG, 0x18), 431 REG(DEV_MAC_ENA_CFG, 0x1c), 432 REG(DEV_MAC_MODE_CFG, 0x20), 433 REG(DEV_MAC_MAXLEN_CFG, 0x24), 434 REG(DEV_MAC_TAGS_CFG, 0x28), 435 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 436 REG(DEV_MAC_IFG_CFG, 0x30), 437 REG(DEV_MAC_HDX_CFG, 0x34), 438 REG(DEV_MAC_DBG_CFG, 0x38), 439 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 440 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 441 REG(DEV_MAC_STICKY, 0x44), 442 REG_RESERVED(PCS1G_CFG), 443 REG_RESERVED(PCS1G_MODE_CFG), 444 REG_RESERVED(PCS1G_SD_CFG), 445 REG_RESERVED(PCS1G_ANEG_CFG), 446 REG_RESERVED(PCS1G_ANEG_NP_CFG), 447 REG_RESERVED(PCS1G_LB_CFG), 448 REG_RESERVED(PCS1G_DBG_CFG), 449 REG_RESERVED(PCS1G_CDET_CFG), 450 REG_RESERVED(PCS1G_ANEG_STATUS), 451 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 452 REG_RESERVED(PCS1G_LINK_STATUS), 453 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 454 REG_RESERVED(PCS1G_STICKY), 455 REG_RESERVED(PCS1G_DEBUG_STATUS), 456 REG_RESERVED(PCS1G_LPI_CFG), 457 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 458 REG_RESERVED(PCS1G_LPI_STATUS), 459 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 460 REG_RESERVED(PCS1G_TSTPAT_STATUS), 461 REG_RESERVED(DEV_PCS_FX100_CFG), 462 REG_RESERVED(DEV_PCS_FX100_STATUS), 463 }; 464 465 static const u32 *vsc9959_regmap[TARGET_MAX] = { 466 [ANA] = vsc9959_ana_regmap, 467 [QS] = vsc9959_qs_regmap, 468 [QSYS] = vsc9959_qsys_regmap, 469 [REW] = vsc9959_rew_regmap, 470 [SYS] = vsc9959_sys_regmap, 471 [S0] = vsc9959_vcap_regmap, 472 [S1] = vsc9959_vcap_regmap, 473 [S2] = vsc9959_vcap_regmap, 474 [PTP] = vsc9959_ptp_regmap, 475 [GCB] = vsc9959_gcb_regmap, 476 [DEV_GMII] = vsc9959_dev_gmii_regmap, 477 }; 478 479 /* Addresses are relative to the PCI device's base address */ 480 static const struct resource vsc9959_resources[] = { 481 DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"), 482 DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"), 483 DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"), 484 DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"), 485 DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"), 486 DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"), 487 DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"), 488 DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"), 489 DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"), 490 DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"), 491 DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"), 492 DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"), 493 DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"), 494 DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"), 495 DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"), 496 DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"), 497 }; 498 499 static const char * const vsc9959_resource_names[TARGET_MAX] = { 500 [SYS] = "sys", 501 [REW] = "rew", 502 [S0] = "s0", 503 [S1] = "s1", 504 [S2] = "s2", 505 [GCB] = "devcpu_gcb", 506 [QS] = "qs", 507 [PTP] = "ptp", 508 [QSYS] = "qsys", 509 [ANA] = "ana", 510 }; 511 512 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 513 * SGMII/QSGMII MAC PCS can be found. 514 */ 515 static const struct resource vsc9959_imdio_res = 516 DEFINE_RES_MEM_NAMED(0x8030, 0x8040, "imdio"); 517 518 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 519 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 520 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 521 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 522 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 523 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 524 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 525 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 526 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 527 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 528 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 529 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 530 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 531 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 532 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 533 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 534 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 535 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 536 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 537 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 538 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 539 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 540 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 541 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 542 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 543 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 544 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 545 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 546 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 547 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 548 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 549 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 550 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 551 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 552 /* Replicated per number of ports (7), register size 4 per port */ 553 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 554 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 555 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 556 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 557 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 558 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 559 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 560 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 561 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 562 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 563 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 564 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 565 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 566 }; 567 568 static const struct ocelot_stat_layout vsc9959_stats_layout[OCELOT_NUM_STATS] = { 569 OCELOT_COMMON_STATS, 570 }; 571 572 static const struct vcap_field vsc9959_vcap_es0_keys[] = { 573 [VCAP_ES0_EGR_PORT] = { 0, 3}, 574 [VCAP_ES0_IGR_PORT] = { 3, 3}, 575 [VCAP_ES0_RSV] = { 6, 2}, 576 [VCAP_ES0_L2_MC] = { 8, 1}, 577 [VCAP_ES0_L2_BC] = { 9, 1}, 578 [VCAP_ES0_VID] = { 10, 12}, 579 [VCAP_ES0_DP] = { 22, 1}, 580 [VCAP_ES0_PCP] = { 23, 3}, 581 }; 582 583 static const struct vcap_field vsc9959_vcap_es0_actions[] = { 584 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 585 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 586 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 587 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 588 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 589 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 590 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 591 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 592 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 593 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 594 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 595 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 596 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 597 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 598 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 599 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 600 [VCAP_ES0_ACT_RSV] = { 49, 23}, 601 [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 602 }; 603 604 static const struct vcap_field vsc9959_vcap_is1_keys[] = { 605 [VCAP_IS1_HK_TYPE] = { 0, 1}, 606 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 607 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 608 [VCAP_IS1_HK_RSV] = { 10, 9}, 609 [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 610 [VCAP_IS1_HK_L2_MC] = { 20, 1}, 611 [VCAP_IS1_HK_L2_BC] = { 21, 1}, 612 [VCAP_IS1_HK_IP_MC] = { 22, 1}, 613 [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 614 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 615 [VCAP_IS1_HK_TPID] = { 25, 1}, 616 [VCAP_IS1_HK_VID] = { 26, 12}, 617 [VCAP_IS1_HK_DEI] = { 38, 1}, 618 [VCAP_IS1_HK_PCP] = { 39, 3}, 619 /* Specific Fields for IS1 Half Key S1_NORMAL */ 620 [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 621 [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 622 [VCAP_IS1_HK_ETYPE] = { 91, 16}, 623 [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 624 [VCAP_IS1_HK_IP4] = {108, 1}, 625 /* Layer-3 Information */ 626 [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 627 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 628 [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 629 [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 630 [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 631 /* Layer-4 Information */ 632 [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 633 [VCAP_IS1_HK_TCP] = {151, 1}, 634 [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 635 [VCAP_IS1_HK_L4_RNG] = {168, 8}, 636 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 637 [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 638 [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 639 [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 640 [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 641 [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 642 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 643 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 644 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 645 [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 646 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 647 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 648 [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 649 [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 650 [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 651 [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 652 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 653 }; 654 655 static const struct vcap_field vsc9959_vcap_is1_actions[] = { 656 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 657 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 658 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 659 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 660 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 661 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 662 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 663 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 664 [VCAP_IS1_ACT_RSV] = { 29, 9}, 665 /* The fields below are incorrectly shifted by 2 in the manual */ 666 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 667 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 668 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 669 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 670 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 671 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 672 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 673 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 674 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 675 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 676 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 677 }; 678 679 static struct vcap_field vsc9959_vcap_is2_keys[] = { 680 /* Common: 41 bits */ 681 [VCAP_IS2_TYPE] = { 0, 4}, 682 [VCAP_IS2_HK_FIRST] = { 4, 1}, 683 [VCAP_IS2_HK_PAG] = { 5, 8}, 684 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 685 [VCAP_IS2_HK_RSV2] = { 20, 1}, 686 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 687 [VCAP_IS2_HK_L2_MC] = { 22, 1}, 688 [VCAP_IS2_HK_L2_BC] = { 23, 1}, 689 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 690 [VCAP_IS2_HK_VID] = { 25, 12}, 691 [VCAP_IS2_HK_DEI] = { 37, 1}, 692 [VCAP_IS2_HK_PCP] = { 38, 3}, 693 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 694 [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 695 [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 696 /* MAC_ETYPE (TYPE=000) */ 697 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 698 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 699 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 700 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 701 /* MAC_LLC (TYPE=001) */ 702 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 703 /* MAC_SNAP (TYPE=010) */ 704 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 705 /* MAC_ARP (TYPE=011) */ 706 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 707 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 708 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 709 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 710 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 711 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 712 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 713 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 714 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 715 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 716 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 717 /* IP4_TCP_UDP / IP4_OTHER common */ 718 [VCAP_IS2_HK_IP4] = { 41, 1}, 719 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 720 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 721 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 722 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 723 [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 724 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 725 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 726 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 727 /* IP4_TCP_UDP (TYPE=100) */ 728 [VCAP_IS2_HK_TCP] = {119, 1}, 729 [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 730 [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 731 [VCAP_IS2_HK_L4_RNG] = {152, 8}, 732 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 733 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 734 [VCAP_IS2_HK_L4_FIN] = {162, 1}, 735 [VCAP_IS2_HK_L4_SYN] = {163, 1}, 736 [VCAP_IS2_HK_L4_RST] = {164, 1}, 737 [VCAP_IS2_HK_L4_PSH] = {165, 1}, 738 [VCAP_IS2_HK_L4_ACK] = {166, 1}, 739 [VCAP_IS2_HK_L4_URG] = {167, 1}, 740 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 741 [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 742 /* IP4_OTHER (TYPE=101) */ 743 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 744 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 745 /* IP6_STD (TYPE=110) */ 746 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 747 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 748 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 749 /* OAM (TYPE=111) */ 750 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 751 [VCAP_IS2_HK_OAM_VER] = {144, 5}, 752 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 753 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 754 [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 755 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 756 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 757 }; 758 759 static struct vcap_field vsc9959_vcap_is2_actions[] = { 760 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 761 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 762 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 763 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 764 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 765 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 766 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 767 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 768 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 769 [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 770 [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 771 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 772 [VCAP_IS2_ACT_RSV] = { 36, 2}, 773 [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 774 [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 775 }; 776 777 static struct vcap_props vsc9959_vcap_props[] = { 778 [VCAP_ES0] = { 779 .action_type_width = 0, 780 .action_table = { 781 [ES0_ACTION_TYPE_NORMAL] = { 782 .width = 72, /* HIT_STICKY not included */ 783 .count = 1, 784 }, 785 }, 786 .target = S0, 787 .keys = vsc9959_vcap_es0_keys, 788 .actions = vsc9959_vcap_es0_actions, 789 }, 790 [VCAP_IS1] = { 791 .action_type_width = 0, 792 .action_table = { 793 [IS1_ACTION_TYPE_NORMAL] = { 794 .width = 78, /* HIT_STICKY not included */ 795 .count = 4, 796 }, 797 }, 798 .target = S1, 799 .keys = vsc9959_vcap_is1_keys, 800 .actions = vsc9959_vcap_is1_actions, 801 }, 802 [VCAP_IS2] = { 803 .action_type_width = 1, 804 .action_table = { 805 [IS2_ACTION_TYPE_NORMAL] = { 806 .width = 44, 807 .count = 2 808 }, 809 [IS2_ACTION_TYPE_SMAC_SIP] = { 810 .width = 6, 811 .count = 4 812 }, 813 }, 814 .target = S2, 815 .keys = vsc9959_vcap_is2_keys, 816 .actions = vsc9959_vcap_is2_actions, 817 }, 818 }; 819 820 static const struct ptp_clock_info vsc9959_ptp_caps = { 821 .owner = THIS_MODULE, 822 .name = "felix ptp", 823 .max_adj = 0x7fffffff, 824 .n_alarm = 0, 825 .n_ext_ts = 0, 826 .n_per_out = OCELOT_PTP_PINS_NUM, 827 .n_pins = OCELOT_PTP_PINS_NUM, 828 .pps = 0, 829 .gettime64 = ocelot_ptp_gettime64, 830 .settime64 = ocelot_ptp_settime64, 831 .adjtime = ocelot_ptp_adjtime, 832 .adjfine = ocelot_ptp_adjfine, 833 .verify = ocelot_ptp_verify, 834 .enable = ocelot_ptp_enable, 835 }; 836 837 #define VSC9959_INIT_TIMEOUT 50000 838 #define VSC9959_GCB_RST_SLEEP 100 839 #define VSC9959_SYS_RAMINIT_SLEEP 80 840 841 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 842 { 843 int val; 844 845 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 846 847 return val; 848 } 849 850 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 851 { 852 return ocelot_read(ocelot, SYS_RAM_INIT); 853 } 854 855 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 856 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 857 */ 858 static int vsc9959_reset(struct ocelot *ocelot) 859 { 860 int val, err; 861 862 /* soft-reset the switch core */ 863 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 864 865 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 866 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 867 if (err) { 868 dev_err(ocelot->dev, "timeout: switch core reset\n"); 869 return err; 870 } 871 872 /* initialize switch mem ~40us */ 873 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 874 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 875 VSC9959_SYS_RAMINIT_SLEEP, 876 VSC9959_INIT_TIMEOUT); 877 if (err) { 878 dev_err(ocelot->dev, "timeout: switch sram init\n"); 879 return err; 880 } 881 882 /* enable switch core */ 883 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 884 885 return 0; 886 } 887 888 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port, 889 unsigned long *supported, 890 struct phylink_link_state *state) 891 { 892 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 893 894 phylink_set_port_modes(mask); 895 phylink_set(mask, Autoneg); 896 phylink_set(mask, Pause); 897 phylink_set(mask, Asym_Pause); 898 phylink_set(mask, 10baseT_Half); 899 phylink_set(mask, 10baseT_Full); 900 phylink_set(mask, 100baseT_Half); 901 phylink_set(mask, 100baseT_Full); 902 phylink_set(mask, 1000baseT_Half); 903 phylink_set(mask, 1000baseT_Full); 904 phylink_set(mask, 1000baseX_Full); 905 906 if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 907 state->interface == PHY_INTERFACE_MODE_2500BASEX || 908 state->interface == PHY_INTERFACE_MODE_USXGMII) { 909 phylink_set(mask, 2500baseT_Full); 910 phylink_set(mask, 2500baseX_Full); 911 } 912 913 linkmode_and(supported, supported, mask); 914 linkmode_and(state->advertising, state->advertising, mask); 915 } 916 917 /* Watermark encode 918 * Bit 8: Unit; 0:1, 1:16 919 * Bit 7-0: Value to be multiplied with unit 920 */ 921 static u16 vsc9959_wm_enc(u16 value) 922 { 923 WARN_ON(value >= 16 * BIT(8)); 924 925 if (value >= BIT(8)) 926 return BIT(8) | (value / 16); 927 928 return value; 929 } 930 931 static u16 vsc9959_wm_dec(u16 wm) 932 { 933 WARN_ON(wm & ~GENMASK(8, 0)); 934 935 if (wm & BIT(8)) 936 return (wm & GENMASK(7, 0)) * 16; 937 938 return wm; 939 } 940 941 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 942 { 943 *inuse = (val & GENMASK(23, 12)) >> 12; 944 *maxuse = val & GENMASK(11, 0); 945 } 946 947 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 948 { 949 struct pci_dev *pdev = to_pci_dev(ocelot->dev); 950 struct felix *felix = ocelot_to_felix(ocelot); 951 struct enetc_mdio_priv *mdio_priv; 952 struct device *dev = ocelot->dev; 953 resource_size_t imdio_base; 954 void __iomem *imdio_regs; 955 struct resource res; 956 struct enetc_hw *hw; 957 struct mii_bus *bus; 958 int port; 959 int rc; 960 961 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 962 sizeof(struct phylink_pcs *), 963 GFP_KERNEL); 964 if (!felix->pcs) { 965 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 966 return -ENOMEM; 967 } 968 969 imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); 970 971 memcpy(&res, &vsc9959_imdio_res, sizeof(res)); 972 res.start += imdio_base; 973 res.end += imdio_base; 974 975 imdio_regs = devm_ioremap_resource(dev, &res); 976 if (IS_ERR(imdio_regs)) 977 return PTR_ERR(imdio_regs); 978 979 hw = enetc_hw_alloc(dev, imdio_regs); 980 if (IS_ERR(hw)) { 981 dev_err(dev, "failed to allocate ENETC HW structure\n"); 982 return PTR_ERR(hw); 983 } 984 985 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 986 if (!bus) 987 return -ENOMEM; 988 989 bus->name = "VSC9959 internal MDIO bus"; 990 bus->read = enetc_mdio_read; 991 bus->write = enetc_mdio_write; 992 bus->parent = dev; 993 mdio_priv = bus->priv; 994 mdio_priv->hw = hw; 995 /* This gets added to imdio_regs, which already maps addresses 996 * starting with the proper offset. 997 */ 998 mdio_priv->mdio_base = 0; 999 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1000 1001 /* Needed in order to initialize the bus mutex lock */ 1002 rc = mdiobus_register(bus); 1003 if (rc < 0) { 1004 dev_err(dev, "failed to register MDIO bus\n"); 1005 mdiobus_free(bus); 1006 return rc; 1007 } 1008 1009 felix->imdio = bus; 1010 1011 for (port = 0; port < felix->info->num_ports; port++) { 1012 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1013 struct phylink_pcs *phylink_pcs; 1014 struct mdio_device *mdio_device; 1015 1016 if (dsa_is_unused_port(felix->ds, port)) 1017 continue; 1018 1019 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1020 continue; 1021 1022 mdio_device = mdio_device_create(felix->imdio, port); 1023 if (IS_ERR(mdio_device)) 1024 continue; 1025 1026 phylink_pcs = lynx_pcs_create(mdio_device); 1027 if (!phylink_pcs) { 1028 mdio_device_free(mdio_device); 1029 continue; 1030 } 1031 1032 felix->pcs[port] = phylink_pcs; 1033 1034 dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1035 } 1036 1037 return 0; 1038 } 1039 1040 static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1041 { 1042 struct felix *felix = ocelot_to_felix(ocelot); 1043 int port; 1044 1045 for (port = 0; port < ocelot->num_phys_ports; port++) { 1046 struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1047 struct mdio_device *mdio_device; 1048 1049 if (!phylink_pcs) 1050 continue; 1051 1052 mdio_device = lynx_get_mdio_device(phylink_pcs); 1053 mdio_device_free(mdio_device); 1054 lynx_pcs_destroy(phylink_pcs); 1055 } 1056 mdiobus_unregister(felix->imdio); 1057 mdiobus_free(felix->imdio); 1058 } 1059 1060 /* The switch considers any frame (regardless of size) as eligible for 1061 * transmission if the traffic class gate is open for at least 33 ns. 1062 * Overruns are prevented by cropping an interval at the end of the gate time 1063 * slot for which egress scheduling is blocked, but we need to still keep 33 ns 1064 * available for one packet to be transmitted, otherwise the port tc will hang. 1065 * This function returns the size of a gate interval that remains available for 1066 * setting the guard band, after reserving the space for one egress frame. 1067 */ 1068 static u64 vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns) 1069 { 1070 /* Gate always open */ 1071 if (gate_len_ns == U64_MAX) 1072 return U64_MAX; 1073 1074 return (gate_len_ns - VSC9959_TAS_MIN_GATE_LEN_NS) * PSEC_PER_NSEC; 1075 } 1076 1077 /* Extract shortest continuous gate open intervals in ns for each traffic class 1078 * of a cyclic tc-taprio schedule. If a gate is always open, the duration is 1079 * considered U64_MAX. If the gate is always closed, it is considered 0. 1080 */ 1081 static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio, 1082 u64 min_gate_len[OCELOT_NUM_TC]) 1083 { 1084 struct tc_taprio_sched_entry *entry; 1085 u64 gate_len[OCELOT_NUM_TC]; 1086 u8 gates_ever_opened = 0; 1087 int tc, i, n; 1088 1089 /* Initialize arrays */ 1090 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1091 min_gate_len[tc] = U64_MAX; 1092 gate_len[tc] = 0; 1093 } 1094 1095 /* If we don't have taprio, consider all gates as permanently open */ 1096 if (!taprio) 1097 return; 1098 1099 n = taprio->num_entries; 1100 1101 /* Walk through the gate list twice to determine the length 1102 * of consecutively open gates for a traffic class, including 1103 * open gates that wrap around. We are just interested in the 1104 * minimum window size, and this doesn't change what the 1105 * minimum is (if the gate never closes, min_gate_len will 1106 * remain U64_MAX). 1107 */ 1108 for (i = 0; i < 2 * n; i++) { 1109 entry = &taprio->entries[i % n]; 1110 1111 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1112 if (entry->gate_mask & BIT(tc)) { 1113 gate_len[tc] += entry->interval; 1114 gates_ever_opened |= BIT(tc); 1115 } else { 1116 /* Gate closes now, record a potential new 1117 * minimum and reinitialize length 1118 */ 1119 if (min_gate_len[tc] > gate_len[tc] && 1120 gate_len[tc]) 1121 min_gate_len[tc] = gate_len[tc]; 1122 gate_len[tc] = 0; 1123 } 1124 } 1125 } 1126 1127 /* min_gate_len[tc] actually tracks minimum *open* gate time, so for 1128 * permanently closed gates, min_gate_len[tc] will still be U64_MAX. 1129 * Therefore they are currently indistinguishable from permanently 1130 * open gates. Overwrite the gate len with 0 when we know they're 1131 * actually permanently closed, i.e. after the loop above. 1132 */ 1133 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 1134 if (!(gates_ever_opened & BIT(tc))) 1135 min_gate_len[tc] = 0; 1136 } 1137 1138 /* ocelot_write_rix is a macro that concatenates QSYS_MAXSDU_CFG_* with _RSZ, 1139 * so we need to spell out the register access to each traffic class in helper 1140 * functions, to simplify callers 1141 */ 1142 static void vsc9959_port_qmaxsdu_set(struct ocelot *ocelot, int port, int tc, 1143 u32 max_sdu) 1144 { 1145 switch (tc) { 1146 case 0: 1147 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0, 1148 port); 1149 break; 1150 case 1: 1151 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1, 1152 port); 1153 break; 1154 case 2: 1155 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2, 1156 port); 1157 break; 1158 case 3: 1159 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3, 1160 port); 1161 break; 1162 case 4: 1163 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4, 1164 port); 1165 break; 1166 case 5: 1167 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5, 1168 port); 1169 break; 1170 case 6: 1171 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6, 1172 port); 1173 break; 1174 case 7: 1175 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7, 1176 port); 1177 break; 1178 } 1179 } 1180 1181 static u32 vsc9959_port_qmaxsdu_get(struct ocelot *ocelot, int port, int tc) 1182 { 1183 switch (tc) { 1184 case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port); 1185 case 1: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_1, port); 1186 case 2: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_2, port); 1187 case 3: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_3, port); 1188 case 4: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_4, port); 1189 case 5: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_5, port); 1190 case 6: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_6, port); 1191 case 7: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_7, port); 1192 default: 1193 return 0; 1194 } 1195 } 1196 1197 static u32 vsc9959_tas_tc_max_sdu(struct tc_taprio_qopt_offload *taprio, int tc) 1198 { 1199 if (!taprio || !taprio->max_sdu[tc]) 1200 return 0; 1201 1202 return taprio->max_sdu[tc] + ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN; 1203 } 1204 1205 /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the 1206 * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU 1207 * values (the default value is 1518). Also, for traffic class windows smaller 1208 * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame 1209 * dropping, such that these won't hang the port, as they will never be sent. 1210 */ 1211 static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port) 1212 { 1213 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1214 struct tc_taprio_qopt_offload *taprio; 1215 u64 min_gate_len[OCELOT_NUM_TC]; 1216 int speed, picos_per_byte; 1217 u64 needed_bit_time_ps; 1218 u32 val, maxlen; 1219 u8 tas_speed; 1220 int tc; 1221 1222 lockdep_assert_held(&ocelot->tas_lock); 1223 1224 taprio = ocelot_port->taprio; 1225 1226 val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port); 1227 tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val); 1228 1229 switch (tas_speed) { 1230 case OCELOT_SPEED_10: 1231 speed = SPEED_10; 1232 break; 1233 case OCELOT_SPEED_100: 1234 speed = SPEED_100; 1235 break; 1236 case OCELOT_SPEED_1000: 1237 speed = SPEED_1000; 1238 break; 1239 case OCELOT_SPEED_2500: 1240 speed = SPEED_2500; 1241 break; 1242 default: 1243 return; 1244 } 1245 1246 picos_per_byte = (USEC_PER_SEC * 8) / speed; 1247 1248 val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG); 1249 /* MAXLEN_CFG accounts automatically for VLAN. We need to include it 1250 * manually in the bit time calculation, plus the preamble and SFD. 1251 */ 1252 maxlen = val + 2 * VLAN_HLEN; 1253 /* Consider the standard Ethernet overhead of 8 octets preamble+SFD, 1254 * 4 octets FCS, 12 octets IFG. 1255 */ 1256 needed_bit_time_ps = (maxlen + 24) * picos_per_byte; 1257 1258 dev_dbg(ocelot->dev, 1259 "port %d: max frame size %d needs %llu ps at speed %d\n", 1260 port, maxlen, needed_bit_time_ps, speed); 1261 1262 vsc9959_tas_min_gate_lengths(taprio, min_gate_len); 1263 1264 mutex_lock(&ocelot->fwd_domain_lock); 1265 1266 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1267 u32 requested_max_sdu = vsc9959_tas_tc_max_sdu(taprio, tc); 1268 u64 remaining_gate_len_ps; 1269 u32 max_sdu; 1270 1271 remaining_gate_len_ps = 1272 vsc9959_tas_remaining_gate_len_ps(min_gate_len[tc]); 1273 1274 if (remaining_gate_len_ps > needed_bit_time_ps) { 1275 /* Setting QMAXSDU_CFG to 0 disables oversized frame 1276 * dropping. 1277 */ 1278 max_sdu = requested_max_sdu; 1279 dev_dbg(ocelot->dev, 1280 "port %d tc %d min gate len %llu" 1281 ", sending all frames\n", 1282 port, tc, min_gate_len[tc]); 1283 } else { 1284 /* If traffic class doesn't support a full MTU sized 1285 * frame, make sure to enable oversize frame dropping 1286 * for frames larger than the smallest that would fit. 1287 * 1288 * However, the exact same register, QSYS_QMAXSDU_CFG_*, 1289 * controls not only oversized frame dropping, but also 1290 * per-tc static guard band lengths, so it reduces the 1291 * useful gate interval length. Therefore, be careful 1292 * to calculate a guard band (and therefore max_sdu) 1293 * that still leaves 33 ns available in the time slot. 1294 */ 1295 max_sdu = div_u64(remaining_gate_len_ps, picos_per_byte); 1296 /* A TC gate may be completely closed, which is a 1297 * special case where all packets are oversized. 1298 * Any limit smaller than 64 octets accomplishes this 1299 */ 1300 if (!max_sdu) 1301 max_sdu = 1; 1302 /* Take L1 overhead into account, but just don't allow 1303 * max_sdu to go negative or to 0. Here we use 20 1304 * because QSYS_MAXSDU_CFG_* already counts the 4 FCS 1305 * octets as part of packet size. 1306 */ 1307 if (max_sdu > 20) 1308 max_sdu -= 20; 1309 1310 if (requested_max_sdu && requested_max_sdu < max_sdu) 1311 max_sdu = requested_max_sdu; 1312 1313 dev_info(ocelot->dev, 1314 "port %d tc %d min gate length %llu" 1315 " ns not enough for max frame size %d at %d" 1316 " Mbps, dropping frames over %d" 1317 " octets including FCS\n", 1318 port, tc, min_gate_len[tc], maxlen, speed, 1319 max_sdu); 1320 } 1321 1322 vsc9959_port_qmaxsdu_set(ocelot, port, tc, max_sdu); 1323 } 1324 1325 ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port); 1326 1327 ocelot->ops->cut_through_fwd(ocelot); 1328 1329 mutex_unlock(&ocelot->fwd_domain_lock); 1330 } 1331 1332 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1333 u32 speed) 1334 { 1335 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1336 u8 tas_speed; 1337 1338 switch (speed) { 1339 case SPEED_10: 1340 tas_speed = OCELOT_SPEED_10; 1341 break; 1342 case SPEED_100: 1343 tas_speed = OCELOT_SPEED_100; 1344 break; 1345 case SPEED_1000: 1346 tas_speed = OCELOT_SPEED_1000; 1347 break; 1348 case SPEED_2500: 1349 tas_speed = OCELOT_SPEED_2500; 1350 break; 1351 default: 1352 tas_speed = OCELOT_SPEED_1000; 1353 break; 1354 } 1355 1356 mutex_lock(&ocelot->tas_lock); 1357 1358 ocelot_rmw_rix(ocelot, 1359 QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1360 QSYS_TAG_CONFIG_LINK_SPEED_M, 1361 QSYS_TAG_CONFIG, port); 1362 1363 if (ocelot_port->taprio) 1364 vsc9959_tas_guard_bands_update(ocelot, port); 1365 1366 mutex_unlock(&ocelot->tas_lock); 1367 } 1368 1369 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1370 u64 cycle_time, 1371 struct timespec64 *new_base_ts) 1372 { 1373 struct timespec64 ts; 1374 ktime_t new_base_time; 1375 ktime_t current_time; 1376 1377 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1378 current_time = timespec64_to_ktime(ts); 1379 new_base_time = base_time; 1380 1381 if (base_time < current_time) { 1382 u64 nr_of_cycles = current_time - base_time; 1383 1384 do_div(nr_of_cycles, cycle_time); 1385 new_base_time += cycle_time * (nr_of_cycles + 1); 1386 } 1387 1388 *new_base_ts = ktime_to_timespec64(new_base_time); 1389 } 1390 1391 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1392 { 1393 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1394 } 1395 1396 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1397 struct tc_taprio_sched_entry *entry) 1398 { 1399 ocelot_write(ocelot, 1400 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1401 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1402 QSYS_GCL_CFG_REG_1); 1403 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1404 } 1405 1406 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1407 struct tc_taprio_qopt_offload *taprio) 1408 { 1409 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1410 struct timespec64 base_ts; 1411 int ret, i; 1412 u32 val; 1413 1414 mutex_lock(&ocelot->tas_lock); 1415 1416 if (!taprio->enable) { 1417 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1418 QSYS_TAG_CONFIG, port); 1419 1420 taprio_offload_free(ocelot_port->taprio); 1421 ocelot_port->taprio = NULL; 1422 1423 vsc9959_tas_guard_bands_update(ocelot, port); 1424 1425 mutex_unlock(&ocelot->tas_lock); 1426 return 0; 1427 } 1428 1429 if (taprio->cycle_time > NSEC_PER_SEC || 1430 taprio->cycle_time_extension >= NSEC_PER_SEC) { 1431 ret = -EINVAL; 1432 goto err; 1433 } 1434 1435 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) { 1436 ret = -ERANGE; 1437 goto err; 1438 } 1439 1440 /* Enable guard band. The switch will schedule frames without taking 1441 * their length into account. Thus we'll always need to enable the 1442 * guard band which reserves the time of a maximum sized frame at the 1443 * end of the time window. 1444 * 1445 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1446 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1447 * operate on the port number. 1448 */ 1449 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1450 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1451 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1452 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1453 QSYS_TAS_PARAM_CFG_CTRL); 1454 1455 /* Hardware errata - Admin config could not be overwritten if 1456 * config is pending, need reset the TAS module 1457 */ 1458 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1459 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) { 1460 ret = -EBUSY; 1461 goto err; 1462 } 1463 1464 ocelot_rmw_rix(ocelot, 1465 QSYS_TAG_CONFIG_ENABLE | 1466 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1467 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1468 QSYS_TAG_CONFIG_ENABLE | 1469 QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1470 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1471 QSYS_TAG_CONFIG, port); 1472 1473 vsc9959_new_base_time(ocelot, taprio->base_time, 1474 taprio->cycle_time, &base_ts); 1475 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1476 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1477 val = upper_32_bits(base_ts.tv_sec); 1478 ocelot_write(ocelot, 1479 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1480 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1481 QSYS_PARAM_CFG_REG_3); 1482 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1483 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1484 1485 for (i = 0; i < taprio->num_entries; i++) 1486 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1487 1488 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1489 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1490 QSYS_TAS_PARAM_CFG_CTRL); 1491 1492 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1493 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1494 10, 100000); 1495 if (ret) 1496 goto err; 1497 1498 ocelot_port->taprio = taprio_offload_get(taprio); 1499 vsc9959_tas_guard_bands_update(ocelot, port); 1500 1501 err: 1502 mutex_unlock(&ocelot->tas_lock); 1503 1504 return ret; 1505 } 1506 1507 static void vsc9959_tas_clock_adjust(struct ocelot *ocelot) 1508 { 1509 struct tc_taprio_qopt_offload *taprio; 1510 struct ocelot_port *ocelot_port; 1511 struct timespec64 base_ts; 1512 int port; 1513 u32 val; 1514 1515 mutex_lock(&ocelot->tas_lock); 1516 1517 for (port = 0; port < ocelot->num_phys_ports; port++) { 1518 ocelot_port = ocelot->ports[port]; 1519 taprio = ocelot_port->taprio; 1520 if (!taprio) 1521 continue; 1522 1523 ocelot_rmw(ocelot, 1524 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port), 1525 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M, 1526 QSYS_TAS_PARAM_CFG_CTRL); 1527 1528 /* Disable time-aware shaper */ 1529 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1530 QSYS_TAG_CONFIG, port); 1531 1532 vsc9959_new_base_time(ocelot, taprio->base_time, 1533 taprio->cycle_time, &base_ts); 1534 1535 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1536 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), 1537 QSYS_PARAM_CFG_REG_2); 1538 val = upper_32_bits(base_ts.tv_sec); 1539 ocelot_rmw(ocelot, 1540 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val), 1541 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M, 1542 QSYS_PARAM_CFG_REG_3); 1543 1544 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1545 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1546 QSYS_TAS_PARAM_CFG_CTRL); 1547 1548 /* Re-enable time-aware shaper */ 1549 ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE, 1550 QSYS_TAG_CONFIG_ENABLE, 1551 QSYS_TAG_CONFIG, port); 1552 } 1553 mutex_unlock(&ocelot->tas_lock); 1554 } 1555 1556 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 1557 struct tc_cbs_qopt_offload *cbs_qopt) 1558 { 1559 struct ocelot *ocelot = ds->priv; 1560 int port_ix = port * 8 + cbs_qopt->queue; 1561 u32 rate, burst; 1562 1563 if (cbs_qopt->queue >= ds->num_tx_queues) 1564 return -EINVAL; 1565 1566 if (!cbs_qopt->enable) { 1567 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 1568 QSYS_CIR_CFG_CIR_BURST(0), 1569 QSYS_CIR_CFG, port_ix); 1570 1571 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 1572 QSYS_SE_CFG, port_ix); 1573 1574 return 0; 1575 } 1576 1577 /* Rate unit is 100 kbps */ 1578 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 1579 /* Avoid using zero rate */ 1580 rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 1581 /* Burst unit is 4kB */ 1582 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 1583 /* Avoid using zero burst size */ 1584 burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 1585 ocelot_write_gix(ocelot, 1586 QSYS_CIR_CFG_CIR_RATE(rate) | 1587 QSYS_CIR_CFG_CIR_BURST(burst), 1588 QSYS_CIR_CFG, 1589 port_ix); 1590 1591 ocelot_rmw_gix(ocelot, 1592 QSYS_SE_CFG_SE_FRM_MODE(0) | 1593 QSYS_SE_CFG_SE_AVB_ENA, 1594 QSYS_SE_CFG_SE_AVB_ENA | 1595 QSYS_SE_CFG_SE_FRM_MODE_M, 1596 QSYS_SE_CFG, 1597 port_ix); 1598 1599 return 0; 1600 } 1601 1602 static int vsc9959_qos_query_caps(struct tc_query_caps_base *base) 1603 { 1604 switch (base->type) { 1605 case TC_SETUP_QDISC_TAPRIO: { 1606 struct tc_taprio_caps *caps = base->caps; 1607 1608 caps->supports_queue_max_sdu = true; 1609 1610 return 0; 1611 } 1612 default: 1613 return -EOPNOTSUPP; 1614 } 1615 } 1616 1617 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1618 enum tc_setup_type type, 1619 void *type_data) 1620 { 1621 struct ocelot *ocelot = ds->priv; 1622 1623 switch (type) { 1624 case TC_QUERY_CAPS: 1625 return vsc9959_qos_query_caps(type_data); 1626 case TC_SETUP_QDISC_TAPRIO: 1627 return vsc9959_qos_port_tas_set(ocelot, port, type_data); 1628 case TC_SETUP_QDISC_CBS: 1629 return vsc9959_qos_port_cbs_set(ds, port, type_data); 1630 default: 1631 return -EOPNOTSUPP; 1632 } 1633 } 1634 1635 #define VSC9959_PSFP_SFID_MAX 175 1636 #define VSC9959_PSFP_GATE_ID_MAX 183 1637 #define VSC9959_PSFP_POLICER_BASE 63 1638 #define VSC9959_PSFP_POLICER_MAX 383 1639 #define VSC9959_PSFP_GATE_LIST_NUM 4 1640 #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 1641 1642 struct felix_stream { 1643 struct list_head list; 1644 unsigned long id; 1645 bool dummy; 1646 int ports; 1647 int port; 1648 u8 dmac[ETH_ALEN]; 1649 u16 vid; 1650 s8 prio; 1651 u8 sfid_valid; 1652 u8 ssid_valid; 1653 u32 sfid; 1654 u32 ssid; 1655 }; 1656 1657 struct felix_stream_filter_counters { 1658 u64 match; 1659 u64 not_pass_gate; 1660 u64 not_pass_sdu; 1661 u64 red; 1662 }; 1663 1664 struct felix_stream_filter { 1665 struct felix_stream_filter_counters stats; 1666 struct list_head list; 1667 refcount_t refcount; 1668 u32 index; 1669 u8 enable; 1670 int portmask; 1671 u8 sg_valid; 1672 u32 sgid; 1673 u8 fm_valid; 1674 u32 fmid; 1675 u8 prio_valid; 1676 u8 prio; 1677 u32 maxsdu; 1678 }; 1679 1680 struct felix_stream_gate { 1681 u32 index; 1682 u8 enable; 1683 u8 ipv_valid; 1684 u8 init_ipv; 1685 u64 basetime; 1686 u64 cycletime; 1687 u64 cycletime_ext; 1688 u32 num_entries; 1689 struct action_gate_entry entries[]; 1690 }; 1691 1692 struct felix_stream_gate_entry { 1693 struct list_head list; 1694 refcount_t refcount; 1695 u32 index; 1696 }; 1697 1698 static int vsc9959_stream_identify(struct flow_cls_offload *f, 1699 struct felix_stream *stream) 1700 { 1701 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 1702 struct flow_dissector *dissector = rule->match.dissector; 1703 1704 if (dissector->used_keys & 1705 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 1706 BIT(FLOW_DISSECTOR_KEY_BASIC) | 1707 BIT(FLOW_DISSECTOR_KEY_VLAN) | 1708 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 1709 return -EOPNOTSUPP; 1710 1711 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 1712 struct flow_match_eth_addrs match; 1713 1714 flow_rule_match_eth_addrs(rule, &match); 1715 ether_addr_copy(stream->dmac, match.key->dst); 1716 if (!is_zero_ether_addr(match.mask->src)) 1717 return -EOPNOTSUPP; 1718 } else { 1719 return -EOPNOTSUPP; 1720 } 1721 1722 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 1723 struct flow_match_vlan match; 1724 1725 flow_rule_match_vlan(rule, &match); 1726 if (match.mask->vlan_priority) 1727 stream->prio = match.key->vlan_priority; 1728 else 1729 stream->prio = -1; 1730 1731 if (!match.mask->vlan_id) 1732 return -EOPNOTSUPP; 1733 stream->vid = match.key->vlan_id; 1734 } else { 1735 return -EOPNOTSUPP; 1736 } 1737 1738 stream->id = f->cookie; 1739 1740 return 0; 1741 } 1742 1743 static int vsc9959_mact_stream_set(struct ocelot *ocelot, 1744 struct felix_stream *stream, 1745 struct netlink_ext_ack *extack) 1746 { 1747 enum macaccess_entry_type type; 1748 int ret, sfid, ssid; 1749 u32 vid, dst_idx; 1750 u8 mac[ETH_ALEN]; 1751 1752 ether_addr_copy(mac, stream->dmac); 1753 vid = stream->vid; 1754 1755 /* Stream identification desn't support to add a stream with non 1756 * existent MAC (The MAC entry has not been learned in MAC table). 1757 */ 1758 ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 1759 if (ret) { 1760 if (extack) 1761 NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 1762 return -EOPNOTSUPP; 1763 } 1764 1765 if ((stream->sfid_valid || stream->ssid_valid) && 1766 type == ENTRYTYPE_NORMAL) 1767 type = ENTRYTYPE_LOCKED; 1768 1769 sfid = stream->sfid_valid ? stream->sfid : -1; 1770 ssid = stream->ssid_valid ? stream->ssid : -1; 1771 1772 ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 1773 sfid, ssid); 1774 1775 return ret; 1776 } 1777 1778 static struct felix_stream * 1779 vsc9959_stream_table_lookup(struct list_head *stream_list, 1780 struct felix_stream *stream) 1781 { 1782 struct felix_stream *tmp; 1783 1784 list_for_each_entry(tmp, stream_list, list) 1785 if (ether_addr_equal(tmp->dmac, stream->dmac) && 1786 tmp->vid == stream->vid) 1787 return tmp; 1788 1789 return NULL; 1790 } 1791 1792 static int vsc9959_stream_table_add(struct ocelot *ocelot, 1793 struct list_head *stream_list, 1794 struct felix_stream *stream, 1795 struct netlink_ext_ack *extack) 1796 { 1797 struct felix_stream *stream_entry; 1798 int ret; 1799 1800 stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL); 1801 if (!stream_entry) 1802 return -ENOMEM; 1803 1804 if (!stream->dummy) { 1805 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 1806 if (ret) { 1807 kfree(stream_entry); 1808 return ret; 1809 } 1810 } 1811 1812 list_add_tail(&stream_entry->list, stream_list); 1813 1814 return 0; 1815 } 1816 1817 static struct felix_stream * 1818 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 1819 { 1820 struct felix_stream *tmp; 1821 1822 list_for_each_entry(tmp, stream_list, list) 1823 if (tmp->id == id) 1824 return tmp; 1825 1826 return NULL; 1827 } 1828 1829 static void vsc9959_stream_table_del(struct ocelot *ocelot, 1830 struct felix_stream *stream) 1831 { 1832 if (!stream->dummy) 1833 vsc9959_mact_stream_set(ocelot, stream, NULL); 1834 1835 list_del(&stream->list); 1836 kfree(stream); 1837 } 1838 1839 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 1840 { 1841 return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 1842 } 1843 1844 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 1845 struct felix_stream_filter *sfi) 1846 { 1847 u32 val; 1848 1849 if (sfi->index > VSC9959_PSFP_SFID_MAX) 1850 return -EINVAL; 1851 1852 if (!sfi->enable) { 1853 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1854 ANA_TABLES_SFIDTIDX); 1855 1856 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 1857 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 1858 1859 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1860 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1861 10, 100000); 1862 } 1863 1864 if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 1865 sfi->fmid > VSC9959_PSFP_POLICER_MAX) 1866 return -EINVAL; 1867 1868 ocelot_write(ocelot, 1869 (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 1870 ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 1871 (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 1872 ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 1873 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1874 ANA_TABLES_SFIDTIDX); 1875 1876 ocelot_write(ocelot, 1877 (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 1878 ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 1879 ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 1880 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1881 ANA_TABLES_SFIDACCESS); 1882 1883 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1884 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1885 10, 100000); 1886 } 1887 1888 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) 1889 { 1890 u32 val; 1891 1892 ocelot_rmw(ocelot, 1893 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), 1894 ANA_TABLES_SFIDTIDX_SFID_INDEX_M, 1895 ANA_TABLES_SFIDTIDX); 1896 1897 ocelot_write(ocelot, 1898 ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | 1899 ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, 1900 ANA_TABLES_SFID_MASK); 1901 1902 ocelot_rmw(ocelot, 1903 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1904 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, 1905 ANA_TABLES_SFIDACCESS); 1906 1907 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1908 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1909 10, 100000); 1910 } 1911 1912 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, 1913 struct felix_stream_filter *sfi, 1914 struct list_head *pos) 1915 { 1916 struct felix_stream_filter *sfi_entry; 1917 int ret; 1918 1919 sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL); 1920 if (!sfi_entry) 1921 return -ENOMEM; 1922 1923 refcount_set(&sfi_entry->refcount, 1); 1924 1925 ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 1926 if (ret) { 1927 kfree(sfi_entry); 1928 return ret; 1929 } 1930 1931 vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask); 1932 1933 list_add(&sfi_entry->list, pos); 1934 1935 return 0; 1936 } 1937 1938 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 1939 struct felix_stream_filter *sfi) 1940 { 1941 struct list_head *pos, *q, *last; 1942 struct felix_stream_filter *tmp; 1943 struct ocelot_psfp_list *psfp; 1944 u32 insert = 0; 1945 1946 psfp = &ocelot->psfp; 1947 last = &psfp->sfi_list; 1948 1949 list_for_each_safe(pos, q, &psfp->sfi_list) { 1950 tmp = list_entry(pos, struct felix_stream_filter, list); 1951 if (sfi->sg_valid == tmp->sg_valid && 1952 sfi->fm_valid == tmp->fm_valid && 1953 sfi->portmask == tmp->portmask && 1954 tmp->sgid == sfi->sgid && 1955 tmp->fmid == sfi->fmid) { 1956 sfi->index = tmp->index; 1957 refcount_inc(&tmp->refcount); 1958 return 0; 1959 } 1960 /* Make sure that the index is increasing in order. */ 1961 if (tmp->index == insert) { 1962 last = pos; 1963 insert++; 1964 } 1965 } 1966 sfi->index = insert; 1967 1968 return vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1969 } 1970 1971 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, 1972 struct felix_stream_filter *sfi, 1973 struct felix_stream_filter *sfi2) 1974 { 1975 struct felix_stream_filter *tmp; 1976 struct list_head *pos, *q, *last; 1977 struct ocelot_psfp_list *psfp; 1978 u32 insert = 0; 1979 int ret; 1980 1981 psfp = &ocelot->psfp; 1982 last = &psfp->sfi_list; 1983 1984 list_for_each_safe(pos, q, &psfp->sfi_list) { 1985 tmp = list_entry(pos, struct felix_stream_filter, list); 1986 /* Make sure that the index is increasing in order. */ 1987 if (tmp->index >= insert + 2) 1988 break; 1989 1990 insert = tmp->index + 1; 1991 last = pos; 1992 } 1993 sfi->index = insert; 1994 1995 ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1996 if (ret) 1997 return ret; 1998 1999 sfi2->index = insert + 1; 2000 2001 return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next); 2002 } 2003 2004 static struct felix_stream_filter * 2005 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 2006 { 2007 struct felix_stream_filter *tmp; 2008 2009 list_for_each_entry(tmp, sfi_list, list) 2010 if (tmp->index == index) 2011 return tmp; 2012 2013 return NULL; 2014 } 2015 2016 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 2017 { 2018 struct felix_stream_filter *tmp, *n; 2019 struct ocelot_psfp_list *psfp; 2020 u8 z; 2021 2022 psfp = &ocelot->psfp; 2023 2024 list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 2025 if (tmp->index == index) { 2026 z = refcount_dec_and_test(&tmp->refcount); 2027 if (z) { 2028 tmp->enable = 0; 2029 vsc9959_psfp_sfi_set(ocelot, tmp); 2030 list_del(&tmp->list); 2031 kfree(tmp); 2032 } 2033 break; 2034 } 2035 } 2036 2037 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 2038 struct felix_stream_gate *sgi) 2039 { 2040 sgi->index = entry->hw_index; 2041 sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 2042 sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 2043 sgi->basetime = entry->gate.basetime; 2044 sgi->cycletime = entry->gate.cycletime; 2045 sgi->num_entries = entry->gate.num_entries; 2046 sgi->enable = 1; 2047 2048 memcpy(sgi->entries, entry->gate.entries, 2049 entry->gate.num_entries * sizeof(struct action_gate_entry)); 2050 } 2051 2052 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 2053 { 2054 return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 2055 } 2056 2057 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 2058 struct felix_stream_gate *sgi) 2059 { 2060 struct action_gate_entry *e; 2061 struct timespec64 base_ts; 2062 u32 interval_sum = 0; 2063 u32 val; 2064 int i; 2065 2066 if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 2067 return -EINVAL; 2068 2069 ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 2070 ANA_SG_ACCESS_CTRL); 2071 2072 if (!sgi->enable) { 2073 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 2074 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2075 ANA_SG_CONFIG_REG_3_GATE_ENABLE, 2076 ANA_SG_CONFIG_REG_3); 2077 2078 return 0; 2079 } 2080 2081 if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 2082 sgi->cycletime > NSEC_PER_SEC) 2083 return -EINVAL; 2084 2085 if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 2086 return -EINVAL; 2087 2088 vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 2089 ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 2090 val = lower_32_bits(base_ts.tv_sec); 2091 ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 2092 2093 val = upper_32_bits(base_ts.tv_sec); 2094 ocelot_write(ocelot, 2095 (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 2096 ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 2097 ANA_SG_CONFIG_REG_3_GATE_ENABLE | 2098 ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 2099 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2100 ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 2101 ANA_SG_CONFIG_REG_3); 2102 2103 ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 2104 2105 e = sgi->entries; 2106 for (i = 0; i < sgi->num_entries; i++) { 2107 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 2108 2109 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 2110 (e[i].gate_state ? 2111 ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 2112 ANA_SG_GCL_GS_CONFIG, i); 2113 2114 interval_sum += e[i].interval; 2115 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 2116 } 2117 2118 ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2119 ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2120 ANA_SG_ACCESS_CTRL); 2121 2122 return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 2123 (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 2124 10, 100000); 2125 } 2126 2127 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 2128 struct felix_stream_gate *sgi) 2129 { 2130 struct felix_stream_gate_entry *tmp; 2131 struct ocelot_psfp_list *psfp; 2132 int ret; 2133 2134 psfp = &ocelot->psfp; 2135 2136 list_for_each_entry(tmp, &psfp->sgi_list, list) 2137 if (tmp->index == sgi->index) { 2138 refcount_inc(&tmp->refcount); 2139 return 0; 2140 } 2141 2142 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 2143 if (!tmp) 2144 return -ENOMEM; 2145 2146 ret = vsc9959_psfp_sgi_set(ocelot, sgi); 2147 if (ret) { 2148 kfree(tmp); 2149 return ret; 2150 } 2151 2152 tmp->index = sgi->index; 2153 refcount_set(&tmp->refcount, 1); 2154 list_add_tail(&tmp->list, &psfp->sgi_list); 2155 2156 return 0; 2157 } 2158 2159 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 2160 u32 index) 2161 { 2162 struct felix_stream_gate_entry *tmp, *n; 2163 struct felix_stream_gate sgi = {0}; 2164 struct ocelot_psfp_list *psfp; 2165 u8 z; 2166 2167 psfp = &ocelot->psfp; 2168 2169 list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 2170 if (tmp->index == index) { 2171 z = refcount_dec_and_test(&tmp->refcount); 2172 if (z) { 2173 sgi.index = index; 2174 sgi.enable = 0; 2175 vsc9959_psfp_sgi_set(ocelot, &sgi); 2176 list_del(&tmp->list); 2177 kfree(tmp); 2178 } 2179 break; 2180 } 2181 } 2182 2183 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, 2184 struct flow_cls_offload *f) 2185 { 2186 struct netlink_ext_ack *extack = f->common.extack; 2187 struct felix_stream_filter old_sfi, *sfi_entry; 2188 struct felix_stream_filter sfi = {0}; 2189 const struct flow_action_entry *a; 2190 struct felix_stream *stream_entry; 2191 struct felix_stream stream = {0}; 2192 struct felix_stream_gate *sgi; 2193 struct ocelot_psfp_list *psfp; 2194 struct ocelot_policer pol; 2195 int ret, i, size; 2196 u64 rate, burst; 2197 u32 index; 2198 2199 psfp = &ocelot->psfp; 2200 2201 ret = vsc9959_stream_identify(f, &stream); 2202 if (ret) { 2203 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 2204 return ret; 2205 } 2206 2207 mutex_lock(&psfp->lock); 2208 2209 flow_action_for_each(i, a, &f->rule->action) { 2210 switch (a->id) { 2211 case FLOW_ACTION_GATE: 2212 size = struct_size(sgi, entries, a->gate.num_entries); 2213 sgi = kzalloc(size, GFP_KERNEL); 2214 if (!sgi) { 2215 ret = -ENOMEM; 2216 goto err; 2217 } 2218 vsc9959_psfp_parse_gate(a, sgi); 2219 ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 2220 if (ret) { 2221 kfree(sgi); 2222 goto err; 2223 } 2224 sfi.sg_valid = 1; 2225 sfi.sgid = sgi->index; 2226 kfree(sgi); 2227 break; 2228 case FLOW_ACTION_POLICE: 2229 index = a->hw_index + VSC9959_PSFP_POLICER_BASE; 2230 if (index > VSC9959_PSFP_POLICER_MAX) { 2231 ret = -EINVAL; 2232 goto err; 2233 } 2234 2235 rate = a->police.rate_bytes_ps; 2236 burst = rate * PSCHED_NS2TICKS(a->police.burst); 2237 pol = (struct ocelot_policer) { 2238 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC), 2239 .rate = div_u64(rate, 1000) * 8, 2240 }; 2241 ret = ocelot_vcap_policer_add(ocelot, index, &pol); 2242 if (ret) 2243 goto err; 2244 2245 sfi.fm_valid = 1; 2246 sfi.fmid = index; 2247 sfi.maxsdu = a->police.mtu; 2248 break; 2249 default: 2250 mutex_unlock(&psfp->lock); 2251 return -EOPNOTSUPP; 2252 } 2253 } 2254 2255 stream.ports = BIT(port); 2256 stream.port = port; 2257 2258 sfi.portmask = stream.ports; 2259 sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 2260 sfi.prio = (sfi.prio_valid ? stream.prio : 0); 2261 sfi.enable = 1; 2262 2263 /* Check if stream is set. */ 2264 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 2265 if (stream_entry) { 2266 if (stream_entry->ports & BIT(port)) { 2267 NL_SET_ERR_MSG_MOD(extack, 2268 "The stream is added on this port"); 2269 ret = -EEXIST; 2270 goto err; 2271 } 2272 2273 if (stream_entry->ports != BIT(stream_entry->port)) { 2274 NL_SET_ERR_MSG_MOD(extack, 2275 "The stream is added on two ports"); 2276 ret = -EEXIST; 2277 goto err; 2278 } 2279 2280 stream_entry->ports |= BIT(port); 2281 stream.ports = stream_entry->ports; 2282 2283 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, 2284 stream_entry->sfid); 2285 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); 2286 2287 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid); 2288 2289 old_sfi.portmask = stream_entry->ports; 2290 sfi.portmask = stream.ports; 2291 2292 if (stream_entry->port > port) { 2293 ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi, 2294 &old_sfi); 2295 stream_entry->dummy = true; 2296 } else { 2297 ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi, 2298 &sfi); 2299 stream.dummy = true; 2300 } 2301 if (ret) 2302 goto err; 2303 2304 stream_entry->sfid = old_sfi.index; 2305 } else { 2306 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 2307 if (ret) 2308 goto err; 2309 } 2310 2311 stream.sfid = sfi.index; 2312 stream.sfid_valid = 1; 2313 ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 2314 &stream, extack); 2315 if (ret) { 2316 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 2317 goto err; 2318 } 2319 2320 mutex_unlock(&psfp->lock); 2321 2322 return 0; 2323 2324 err: 2325 if (sfi.sg_valid) 2326 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 2327 2328 if (sfi.fm_valid) 2329 ocelot_vcap_policer_del(ocelot, sfi.fmid); 2330 2331 mutex_unlock(&psfp->lock); 2332 2333 return ret; 2334 } 2335 2336 static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 2337 struct flow_cls_offload *f) 2338 { 2339 struct felix_stream *stream, tmp, *stream_entry; 2340 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2341 static struct felix_stream_filter *sfi; 2342 2343 mutex_lock(&psfp->lock); 2344 2345 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2346 if (!stream) { 2347 mutex_unlock(&psfp->lock); 2348 return -ENOMEM; 2349 } 2350 2351 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2352 if (!sfi) { 2353 mutex_unlock(&psfp->lock); 2354 return -ENOMEM; 2355 } 2356 2357 if (sfi->sg_valid) 2358 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 2359 2360 if (sfi->fm_valid) 2361 ocelot_vcap_policer_del(ocelot, sfi->fmid); 2362 2363 vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 2364 2365 memcpy(&tmp, stream, sizeof(tmp)); 2366 2367 stream->sfid_valid = 0; 2368 vsc9959_stream_table_del(ocelot, stream); 2369 2370 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp); 2371 if (stream_entry) { 2372 stream_entry->ports = BIT(stream_entry->port); 2373 if (stream_entry->dummy) { 2374 stream_entry->dummy = false; 2375 vsc9959_mact_stream_set(ocelot, stream_entry, NULL); 2376 } 2377 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid, 2378 stream_entry->ports); 2379 } 2380 2381 mutex_unlock(&psfp->lock); 2382 2383 return 0; 2384 } 2385 2386 static void vsc9959_update_sfid_stats(struct ocelot *ocelot, 2387 struct felix_stream_filter *sfi) 2388 { 2389 struct felix_stream_filter_counters *s = &sfi->stats; 2390 u32 match, not_pass_gate, not_pass_sdu, red; 2391 u32 sfid = sfi->index; 2392 2393 lockdep_assert_held(&ocelot->stat_view_lock); 2394 2395 ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(sfid), 2396 SYS_STAT_CFG_STAT_VIEW_M, 2397 SYS_STAT_CFG); 2398 2399 match = ocelot_read(ocelot, SYS_COUNT_SF_MATCHING_FRAMES); 2400 not_pass_gate = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_FRAMES); 2401 not_pass_sdu = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_SDU); 2402 red = ocelot_read(ocelot, SYS_COUNT_SF_RED_FRAMES); 2403 2404 /* Clear the PSFP counter. */ 2405 ocelot_write(ocelot, 2406 SYS_STAT_CFG_STAT_VIEW(sfid) | 2407 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 2408 SYS_STAT_CFG); 2409 2410 s->match += match; 2411 s->not_pass_gate += not_pass_gate; 2412 s->not_pass_sdu += not_pass_sdu; 2413 s->red += red; 2414 } 2415 2416 /* Caller must hold &ocelot->stat_view_lock */ 2417 static void vsc9959_update_stats(struct ocelot *ocelot) 2418 { 2419 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2420 struct felix_stream_filter *sfi; 2421 2422 mutex_lock(&psfp->lock); 2423 2424 list_for_each_entry(sfi, &psfp->sfi_list, list) 2425 vsc9959_update_sfid_stats(ocelot, sfi); 2426 2427 mutex_unlock(&psfp->lock); 2428 } 2429 2430 static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 2431 struct flow_cls_offload *f, 2432 struct flow_stats *stats) 2433 { 2434 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2435 struct felix_stream_filter_counters *s; 2436 static struct felix_stream_filter *sfi; 2437 struct felix_stream *stream; 2438 2439 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2440 if (!stream) 2441 return -ENOMEM; 2442 2443 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2444 if (!sfi) 2445 return -EINVAL; 2446 2447 mutex_lock(&ocelot->stat_view_lock); 2448 2449 vsc9959_update_sfid_stats(ocelot, sfi); 2450 2451 s = &sfi->stats; 2452 stats->pkts = s->match; 2453 stats->drops = s->not_pass_gate + s->not_pass_sdu + s->red; 2454 2455 memset(s, 0, sizeof(*s)); 2456 2457 mutex_unlock(&ocelot->stat_view_lock); 2458 2459 return 0; 2460 } 2461 2462 static void vsc9959_psfp_init(struct ocelot *ocelot) 2463 { 2464 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2465 2466 INIT_LIST_HEAD(&psfp->stream_list); 2467 INIT_LIST_HEAD(&psfp->sfi_list); 2468 INIT_LIST_HEAD(&psfp->sgi_list); 2469 mutex_init(&psfp->lock); 2470 } 2471 2472 /* When using cut-through forwarding and the egress port runs at a higher data 2473 * rate than the ingress port, the packet currently under transmission would 2474 * suffer an underrun since it would be transmitted faster than it is received. 2475 * The Felix switch implementation of cut-through forwarding does not check in 2476 * hardware whether this condition is satisfied or not, so we must restrict the 2477 * list of ports that have cut-through forwarding enabled on egress to only be 2478 * the ports operating at the lowest link speed within their respective 2479 * forwarding domain. 2480 */ 2481 static void vsc9959_cut_through_fwd(struct ocelot *ocelot) 2482 { 2483 struct felix *felix = ocelot_to_felix(ocelot); 2484 struct dsa_switch *ds = felix->ds; 2485 int tc, port, other_port; 2486 2487 lockdep_assert_held(&ocelot->fwd_domain_lock); 2488 2489 for (port = 0; port < ocelot->num_phys_ports; port++) { 2490 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2491 int min_speed = ocelot_port->speed; 2492 unsigned long mask = 0; 2493 u32 tmp, val = 0; 2494 2495 /* Disable cut-through on ports that are down */ 2496 if (ocelot_port->speed <= 0) 2497 goto set; 2498 2499 if (dsa_is_cpu_port(ds, port)) { 2500 /* Ocelot switches forward from the NPI port towards 2501 * any port, regardless of it being in the NPI port's 2502 * forwarding domain or not. 2503 */ 2504 mask = dsa_user_ports(ds); 2505 } else { 2506 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 2507 mask &= ~BIT(port); 2508 if (ocelot->npi >= 0) 2509 mask |= BIT(ocelot->npi); 2510 else 2511 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 2512 port); 2513 } 2514 2515 /* Calculate the minimum link speed, among the ports that are 2516 * up, of this source port's forwarding domain. 2517 */ 2518 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { 2519 struct ocelot_port *other_ocelot_port; 2520 2521 other_ocelot_port = ocelot->ports[other_port]; 2522 if (other_ocelot_port->speed <= 0) 2523 continue; 2524 2525 if (min_speed > other_ocelot_port->speed) 2526 min_speed = other_ocelot_port->speed; 2527 } 2528 2529 /* Enable cut-through forwarding for all traffic classes that 2530 * don't have oversized dropping enabled, since this check is 2531 * bypassed in cut-through mode. 2532 */ 2533 if (ocelot_port->speed == min_speed) { 2534 val = GENMASK(7, 0); 2535 2536 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 2537 if (vsc9959_port_qmaxsdu_get(ocelot, port, tc)) 2538 val &= ~BIT(tc); 2539 } 2540 2541 set: 2542 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); 2543 if (tmp == val) 2544 continue; 2545 2546 dev_dbg(ocelot->dev, 2547 "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding on TC mask 0x%x\n", 2548 port, mask, ocelot_port->speed, min_speed, 2549 val ? "enabling" : "disabling", val); 2550 2551 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); 2552 } 2553 } 2554 2555 static const struct ocelot_ops vsc9959_ops = { 2556 .reset = vsc9959_reset, 2557 .wm_enc = vsc9959_wm_enc, 2558 .wm_dec = vsc9959_wm_dec, 2559 .wm_stat = vsc9959_wm_stat, 2560 .port_to_netdev = felix_port_to_netdev, 2561 .netdev_to_port = felix_netdev_to_port, 2562 .psfp_init = vsc9959_psfp_init, 2563 .psfp_filter_add = vsc9959_psfp_filter_add, 2564 .psfp_filter_del = vsc9959_psfp_filter_del, 2565 .psfp_stats_get = vsc9959_psfp_stats_get, 2566 .cut_through_fwd = vsc9959_cut_through_fwd, 2567 .tas_clock_adjust = vsc9959_tas_clock_adjust, 2568 .update_stats = vsc9959_update_stats, 2569 }; 2570 2571 static const struct felix_info felix_info_vsc9959 = { 2572 .resources = vsc9959_resources, 2573 .num_resources = ARRAY_SIZE(vsc9959_resources), 2574 .resource_names = vsc9959_resource_names, 2575 .regfields = vsc9959_regfields, 2576 .map = vsc9959_regmap, 2577 .ops = &vsc9959_ops, 2578 .stats_layout = vsc9959_stats_layout, 2579 .vcap = vsc9959_vcap_props, 2580 .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 2581 .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 2582 .vcap_pol_base2 = 0, 2583 .vcap_pol_max2 = 0, 2584 .num_mact_rows = 2048, 2585 .num_ports = VSC9959_NUM_PORTS, 2586 .num_tx_queues = OCELOT_NUM_TC, 2587 .quirk_no_xtr_irq = true, 2588 .ptp_caps = &vsc9959_ptp_caps, 2589 .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2590 .mdio_bus_free = vsc9959_mdio_bus_free, 2591 .phylink_validate = vsc9959_phylink_validate, 2592 .port_modes = vsc9959_port_modes, 2593 .port_setup_tc = vsc9959_port_setup_tc, 2594 .port_sched_speed_set = vsc9959_sched_speed_set, 2595 .tas_guard_bands_update = vsc9959_tas_guard_bands_update, 2596 }; 2597 2598 static irqreturn_t felix_irq_handler(int irq, void *data) 2599 { 2600 struct ocelot *ocelot = (struct ocelot *)data; 2601 2602 /* The INTB interrupt is used for both PTP TX timestamp interrupt 2603 * and preemption status change interrupt on each port. 2604 * 2605 * - Get txtstamp if have 2606 * - TODO: handle preemption. Without handling it, driver may get 2607 * interrupt storm. 2608 */ 2609 2610 ocelot_get_txtstamp(ocelot); 2611 2612 return IRQ_HANDLED; 2613 } 2614 2615 static int felix_pci_probe(struct pci_dev *pdev, 2616 const struct pci_device_id *id) 2617 { 2618 struct dsa_switch *ds; 2619 struct ocelot *ocelot; 2620 struct felix *felix; 2621 int err; 2622 2623 if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 2624 dev_info(&pdev->dev, "device is disabled, skipping\n"); 2625 return -ENODEV; 2626 } 2627 2628 err = pci_enable_device(pdev); 2629 if (err) { 2630 dev_err(&pdev->dev, "device enable failed\n"); 2631 goto err_pci_enable; 2632 } 2633 2634 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 2635 if (!felix) { 2636 err = -ENOMEM; 2637 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 2638 goto err_alloc_felix; 2639 } 2640 2641 pci_set_drvdata(pdev, felix); 2642 ocelot = &felix->ocelot; 2643 ocelot->dev = &pdev->dev; 2644 ocelot->num_flooding_pgids = OCELOT_NUM_TC; 2645 felix->info = &felix_info_vsc9959; 2646 felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); 2647 2648 pci_set_master(pdev); 2649 2650 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 2651 &felix_irq_handler, IRQF_ONESHOT, 2652 "felix-intb", ocelot); 2653 if (err) { 2654 dev_err(&pdev->dev, "Failed to request irq\n"); 2655 goto err_alloc_irq; 2656 } 2657 2658 ocelot->ptp = 1; 2659 2660 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 2661 if (!ds) { 2662 err = -ENOMEM; 2663 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 2664 goto err_alloc_ds; 2665 } 2666 2667 ds->dev = &pdev->dev; 2668 ds->num_ports = felix->info->num_ports; 2669 ds->num_tx_queues = felix->info->num_tx_queues; 2670 ds->ops = &felix_switch_ops; 2671 ds->priv = ocelot; 2672 felix->ds = ds; 2673 felix->tag_proto = DSA_TAG_PROTO_OCELOT; 2674 2675 err = dsa_register_switch(ds); 2676 if (err) { 2677 dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n"); 2678 goto err_register_ds; 2679 } 2680 2681 return 0; 2682 2683 err_register_ds: 2684 kfree(ds); 2685 err_alloc_ds: 2686 err_alloc_irq: 2687 kfree(felix); 2688 err_alloc_felix: 2689 pci_disable_device(pdev); 2690 err_pci_enable: 2691 return err; 2692 } 2693 2694 static void felix_pci_remove(struct pci_dev *pdev) 2695 { 2696 struct felix *felix = pci_get_drvdata(pdev); 2697 2698 if (!felix) 2699 return; 2700 2701 dsa_unregister_switch(felix->ds); 2702 2703 kfree(felix->ds); 2704 kfree(felix); 2705 2706 pci_disable_device(pdev); 2707 } 2708 2709 static void felix_pci_shutdown(struct pci_dev *pdev) 2710 { 2711 struct felix *felix = pci_get_drvdata(pdev); 2712 2713 if (!felix) 2714 return; 2715 2716 dsa_switch_shutdown(felix->ds); 2717 2718 pci_set_drvdata(pdev, NULL); 2719 } 2720 2721 static struct pci_device_id felix_ids[] = { 2722 { 2723 /* NXP LS1028A */ 2724 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 2725 }, 2726 { 0, } 2727 }; 2728 MODULE_DEVICE_TABLE(pci, felix_ids); 2729 2730 static struct pci_driver felix_vsc9959_pci_driver = { 2731 .name = "mscc_felix", 2732 .id_table = felix_ids, 2733 .probe = felix_pci_probe, 2734 .remove = felix_pci_remove, 2735 .shutdown = felix_pci_shutdown, 2736 }; 2737 module_pci_driver(felix_vsc9959_pci_driver); 2738 2739 MODULE_DESCRIPTION("Felix Switch driver"); 2740 MODULE_LICENSE("GPL v2"); 2741