1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright 2017 Microsemi Corporation 3 * Copyright 2018-2019 NXP 4 */ 5 #include <linux/fsl/enetc_mdio.h> 6 #include <soc/mscc/ocelot_qsys.h> 7 #include <soc/mscc/ocelot_vcap.h> 8 #include <soc/mscc/ocelot_ana.h> 9 #include <soc/mscc/ocelot_dev.h> 10 #include <soc/mscc/ocelot_ptp.h> 11 #include <soc/mscc/ocelot_sys.h> 12 #include <net/tc_act/tc_gate.h> 13 #include <soc/mscc/ocelot.h> 14 #include <linux/dsa/ocelot.h> 15 #include <linux/pcs-lynx.h> 16 #include <net/pkt_sched.h> 17 #include <linux/iopoll.h> 18 #include <linux/mdio.h> 19 #include <linux/pci.h> 20 #include <linux/time.h> 21 #include "felix.h" 22 23 #define VSC9959_NUM_PORTS 6 24 25 #define VSC9959_TAS_GCL_ENTRY_MAX 63 26 #define VSC9959_TAS_MIN_GATE_LEN_NS 33 27 #define VSC9959_VCAP_POLICER_BASE 63 28 #define VSC9959_VCAP_POLICER_MAX 383 29 #define VSC9959_SWITCH_PCI_BAR 4 30 #define VSC9959_IMDIO_PCI_BAR 0 31 32 #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ 33 OCELOT_PORT_MODE_QSGMII | \ 34 OCELOT_PORT_MODE_1000BASEX | \ 35 OCELOT_PORT_MODE_2500BASEX | \ 36 OCELOT_PORT_MODE_USXGMII) 37 38 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { 39 VSC9959_PORT_MODE_SERDES, 40 VSC9959_PORT_MODE_SERDES, 41 VSC9959_PORT_MODE_SERDES, 42 VSC9959_PORT_MODE_SERDES, 43 OCELOT_PORT_MODE_INTERNAL, 44 OCELOT_PORT_MODE_INTERNAL, 45 }; 46 47 static const u32 vsc9959_ana_regmap[] = { 48 REG(ANA_ADVLEARN, 0x0089a0), 49 REG(ANA_VLANMASK, 0x0089a4), 50 REG_RESERVED(ANA_PORT_B_DOMAIN), 51 REG(ANA_ANAGEFIL, 0x0089ac), 52 REG(ANA_ANEVENTS, 0x0089b0), 53 REG(ANA_STORMLIMIT_BURST, 0x0089b4), 54 REG(ANA_STORMLIMIT_CFG, 0x0089b8), 55 REG(ANA_ISOLATED_PORTS, 0x0089c8), 56 REG(ANA_COMMUNITY_PORTS, 0x0089cc), 57 REG(ANA_AUTOAGE, 0x0089d0), 58 REG(ANA_MACTOPTIONS, 0x0089d4), 59 REG(ANA_LEARNDISC, 0x0089d8), 60 REG(ANA_AGENCTRL, 0x0089dc), 61 REG(ANA_MIRRORPORTS, 0x0089e0), 62 REG(ANA_EMIRRORPORTS, 0x0089e4), 63 REG(ANA_FLOODING, 0x0089e8), 64 REG(ANA_FLOODING_IPMC, 0x008a08), 65 REG(ANA_SFLOW_CFG, 0x008a0c), 66 REG(ANA_PORT_MODE, 0x008a28), 67 REG(ANA_CUT_THRU_CFG, 0x008a48), 68 REG(ANA_PGID_PGID, 0x008400), 69 REG(ANA_TABLES_ANMOVED, 0x007f1c), 70 REG(ANA_TABLES_MACHDATA, 0x007f20), 71 REG(ANA_TABLES_MACLDATA, 0x007f24), 72 REG(ANA_TABLES_STREAMDATA, 0x007f28), 73 REG(ANA_TABLES_MACACCESS, 0x007f2c), 74 REG(ANA_TABLES_MACTINDX, 0x007f30), 75 REG(ANA_TABLES_VLANACCESS, 0x007f34), 76 REG(ANA_TABLES_VLANTIDX, 0x007f38), 77 REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 78 REG(ANA_TABLES_ISDXTIDX, 0x007f40), 79 REG(ANA_TABLES_ENTRYLIM, 0x007f00), 80 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 81 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 82 REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 83 REG(ANA_TABLES_STREAMTIDX, 0x007f50), 84 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 85 REG(ANA_TABLES_SEQ_MASK, 0x007f58), 86 REG(ANA_TABLES_SFID_MASK, 0x007f5c), 87 REG(ANA_TABLES_SFIDACCESS, 0x007f60), 88 REG(ANA_TABLES_SFIDTIDX, 0x007f64), 89 REG(ANA_MSTI_STATE, 0x008600), 90 REG(ANA_OAM_UPM_LM_CNT, 0x008000), 91 REG(ANA_SG_ACCESS_CTRL, 0x008a64), 92 REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 93 REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 94 REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 95 REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 96 REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 97 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 98 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 99 REG(ANA_SG_STATUS_REG_1, 0x008980), 100 REG(ANA_SG_STATUS_REG_2, 0x008984), 101 REG(ANA_SG_STATUS_REG_3, 0x008988), 102 REG(ANA_PORT_VLAN_CFG, 0x007800), 103 REG(ANA_PORT_DROP_CFG, 0x007804), 104 REG(ANA_PORT_QOS_CFG, 0x007808), 105 REG(ANA_PORT_VCAP_CFG, 0x00780c), 106 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 107 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 108 REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 109 REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 110 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 111 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 112 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 113 REG(ANA_PORT_PORT_CFG, 0x007870), 114 REG(ANA_PORT_POL_CFG, 0x007874), 115 REG(ANA_PORT_PTP_CFG, 0x007878), 116 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 117 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 118 REG(ANA_PORT_SFID_CFG, 0x007884), 119 REG(ANA_PFC_PFC_CFG, 0x008800), 120 REG_RESERVED(ANA_PFC_PFC_TIMER), 121 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 122 REG_RESERVED(ANA_IPT_IPT), 123 REG_RESERVED(ANA_PPT_PPT), 124 REG_RESERVED(ANA_FID_MAP_FID_MAP), 125 REG(ANA_AGGR_CFG, 0x008a68), 126 REG(ANA_CPUQ_CFG, 0x008a6c), 127 REG_RESERVED(ANA_CPUQ_CFG2), 128 REG(ANA_CPUQ_8021_CFG, 0x008a74), 129 REG(ANA_DSCP_CFG, 0x008ab4), 130 REG(ANA_DSCP_REWR_CFG, 0x008bb4), 131 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 132 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 133 REG_RESERVED(ANA_VRAP_CFG), 134 REG_RESERVED(ANA_VRAP_HDR_DATA), 135 REG_RESERVED(ANA_VRAP_HDR_MASK), 136 REG(ANA_DISCARD_CFG, 0x008c40), 137 REG(ANA_FID_CFG, 0x008c44), 138 REG(ANA_POL_PIR_CFG, 0x004000), 139 REG(ANA_POL_CIR_CFG, 0x004004), 140 REG(ANA_POL_MODE_CFG, 0x004008), 141 REG(ANA_POL_PIR_STATE, 0x00400c), 142 REG(ANA_POL_CIR_STATE, 0x004010), 143 REG_RESERVED(ANA_POL_STATE), 144 REG(ANA_POL_FLOWC, 0x008c48), 145 REG(ANA_POL_HYST, 0x008cb4), 146 REG_RESERVED(ANA_POL_MISC_CFG), 147 }; 148 149 static const u32 vsc9959_qs_regmap[] = { 150 REG(QS_XTR_GRP_CFG, 0x000000), 151 REG(QS_XTR_RD, 0x000008), 152 REG(QS_XTR_FRM_PRUNING, 0x000010), 153 REG(QS_XTR_FLUSH, 0x000018), 154 REG(QS_XTR_DATA_PRESENT, 0x00001c), 155 REG(QS_XTR_CFG, 0x000020), 156 REG(QS_INJ_GRP_CFG, 0x000024), 157 REG(QS_INJ_WR, 0x00002c), 158 REG(QS_INJ_CTRL, 0x000034), 159 REG(QS_INJ_STATUS, 0x00003c), 160 REG(QS_INJ_ERR, 0x000040), 161 REG_RESERVED(QS_INH_DBG), 162 }; 163 164 static const u32 vsc9959_vcap_regmap[] = { 165 /* VCAP_CORE_CFG */ 166 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 167 REG(VCAP_CORE_MV_CFG, 0x000004), 168 /* VCAP_CORE_CACHE */ 169 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 170 REG(VCAP_CACHE_MASK_DAT, 0x000108), 171 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 172 REG(VCAP_CACHE_CNT_DAT, 0x000308), 173 REG(VCAP_CACHE_TG_DAT, 0x000388), 174 /* VCAP_CONST */ 175 REG(VCAP_CONST_VCAP_VER, 0x000398), 176 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 177 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 178 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 179 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 180 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 181 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 182 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 183 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 184 REG(VCAP_CONST_IF_CNT, 0x0003bc), 185 }; 186 187 static const u32 vsc9959_qsys_regmap[] = { 188 REG(QSYS_PORT_MODE, 0x00f460), 189 REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 190 REG(QSYS_STAT_CNT_CFG, 0x00f49c), 191 REG(QSYS_EEE_CFG, 0x00f4a0), 192 REG(QSYS_EEE_THRES, 0x00f4b8), 193 REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 194 REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 195 REG(QSYS_SW_STATUS, 0x00f4c4), 196 REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 197 REG_RESERVED(QSYS_PAD_CFG), 198 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 199 REG_RESERVED(QSYS_QMAP), 200 REG_RESERVED(QSYS_ISDX_SGRP), 201 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 202 REG(QSYS_TFRM_MISC, 0x00f50c), 203 REG(QSYS_TFRM_PORT_DLY, 0x00f510), 204 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 205 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 206 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 207 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 208 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 209 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 210 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 211 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 212 REG(QSYS_RED_PROFILE, 0x00f534), 213 REG(QSYS_RES_QOS_MODE, 0x00f574), 214 REG(QSYS_RES_CFG, 0x00c000), 215 REG(QSYS_RES_STAT, 0x00c004), 216 REG(QSYS_EGR_DROP_MODE, 0x00f578), 217 REG(QSYS_EQ_CTRL, 0x00f57c), 218 REG_RESERVED(QSYS_EVENTS_CORE), 219 REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 220 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 221 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 222 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 223 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 224 REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 225 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 226 REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 227 REG(QSYS_PREEMPTION_CFG, 0x00f664), 228 REG(QSYS_CIR_CFG, 0x000000), 229 REG(QSYS_EIR_CFG, 0x000004), 230 REG(QSYS_SE_CFG, 0x000008), 231 REG(QSYS_SE_DWRR_CFG, 0x00000c), 232 REG_RESERVED(QSYS_SE_CONNECT), 233 REG(QSYS_SE_DLB_SENSE, 0x000040), 234 REG(QSYS_CIR_STATE, 0x000044), 235 REG(QSYS_EIR_STATE, 0x000048), 236 REG_RESERVED(QSYS_SE_STATE), 237 REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 238 REG(QSYS_TAG_CONFIG, 0x00f680), 239 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 240 REG(QSYS_PORT_MAX_SDU, 0x00f69c), 241 REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 242 REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 243 REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 244 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 245 REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 246 REG(QSYS_GCL_CFG_REG_1, 0x00f454), 247 REG(QSYS_GCL_CFG_REG_2, 0x00f458), 248 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 249 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 250 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 251 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 252 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 253 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 254 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 255 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 256 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 257 REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 258 REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 259 }; 260 261 static const u32 vsc9959_rew_regmap[] = { 262 REG(REW_PORT_VLAN_CFG, 0x000000), 263 REG(REW_TAG_CFG, 0x000004), 264 REG(REW_PORT_CFG, 0x000008), 265 REG(REW_DSCP_CFG, 0x00000c), 266 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 267 REG(REW_PTP_CFG, 0x000050), 268 REG(REW_PTP_DLY1_CFG, 0x000054), 269 REG(REW_RED_TAG_CFG, 0x000058), 270 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 271 REG(REW_DSCP_REMAP_CFG, 0x000510), 272 REG_RESERVED(REW_STAT_CFG), 273 REG_RESERVED(REW_REW_STICKY), 274 REG_RESERVED(REW_PPT), 275 }; 276 277 static const u32 vsc9959_sys_regmap[] = { 278 REG(SYS_COUNT_RX_OCTETS, 0x000000), 279 REG(SYS_COUNT_RX_UNICAST, 0x000004), 280 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 281 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 282 REG(SYS_COUNT_RX_SHORTS, 0x000010), 283 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 284 REG(SYS_COUNT_RX_JABBERS, 0x000018), 285 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 286 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 287 REG(SYS_COUNT_RX_64, 0x000024), 288 REG(SYS_COUNT_RX_65_127, 0x000028), 289 REG(SYS_COUNT_RX_128_255, 0x00002c), 290 REG(SYS_COUNT_RX_256_511, 0x000030), 291 REG(SYS_COUNT_RX_512_1023, 0x000034), 292 REG(SYS_COUNT_RX_1024_1526, 0x000038), 293 REG(SYS_COUNT_RX_1527_MAX, 0x00003c), 294 REG(SYS_COUNT_RX_PAUSE, 0x000040), 295 REG(SYS_COUNT_RX_CONTROL, 0x000044), 296 REG(SYS_COUNT_RX_LONGS, 0x000048), 297 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), 298 REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), 299 REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), 300 REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), 301 REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), 302 REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), 303 REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), 304 REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), 305 REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), 306 REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), 307 REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), 308 REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), 309 REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), 310 REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), 311 REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), 312 REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), 313 REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), 314 REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), 315 REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), 316 REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), 317 REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), 318 REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), 319 REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), 320 REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), 321 REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), 322 REG(SYS_COUNT_RX_ASSEMBLY_ERRS, 0x0000b0), 323 REG(SYS_COUNT_RX_SMD_ERRS, 0x0000b4), 324 REG(SYS_COUNT_RX_ASSEMBLY_OK, 0x0000b8), 325 REG(SYS_COUNT_RX_MERGE_FRAGMENTS, 0x0000bc), 326 REG(SYS_COUNT_RX_PMAC_OCTETS, 0x0000c0), 327 REG(SYS_COUNT_RX_PMAC_UNICAST, 0x0000c4), 328 REG(SYS_COUNT_RX_PMAC_MULTICAST, 0x0000c8), 329 REG(SYS_COUNT_RX_PMAC_BROADCAST, 0x0000cc), 330 REG(SYS_COUNT_RX_PMAC_SHORTS, 0x0000d0), 331 REG(SYS_COUNT_RX_PMAC_FRAGMENTS, 0x0000d4), 332 REG(SYS_COUNT_RX_PMAC_JABBERS, 0x0000d8), 333 REG(SYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS, 0x0000dc), 334 REG(SYS_COUNT_RX_PMAC_SYM_ERRS, 0x0000e0), 335 REG(SYS_COUNT_RX_PMAC_64, 0x0000e4), 336 REG(SYS_COUNT_RX_PMAC_65_127, 0x0000e8), 337 REG(SYS_COUNT_RX_PMAC_128_255, 0x0000ec), 338 REG(SYS_COUNT_RX_PMAC_256_511, 0x0000f0), 339 REG(SYS_COUNT_RX_PMAC_512_1023, 0x0000f4), 340 REG(SYS_COUNT_RX_PMAC_1024_1526, 0x0000f8), 341 REG(SYS_COUNT_RX_PMAC_1527_MAX, 0x0000fc), 342 REG(SYS_COUNT_RX_PMAC_PAUSE, 0x000100), 343 REG(SYS_COUNT_RX_PMAC_CONTROL, 0x000104), 344 REG(SYS_COUNT_RX_PMAC_LONGS, 0x000108), 345 REG(SYS_COUNT_TX_OCTETS, 0x000200), 346 REG(SYS_COUNT_TX_UNICAST, 0x000204), 347 REG(SYS_COUNT_TX_MULTICAST, 0x000208), 348 REG(SYS_COUNT_TX_BROADCAST, 0x00020c), 349 REG(SYS_COUNT_TX_COLLISION, 0x000210), 350 REG(SYS_COUNT_TX_DROPS, 0x000214), 351 REG(SYS_COUNT_TX_PAUSE, 0x000218), 352 REG(SYS_COUNT_TX_64, 0x00021c), 353 REG(SYS_COUNT_TX_65_127, 0x000220), 354 REG(SYS_COUNT_TX_128_255, 0x000224), 355 REG(SYS_COUNT_TX_256_511, 0x000228), 356 REG(SYS_COUNT_TX_512_1023, 0x00022c), 357 REG(SYS_COUNT_TX_1024_1526, 0x000230), 358 REG(SYS_COUNT_TX_1527_MAX, 0x000234), 359 REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238), 360 REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c), 361 REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240), 362 REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244), 363 REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248), 364 REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c), 365 REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250), 366 REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254), 367 REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258), 368 REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c), 369 REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260), 370 REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264), 371 REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268), 372 REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c), 373 REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270), 374 REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274), 375 REG(SYS_COUNT_TX_AGED, 0x000278), 376 REG(SYS_COUNT_TX_MM_HOLD, 0x00027c), 377 REG(SYS_COUNT_TX_MERGE_FRAGMENTS, 0x000280), 378 REG(SYS_COUNT_TX_PMAC_OCTETS, 0x000284), 379 REG(SYS_COUNT_TX_PMAC_UNICAST, 0x000288), 380 REG(SYS_COUNT_TX_PMAC_MULTICAST, 0x00028c), 381 REG(SYS_COUNT_TX_PMAC_BROADCAST, 0x000290), 382 REG(SYS_COUNT_TX_PMAC_PAUSE, 0x000294), 383 REG(SYS_COUNT_TX_PMAC_64, 0x000298), 384 REG(SYS_COUNT_TX_PMAC_65_127, 0x00029c), 385 REG(SYS_COUNT_TX_PMAC_128_255, 0x0002a0), 386 REG(SYS_COUNT_TX_PMAC_256_511, 0x0002a4), 387 REG(SYS_COUNT_TX_PMAC_512_1023, 0x0002a8), 388 REG(SYS_COUNT_TX_PMAC_1024_1526, 0x0002ac), 389 REG(SYS_COUNT_TX_PMAC_1527_MAX, 0x0002b0), 390 REG(SYS_COUNT_DROP_LOCAL, 0x000400), 391 REG(SYS_COUNT_DROP_TAIL, 0x000404), 392 REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408), 393 REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c), 394 REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410), 395 REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414), 396 REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418), 397 REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c), 398 REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420), 399 REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424), 400 REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428), 401 REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c), 402 REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430), 403 REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434), 404 REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438), 405 REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c), 406 REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440), 407 REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444), 408 REG(SYS_COUNT_SF_MATCHING_FRAMES, 0x000800), 409 REG(SYS_COUNT_SF_NOT_PASSING_FRAMES, 0x000804), 410 REG(SYS_COUNT_SF_NOT_PASSING_SDU, 0x000808), 411 REG(SYS_COUNT_SF_RED_FRAMES, 0x00080c), 412 REG(SYS_RESET_CFG, 0x000e00), 413 REG(SYS_SR_ETYPE_CFG, 0x000e04), 414 REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 415 REG(SYS_PORT_MODE, 0x000e0c), 416 REG(SYS_FRONT_PORT_MODE, 0x000e2c), 417 REG(SYS_FRM_AGING, 0x000e44), 418 REG(SYS_STAT_CFG, 0x000e48), 419 REG(SYS_SW_STATUS, 0x000e4c), 420 REG_RESERVED(SYS_MISC_CFG), 421 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 422 REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 423 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 424 REG(SYS_PAUSE_CFG, 0x000ea0), 425 REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 426 REG(SYS_ATOP, 0x000ec0), 427 REG(SYS_ATOP_TOT_CFG, 0x000edc), 428 REG(SYS_MAC_FC_CFG, 0x000ee0), 429 REG(SYS_MMGT, 0x000ef8), 430 REG_RESERVED(SYS_MMGT_FAST), 431 REG_RESERVED(SYS_EVENTS_DIF), 432 REG_RESERVED(SYS_EVENTS_CORE), 433 REG(SYS_PTP_STATUS, 0x000f14), 434 REG(SYS_PTP_TXSTAMP, 0x000f18), 435 REG(SYS_PTP_NXT, 0x000f1c), 436 REG(SYS_PTP_CFG, 0x000f20), 437 REG(SYS_RAM_INIT, 0x000f24), 438 REG_RESERVED(SYS_CM_ADDR), 439 REG_RESERVED(SYS_CM_DATA_WR), 440 REG_RESERVED(SYS_CM_DATA_RD), 441 REG_RESERVED(SYS_CM_OP), 442 REG_RESERVED(SYS_CM_DATA), 443 }; 444 445 static const u32 vsc9959_ptp_regmap[] = { 446 REG(PTP_PIN_CFG, 0x000000), 447 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 448 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 449 REG(PTP_PIN_TOD_NSEC, 0x00000c), 450 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 451 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 452 REG(PTP_CFG_MISC, 0x0000a0), 453 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 454 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 455 }; 456 457 static const u32 vsc9959_gcb_regmap[] = { 458 REG(GCB_SOFT_RST, 0x000004), 459 }; 460 461 static const u32 vsc9959_dev_gmii_regmap[] = { 462 REG(DEV_CLOCK_CFG, 0x0), 463 REG(DEV_PORT_MISC, 0x4), 464 REG(DEV_EVENTS, 0x8), 465 REG(DEV_EEE_CFG, 0xc), 466 REG(DEV_RX_PATH_DELAY, 0x10), 467 REG(DEV_TX_PATH_DELAY, 0x14), 468 REG(DEV_PTP_PREDICT_CFG, 0x18), 469 REG(DEV_MAC_ENA_CFG, 0x1c), 470 REG(DEV_MAC_MODE_CFG, 0x20), 471 REG(DEV_MAC_MAXLEN_CFG, 0x24), 472 REG(DEV_MAC_TAGS_CFG, 0x28), 473 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 474 REG(DEV_MAC_IFG_CFG, 0x30), 475 REG(DEV_MAC_HDX_CFG, 0x34), 476 REG(DEV_MAC_DBG_CFG, 0x38), 477 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 478 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 479 REG(DEV_MAC_STICKY, 0x44), 480 REG(DEV_MM_ENABLE_CONFIG, 0x48), 481 REG(DEV_MM_VERIF_CONFIG, 0x4C), 482 REG(DEV_MM_STATUS, 0x50), 483 REG_RESERVED(PCS1G_CFG), 484 REG_RESERVED(PCS1G_MODE_CFG), 485 REG_RESERVED(PCS1G_SD_CFG), 486 REG_RESERVED(PCS1G_ANEG_CFG), 487 REG_RESERVED(PCS1G_ANEG_NP_CFG), 488 REG_RESERVED(PCS1G_LB_CFG), 489 REG_RESERVED(PCS1G_DBG_CFG), 490 REG_RESERVED(PCS1G_CDET_CFG), 491 REG_RESERVED(PCS1G_ANEG_STATUS), 492 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 493 REG_RESERVED(PCS1G_LINK_STATUS), 494 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 495 REG_RESERVED(PCS1G_STICKY), 496 REG_RESERVED(PCS1G_DEBUG_STATUS), 497 REG_RESERVED(PCS1G_LPI_CFG), 498 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 499 REG_RESERVED(PCS1G_LPI_STATUS), 500 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 501 REG_RESERVED(PCS1G_TSTPAT_STATUS), 502 REG_RESERVED(DEV_PCS_FX100_CFG), 503 REG_RESERVED(DEV_PCS_FX100_STATUS), 504 }; 505 506 static const u32 *vsc9959_regmap[TARGET_MAX] = { 507 [ANA] = vsc9959_ana_regmap, 508 [QS] = vsc9959_qs_regmap, 509 [QSYS] = vsc9959_qsys_regmap, 510 [REW] = vsc9959_rew_regmap, 511 [SYS] = vsc9959_sys_regmap, 512 [S0] = vsc9959_vcap_regmap, 513 [S1] = vsc9959_vcap_regmap, 514 [S2] = vsc9959_vcap_regmap, 515 [PTP] = vsc9959_ptp_regmap, 516 [GCB] = vsc9959_gcb_regmap, 517 [DEV_GMII] = vsc9959_dev_gmii_regmap, 518 }; 519 520 /* Addresses are relative to the PCI device's base address */ 521 static const struct resource vsc9959_resources[] = { 522 DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"), 523 DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"), 524 DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"), 525 DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"), 526 DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"), 527 DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"), 528 DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"), 529 DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"), 530 DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"), 531 DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"), 532 DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"), 533 DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"), 534 DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"), 535 DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"), 536 DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"), 537 DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"), 538 }; 539 540 static const char * const vsc9959_resource_names[TARGET_MAX] = { 541 [SYS] = "sys", 542 [REW] = "rew", 543 [S0] = "s0", 544 [S1] = "s1", 545 [S2] = "s2", 546 [GCB] = "devcpu_gcb", 547 [QS] = "qs", 548 [PTP] = "ptp", 549 [QSYS] = "qsys", 550 [ANA] = "ana", 551 }; 552 553 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 554 * SGMII/QSGMII MAC PCS can be found. 555 */ 556 static const struct resource vsc9959_imdio_res = 557 DEFINE_RES_MEM_NAMED(0x8030, 0x10, "imdio"); 558 559 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 560 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 561 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 562 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 563 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 564 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 565 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 566 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 567 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 568 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 569 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 570 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 571 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 572 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 573 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 574 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 575 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 576 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 577 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 578 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 579 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 580 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 581 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 582 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 583 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 584 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 585 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 586 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 587 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 588 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 589 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 590 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 591 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 592 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 593 /* Replicated per number of ports (7), register size 4 per port */ 594 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 595 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 596 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 597 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 598 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 599 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 600 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 601 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 602 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 603 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 604 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 605 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 606 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 607 }; 608 609 static const struct vcap_field vsc9959_vcap_es0_keys[] = { 610 [VCAP_ES0_EGR_PORT] = { 0, 3}, 611 [VCAP_ES0_IGR_PORT] = { 3, 3}, 612 [VCAP_ES0_RSV] = { 6, 2}, 613 [VCAP_ES0_L2_MC] = { 8, 1}, 614 [VCAP_ES0_L2_BC] = { 9, 1}, 615 [VCAP_ES0_VID] = { 10, 12}, 616 [VCAP_ES0_DP] = { 22, 1}, 617 [VCAP_ES0_PCP] = { 23, 3}, 618 }; 619 620 static const struct vcap_field vsc9959_vcap_es0_actions[] = { 621 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 622 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 623 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 624 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 625 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 626 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 627 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 628 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 629 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 630 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 631 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 632 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 633 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 634 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 635 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 636 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 637 [VCAP_ES0_ACT_RSV] = { 49, 23}, 638 [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 639 }; 640 641 static const struct vcap_field vsc9959_vcap_is1_keys[] = { 642 [VCAP_IS1_HK_TYPE] = { 0, 1}, 643 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 644 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 645 [VCAP_IS1_HK_RSV] = { 10, 9}, 646 [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 647 [VCAP_IS1_HK_L2_MC] = { 20, 1}, 648 [VCAP_IS1_HK_L2_BC] = { 21, 1}, 649 [VCAP_IS1_HK_IP_MC] = { 22, 1}, 650 [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 651 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 652 [VCAP_IS1_HK_TPID] = { 25, 1}, 653 [VCAP_IS1_HK_VID] = { 26, 12}, 654 [VCAP_IS1_HK_DEI] = { 38, 1}, 655 [VCAP_IS1_HK_PCP] = { 39, 3}, 656 /* Specific Fields for IS1 Half Key S1_NORMAL */ 657 [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 658 [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 659 [VCAP_IS1_HK_ETYPE] = { 91, 16}, 660 [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 661 [VCAP_IS1_HK_IP4] = {108, 1}, 662 /* Layer-3 Information */ 663 [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 664 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 665 [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 666 [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 667 [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 668 /* Layer-4 Information */ 669 [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 670 [VCAP_IS1_HK_TCP] = {151, 1}, 671 [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 672 [VCAP_IS1_HK_L4_RNG] = {168, 8}, 673 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 674 [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 675 [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 676 [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 677 [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 678 [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 679 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 680 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 681 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 682 [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 683 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 684 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 685 [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 686 [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 687 [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 688 [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 689 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 690 }; 691 692 static const struct vcap_field vsc9959_vcap_is1_actions[] = { 693 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 694 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 695 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 696 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 697 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 698 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 699 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 700 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 701 [VCAP_IS1_ACT_RSV] = { 29, 9}, 702 /* The fields below are incorrectly shifted by 2 in the manual */ 703 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 704 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 705 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 706 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 707 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 708 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 709 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 710 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 711 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 712 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 713 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 714 }; 715 716 static struct vcap_field vsc9959_vcap_is2_keys[] = { 717 /* Common: 41 bits */ 718 [VCAP_IS2_TYPE] = { 0, 4}, 719 [VCAP_IS2_HK_FIRST] = { 4, 1}, 720 [VCAP_IS2_HK_PAG] = { 5, 8}, 721 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 722 [VCAP_IS2_HK_RSV2] = { 20, 1}, 723 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 724 [VCAP_IS2_HK_L2_MC] = { 22, 1}, 725 [VCAP_IS2_HK_L2_BC] = { 23, 1}, 726 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 727 [VCAP_IS2_HK_VID] = { 25, 12}, 728 [VCAP_IS2_HK_DEI] = { 37, 1}, 729 [VCAP_IS2_HK_PCP] = { 38, 3}, 730 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 731 [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 732 [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 733 /* MAC_ETYPE (TYPE=000) */ 734 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 735 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 736 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 737 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 738 /* MAC_LLC (TYPE=001) */ 739 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 740 /* MAC_SNAP (TYPE=010) */ 741 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 742 /* MAC_ARP (TYPE=011) */ 743 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 744 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 745 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 746 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 747 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 748 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 749 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 750 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 751 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 752 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 753 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 754 /* IP4_TCP_UDP / IP4_OTHER common */ 755 [VCAP_IS2_HK_IP4] = { 41, 1}, 756 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 757 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 758 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 759 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 760 [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 761 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 762 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 763 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 764 /* IP4_TCP_UDP (TYPE=100) */ 765 [VCAP_IS2_HK_TCP] = {119, 1}, 766 [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 767 [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 768 [VCAP_IS2_HK_L4_RNG] = {152, 8}, 769 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 770 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 771 [VCAP_IS2_HK_L4_FIN] = {162, 1}, 772 [VCAP_IS2_HK_L4_SYN] = {163, 1}, 773 [VCAP_IS2_HK_L4_RST] = {164, 1}, 774 [VCAP_IS2_HK_L4_PSH] = {165, 1}, 775 [VCAP_IS2_HK_L4_ACK] = {166, 1}, 776 [VCAP_IS2_HK_L4_URG] = {167, 1}, 777 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 778 [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 779 /* IP4_OTHER (TYPE=101) */ 780 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 781 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 782 /* IP6_STD (TYPE=110) */ 783 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 784 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 785 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 786 /* OAM (TYPE=111) */ 787 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 788 [VCAP_IS2_HK_OAM_VER] = {144, 5}, 789 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 790 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 791 [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 792 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 793 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 794 }; 795 796 static struct vcap_field vsc9959_vcap_is2_actions[] = { 797 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 798 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 799 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 800 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 801 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 802 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 803 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 804 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 805 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 806 [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 807 [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 808 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 809 [VCAP_IS2_ACT_RSV] = { 36, 2}, 810 [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 811 [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 812 }; 813 814 static struct vcap_props vsc9959_vcap_props[] = { 815 [VCAP_ES0] = { 816 .action_type_width = 0, 817 .action_table = { 818 [ES0_ACTION_TYPE_NORMAL] = { 819 .width = 72, /* HIT_STICKY not included */ 820 .count = 1, 821 }, 822 }, 823 .target = S0, 824 .keys = vsc9959_vcap_es0_keys, 825 .actions = vsc9959_vcap_es0_actions, 826 }, 827 [VCAP_IS1] = { 828 .action_type_width = 0, 829 .action_table = { 830 [IS1_ACTION_TYPE_NORMAL] = { 831 .width = 78, /* HIT_STICKY not included */ 832 .count = 4, 833 }, 834 }, 835 .target = S1, 836 .keys = vsc9959_vcap_is1_keys, 837 .actions = vsc9959_vcap_is1_actions, 838 }, 839 [VCAP_IS2] = { 840 .action_type_width = 1, 841 .action_table = { 842 [IS2_ACTION_TYPE_NORMAL] = { 843 .width = 44, 844 .count = 2 845 }, 846 [IS2_ACTION_TYPE_SMAC_SIP] = { 847 .width = 6, 848 .count = 4 849 }, 850 }, 851 .target = S2, 852 .keys = vsc9959_vcap_is2_keys, 853 .actions = vsc9959_vcap_is2_actions, 854 }, 855 }; 856 857 static const struct ptp_clock_info vsc9959_ptp_caps = { 858 .owner = THIS_MODULE, 859 .name = "felix ptp", 860 .max_adj = 0x7fffffff, 861 .n_alarm = 0, 862 .n_ext_ts = 0, 863 .n_per_out = OCELOT_PTP_PINS_NUM, 864 .n_pins = OCELOT_PTP_PINS_NUM, 865 .pps = 0, 866 .gettime64 = ocelot_ptp_gettime64, 867 .settime64 = ocelot_ptp_settime64, 868 .adjtime = ocelot_ptp_adjtime, 869 .adjfine = ocelot_ptp_adjfine, 870 .verify = ocelot_ptp_verify, 871 .enable = ocelot_ptp_enable, 872 }; 873 874 #define VSC9959_INIT_TIMEOUT 50000 875 #define VSC9959_GCB_RST_SLEEP 100 876 #define VSC9959_SYS_RAMINIT_SLEEP 80 877 878 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 879 { 880 int val; 881 882 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 883 884 return val; 885 } 886 887 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 888 { 889 return ocelot_read(ocelot, SYS_RAM_INIT); 890 } 891 892 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 893 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 894 */ 895 static int vsc9959_reset(struct ocelot *ocelot) 896 { 897 int val, err; 898 899 /* soft-reset the switch core */ 900 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 901 902 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 903 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 904 if (err) { 905 dev_err(ocelot->dev, "timeout: switch core reset\n"); 906 return err; 907 } 908 909 /* initialize switch mem ~40us */ 910 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 911 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 912 VSC9959_SYS_RAMINIT_SLEEP, 913 VSC9959_INIT_TIMEOUT); 914 if (err) { 915 dev_err(ocelot->dev, "timeout: switch sram init\n"); 916 return err; 917 } 918 919 /* enable switch core */ 920 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 921 922 return 0; 923 } 924 925 /* Watermark encode 926 * Bit 8: Unit; 0:1, 1:16 927 * Bit 7-0: Value to be multiplied with unit 928 */ 929 static u16 vsc9959_wm_enc(u16 value) 930 { 931 WARN_ON(value >= 16 * BIT(8)); 932 933 if (value >= BIT(8)) 934 return BIT(8) | (value / 16); 935 936 return value; 937 } 938 939 static u16 vsc9959_wm_dec(u16 wm) 940 { 941 WARN_ON(wm & ~GENMASK(8, 0)); 942 943 if (wm & BIT(8)) 944 return (wm & GENMASK(7, 0)) * 16; 945 946 return wm; 947 } 948 949 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 950 { 951 *inuse = (val & GENMASK(23, 12)) >> 12; 952 *maxuse = val & GENMASK(11, 0); 953 } 954 955 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 956 { 957 struct pci_dev *pdev = to_pci_dev(ocelot->dev); 958 struct felix *felix = ocelot_to_felix(ocelot); 959 struct enetc_mdio_priv *mdio_priv; 960 struct device *dev = ocelot->dev; 961 resource_size_t imdio_base; 962 void __iomem *imdio_regs; 963 struct resource res; 964 struct enetc_hw *hw; 965 struct mii_bus *bus; 966 int port; 967 int rc; 968 969 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 970 sizeof(struct phylink_pcs *), 971 GFP_KERNEL); 972 if (!felix->pcs) { 973 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 974 return -ENOMEM; 975 } 976 977 imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); 978 979 memcpy(&res, &vsc9959_imdio_res, sizeof(res)); 980 res.start += imdio_base; 981 res.end += imdio_base; 982 983 imdio_regs = devm_ioremap_resource(dev, &res); 984 if (IS_ERR(imdio_regs)) 985 return PTR_ERR(imdio_regs); 986 987 hw = enetc_hw_alloc(dev, imdio_regs); 988 if (IS_ERR(hw)) { 989 dev_err(dev, "failed to allocate ENETC HW structure\n"); 990 return PTR_ERR(hw); 991 } 992 993 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 994 if (!bus) 995 return -ENOMEM; 996 997 bus->name = "VSC9959 internal MDIO bus"; 998 bus->read = enetc_mdio_read_c22; 999 bus->write = enetc_mdio_write_c22; 1000 bus->read_c45 = enetc_mdio_read_c45; 1001 bus->write_c45 = enetc_mdio_write_c45; 1002 bus->parent = dev; 1003 mdio_priv = bus->priv; 1004 mdio_priv->hw = hw; 1005 /* This gets added to imdio_regs, which already maps addresses 1006 * starting with the proper offset. 1007 */ 1008 mdio_priv->mdio_base = 0; 1009 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1010 1011 /* Needed in order to initialize the bus mutex lock */ 1012 rc = mdiobus_register(bus); 1013 if (rc < 0) { 1014 dev_err(dev, "failed to register MDIO bus\n"); 1015 mdiobus_free(bus); 1016 return rc; 1017 } 1018 1019 felix->imdio = bus; 1020 1021 for (port = 0; port < felix->info->num_ports; port++) { 1022 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1023 struct phylink_pcs *phylink_pcs; 1024 struct mdio_device *mdio_device; 1025 1026 if (dsa_is_unused_port(felix->ds, port)) 1027 continue; 1028 1029 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1030 continue; 1031 1032 mdio_device = mdio_device_create(felix->imdio, port); 1033 if (IS_ERR(mdio_device)) 1034 continue; 1035 1036 phylink_pcs = lynx_pcs_create(mdio_device); 1037 if (!phylink_pcs) { 1038 mdio_device_free(mdio_device); 1039 continue; 1040 } 1041 1042 felix->pcs[port] = phylink_pcs; 1043 1044 dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1045 } 1046 1047 return 0; 1048 } 1049 1050 static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1051 { 1052 struct felix *felix = ocelot_to_felix(ocelot); 1053 int port; 1054 1055 for (port = 0; port < ocelot->num_phys_ports; port++) { 1056 struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1057 struct mdio_device *mdio_device; 1058 1059 if (!phylink_pcs) 1060 continue; 1061 1062 mdio_device = lynx_get_mdio_device(phylink_pcs); 1063 mdio_device_free(mdio_device); 1064 lynx_pcs_destroy(phylink_pcs); 1065 } 1066 mdiobus_unregister(felix->imdio); 1067 mdiobus_free(felix->imdio); 1068 } 1069 1070 /* The switch considers any frame (regardless of size) as eligible for 1071 * transmission if the traffic class gate is open for at least 33 ns. 1072 * Overruns are prevented by cropping an interval at the end of the gate time 1073 * slot for which egress scheduling is blocked, but we need to still keep 33 ns 1074 * available for one packet to be transmitted, otherwise the port tc will hang. 1075 * This function returns the size of a gate interval that remains available for 1076 * setting the guard band, after reserving the space for one egress frame. 1077 */ 1078 static u64 vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns) 1079 { 1080 /* Gate always open */ 1081 if (gate_len_ns == U64_MAX) 1082 return U64_MAX; 1083 1084 return (gate_len_ns - VSC9959_TAS_MIN_GATE_LEN_NS) * PSEC_PER_NSEC; 1085 } 1086 1087 /* Extract shortest continuous gate open intervals in ns for each traffic class 1088 * of a cyclic tc-taprio schedule. If a gate is always open, the duration is 1089 * considered U64_MAX. If the gate is always closed, it is considered 0. 1090 */ 1091 static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio, 1092 u64 min_gate_len[OCELOT_NUM_TC]) 1093 { 1094 struct tc_taprio_sched_entry *entry; 1095 u64 gate_len[OCELOT_NUM_TC]; 1096 u8 gates_ever_opened = 0; 1097 int tc, i, n; 1098 1099 /* Initialize arrays */ 1100 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1101 min_gate_len[tc] = U64_MAX; 1102 gate_len[tc] = 0; 1103 } 1104 1105 /* If we don't have taprio, consider all gates as permanently open */ 1106 if (!taprio) 1107 return; 1108 1109 n = taprio->num_entries; 1110 1111 /* Walk through the gate list twice to determine the length 1112 * of consecutively open gates for a traffic class, including 1113 * open gates that wrap around. We are just interested in the 1114 * minimum window size, and this doesn't change what the 1115 * minimum is (if the gate never closes, min_gate_len will 1116 * remain U64_MAX). 1117 */ 1118 for (i = 0; i < 2 * n; i++) { 1119 entry = &taprio->entries[i % n]; 1120 1121 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1122 if (entry->gate_mask & BIT(tc)) { 1123 gate_len[tc] += entry->interval; 1124 gates_ever_opened |= BIT(tc); 1125 } else { 1126 /* Gate closes now, record a potential new 1127 * minimum and reinitialize length 1128 */ 1129 if (min_gate_len[tc] > gate_len[tc] && 1130 gate_len[tc]) 1131 min_gate_len[tc] = gate_len[tc]; 1132 gate_len[tc] = 0; 1133 } 1134 } 1135 } 1136 1137 /* min_gate_len[tc] actually tracks minimum *open* gate time, so for 1138 * permanently closed gates, min_gate_len[tc] will still be U64_MAX. 1139 * Therefore they are currently indistinguishable from permanently 1140 * open gates. Overwrite the gate len with 0 when we know they're 1141 * actually permanently closed, i.e. after the loop above. 1142 */ 1143 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 1144 if (!(gates_ever_opened & BIT(tc))) 1145 min_gate_len[tc] = 0; 1146 } 1147 1148 /* ocelot_write_rix is a macro that concatenates QSYS_MAXSDU_CFG_* with _RSZ, 1149 * so we need to spell out the register access to each traffic class in helper 1150 * functions, to simplify callers 1151 */ 1152 static void vsc9959_port_qmaxsdu_set(struct ocelot *ocelot, int port, int tc, 1153 u32 max_sdu) 1154 { 1155 switch (tc) { 1156 case 0: 1157 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0, 1158 port); 1159 break; 1160 case 1: 1161 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1, 1162 port); 1163 break; 1164 case 2: 1165 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2, 1166 port); 1167 break; 1168 case 3: 1169 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3, 1170 port); 1171 break; 1172 case 4: 1173 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4, 1174 port); 1175 break; 1176 case 5: 1177 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5, 1178 port); 1179 break; 1180 case 6: 1181 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6, 1182 port); 1183 break; 1184 case 7: 1185 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7, 1186 port); 1187 break; 1188 } 1189 } 1190 1191 static u32 vsc9959_port_qmaxsdu_get(struct ocelot *ocelot, int port, int tc) 1192 { 1193 switch (tc) { 1194 case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port); 1195 case 1: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_1, port); 1196 case 2: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_2, port); 1197 case 3: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_3, port); 1198 case 4: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_4, port); 1199 case 5: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_5, port); 1200 case 6: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_6, port); 1201 case 7: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_7, port); 1202 default: 1203 return 0; 1204 } 1205 } 1206 1207 static u32 vsc9959_tas_tc_max_sdu(struct tc_taprio_qopt_offload *taprio, int tc) 1208 { 1209 if (!taprio || !taprio->max_sdu[tc]) 1210 return 0; 1211 1212 return taprio->max_sdu[tc] + ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN; 1213 } 1214 1215 /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the 1216 * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU 1217 * values (the default value is 1518). Also, for traffic class windows smaller 1218 * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame 1219 * dropping, such that these won't hang the port, as they will never be sent. 1220 */ 1221 static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port) 1222 { 1223 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1224 struct tc_taprio_qopt_offload *taprio; 1225 u64 min_gate_len[OCELOT_NUM_TC]; 1226 int speed, picos_per_byte; 1227 u64 needed_bit_time_ps; 1228 u32 val, maxlen; 1229 u8 tas_speed; 1230 int tc; 1231 1232 lockdep_assert_held(&ocelot->tas_lock); 1233 1234 taprio = ocelot_port->taprio; 1235 1236 val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port); 1237 tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val); 1238 1239 switch (tas_speed) { 1240 case OCELOT_SPEED_10: 1241 speed = SPEED_10; 1242 break; 1243 case OCELOT_SPEED_100: 1244 speed = SPEED_100; 1245 break; 1246 case OCELOT_SPEED_1000: 1247 speed = SPEED_1000; 1248 break; 1249 case OCELOT_SPEED_2500: 1250 speed = SPEED_2500; 1251 break; 1252 default: 1253 return; 1254 } 1255 1256 picos_per_byte = (USEC_PER_SEC * 8) / speed; 1257 1258 val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG); 1259 /* MAXLEN_CFG accounts automatically for VLAN. We need to include it 1260 * manually in the bit time calculation, plus the preamble and SFD. 1261 */ 1262 maxlen = val + 2 * VLAN_HLEN; 1263 /* Consider the standard Ethernet overhead of 8 octets preamble+SFD, 1264 * 4 octets FCS, 12 octets IFG. 1265 */ 1266 needed_bit_time_ps = (u64)(maxlen + 24) * picos_per_byte; 1267 1268 dev_dbg(ocelot->dev, 1269 "port %d: max frame size %d needs %llu ps at speed %d\n", 1270 port, maxlen, needed_bit_time_ps, speed); 1271 1272 vsc9959_tas_min_gate_lengths(taprio, min_gate_len); 1273 1274 mutex_lock(&ocelot->fwd_domain_lock); 1275 1276 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1277 u32 requested_max_sdu = vsc9959_tas_tc_max_sdu(taprio, tc); 1278 u64 remaining_gate_len_ps; 1279 u32 max_sdu; 1280 1281 remaining_gate_len_ps = 1282 vsc9959_tas_remaining_gate_len_ps(min_gate_len[tc]); 1283 1284 if (remaining_gate_len_ps > needed_bit_time_ps) { 1285 /* Setting QMAXSDU_CFG to 0 disables oversized frame 1286 * dropping. 1287 */ 1288 max_sdu = requested_max_sdu; 1289 dev_dbg(ocelot->dev, 1290 "port %d tc %d min gate len %llu" 1291 ", sending all frames\n", 1292 port, tc, min_gate_len[tc]); 1293 } else { 1294 /* If traffic class doesn't support a full MTU sized 1295 * frame, make sure to enable oversize frame dropping 1296 * for frames larger than the smallest that would fit. 1297 * 1298 * However, the exact same register, QSYS_QMAXSDU_CFG_*, 1299 * controls not only oversized frame dropping, but also 1300 * per-tc static guard band lengths, so it reduces the 1301 * useful gate interval length. Therefore, be careful 1302 * to calculate a guard band (and therefore max_sdu) 1303 * that still leaves 33 ns available in the time slot. 1304 */ 1305 max_sdu = div_u64(remaining_gate_len_ps, picos_per_byte); 1306 /* A TC gate may be completely closed, which is a 1307 * special case where all packets are oversized. 1308 * Any limit smaller than 64 octets accomplishes this 1309 */ 1310 if (!max_sdu) 1311 max_sdu = 1; 1312 /* Take L1 overhead into account, but just don't allow 1313 * max_sdu to go negative or to 0. Here we use 20 1314 * because QSYS_MAXSDU_CFG_* already counts the 4 FCS 1315 * octets as part of packet size. 1316 */ 1317 if (max_sdu > 20) 1318 max_sdu -= 20; 1319 1320 if (requested_max_sdu && requested_max_sdu < max_sdu) 1321 max_sdu = requested_max_sdu; 1322 1323 dev_info(ocelot->dev, 1324 "port %d tc %d min gate length %llu" 1325 " ns not enough for max frame size %d at %d" 1326 " Mbps, dropping frames over %d" 1327 " octets including FCS\n", 1328 port, tc, min_gate_len[tc], maxlen, speed, 1329 max_sdu); 1330 } 1331 1332 vsc9959_port_qmaxsdu_set(ocelot, port, tc, max_sdu); 1333 } 1334 1335 ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port); 1336 1337 ocelot->ops->cut_through_fwd(ocelot); 1338 1339 mutex_unlock(&ocelot->fwd_domain_lock); 1340 } 1341 1342 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1343 u32 speed) 1344 { 1345 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1346 u8 tas_speed; 1347 1348 switch (speed) { 1349 case SPEED_10: 1350 tas_speed = OCELOT_SPEED_10; 1351 break; 1352 case SPEED_100: 1353 tas_speed = OCELOT_SPEED_100; 1354 break; 1355 case SPEED_1000: 1356 tas_speed = OCELOT_SPEED_1000; 1357 break; 1358 case SPEED_2500: 1359 tas_speed = OCELOT_SPEED_2500; 1360 break; 1361 default: 1362 tas_speed = OCELOT_SPEED_1000; 1363 break; 1364 } 1365 1366 mutex_lock(&ocelot->tas_lock); 1367 1368 ocelot_rmw_rix(ocelot, 1369 QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1370 QSYS_TAG_CONFIG_LINK_SPEED_M, 1371 QSYS_TAG_CONFIG, port); 1372 1373 if (ocelot_port->taprio) 1374 vsc9959_tas_guard_bands_update(ocelot, port); 1375 1376 mutex_unlock(&ocelot->tas_lock); 1377 } 1378 1379 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1380 u64 cycle_time, 1381 struct timespec64 *new_base_ts) 1382 { 1383 struct timespec64 ts; 1384 ktime_t new_base_time; 1385 ktime_t current_time; 1386 1387 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1388 current_time = timespec64_to_ktime(ts); 1389 new_base_time = base_time; 1390 1391 if (base_time < current_time) { 1392 u64 nr_of_cycles = current_time - base_time; 1393 1394 do_div(nr_of_cycles, cycle_time); 1395 new_base_time += cycle_time * (nr_of_cycles + 1); 1396 } 1397 1398 *new_base_ts = ktime_to_timespec64(new_base_time); 1399 } 1400 1401 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1402 { 1403 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1404 } 1405 1406 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1407 struct tc_taprio_sched_entry *entry) 1408 { 1409 ocelot_write(ocelot, 1410 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1411 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1412 QSYS_GCL_CFG_REG_1); 1413 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1414 } 1415 1416 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1417 struct tc_taprio_qopt_offload *taprio) 1418 { 1419 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1420 struct timespec64 base_ts; 1421 int ret, i; 1422 u32 val; 1423 1424 mutex_lock(&ocelot->tas_lock); 1425 1426 if (!taprio->enable) { 1427 ocelot_port_mqprio(ocelot, port, &taprio->mqprio); 1428 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1429 QSYS_TAG_CONFIG, port); 1430 1431 taprio_offload_free(ocelot_port->taprio); 1432 ocelot_port->taprio = NULL; 1433 1434 vsc9959_tas_guard_bands_update(ocelot, port); 1435 1436 mutex_unlock(&ocelot->tas_lock); 1437 return 0; 1438 } 1439 1440 ret = ocelot_port_mqprio(ocelot, port, &taprio->mqprio); 1441 if (ret) 1442 goto err_unlock; 1443 1444 if (taprio->cycle_time > NSEC_PER_SEC || 1445 taprio->cycle_time_extension >= NSEC_PER_SEC) { 1446 ret = -EINVAL; 1447 goto err_reset_tc; 1448 } 1449 1450 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) { 1451 ret = -ERANGE; 1452 goto err_reset_tc; 1453 } 1454 1455 /* Enable guard band. The switch will schedule frames without taking 1456 * their length into account. Thus we'll always need to enable the 1457 * guard band which reserves the time of a maximum sized frame at the 1458 * end of the time window. 1459 * 1460 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1461 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1462 * operate on the port number. 1463 */ 1464 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1465 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1466 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1467 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1468 QSYS_TAS_PARAM_CFG_CTRL); 1469 1470 /* Hardware errata - Admin config could not be overwritten if 1471 * config is pending, need reset the TAS module 1472 */ 1473 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1474 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) { 1475 ret = -EBUSY; 1476 goto err_reset_tc; 1477 } 1478 1479 ocelot_rmw_rix(ocelot, 1480 QSYS_TAG_CONFIG_ENABLE | 1481 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1482 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1483 QSYS_TAG_CONFIG_ENABLE | 1484 QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1485 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1486 QSYS_TAG_CONFIG, port); 1487 1488 vsc9959_new_base_time(ocelot, taprio->base_time, 1489 taprio->cycle_time, &base_ts); 1490 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1491 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1492 val = upper_32_bits(base_ts.tv_sec); 1493 ocelot_write(ocelot, 1494 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1495 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1496 QSYS_PARAM_CFG_REG_3); 1497 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1498 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1499 1500 for (i = 0; i < taprio->num_entries; i++) 1501 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1502 1503 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1504 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1505 QSYS_TAS_PARAM_CFG_CTRL); 1506 1507 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1508 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1509 10, 100000); 1510 if (ret) 1511 goto err_reset_tc; 1512 1513 ocelot_port->taprio = taprio_offload_get(taprio); 1514 vsc9959_tas_guard_bands_update(ocelot, port); 1515 1516 mutex_unlock(&ocelot->tas_lock); 1517 1518 return 0; 1519 1520 err_reset_tc: 1521 taprio->mqprio.qopt.num_tc = 0; 1522 ocelot_port_mqprio(ocelot, port, &taprio->mqprio); 1523 err_unlock: 1524 mutex_unlock(&ocelot->tas_lock); 1525 1526 return ret; 1527 } 1528 1529 static void vsc9959_tas_clock_adjust(struct ocelot *ocelot) 1530 { 1531 struct tc_taprio_qopt_offload *taprio; 1532 struct ocelot_port *ocelot_port; 1533 struct timespec64 base_ts; 1534 int port; 1535 u32 val; 1536 1537 mutex_lock(&ocelot->tas_lock); 1538 1539 for (port = 0; port < ocelot->num_phys_ports; port++) { 1540 ocelot_port = ocelot->ports[port]; 1541 taprio = ocelot_port->taprio; 1542 if (!taprio) 1543 continue; 1544 1545 ocelot_rmw(ocelot, 1546 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port), 1547 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M, 1548 QSYS_TAS_PARAM_CFG_CTRL); 1549 1550 /* Disable time-aware shaper */ 1551 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1552 QSYS_TAG_CONFIG, port); 1553 1554 vsc9959_new_base_time(ocelot, taprio->base_time, 1555 taprio->cycle_time, &base_ts); 1556 1557 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1558 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), 1559 QSYS_PARAM_CFG_REG_2); 1560 val = upper_32_bits(base_ts.tv_sec); 1561 ocelot_rmw(ocelot, 1562 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val), 1563 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M, 1564 QSYS_PARAM_CFG_REG_3); 1565 1566 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1567 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1568 QSYS_TAS_PARAM_CFG_CTRL); 1569 1570 /* Re-enable time-aware shaper */ 1571 ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE, 1572 QSYS_TAG_CONFIG_ENABLE, 1573 QSYS_TAG_CONFIG, port); 1574 } 1575 mutex_unlock(&ocelot->tas_lock); 1576 } 1577 1578 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 1579 struct tc_cbs_qopt_offload *cbs_qopt) 1580 { 1581 struct ocelot *ocelot = ds->priv; 1582 int port_ix = port * 8 + cbs_qopt->queue; 1583 u32 rate, burst; 1584 1585 if (cbs_qopt->queue >= ds->num_tx_queues) 1586 return -EINVAL; 1587 1588 if (!cbs_qopt->enable) { 1589 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 1590 QSYS_CIR_CFG_CIR_BURST(0), 1591 QSYS_CIR_CFG, port_ix); 1592 1593 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 1594 QSYS_SE_CFG, port_ix); 1595 1596 return 0; 1597 } 1598 1599 /* Rate unit is 100 kbps */ 1600 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 1601 /* Avoid using zero rate */ 1602 rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 1603 /* Burst unit is 4kB */ 1604 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 1605 /* Avoid using zero burst size */ 1606 burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 1607 ocelot_write_gix(ocelot, 1608 QSYS_CIR_CFG_CIR_RATE(rate) | 1609 QSYS_CIR_CFG_CIR_BURST(burst), 1610 QSYS_CIR_CFG, 1611 port_ix); 1612 1613 ocelot_rmw_gix(ocelot, 1614 QSYS_SE_CFG_SE_FRM_MODE(0) | 1615 QSYS_SE_CFG_SE_AVB_ENA, 1616 QSYS_SE_CFG_SE_AVB_ENA | 1617 QSYS_SE_CFG_SE_FRM_MODE_M, 1618 QSYS_SE_CFG, 1619 port_ix); 1620 1621 return 0; 1622 } 1623 1624 static int vsc9959_qos_query_caps(struct tc_query_caps_base *base) 1625 { 1626 switch (base->type) { 1627 case TC_SETUP_QDISC_MQPRIO: { 1628 struct tc_mqprio_caps *caps = base->caps; 1629 1630 caps->validate_queue_counts = true; 1631 1632 return 0; 1633 } 1634 case TC_SETUP_QDISC_TAPRIO: { 1635 struct tc_taprio_caps *caps = base->caps; 1636 1637 caps->supports_queue_max_sdu = true; 1638 1639 return 0; 1640 } 1641 default: 1642 return -EOPNOTSUPP; 1643 } 1644 } 1645 1646 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1647 enum tc_setup_type type, 1648 void *type_data) 1649 { 1650 struct ocelot *ocelot = ds->priv; 1651 1652 switch (type) { 1653 case TC_QUERY_CAPS: 1654 return vsc9959_qos_query_caps(type_data); 1655 case TC_SETUP_QDISC_TAPRIO: 1656 return vsc9959_qos_port_tas_set(ocelot, port, type_data); 1657 case TC_SETUP_QDISC_MQPRIO: 1658 return ocelot_port_mqprio(ocelot, port, type_data); 1659 case TC_SETUP_QDISC_CBS: 1660 return vsc9959_qos_port_cbs_set(ds, port, type_data); 1661 default: 1662 return -EOPNOTSUPP; 1663 } 1664 } 1665 1666 #define VSC9959_PSFP_SFID_MAX 175 1667 #define VSC9959_PSFP_GATE_ID_MAX 183 1668 #define VSC9959_PSFP_POLICER_BASE 63 1669 #define VSC9959_PSFP_POLICER_MAX 383 1670 #define VSC9959_PSFP_GATE_LIST_NUM 4 1671 #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 1672 1673 struct felix_stream { 1674 struct list_head list; 1675 unsigned long id; 1676 bool dummy; 1677 int ports; 1678 int port; 1679 u8 dmac[ETH_ALEN]; 1680 u16 vid; 1681 s8 prio; 1682 u8 sfid_valid; 1683 u8 ssid_valid; 1684 u32 sfid; 1685 u32 ssid; 1686 }; 1687 1688 struct felix_stream_filter_counters { 1689 u64 match; 1690 u64 not_pass_gate; 1691 u64 not_pass_sdu; 1692 u64 red; 1693 }; 1694 1695 struct felix_stream_filter { 1696 struct felix_stream_filter_counters stats; 1697 struct list_head list; 1698 refcount_t refcount; 1699 u32 index; 1700 u8 enable; 1701 int portmask; 1702 u8 sg_valid; 1703 u32 sgid; 1704 u8 fm_valid; 1705 u32 fmid; 1706 u8 prio_valid; 1707 u8 prio; 1708 u32 maxsdu; 1709 }; 1710 1711 struct felix_stream_gate { 1712 u32 index; 1713 u8 enable; 1714 u8 ipv_valid; 1715 u8 init_ipv; 1716 u64 basetime; 1717 u64 cycletime; 1718 u64 cycletime_ext; 1719 u32 num_entries; 1720 struct action_gate_entry entries[]; 1721 }; 1722 1723 struct felix_stream_gate_entry { 1724 struct list_head list; 1725 refcount_t refcount; 1726 u32 index; 1727 }; 1728 1729 static int vsc9959_stream_identify(struct flow_cls_offload *f, 1730 struct felix_stream *stream) 1731 { 1732 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 1733 struct flow_dissector *dissector = rule->match.dissector; 1734 1735 if (dissector->used_keys & 1736 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 1737 BIT(FLOW_DISSECTOR_KEY_BASIC) | 1738 BIT(FLOW_DISSECTOR_KEY_VLAN) | 1739 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 1740 return -EOPNOTSUPP; 1741 1742 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 1743 struct flow_match_eth_addrs match; 1744 1745 flow_rule_match_eth_addrs(rule, &match); 1746 ether_addr_copy(stream->dmac, match.key->dst); 1747 if (!is_zero_ether_addr(match.mask->src)) 1748 return -EOPNOTSUPP; 1749 } else { 1750 return -EOPNOTSUPP; 1751 } 1752 1753 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 1754 struct flow_match_vlan match; 1755 1756 flow_rule_match_vlan(rule, &match); 1757 if (match.mask->vlan_priority) 1758 stream->prio = match.key->vlan_priority; 1759 else 1760 stream->prio = -1; 1761 1762 if (!match.mask->vlan_id) 1763 return -EOPNOTSUPP; 1764 stream->vid = match.key->vlan_id; 1765 } else { 1766 return -EOPNOTSUPP; 1767 } 1768 1769 stream->id = f->cookie; 1770 1771 return 0; 1772 } 1773 1774 static int vsc9959_mact_stream_set(struct ocelot *ocelot, 1775 struct felix_stream *stream, 1776 struct netlink_ext_ack *extack) 1777 { 1778 enum macaccess_entry_type type; 1779 int ret, sfid, ssid; 1780 u32 vid, dst_idx; 1781 u8 mac[ETH_ALEN]; 1782 1783 ether_addr_copy(mac, stream->dmac); 1784 vid = stream->vid; 1785 1786 /* Stream identification desn't support to add a stream with non 1787 * existent MAC (The MAC entry has not been learned in MAC table). 1788 */ 1789 ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 1790 if (ret) { 1791 if (extack) 1792 NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 1793 return -EOPNOTSUPP; 1794 } 1795 1796 if ((stream->sfid_valid || stream->ssid_valid) && 1797 type == ENTRYTYPE_NORMAL) 1798 type = ENTRYTYPE_LOCKED; 1799 1800 sfid = stream->sfid_valid ? stream->sfid : -1; 1801 ssid = stream->ssid_valid ? stream->ssid : -1; 1802 1803 ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 1804 sfid, ssid); 1805 1806 return ret; 1807 } 1808 1809 static struct felix_stream * 1810 vsc9959_stream_table_lookup(struct list_head *stream_list, 1811 struct felix_stream *stream) 1812 { 1813 struct felix_stream *tmp; 1814 1815 list_for_each_entry(tmp, stream_list, list) 1816 if (ether_addr_equal(tmp->dmac, stream->dmac) && 1817 tmp->vid == stream->vid) 1818 return tmp; 1819 1820 return NULL; 1821 } 1822 1823 static int vsc9959_stream_table_add(struct ocelot *ocelot, 1824 struct list_head *stream_list, 1825 struct felix_stream *stream, 1826 struct netlink_ext_ack *extack) 1827 { 1828 struct felix_stream *stream_entry; 1829 int ret; 1830 1831 stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL); 1832 if (!stream_entry) 1833 return -ENOMEM; 1834 1835 if (!stream->dummy) { 1836 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 1837 if (ret) { 1838 kfree(stream_entry); 1839 return ret; 1840 } 1841 } 1842 1843 list_add_tail(&stream_entry->list, stream_list); 1844 1845 return 0; 1846 } 1847 1848 static struct felix_stream * 1849 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 1850 { 1851 struct felix_stream *tmp; 1852 1853 list_for_each_entry(tmp, stream_list, list) 1854 if (tmp->id == id) 1855 return tmp; 1856 1857 return NULL; 1858 } 1859 1860 static void vsc9959_stream_table_del(struct ocelot *ocelot, 1861 struct felix_stream *stream) 1862 { 1863 if (!stream->dummy) 1864 vsc9959_mact_stream_set(ocelot, stream, NULL); 1865 1866 list_del(&stream->list); 1867 kfree(stream); 1868 } 1869 1870 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 1871 { 1872 return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 1873 } 1874 1875 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 1876 struct felix_stream_filter *sfi) 1877 { 1878 u32 val; 1879 1880 if (sfi->index > VSC9959_PSFP_SFID_MAX) 1881 return -EINVAL; 1882 1883 if (!sfi->enable) { 1884 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1885 ANA_TABLES_SFIDTIDX); 1886 1887 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 1888 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 1889 1890 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1891 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1892 10, 100000); 1893 } 1894 1895 if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 1896 sfi->fmid > VSC9959_PSFP_POLICER_MAX) 1897 return -EINVAL; 1898 1899 ocelot_write(ocelot, 1900 (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 1901 ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 1902 (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 1903 ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 1904 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1905 ANA_TABLES_SFIDTIDX); 1906 1907 ocelot_write(ocelot, 1908 (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 1909 ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 1910 ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 1911 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1912 ANA_TABLES_SFIDACCESS); 1913 1914 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1915 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1916 10, 100000); 1917 } 1918 1919 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) 1920 { 1921 u32 val; 1922 1923 ocelot_rmw(ocelot, 1924 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), 1925 ANA_TABLES_SFIDTIDX_SFID_INDEX_M, 1926 ANA_TABLES_SFIDTIDX); 1927 1928 ocelot_write(ocelot, 1929 ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | 1930 ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, 1931 ANA_TABLES_SFID_MASK); 1932 1933 ocelot_rmw(ocelot, 1934 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1935 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, 1936 ANA_TABLES_SFIDACCESS); 1937 1938 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1939 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1940 10, 100000); 1941 } 1942 1943 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, 1944 struct felix_stream_filter *sfi, 1945 struct list_head *pos) 1946 { 1947 struct felix_stream_filter *sfi_entry; 1948 int ret; 1949 1950 sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL); 1951 if (!sfi_entry) 1952 return -ENOMEM; 1953 1954 refcount_set(&sfi_entry->refcount, 1); 1955 1956 ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 1957 if (ret) { 1958 kfree(sfi_entry); 1959 return ret; 1960 } 1961 1962 vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask); 1963 1964 list_add(&sfi_entry->list, pos); 1965 1966 return 0; 1967 } 1968 1969 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 1970 struct felix_stream_filter *sfi) 1971 { 1972 struct list_head *pos, *q, *last; 1973 struct felix_stream_filter *tmp; 1974 struct ocelot_psfp_list *psfp; 1975 u32 insert = 0; 1976 1977 psfp = &ocelot->psfp; 1978 last = &psfp->sfi_list; 1979 1980 list_for_each_safe(pos, q, &psfp->sfi_list) { 1981 tmp = list_entry(pos, struct felix_stream_filter, list); 1982 if (sfi->sg_valid == tmp->sg_valid && 1983 sfi->fm_valid == tmp->fm_valid && 1984 sfi->portmask == tmp->portmask && 1985 tmp->sgid == sfi->sgid && 1986 tmp->fmid == sfi->fmid) { 1987 sfi->index = tmp->index; 1988 refcount_inc(&tmp->refcount); 1989 return 0; 1990 } 1991 /* Make sure that the index is increasing in order. */ 1992 if (tmp->index == insert) { 1993 last = pos; 1994 insert++; 1995 } 1996 } 1997 sfi->index = insert; 1998 1999 return vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 2000 } 2001 2002 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, 2003 struct felix_stream_filter *sfi, 2004 struct felix_stream_filter *sfi2) 2005 { 2006 struct felix_stream_filter *tmp; 2007 struct list_head *pos, *q, *last; 2008 struct ocelot_psfp_list *psfp; 2009 u32 insert = 0; 2010 int ret; 2011 2012 psfp = &ocelot->psfp; 2013 last = &psfp->sfi_list; 2014 2015 list_for_each_safe(pos, q, &psfp->sfi_list) { 2016 tmp = list_entry(pos, struct felix_stream_filter, list); 2017 /* Make sure that the index is increasing in order. */ 2018 if (tmp->index >= insert + 2) 2019 break; 2020 2021 insert = tmp->index + 1; 2022 last = pos; 2023 } 2024 sfi->index = insert; 2025 2026 ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 2027 if (ret) 2028 return ret; 2029 2030 sfi2->index = insert + 1; 2031 2032 return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next); 2033 } 2034 2035 static struct felix_stream_filter * 2036 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 2037 { 2038 struct felix_stream_filter *tmp; 2039 2040 list_for_each_entry(tmp, sfi_list, list) 2041 if (tmp->index == index) 2042 return tmp; 2043 2044 return NULL; 2045 } 2046 2047 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 2048 { 2049 struct felix_stream_filter *tmp, *n; 2050 struct ocelot_psfp_list *psfp; 2051 u8 z; 2052 2053 psfp = &ocelot->psfp; 2054 2055 list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 2056 if (tmp->index == index) { 2057 z = refcount_dec_and_test(&tmp->refcount); 2058 if (z) { 2059 tmp->enable = 0; 2060 vsc9959_psfp_sfi_set(ocelot, tmp); 2061 list_del(&tmp->list); 2062 kfree(tmp); 2063 } 2064 break; 2065 } 2066 } 2067 2068 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 2069 struct felix_stream_gate *sgi) 2070 { 2071 sgi->index = entry->hw_index; 2072 sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 2073 sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 2074 sgi->basetime = entry->gate.basetime; 2075 sgi->cycletime = entry->gate.cycletime; 2076 sgi->num_entries = entry->gate.num_entries; 2077 sgi->enable = 1; 2078 2079 memcpy(sgi->entries, entry->gate.entries, 2080 entry->gate.num_entries * sizeof(struct action_gate_entry)); 2081 } 2082 2083 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 2084 { 2085 return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 2086 } 2087 2088 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 2089 struct felix_stream_gate *sgi) 2090 { 2091 struct action_gate_entry *e; 2092 struct timespec64 base_ts; 2093 u32 interval_sum = 0; 2094 u32 val; 2095 int i; 2096 2097 if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 2098 return -EINVAL; 2099 2100 ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 2101 ANA_SG_ACCESS_CTRL); 2102 2103 if (!sgi->enable) { 2104 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 2105 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2106 ANA_SG_CONFIG_REG_3_GATE_ENABLE, 2107 ANA_SG_CONFIG_REG_3); 2108 2109 return 0; 2110 } 2111 2112 if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 2113 sgi->cycletime > NSEC_PER_SEC) 2114 return -EINVAL; 2115 2116 if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 2117 return -EINVAL; 2118 2119 vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 2120 ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 2121 val = lower_32_bits(base_ts.tv_sec); 2122 ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 2123 2124 val = upper_32_bits(base_ts.tv_sec); 2125 ocelot_write(ocelot, 2126 (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 2127 ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 2128 ANA_SG_CONFIG_REG_3_GATE_ENABLE | 2129 ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 2130 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2131 ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 2132 ANA_SG_CONFIG_REG_3); 2133 2134 ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 2135 2136 e = sgi->entries; 2137 for (i = 0; i < sgi->num_entries; i++) { 2138 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 2139 2140 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 2141 (e[i].gate_state ? 2142 ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 2143 ANA_SG_GCL_GS_CONFIG, i); 2144 2145 interval_sum += e[i].interval; 2146 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 2147 } 2148 2149 ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2150 ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2151 ANA_SG_ACCESS_CTRL); 2152 2153 return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 2154 (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 2155 10, 100000); 2156 } 2157 2158 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 2159 struct felix_stream_gate *sgi) 2160 { 2161 struct felix_stream_gate_entry *tmp; 2162 struct ocelot_psfp_list *psfp; 2163 int ret; 2164 2165 psfp = &ocelot->psfp; 2166 2167 list_for_each_entry(tmp, &psfp->sgi_list, list) 2168 if (tmp->index == sgi->index) { 2169 refcount_inc(&tmp->refcount); 2170 return 0; 2171 } 2172 2173 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 2174 if (!tmp) 2175 return -ENOMEM; 2176 2177 ret = vsc9959_psfp_sgi_set(ocelot, sgi); 2178 if (ret) { 2179 kfree(tmp); 2180 return ret; 2181 } 2182 2183 tmp->index = sgi->index; 2184 refcount_set(&tmp->refcount, 1); 2185 list_add_tail(&tmp->list, &psfp->sgi_list); 2186 2187 return 0; 2188 } 2189 2190 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 2191 u32 index) 2192 { 2193 struct felix_stream_gate_entry *tmp, *n; 2194 struct felix_stream_gate sgi = {0}; 2195 struct ocelot_psfp_list *psfp; 2196 u8 z; 2197 2198 psfp = &ocelot->psfp; 2199 2200 list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 2201 if (tmp->index == index) { 2202 z = refcount_dec_and_test(&tmp->refcount); 2203 if (z) { 2204 sgi.index = index; 2205 sgi.enable = 0; 2206 vsc9959_psfp_sgi_set(ocelot, &sgi); 2207 list_del(&tmp->list); 2208 kfree(tmp); 2209 } 2210 break; 2211 } 2212 } 2213 2214 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, 2215 struct flow_cls_offload *f) 2216 { 2217 struct netlink_ext_ack *extack = f->common.extack; 2218 struct felix_stream_filter old_sfi, *sfi_entry; 2219 struct felix_stream_filter sfi = {0}; 2220 const struct flow_action_entry *a; 2221 struct felix_stream *stream_entry; 2222 struct felix_stream stream = {0}; 2223 struct felix_stream_gate *sgi; 2224 struct ocelot_psfp_list *psfp; 2225 struct ocelot_policer pol; 2226 int ret, i, size; 2227 u64 rate, burst; 2228 u32 index; 2229 2230 psfp = &ocelot->psfp; 2231 2232 ret = vsc9959_stream_identify(f, &stream); 2233 if (ret) { 2234 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 2235 return ret; 2236 } 2237 2238 mutex_lock(&psfp->lock); 2239 2240 flow_action_for_each(i, a, &f->rule->action) { 2241 switch (a->id) { 2242 case FLOW_ACTION_GATE: 2243 size = struct_size(sgi, entries, a->gate.num_entries); 2244 sgi = kzalloc(size, GFP_KERNEL); 2245 if (!sgi) { 2246 ret = -ENOMEM; 2247 goto err; 2248 } 2249 vsc9959_psfp_parse_gate(a, sgi); 2250 ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 2251 if (ret) { 2252 kfree(sgi); 2253 goto err; 2254 } 2255 sfi.sg_valid = 1; 2256 sfi.sgid = sgi->index; 2257 kfree(sgi); 2258 break; 2259 case FLOW_ACTION_POLICE: 2260 index = a->hw_index + VSC9959_PSFP_POLICER_BASE; 2261 if (index > VSC9959_PSFP_POLICER_MAX) { 2262 ret = -EINVAL; 2263 goto err; 2264 } 2265 2266 rate = a->police.rate_bytes_ps; 2267 burst = rate * PSCHED_NS2TICKS(a->police.burst); 2268 pol = (struct ocelot_policer) { 2269 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC), 2270 .rate = div_u64(rate, 1000) * 8, 2271 }; 2272 ret = ocelot_vcap_policer_add(ocelot, index, &pol); 2273 if (ret) 2274 goto err; 2275 2276 sfi.fm_valid = 1; 2277 sfi.fmid = index; 2278 sfi.maxsdu = a->police.mtu; 2279 break; 2280 default: 2281 mutex_unlock(&psfp->lock); 2282 return -EOPNOTSUPP; 2283 } 2284 } 2285 2286 stream.ports = BIT(port); 2287 stream.port = port; 2288 2289 sfi.portmask = stream.ports; 2290 sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 2291 sfi.prio = (sfi.prio_valid ? stream.prio : 0); 2292 sfi.enable = 1; 2293 2294 /* Check if stream is set. */ 2295 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 2296 if (stream_entry) { 2297 if (stream_entry->ports & BIT(port)) { 2298 NL_SET_ERR_MSG_MOD(extack, 2299 "The stream is added on this port"); 2300 ret = -EEXIST; 2301 goto err; 2302 } 2303 2304 if (stream_entry->ports != BIT(stream_entry->port)) { 2305 NL_SET_ERR_MSG_MOD(extack, 2306 "The stream is added on two ports"); 2307 ret = -EEXIST; 2308 goto err; 2309 } 2310 2311 stream_entry->ports |= BIT(port); 2312 stream.ports = stream_entry->ports; 2313 2314 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, 2315 stream_entry->sfid); 2316 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); 2317 2318 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid); 2319 2320 old_sfi.portmask = stream_entry->ports; 2321 sfi.portmask = stream.ports; 2322 2323 if (stream_entry->port > port) { 2324 ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi, 2325 &old_sfi); 2326 stream_entry->dummy = true; 2327 } else { 2328 ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi, 2329 &sfi); 2330 stream.dummy = true; 2331 } 2332 if (ret) 2333 goto err; 2334 2335 stream_entry->sfid = old_sfi.index; 2336 } else { 2337 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 2338 if (ret) 2339 goto err; 2340 } 2341 2342 stream.sfid = sfi.index; 2343 stream.sfid_valid = 1; 2344 ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 2345 &stream, extack); 2346 if (ret) { 2347 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 2348 goto err; 2349 } 2350 2351 mutex_unlock(&psfp->lock); 2352 2353 return 0; 2354 2355 err: 2356 if (sfi.sg_valid) 2357 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 2358 2359 if (sfi.fm_valid) 2360 ocelot_vcap_policer_del(ocelot, sfi.fmid); 2361 2362 mutex_unlock(&psfp->lock); 2363 2364 return ret; 2365 } 2366 2367 static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 2368 struct flow_cls_offload *f) 2369 { 2370 struct felix_stream *stream, tmp, *stream_entry; 2371 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2372 static struct felix_stream_filter *sfi; 2373 2374 mutex_lock(&psfp->lock); 2375 2376 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2377 if (!stream) { 2378 mutex_unlock(&psfp->lock); 2379 return -ENOMEM; 2380 } 2381 2382 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2383 if (!sfi) { 2384 mutex_unlock(&psfp->lock); 2385 return -ENOMEM; 2386 } 2387 2388 if (sfi->sg_valid) 2389 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 2390 2391 if (sfi->fm_valid) 2392 ocelot_vcap_policer_del(ocelot, sfi->fmid); 2393 2394 vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 2395 2396 memcpy(&tmp, stream, sizeof(tmp)); 2397 2398 stream->sfid_valid = 0; 2399 vsc9959_stream_table_del(ocelot, stream); 2400 2401 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp); 2402 if (stream_entry) { 2403 stream_entry->ports = BIT(stream_entry->port); 2404 if (stream_entry->dummy) { 2405 stream_entry->dummy = false; 2406 vsc9959_mact_stream_set(ocelot, stream_entry, NULL); 2407 } 2408 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid, 2409 stream_entry->ports); 2410 } 2411 2412 mutex_unlock(&psfp->lock); 2413 2414 return 0; 2415 } 2416 2417 static void vsc9959_update_sfid_stats(struct ocelot *ocelot, 2418 struct felix_stream_filter *sfi) 2419 { 2420 struct felix_stream_filter_counters *s = &sfi->stats; 2421 u32 match, not_pass_gate, not_pass_sdu, red; 2422 u32 sfid = sfi->index; 2423 2424 lockdep_assert_held(&ocelot->stat_view_lock); 2425 2426 ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(sfid), 2427 SYS_STAT_CFG_STAT_VIEW_M, 2428 SYS_STAT_CFG); 2429 2430 match = ocelot_read(ocelot, SYS_COUNT_SF_MATCHING_FRAMES); 2431 not_pass_gate = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_FRAMES); 2432 not_pass_sdu = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_SDU); 2433 red = ocelot_read(ocelot, SYS_COUNT_SF_RED_FRAMES); 2434 2435 /* Clear the PSFP counter. */ 2436 ocelot_write(ocelot, 2437 SYS_STAT_CFG_STAT_VIEW(sfid) | 2438 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 2439 SYS_STAT_CFG); 2440 2441 s->match += match; 2442 s->not_pass_gate += not_pass_gate; 2443 s->not_pass_sdu += not_pass_sdu; 2444 s->red += red; 2445 } 2446 2447 /* Caller must hold &ocelot->stat_view_lock */ 2448 static void vsc9959_update_stats(struct ocelot *ocelot) 2449 { 2450 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2451 struct felix_stream_filter *sfi; 2452 2453 mutex_lock(&psfp->lock); 2454 2455 list_for_each_entry(sfi, &psfp->sfi_list, list) 2456 vsc9959_update_sfid_stats(ocelot, sfi); 2457 2458 mutex_unlock(&psfp->lock); 2459 } 2460 2461 static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 2462 struct flow_cls_offload *f, 2463 struct flow_stats *stats) 2464 { 2465 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2466 struct felix_stream_filter_counters *s; 2467 static struct felix_stream_filter *sfi; 2468 struct felix_stream *stream; 2469 2470 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2471 if (!stream) 2472 return -ENOMEM; 2473 2474 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2475 if (!sfi) 2476 return -EINVAL; 2477 2478 mutex_lock(&ocelot->stat_view_lock); 2479 2480 vsc9959_update_sfid_stats(ocelot, sfi); 2481 2482 s = &sfi->stats; 2483 stats->pkts = s->match; 2484 stats->drops = s->not_pass_gate + s->not_pass_sdu + s->red; 2485 2486 memset(s, 0, sizeof(*s)); 2487 2488 mutex_unlock(&ocelot->stat_view_lock); 2489 2490 return 0; 2491 } 2492 2493 static void vsc9959_psfp_init(struct ocelot *ocelot) 2494 { 2495 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2496 2497 INIT_LIST_HEAD(&psfp->stream_list); 2498 INIT_LIST_HEAD(&psfp->sfi_list); 2499 INIT_LIST_HEAD(&psfp->sgi_list); 2500 mutex_init(&psfp->lock); 2501 } 2502 2503 /* When using cut-through forwarding and the egress port runs at a higher data 2504 * rate than the ingress port, the packet currently under transmission would 2505 * suffer an underrun since it would be transmitted faster than it is received. 2506 * The Felix switch implementation of cut-through forwarding does not check in 2507 * hardware whether this condition is satisfied or not, so we must restrict the 2508 * list of ports that have cut-through forwarding enabled on egress to only be 2509 * the ports operating at the lowest link speed within their respective 2510 * forwarding domain. 2511 */ 2512 static void vsc9959_cut_through_fwd(struct ocelot *ocelot) 2513 { 2514 struct felix *felix = ocelot_to_felix(ocelot); 2515 struct dsa_switch *ds = felix->ds; 2516 int tc, port, other_port; 2517 2518 lockdep_assert_held(&ocelot->fwd_domain_lock); 2519 2520 for (port = 0; port < ocelot->num_phys_ports; port++) { 2521 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2522 struct ocelot_mm_state *mm = &ocelot->mm[port]; 2523 int min_speed = ocelot_port->speed; 2524 unsigned long mask = 0; 2525 u32 tmp, val = 0; 2526 2527 /* Disable cut-through on ports that are down */ 2528 if (ocelot_port->speed <= 0) 2529 goto set; 2530 2531 if (dsa_is_cpu_port(ds, port)) { 2532 /* Ocelot switches forward from the NPI port towards 2533 * any port, regardless of it being in the NPI port's 2534 * forwarding domain or not. 2535 */ 2536 mask = dsa_user_ports(ds); 2537 } else { 2538 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 2539 mask &= ~BIT(port); 2540 if (ocelot->npi >= 0) 2541 mask |= BIT(ocelot->npi); 2542 else 2543 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 2544 port); 2545 } 2546 2547 /* Calculate the minimum link speed, among the ports that are 2548 * up, of this source port's forwarding domain. 2549 */ 2550 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { 2551 struct ocelot_port *other_ocelot_port; 2552 2553 other_ocelot_port = ocelot->ports[other_port]; 2554 if (other_ocelot_port->speed <= 0) 2555 continue; 2556 2557 if (min_speed > other_ocelot_port->speed) 2558 min_speed = other_ocelot_port->speed; 2559 } 2560 2561 /* Enable cut-through forwarding for all traffic classes that 2562 * don't have oversized dropping enabled, since this check is 2563 * bypassed in cut-through mode. Also exclude preemptible 2564 * traffic classes, since these would hang the port for some 2565 * reason, if sent as cut-through. 2566 */ 2567 if (ocelot_port->speed == min_speed) { 2568 val = GENMASK(7, 0) & ~mm->active_preemptible_tcs; 2569 2570 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 2571 if (vsc9959_port_qmaxsdu_get(ocelot, port, tc)) 2572 val &= ~BIT(tc); 2573 } 2574 2575 set: 2576 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); 2577 if (tmp == val) 2578 continue; 2579 2580 dev_dbg(ocelot->dev, 2581 "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding on TC mask 0x%x\n", 2582 port, mask, ocelot_port->speed, min_speed, 2583 val ? "enabling" : "disabling", val); 2584 2585 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); 2586 } 2587 } 2588 2589 static const struct ocelot_ops vsc9959_ops = { 2590 .reset = vsc9959_reset, 2591 .wm_enc = vsc9959_wm_enc, 2592 .wm_dec = vsc9959_wm_dec, 2593 .wm_stat = vsc9959_wm_stat, 2594 .port_to_netdev = felix_port_to_netdev, 2595 .netdev_to_port = felix_netdev_to_port, 2596 .psfp_init = vsc9959_psfp_init, 2597 .psfp_filter_add = vsc9959_psfp_filter_add, 2598 .psfp_filter_del = vsc9959_psfp_filter_del, 2599 .psfp_stats_get = vsc9959_psfp_stats_get, 2600 .cut_through_fwd = vsc9959_cut_through_fwd, 2601 .tas_clock_adjust = vsc9959_tas_clock_adjust, 2602 .update_stats = vsc9959_update_stats, 2603 }; 2604 2605 static const struct felix_info felix_info_vsc9959 = { 2606 .resources = vsc9959_resources, 2607 .num_resources = ARRAY_SIZE(vsc9959_resources), 2608 .resource_names = vsc9959_resource_names, 2609 .regfields = vsc9959_regfields, 2610 .map = vsc9959_regmap, 2611 .ops = &vsc9959_ops, 2612 .vcap = vsc9959_vcap_props, 2613 .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 2614 .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 2615 .vcap_pol_base2 = 0, 2616 .vcap_pol_max2 = 0, 2617 .num_mact_rows = 2048, 2618 .num_ports = VSC9959_NUM_PORTS, 2619 .num_tx_queues = OCELOT_NUM_TC, 2620 .quirks = FELIX_MAC_QUIRKS, 2621 .quirk_no_xtr_irq = true, 2622 .ptp_caps = &vsc9959_ptp_caps, 2623 .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2624 .mdio_bus_free = vsc9959_mdio_bus_free, 2625 .port_modes = vsc9959_port_modes, 2626 .port_setup_tc = vsc9959_port_setup_tc, 2627 .port_sched_speed_set = vsc9959_sched_speed_set, 2628 .tas_guard_bands_update = vsc9959_tas_guard_bands_update, 2629 }; 2630 2631 /* The INTB interrupt is shared between for PTP TX timestamp availability 2632 * notification and MAC Merge status change on each port. 2633 */ 2634 static irqreturn_t felix_irq_handler(int irq, void *data) 2635 { 2636 struct ocelot *ocelot = (struct ocelot *)data; 2637 2638 ocelot_get_txtstamp(ocelot); 2639 ocelot_mm_irq(ocelot); 2640 2641 return IRQ_HANDLED; 2642 } 2643 2644 static int felix_pci_probe(struct pci_dev *pdev, 2645 const struct pci_device_id *id) 2646 { 2647 struct dsa_switch *ds; 2648 struct ocelot *ocelot; 2649 struct felix *felix; 2650 int err; 2651 2652 if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 2653 dev_info(&pdev->dev, "device is disabled, skipping\n"); 2654 return -ENODEV; 2655 } 2656 2657 err = pci_enable_device(pdev); 2658 if (err) { 2659 dev_err(&pdev->dev, "device enable failed\n"); 2660 goto err_pci_enable; 2661 } 2662 2663 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 2664 if (!felix) { 2665 err = -ENOMEM; 2666 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 2667 goto err_alloc_felix; 2668 } 2669 2670 pci_set_drvdata(pdev, felix); 2671 ocelot = &felix->ocelot; 2672 ocelot->dev = &pdev->dev; 2673 ocelot->num_flooding_pgids = OCELOT_NUM_TC; 2674 felix->info = &felix_info_vsc9959; 2675 felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); 2676 2677 pci_set_master(pdev); 2678 2679 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 2680 &felix_irq_handler, IRQF_ONESHOT, 2681 "felix-intb", ocelot); 2682 if (err) { 2683 dev_err(&pdev->dev, "Failed to request irq\n"); 2684 goto err_alloc_irq; 2685 } 2686 2687 ocelot->ptp = 1; 2688 ocelot->mm_supported = true; 2689 2690 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 2691 if (!ds) { 2692 err = -ENOMEM; 2693 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 2694 goto err_alloc_ds; 2695 } 2696 2697 ds->dev = &pdev->dev; 2698 ds->num_ports = felix->info->num_ports; 2699 ds->num_tx_queues = felix->info->num_tx_queues; 2700 ds->ops = &felix_switch_ops; 2701 ds->priv = ocelot; 2702 felix->ds = ds; 2703 felix->tag_proto = DSA_TAG_PROTO_OCELOT; 2704 2705 err = dsa_register_switch(ds); 2706 if (err) { 2707 dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n"); 2708 goto err_register_ds; 2709 } 2710 2711 return 0; 2712 2713 err_register_ds: 2714 kfree(ds); 2715 err_alloc_ds: 2716 err_alloc_irq: 2717 kfree(felix); 2718 err_alloc_felix: 2719 pci_disable_device(pdev); 2720 err_pci_enable: 2721 return err; 2722 } 2723 2724 static void felix_pci_remove(struct pci_dev *pdev) 2725 { 2726 struct felix *felix = pci_get_drvdata(pdev); 2727 2728 if (!felix) 2729 return; 2730 2731 dsa_unregister_switch(felix->ds); 2732 2733 kfree(felix->ds); 2734 kfree(felix); 2735 2736 pci_disable_device(pdev); 2737 } 2738 2739 static void felix_pci_shutdown(struct pci_dev *pdev) 2740 { 2741 struct felix *felix = pci_get_drvdata(pdev); 2742 2743 if (!felix) 2744 return; 2745 2746 dsa_switch_shutdown(felix->ds); 2747 2748 pci_set_drvdata(pdev, NULL); 2749 } 2750 2751 static struct pci_device_id felix_ids[] = { 2752 { 2753 /* NXP LS1028A */ 2754 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 2755 }, 2756 { 0, } 2757 }; 2758 MODULE_DEVICE_TABLE(pci, felix_ids); 2759 2760 static struct pci_driver felix_vsc9959_pci_driver = { 2761 .name = "mscc_felix", 2762 .id_table = felix_ids, 2763 .probe = felix_pci_probe, 2764 .remove = felix_pci_remove, 2765 .shutdown = felix_pci_shutdown, 2766 }; 2767 module_pci_driver(felix_vsc9959_pci_driver); 2768 2769 MODULE_DESCRIPTION("Felix Switch driver"); 2770 MODULE_LICENSE("GPL v2"); 2771