1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright 2017 Microsemi Corporation 3 * Copyright 2018-2019 NXP 4 */ 5 #include <linux/fsl/enetc_mdio.h> 6 #include <soc/mscc/ocelot_qsys.h> 7 #include <soc/mscc/ocelot_vcap.h> 8 #include <soc/mscc/ocelot_ana.h> 9 #include <soc/mscc/ocelot_ptp.h> 10 #include <soc/mscc/ocelot_sys.h> 11 #include <net/tc_act/tc_gate.h> 12 #include <soc/mscc/ocelot.h> 13 #include <linux/dsa/ocelot.h> 14 #include <linux/pcs-lynx.h> 15 #include <net/pkt_sched.h> 16 #include <linux/iopoll.h> 17 #include <linux/mdio.h> 18 #include <linux/pci.h> 19 #include <linux/time.h> 20 #include "felix.h" 21 22 #define VSC9959_NUM_PORTS 6 23 24 #define VSC9959_TAS_GCL_ENTRY_MAX 63 25 #define VSC9959_VCAP_POLICER_BASE 63 26 #define VSC9959_VCAP_POLICER_MAX 383 27 #define VSC9959_SWITCH_PCI_BAR 4 28 #define VSC9959_IMDIO_PCI_BAR 0 29 30 #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ 31 OCELOT_PORT_MODE_QSGMII | \ 32 OCELOT_PORT_MODE_1000BASEX | \ 33 OCELOT_PORT_MODE_2500BASEX | \ 34 OCELOT_PORT_MODE_USXGMII) 35 36 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { 37 VSC9959_PORT_MODE_SERDES, 38 VSC9959_PORT_MODE_SERDES, 39 VSC9959_PORT_MODE_SERDES, 40 VSC9959_PORT_MODE_SERDES, 41 OCELOT_PORT_MODE_INTERNAL, 42 OCELOT_PORT_MODE_INTERNAL, 43 }; 44 45 static const u32 vsc9959_ana_regmap[] = { 46 REG(ANA_ADVLEARN, 0x0089a0), 47 REG(ANA_VLANMASK, 0x0089a4), 48 REG_RESERVED(ANA_PORT_B_DOMAIN), 49 REG(ANA_ANAGEFIL, 0x0089ac), 50 REG(ANA_ANEVENTS, 0x0089b0), 51 REG(ANA_STORMLIMIT_BURST, 0x0089b4), 52 REG(ANA_STORMLIMIT_CFG, 0x0089b8), 53 REG(ANA_ISOLATED_PORTS, 0x0089c8), 54 REG(ANA_COMMUNITY_PORTS, 0x0089cc), 55 REG(ANA_AUTOAGE, 0x0089d0), 56 REG(ANA_MACTOPTIONS, 0x0089d4), 57 REG(ANA_LEARNDISC, 0x0089d8), 58 REG(ANA_AGENCTRL, 0x0089dc), 59 REG(ANA_MIRRORPORTS, 0x0089e0), 60 REG(ANA_EMIRRORPORTS, 0x0089e4), 61 REG(ANA_FLOODING, 0x0089e8), 62 REG(ANA_FLOODING_IPMC, 0x008a08), 63 REG(ANA_SFLOW_CFG, 0x008a0c), 64 REG(ANA_PORT_MODE, 0x008a28), 65 REG(ANA_CUT_THRU_CFG, 0x008a48), 66 REG(ANA_PGID_PGID, 0x008400), 67 REG(ANA_TABLES_ANMOVED, 0x007f1c), 68 REG(ANA_TABLES_MACHDATA, 0x007f20), 69 REG(ANA_TABLES_MACLDATA, 0x007f24), 70 REG(ANA_TABLES_STREAMDATA, 0x007f28), 71 REG(ANA_TABLES_MACACCESS, 0x007f2c), 72 REG(ANA_TABLES_MACTINDX, 0x007f30), 73 REG(ANA_TABLES_VLANACCESS, 0x007f34), 74 REG(ANA_TABLES_VLANTIDX, 0x007f38), 75 REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 76 REG(ANA_TABLES_ISDXTIDX, 0x007f40), 77 REG(ANA_TABLES_ENTRYLIM, 0x007f00), 78 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 79 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 80 REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 81 REG(ANA_TABLES_STREAMTIDX, 0x007f50), 82 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 83 REG(ANA_TABLES_SEQ_MASK, 0x007f58), 84 REG(ANA_TABLES_SFID_MASK, 0x007f5c), 85 REG(ANA_TABLES_SFIDACCESS, 0x007f60), 86 REG(ANA_TABLES_SFIDTIDX, 0x007f64), 87 REG(ANA_MSTI_STATE, 0x008600), 88 REG(ANA_OAM_UPM_LM_CNT, 0x008000), 89 REG(ANA_SG_ACCESS_CTRL, 0x008a64), 90 REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 91 REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 92 REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 93 REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 94 REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 95 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 96 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 97 REG(ANA_SG_STATUS_REG_1, 0x008980), 98 REG(ANA_SG_STATUS_REG_2, 0x008984), 99 REG(ANA_SG_STATUS_REG_3, 0x008988), 100 REG(ANA_PORT_VLAN_CFG, 0x007800), 101 REG(ANA_PORT_DROP_CFG, 0x007804), 102 REG(ANA_PORT_QOS_CFG, 0x007808), 103 REG(ANA_PORT_VCAP_CFG, 0x00780c), 104 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 105 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 106 REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 107 REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 108 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 109 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 110 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 111 REG(ANA_PORT_PORT_CFG, 0x007870), 112 REG(ANA_PORT_POL_CFG, 0x007874), 113 REG(ANA_PORT_PTP_CFG, 0x007878), 114 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 115 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 116 REG(ANA_PORT_SFID_CFG, 0x007884), 117 REG(ANA_PFC_PFC_CFG, 0x008800), 118 REG_RESERVED(ANA_PFC_PFC_TIMER), 119 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 120 REG_RESERVED(ANA_IPT_IPT), 121 REG_RESERVED(ANA_PPT_PPT), 122 REG_RESERVED(ANA_FID_MAP_FID_MAP), 123 REG(ANA_AGGR_CFG, 0x008a68), 124 REG(ANA_CPUQ_CFG, 0x008a6c), 125 REG_RESERVED(ANA_CPUQ_CFG2), 126 REG(ANA_CPUQ_8021_CFG, 0x008a74), 127 REG(ANA_DSCP_CFG, 0x008ab4), 128 REG(ANA_DSCP_REWR_CFG, 0x008bb4), 129 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 130 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 131 REG_RESERVED(ANA_VRAP_CFG), 132 REG_RESERVED(ANA_VRAP_HDR_DATA), 133 REG_RESERVED(ANA_VRAP_HDR_MASK), 134 REG(ANA_DISCARD_CFG, 0x008c40), 135 REG(ANA_FID_CFG, 0x008c44), 136 REG(ANA_POL_PIR_CFG, 0x004000), 137 REG(ANA_POL_CIR_CFG, 0x004004), 138 REG(ANA_POL_MODE_CFG, 0x004008), 139 REG(ANA_POL_PIR_STATE, 0x00400c), 140 REG(ANA_POL_CIR_STATE, 0x004010), 141 REG_RESERVED(ANA_POL_STATE), 142 REG(ANA_POL_FLOWC, 0x008c48), 143 REG(ANA_POL_HYST, 0x008cb4), 144 REG_RESERVED(ANA_POL_MISC_CFG), 145 }; 146 147 static const u32 vsc9959_qs_regmap[] = { 148 REG(QS_XTR_GRP_CFG, 0x000000), 149 REG(QS_XTR_RD, 0x000008), 150 REG(QS_XTR_FRM_PRUNING, 0x000010), 151 REG(QS_XTR_FLUSH, 0x000018), 152 REG(QS_XTR_DATA_PRESENT, 0x00001c), 153 REG(QS_XTR_CFG, 0x000020), 154 REG(QS_INJ_GRP_CFG, 0x000024), 155 REG(QS_INJ_WR, 0x00002c), 156 REG(QS_INJ_CTRL, 0x000034), 157 REG(QS_INJ_STATUS, 0x00003c), 158 REG(QS_INJ_ERR, 0x000040), 159 REG_RESERVED(QS_INH_DBG), 160 }; 161 162 static const u32 vsc9959_vcap_regmap[] = { 163 /* VCAP_CORE_CFG */ 164 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 165 REG(VCAP_CORE_MV_CFG, 0x000004), 166 /* VCAP_CORE_CACHE */ 167 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 168 REG(VCAP_CACHE_MASK_DAT, 0x000108), 169 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 170 REG(VCAP_CACHE_CNT_DAT, 0x000308), 171 REG(VCAP_CACHE_TG_DAT, 0x000388), 172 /* VCAP_CONST */ 173 REG(VCAP_CONST_VCAP_VER, 0x000398), 174 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 175 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 176 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 177 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 178 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 179 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 180 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 181 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 182 REG(VCAP_CONST_IF_CNT, 0x0003bc), 183 }; 184 185 static const u32 vsc9959_qsys_regmap[] = { 186 REG(QSYS_PORT_MODE, 0x00f460), 187 REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 188 REG(QSYS_STAT_CNT_CFG, 0x00f49c), 189 REG(QSYS_EEE_CFG, 0x00f4a0), 190 REG(QSYS_EEE_THRES, 0x00f4b8), 191 REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 192 REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 193 REG(QSYS_SW_STATUS, 0x00f4c4), 194 REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 195 REG_RESERVED(QSYS_PAD_CFG), 196 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 197 REG_RESERVED(QSYS_QMAP), 198 REG_RESERVED(QSYS_ISDX_SGRP), 199 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 200 REG(QSYS_TFRM_MISC, 0x00f50c), 201 REG(QSYS_TFRM_PORT_DLY, 0x00f510), 202 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 203 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 204 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 205 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 206 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 207 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 208 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 209 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 210 REG(QSYS_RED_PROFILE, 0x00f534), 211 REG(QSYS_RES_QOS_MODE, 0x00f574), 212 REG(QSYS_RES_CFG, 0x00c000), 213 REG(QSYS_RES_STAT, 0x00c004), 214 REG(QSYS_EGR_DROP_MODE, 0x00f578), 215 REG(QSYS_EQ_CTRL, 0x00f57c), 216 REG_RESERVED(QSYS_EVENTS_CORE), 217 REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 218 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 219 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 220 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 221 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 222 REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 223 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 224 REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 225 REG(QSYS_PREEMPTION_CFG, 0x00f664), 226 REG(QSYS_CIR_CFG, 0x000000), 227 REG(QSYS_EIR_CFG, 0x000004), 228 REG(QSYS_SE_CFG, 0x000008), 229 REG(QSYS_SE_DWRR_CFG, 0x00000c), 230 REG_RESERVED(QSYS_SE_CONNECT), 231 REG(QSYS_SE_DLB_SENSE, 0x000040), 232 REG(QSYS_CIR_STATE, 0x000044), 233 REG(QSYS_EIR_STATE, 0x000048), 234 REG_RESERVED(QSYS_SE_STATE), 235 REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 236 REG(QSYS_TAG_CONFIG, 0x00f680), 237 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 238 REG(QSYS_PORT_MAX_SDU, 0x00f69c), 239 REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 240 REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 241 REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 242 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 243 REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 244 REG(QSYS_GCL_CFG_REG_1, 0x00f454), 245 REG(QSYS_GCL_CFG_REG_2, 0x00f458), 246 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 247 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 248 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 249 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 250 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 251 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 252 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 253 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 254 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 255 REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 256 REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 257 }; 258 259 static const u32 vsc9959_rew_regmap[] = { 260 REG(REW_PORT_VLAN_CFG, 0x000000), 261 REG(REW_TAG_CFG, 0x000004), 262 REG(REW_PORT_CFG, 0x000008), 263 REG(REW_DSCP_CFG, 0x00000c), 264 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 265 REG(REW_PTP_CFG, 0x000050), 266 REG(REW_PTP_DLY1_CFG, 0x000054), 267 REG(REW_RED_TAG_CFG, 0x000058), 268 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 269 REG(REW_DSCP_REMAP_CFG, 0x000510), 270 REG_RESERVED(REW_STAT_CFG), 271 REG_RESERVED(REW_REW_STICKY), 272 REG_RESERVED(REW_PPT), 273 }; 274 275 static const u32 vsc9959_sys_regmap[] = { 276 REG(SYS_COUNT_RX_OCTETS, 0x000000), 277 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 278 REG(SYS_COUNT_RX_SHORTS, 0x000010), 279 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 280 REG(SYS_COUNT_RX_JABBERS, 0x000018), 281 REG(SYS_COUNT_RX_64, 0x000024), 282 REG(SYS_COUNT_RX_65_127, 0x000028), 283 REG(SYS_COUNT_RX_128_255, 0x00002c), 284 REG(SYS_COUNT_RX_256_1023, 0x000030), 285 REG(SYS_COUNT_RX_1024_1526, 0x000034), 286 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 287 REG(SYS_COUNT_RX_LONGS, 0x000044), 288 REG(SYS_COUNT_TX_OCTETS, 0x000200), 289 REG(SYS_COUNT_TX_COLLISION, 0x000210), 290 REG(SYS_COUNT_TX_DROPS, 0x000214), 291 REG(SYS_COUNT_TX_64, 0x00021c), 292 REG(SYS_COUNT_TX_65_127, 0x000220), 293 REG(SYS_COUNT_TX_128_511, 0x000224), 294 REG(SYS_COUNT_TX_512_1023, 0x000228), 295 REG(SYS_COUNT_TX_1024_1526, 0x00022c), 296 REG(SYS_COUNT_TX_1527_MAX, 0x000230), 297 REG(SYS_COUNT_TX_AGING, 0x000278), 298 REG(SYS_RESET_CFG, 0x000e00), 299 REG(SYS_SR_ETYPE_CFG, 0x000e04), 300 REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 301 REG(SYS_PORT_MODE, 0x000e0c), 302 REG(SYS_FRONT_PORT_MODE, 0x000e2c), 303 REG(SYS_FRM_AGING, 0x000e44), 304 REG(SYS_STAT_CFG, 0x000e48), 305 REG(SYS_SW_STATUS, 0x000e4c), 306 REG_RESERVED(SYS_MISC_CFG), 307 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 308 REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 309 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 310 REG(SYS_PAUSE_CFG, 0x000ea0), 311 REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 312 REG(SYS_ATOP, 0x000ec0), 313 REG(SYS_ATOP_TOT_CFG, 0x000edc), 314 REG(SYS_MAC_FC_CFG, 0x000ee0), 315 REG(SYS_MMGT, 0x000ef8), 316 REG_RESERVED(SYS_MMGT_FAST), 317 REG_RESERVED(SYS_EVENTS_DIF), 318 REG_RESERVED(SYS_EVENTS_CORE), 319 REG(SYS_CNT, 0x000000), 320 REG(SYS_PTP_STATUS, 0x000f14), 321 REG(SYS_PTP_TXSTAMP, 0x000f18), 322 REG(SYS_PTP_NXT, 0x000f1c), 323 REG(SYS_PTP_CFG, 0x000f20), 324 REG(SYS_RAM_INIT, 0x000f24), 325 REG_RESERVED(SYS_CM_ADDR), 326 REG_RESERVED(SYS_CM_DATA_WR), 327 REG_RESERVED(SYS_CM_DATA_RD), 328 REG_RESERVED(SYS_CM_OP), 329 REG_RESERVED(SYS_CM_DATA), 330 }; 331 332 static const u32 vsc9959_ptp_regmap[] = { 333 REG(PTP_PIN_CFG, 0x000000), 334 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 335 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 336 REG(PTP_PIN_TOD_NSEC, 0x00000c), 337 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 338 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 339 REG(PTP_CFG_MISC, 0x0000a0), 340 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 341 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 342 }; 343 344 static const u32 vsc9959_gcb_regmap[] = { 345 REG(GCB_SOFT_RST, 0x000004), 346 }; 347 348 static const u32 vsc9959_dev_gmii_regmap[] = { 349 REG(DEV_CLOCK_CFG, 0x0), 350 REG(DEV_PORT_MISC, 0x4), 351 REG(DEV_EVENTS, 0x8), 352 REG(DEV_EEE_CFG, 0xc), 353 REG(DEV_RX_PATH_DELAY, 0x10), 354 REG(DEV_TX_PATH_DELAY, 0x14), 355 REG(DEV_PTP_PREDICT_CFG, 0x18), 356 REG(DEV_MAC_ENA_CFG, 0x1c), 357 REG(DEV_MAC_MODE_CFG, 0x20), 358 REG(DEV_MAC_MAXLEN_CFG, 0x24), 359 REG(DEV_MAC_TAGS_CFG, 0x28), 360 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 361 REG(DEV_MAC_IFG_CFG, 0x30), 362 REG(DEV_MAC_HDX_CFG, 0x34), 363 REG(DEV_MAC_DBG_CFG, 0x38), 364 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 365 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 366 REG(DEV_MAC_STICKY, 0x44), 367 REG_RESERVED(PCS1G_CFG), 368 REG_RESERVED(PCS1G_MODE_CFG), 369 REG_RESERVED(PCS1G_SD_CFG), 370 REG_RESERVED(PCS1G_ANEG_CFG), 371 REG_RESERVED(PCS1G_ANEG_NP_CFG), 372 REG_RESERVED(PCS1G_LB_CFG), 373 REG_RESERVED(PCS1G_DBG_CFG), 374 REG_RESERVED(PCS1G_CDET_CFG), 375 REG_RESERVED(PCS1G_ANEG_STATUS), 376 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 377 REG_RESERVED(PCS1G_LINK_STATUS), 378 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 379 REG_RESERVED(PCS1G_STICKY), 380 REG_RESERVED(PCS1G_DEBUG_STATUS), 381 REG_RESERVED(PCS1G_LPI_CFG), 382 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 383 REG_RESERVED(PCS1G_LPI_STATUS), 384 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 385 REG_RESERVED(PCS1G_TSTPAT_STATUS), 386 REG_RESERVED(DEV_PCS_FX100_CFG), 387 REG_RESERVED(DEV_PCS_FX100_STATUS), 388 }; 389 390 static const u32 *vsc9959_regmap[TARGET_MAX] = { 391 [ANA] = vsc9959_ana_regmap, 392 [QS] = vsc9959_qs_regmap, 393 [QSYS] = vsc9959_qsys_regmap, 394 [REW] = vsc9959_rew_regmap, 395 [SYS] = vsc9959_sys_regmap, 396 [S0] = vsc9959_vcap_regmap, 397 [S1] = vsc9959_vcap_regmap, 398 [S2] = vsc9959_vcap_regmap, 399 [PTP] = vsc9959_ptp_regmap, 400 [GCB] = vsc9959_gcb_regmap, 401 [DEV_GMII] = vsc9959_dev_gmii_regmap, 402 }; 403 404 /* Addresses are relative to the PCI device's base address */ 405 static const struct resource vsc9959_target_io_res[TARGET_MAX] = { 406 [ANA] = { 407 .start = 0x0280000, 408 .end = 0x028ffff, 409 .name = "ana", 410 }, 411 [QS] = { 412 .start = 0x0080000, 413 .end = 0x00800ff, 414 .name = "qs", 415 }, 416 [QSYS] = { 417 .start = 0x0200000, 418 .end = 0x021ffff, 419 .name = "qsys", 420 }, 421 [REW] = { 422 .start = 0x0030000, 423 .end = 0x003ffff, 424 .name = "rew", 425 }, 426 [SYS] = { 427 .start = 0x0010000, 428 .end = 0x001ffff, 429 .name = "sys", 430 }, 431 [S0] = { 432 .start = 0x0040000, 433 .end = 0x00403ff, 434 .name = "s0", 435 }, 436 [S1] = { 437 .start = 0x0050000, 438 .end = 0x00503ff, 439 .name = "s1", 440 }, 441 [S2] = { 442 .start = 0x0060000, 443 .end = 0x00603ff, 444 .name = "s2", 445 }, 446 [PTP] = { 447 .start = 0x0090000, 448 .end = 0x00900cb, 449 .name = "ptp", 450 }, 451 [GCB] = { 452 .start = 0x0070000, 453 .end = 0x00701ff, 454 .name = "devcpu_gcb", 455 }, 456 }; 457 458 static const struct resource vsc9959_port_io_res[] = { 459 { 460 .start = 0x0100000, 461 .end = 0x010ffff, 462 .name = "port0", 463 }, 464 { 465 .start = 0x0110000, 466 .end = 0x011ffff, 467 .name = "port1", 468 }, 469 { 470 .start = 0x0120000, 471 .end = 0x012ffff, 472 .name = "port2", 473 }, 474 { 475 .start = 0x0130000, 476 .end = 0x013ffff, 477 .name = "port3", 478 }, 479 { 480 .start = 0x0140000, 481 .end = 0x014ffff, 482 .name = "port4", 483 }, 484 { 485 .start = 0x0150000, 486 .end = 0x015ffff, 487 .name = "port5", 488 }, 489 }; 490 491 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 492 * SGMII/QSGMII MAC PCS can be found. 493 */ 494 static const struct resource vsc9959_imdio_res = { 495 .start = 0x8030, 496 .end = 0x8040, 497 .name = "imdio", 498 }; 499 500 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 501 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 502 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 503 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 504 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 505 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 506 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 507 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 508 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 509 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 510 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 511 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 512 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 513 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 514 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 515 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 516 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 517 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 518 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 519 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 520 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 521 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 522 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 523 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 524 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 525 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 526 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 527 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 528 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 529 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 530 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 531 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 532 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 533 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 534 /* Replicated per number of ports (7), register size 4 per port */ 535 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 536 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 537 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 538 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 539 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 540 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 541 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 542 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 543 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 544 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 545 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 546 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 547 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 548 }; 549 550 static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 551 { .offset = 0x00, .name = "rx_octets", }, 552 { .offset = 0x01, .name = "rx_unicast", }, 553 { .offset = 0x02, .name = "rx_multicast", }, 554 { .offset = 0x03, .name = "rx_broadcast", }, 555 { .offset = 0x04, .name = "rx_shorts", }, 556 { .offset = 0x05, .name = "rx_fragments", }, 557 { .offset = 0x06, .name = "rx_jabbers", }, 558 { .offset = 0x07, .name = "rx_crc_align_errs", }, 559 { .offset = 0x08, .name = "rx_sym_errs", }, 560 { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 561 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 562 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 563 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 564 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 565 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 566 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 567 { .offset = 0x10, .name = "rx_pause", }, 568 { .offset = 0x11, .name = "rx_control", }, 569 { .offset = 0x12, .name = "rx_longs", }, 570 { .offset = 0x13, .name = "rx_classified_drops", }, 571 { .offset = 0x14, .name = "rx_red_prio_0", }, 572 { .offset = 0x15, .name = "rx_red_prio_1", }, 573 { .offset = 0x16, .name = "rx_red_prio_2", }, 574 { .offset = 0x17, .name = "rx_red_prio_3", }, 575 { .offset = 0x18, .name = "rx_red_prio_4", }, 576 { .offset = 0x19, .name = "rx_red_prio_5", }, 577 { .offset = 0x1A, .name = "rx_red_prio_6", }, 578 { .offset = 0x1B, .name = "rx_red_prio_7", }, 579 { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 580 { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 581 { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 582 { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 583 { .offset = 0x20, .name = "rx_yellow_prio_4", }, 584 { .offset = 0x21, .name = "rx_yellow_prio_5", }, 585 { .offset = 0x22, .name = "rx_yellow_prio_6", }, 586 { .offset = 0x23, .name = "rx_yellow_prio_7", }, 587 { .offset = 0x24, .name = "rx_green_prio_0", }, 588 { .offset = 0x25, .name = "rx_green_prio_1", }, 589 { .offset = 0x26, .name = "rx_green_prio_2", }, 590 { .offset = 0x27, .name = "rx_green_prio_3", }, 591 { .offset = 0x28, .name = "rx_green_prio_4", }, 592 { .offset = 0x29, .name = "rx_green_prio_5", }, 593 { .offset = 0x2A, .name = "rx_green_prio_6", }, 594 { .offset = 0x2B, .name = "rx_green_prio_7", }, 595 { .offset = 0x80, .name = "tx_octets", }, 596 { .offset = 0x81, .name = "tx_unicast", }, 597 { .offset = 0x82, .name = "tx_multicast", }, 598 { .offset = 0x83, .name = "tx_broadcast", }, 599 { .offset = 0x84, .name = "tx_collision", }, 600 { .offset = 0x85, .name = "tx_drops", }, 601 { .offset = 0x86, .name = "tx_pause", }, 602 { .offset = 0x87, .name = "tx_frames_below_65_octets", }, 603 { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, 604 { .offset = 0x89, .name = "tx_frames_128_255_octets", }, 605 { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, 606 { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, 607 { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, 608 { .offset = 0x8E, .name = "tx_yellow_prio_0", }, 609 { .offset = 0x8F, .name = "tx_yellow_prio_1", }, 610 { .offset = 0x90, .name = "tx_yellow_prio_2", }, 611 { .offset = 0x91, .name = "tx_yellow_prio_3", }, 612 { .offset = 0x92, .name = "tx_yellow_prio_4", }, 613 { .offset = 0x93, .name = "tx_yellow_prio_5", }, 614 { .offset = 0x94, .name = "tx_yellow_prio_6", }, 615 { .offset = 0x95, .name = "tx_yellow_prio_7", }, 616 { .offset = 0x96, .name = "tx_green_prio_0", }, 617 { .offset = 0x97, .name = "tx_green_prio_1", }, 618 { .offset = 0x98, .name = "tx_green_prio_2", }, 619 { .offset = 0x99, .name = "tx_green_prio_3", }, 620 { .offset = 0x9A, .name = "tx_green_prio_4", }, 621 { .offset = 0x9B, .name = "tx_green_prio_5", }, 622 { .offset = 0x9C, .name = "tx_green_prio_6", }, 623 { .offset = 0x9D, .name = "tx_green_prio_7", }, 624 { .offset = 0x9E, .name = "tx_aged", }, 625 { .offset = 0x100, .name = "drop_local", }, 626 { .offset = 0x101, .name = "drop_tail", }, 627 { .offset = 0x102, .name = "drop_yellow_prio_0", }, 628 { .offset = 0x103, .name = "drop_yellow_prio_1", }, 629 { .offset = 0x104, .name = "drop_yellow_prio_2", }, 630 { .offset = 0x105, .name = "drop_yellow_prio_3", }, 631 { .offset = 0x106, .name = "drop_yellow_prio_4", }, 632 { .offset = 0x107, .name = "drop_yellow_prio_5", }, 633 { .offset = 0x108, .name = "drop_yellow_prio_6", }, 634 { .offset = 0x109, .name = "drop_yellow_prio_7", }, 635 { .offset = 0x10A, .name = "drop_green_prio_0", }, 636 { .offset = 0x10B, .name = "drop_green_prio_1", }, 637 { .offset = 0x10C, .name = "drop_green_prio_2", }, 638 { .offset = 0x10D, .name = "drop_green_prio_3", }, 639 { .offset = 0x10E, .name = "drop_green_prio_4", }, 640 { .offset = 0x10F, .name = "drop_green_prio_5", }, 641 { .offset = 0x110, .name = "drop_green_prio_6", }, 642 { .offset = 0x111, .name = "drop_green_prio_7", }, 643 OCELOT_STAT_END 644 }; 645 646 static const struct vcap_field vsc9959_vcap_es0_keys[] = { 647 [VCAP_ES0_EGR_PORT] = { 0, 3}, 648 [VCAP_ES0_IGR_PORT] = { 3, 3}, 649 [VCAP_ES0_RSV] = { 6, 2}, 650 [VCAP_ES0_L2_MC] = { 8, 1}, 651 [VCAP_ES0_L2_BC] = { 9, 1}, 652 [VCAP_ES0_VID] = { 10, 12}, 653 [VCAP_ES0_DP] = { 22, 1}, 654 [VCAP_ES0_PCP] = { 23, 3}, 655 }; 656 657 static const struct vcap_field vsc9959_vcap_es0_actions[] = { 658 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 659 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 660 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 661 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 662 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 663 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 664 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 665 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 666 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 667 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 668 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 669 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 670 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 671 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 672 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 673 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 674 [VCAP_ES0_ACT_RSV] = { 49, 23}, 675 [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 676 }; 677 678 static const struct vcap_field vsc9959_vcap_is1_keys[] = { 679 [VCAP_IS1_HK_TYPE] = { 0, 1}, 680 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 681 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 682 [VCAP_IS1_HK_RSV] = { 10, 9}, 683 [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 684 [VCAP_IS1_HK_L2_MC] = { 20, 1}, 685 [VCAP_IS1_HK_L2_BC] = { 21, 1}, 686 [VCAP_IS1_HK_IP_MC] = { 22, 1}, 687 [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 688 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 689 [VCAP_IS1_HK_TPID] = { 25, 1}, 690 [VCAP_IS1_HK_VID] = { 26, 12}, 691 [VCAP_IS1_HK_DEI] = { 38, 1}, 692 [VCAP_IS1_HK_PCP] = { 39, 3}, 693 /* Specific Fields for IS1 Half Key S1_NORMAL */ 694 [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 695 [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 696 [VCAP_IS1_HK_ETYPE] = { 91, 16}, 697 [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 698 [VCAP_IS1_HK_IP4] = {108, 1}, 699 /* Layer-3 Information */ 700 [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 701 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 702 [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 703 [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 704 [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 705 /* Layer-4 Information */ 706 [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 707 [VCAP_IS1_HK_TCP] = {151, 1}, 708 [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 709 [VCAP_IS1_HK_L4_RNG] = {168, 8}, 710 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 711 [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 712 [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 713 [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 714 [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 715 [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 716 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 717 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 718 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 719 [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 720 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 721 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 722 [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 723 [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 724 [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 725 [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 726 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 727 }; 728 729 static const struct vcap_field vsc9959_vcap_is1_actions[] = { 730 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 731 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 732 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 733 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 734 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 735 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 736 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 737 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 738 [VCAP_IS1_ACT_RSV] = { 29, 9}, 739 /* The fields below are incorrectly shifted by 2 in the manual */ 740 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 741 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 742 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 743 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 744 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 745 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 746 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 747 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 748 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 749 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 750 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 751 }; 752 753 static struct vcap_field vsc9959_vcap_is2_keys[] = { 754 /* Common: 41 bits */ 755 [VCAP_IS2_TYPE] = { 0, 4}, 756 [VCAP_IS2_HK_FIRST] = { 4, 1}, 757 [VCAP_IS2_HK_PAG] = { 5, 8}, 758 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 759 [VCAP_IS2_HK_RSV2] = { 20, 1}, 760 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 761 [VCAP_IS2_HK_L2_MC] = { 22, 1}, 762 [VCAP_IS2_HK_L2_BC] = { 23, 1}, 763 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 764 [VCAP_IS2_HK_VID] = { 25, 12}, 765 [VCAP_IS2_HK_DEI] = { 37, 1}, 766 [VCAP_IS2_HK_PCP] = { 38, 3}, 767 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 768 [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 769 [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 770 /* MAC_ETYPE (TYPE=000) */ 771 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 772 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 773 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 774 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 775 /* MAC_LLC (TYPE=001) */ 776 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 777 /* MAC_SNAP (TYPE=010) */ 778 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 779 /* MAC_ARP (TYPE=011) */ 780 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 781 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 782 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 783 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 784 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 785 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 786 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 787 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 788 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 789 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 790 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 791 /* IP4_TCP_UDP / IP4_OTHER common */ 792 [VCAP_IS2_HK_IP4] = { 41, 1}, 793 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 794 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 795 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 796 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 797 [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 798 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 799 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 800 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 801 /* IP4_TCP_UDP (TYPE=100) */ 802 [VCAP_IS2_HK_TCP] = {119, 1}, 803 [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 804 [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 805 [VCAP_IS2_HK_L4_RNG] = {152, 8}, 806 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 807 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 808 [VCAP_IS2_HK_L4_FIN] = {162, 1}, 809 [VCAP_IS2_HK_L4_SYN] = {163, 1}, 810 [VCAP_IS2_HK_L4_RST] = {164, 1}, 811 [VCAP_IS2_HK_L4_PSH] = {165, 1}, 812 [VCAP_IS2_HK_L4_ACK] = {166, 1}, 813 [VCAP_IS2_HK_L4_URG] = {167, 1}, 814 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 815 [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 816 /* IP4_OTHER (TYPE=101) */ 817 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 818 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 819 /* IP6_STD (TYPE=110) */ 820 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 821 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 822 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 823 /* OAM (TYPE=111) */ 824 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 825 [VCAP_IS2_HK_OAM_VER] = {144, 5}, 826 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 827 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 828 [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 829 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 830 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 831 }; 832 833 static struct vcap_field vsc9959_vcap_is2_actions[] = { 834 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 835 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 836 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 837 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 838 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 839 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 840 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 841 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 842 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 843 [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 844 [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 845 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 846 [VCAP_IS2_ACT_RSV] = { 36, 2}, 847 [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 848 [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 849 }; 850 851 static struct vcap_props vsc9959_vcap_props[] = { 852 [VCAP_ES0] = { 853 .action_type_width = 0, 854 .action_table = { 855 [ES0_ACTION_TYPE_NORMAL] = { 856 .width = 72, /* HIT_STICKY not included */ 857 .count = 1, 858 }, 859 }, 860 .target = S0, 861 .keys = vsc9959_vcap_es0_keys, 862 .actions = vsc9959_vcap_es0_actions, 863 }, 864 [VCAP_IS1] = { 865 .action_type_width = 0, 866 .action_table = { 867 [IS1_ACTION_TYPE_NORMAL] = { 868 .width = 78, /* HIT_STICKY not included */ 869 .count = 4, 870 }, 871 }, 872 .target = S1, 873 .keys = vsc9959_vcap_is1_keys, 874 .actions = vsc9959_vcap_is1_actions, 875 }, 876 [VCAP_IS2] = { 877 .action_type_width = 1, 878 .action_table = { 879 [IS2_ACTION_TYPE_NORMAL] = { 880 .width = 44, 881 .count = 2 882 }, 883 [IS2_ACTION_TYPE_SMAC_SIP] = { 884 .width = 6, 885 .count = 4 886 }, 887 }, 888 .target = S2, 889 .keys = vsc9959_vcap_is2_keys, 890 .actions = vsc9959_vcap_is2_actions, 891 }, 892 }; 893 894 static const struct ptp_clock_info vsc9959_ptp_caps = { 895 .owner = THIS_MODULE, 896 .name = "felix ptp", 897 .max_adj = 0x7fffffff, 898 .n_alarm = 0, 899 .n_ext_ts = 0, 900 .n_per_out = OCELOT_PTP_PINS_NUM, 901 .n_pins = OCELOT_PTP_PINS_NUM, 902 .pps = 0, 903 .gettime64 = ocelot_ptp_gettime64, 904 .settime64 = ocelot_ptp_settime64, 905 .adjtime = ocelot_ptp_adjtime, 906 .adjfine = ocelot_ptp_adjfine, 907 .verify = ocelot_ptp_verify, 908 .enable = ocelot_ptp_enable, 909 }; 910 911 #define VSC9959_INIT_TIMEOUT 50000 912 #define VSC9959_GCB_RST_SLEEP 100 913 #define VSC9959_SYS_RAMINIT_SLEEP 80 914 915 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 916 { 917 int val; 918 919 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 920 921 return val; 922 } 923 924 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 925 { 926 return ocelot_read(ocelot, SYS_RAM_INIT); 927 } 928 929 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 930 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 931 */ 932 static int vsc9959_reset(struct ocelot *ocelot) 933 { 934 int val, err; 935 936 /* soft-reset the switch core */ 937 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 938 939 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 940 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 941 if (err) { 942 dev_err(ocelot->dev, "timeout: switch core reset\n"); 943 return err; 944 } 945 946 /* initialize switch mem ~40us */ 947 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 948 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 949 VSC9959_SYS_RAMINIT_SLEEP, 950 VSC9959_INIT_TIMEOUT); 951 if (err) { 952 dev_err(ocelot->dev, "timeout: switch sram init\n"); 953 return err; 954 } 955 956 /* enable switch core */ 957 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 958 959 return 0; 960 } 961 962 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port, 963 unsigned long *supported, 964 struct phylink_link_state *state) 965 { 966 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 967 968 phylink_set_port_modes(mask); 969 phylink_set(mask, Autoneg); 970 phylink_set(mask, Pause); 971 phylink_set(mask, Asym_Pause); 972 phylink_set(mask, 10baseT_Half); 973 phylink_set(mask, 10baseT_Full); 974 phylink_set(mask, 100baseT_Half); 975 phylink_set(mask, 100baseT_Full); 976 phylink_set(mask, 1000baseT_Half); 977 phylink_set(mask, 1000baseT_Full); 978 phylink_set(mask, 1000baseX_Full); 979 980 if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 981 state->interface == PHY_INTERFACE_MODE_2500BASEX || 982 state->interface == PHY_INTERFACE_MODE_USXGMII) { 983 phylink_set(mask, 2500baseT_Full); 984 phylink_set(mask, 2500baseX_Full); 985 } 986 987 linkmode_and(supported, supported, mask); 988 linkmode_and(state->advertising, state->advertising, mask); 989 } 990 991 /* Watermark encode 992 * Bit 8: Unit; 0:1, 1:16 993 * Bit 7-0: Value to be multiplied with unit 994 */ 995 static u16 vsc9959_wm_enc(u16 value) 996 { 997 WARN_ON(value >= 16 * BIT(8)); 998 999 if (value >= BIT(8)) 1000 return BIT(8) | (value / 16); 1001 1002 return value; 1003 } 1004 1005 static u16 vsc9959_wm_dec(u16 wm) 1006 { 1007 WARN_ON(wm & ~GENMASK(8, 0)); 1008 1009 if (wm & BIT(8)) 1010 return (wm & GENMASK(7, 0)) * 16; 1011 1012 return wm; 1013 } 1014 1015 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 1016 { 1017 *inuse = (val & GENMASK(23, 12)) >> 12; 1018 *maxuse = val & GENMASK(11, 0); 1019 } 1020 1021 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 1022 { 1023 struct felix *felix = ocelot_to_felix(ocelot); 1024 struct enetc_mdio_priv *mdio_priv; 1025 struct device *dev = ocelot->dev; 1026 void __iomem *imdio_regs; 1027 struct resource res; 1028 struct enetc_hw *hw; 1029 struct mii_bus *bus; 1030 int port; 1031 int rc; 1032 1033 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 1034 sizeof(struct phylink_pcs *), 1035 GFP_KERNEL); 1036 if (!felix->pcs) { 1037 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 1038 return -ENOMEM; 1039 } 1040 1041 memcpy(&res, felix->info->imdio_res, sizeof(res)); 1042 res.flags = IORESOURCE_MEM; 1043 res.start += felix->imdio_base; 1044 res.end += felix->imdio_base; 1045 1046 imdio_regs = devm_ioremap_resource(dev, &res); 1047 if (IS_ERR(imdio_regs)) 1048 return PTR_ERR(imdio_regs); 1049 1050 hw = enetc_hw_alloc(dev, imdio_regs); 1051 if (IS_ERR(hw)) { 1052 dev_err(dev, "failed to allocate ENETC HW structure\n"); 1053 return PTR_ERR(hw); 1054 } 1055 1056 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 1057 if (!bus) 1058 return -ENOMEM; 1059 1060 bus->name = "VSC9959 internal MDIO bus"; 1061 bus->read = enetc_mdio_read; 1062 bus->write = enetc_mdio_write; 1063 bus->parent = dev; 1064 mdio_priv = bus->priv; 1065 mdio_priv->hw = hw; 1066 /* This gets added to imdio_regs, which already maps addresses 1067 * starting with the proper offset. 1068 */ 1069 mdio_priv->mdio_base = 0; 1070 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1071 1072 /* Needed in order to initialize the bus mutex lock */ 1073 rc = mdiobus_register(bus); 1074 if (rc < 0) { 1075 dev_err(dev, "failed to register MDIO bus\n"); 1076 mdiobus_free(bus); 1077 return rc; 1078 } 1079 1080 felix->imdio = bus; 1081 1082 for (port = 0; port < felix->info->num_ports; port++) { 1083 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1084 struct phylink_pcs *phylink_pcs; 1085 struct mdio_device *mdio_device; 1086 1087 if (dsa_is_unused_port(felix->ds, port)) 1088 continue; 1089 1090 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1091 continue; 1092 1093 mdio_device = mdio_device_create(felix->imdio, port); 1094 if (IS_ERR(mdio_device)) 1095 continue; 1096 1097 phylink_pcs = lynx_pcs_create(mdio_device); 1098 if (!phylink_pcs) { 1099 mdio_device_free(mdio_device); 1100 continue; 1101 } 1102 1103 felix->pcs[port] = phylink_pcs; 1104 1105 dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1106 } 1107 1108 return 0; 1109 } 1110 1111 static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1112 { 1113 struct felix *felix = ocelot_to_felix(ocelot); 1114 int port; 1115 1116 for (port = 0; port < ocelot->num_phys_ports; port++) { 1117 struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1118 struct mdio_device *mdio_device; 1119 1120 if (!phylink_pcs) 1121 continue; 1122 1123 mdio_device = lynx_get_mdio_device(phylink_pcs); 1124 mdio_device_free(mdio_device); 1125 lynx_pcs_destroy(phylink_pcs); 1126 } 1127 mdiobus_unregister(felix->imdio); 1128 mdiobus_free(felix->imdio); 1129 } 1130 1131 /* Extract shortest continuous gate open intervals in ns for each traffic class 1132 * of a cyclic tc-taprio schedule. If a gate is always open, the duration is 1133 * considered U64_MAX. If the gate is always closed, it is considered 0. 1134 */ 1135 static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio, 1136 u64 min_gate_len[OCELOT_NUM_TC]) 1137 { 1138 struct tc_taprio_sched_entry *entry; 1139 u64 gate_len[OCELOT_NUM_TC]; 1140 int tc, i, n; 1141 1142 /* Initialize arrays */ 1143 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1144 min_gate_len[tc] = U64_MAX; 1145 gate_len[tc] = 0; 1146 } 1147 1148 /* If we don't have taprio, consider all gates as permanently open */ 1149 if (!taprio) 1150 return; 1151 1152 n = taprio->num_entries; 1153 1154 /* Walk through the gate list twice to determine the length 1155 * of consecutively open gates for a traffic class, including 1156 * open gates that wrap around. We are just interested in the 1157 * minimum window size, and this doesn't change what the 1158 * minimum is (if the gate never closes, min_gate_len will 1159 * remain U64_MAX). 1160 */ 1161 for (i = 0; i < 2 * n; i++) { 1162 entry = &taprio->entries[i % n]; 1163 1164 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1165 if (entry->gate_mask & BIT(tc)) { 1166 gate_len[tc] += entry->interval; 1167 } else { 1168 /* Gate closes now, record a potential new 1169 * minimum and reinitialize length 1170 */ 1171 if (min_gate_len[tc] > gate_len[tc]) 1172 min_gate_len[tc] = gate_len[tc]; 1173 gate_len[tc] = 0; 1174 } 1175 } 1176 } 1177 } 1178 1179 /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the 1180 * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU 1181 * values (the default value is 1518). Also, for traffic class windows smaller 1182 * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame 1183 * dropping, such that these won't hang the port, as they will never be sent. 1184 */ 1185 static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port) 1186 { 1187 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1188 u64 min_gate_len[OCELOT_NUM_TC]; 1189 int speed, picos_per_byte; 1190 u64 needed_bit_time_ps; 1191 u32 val, maxlen; 1192 u8 tas_speed; 1193 int tc; 1194 1195 lockdep_assert_held(&ocelot->tas_lock); 1196 1197 val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port); 1198 tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val); 1199 1200 switch (tas_speed) { 1201 case OCELOT_SPEED_10: 1202 speed = SPEED_10; 1203 break; 1204 case OCELOT_SPEED_100: 1205 speed = SPEED_100; 1206 break; 1207 case OCELOT_SPEED_1000: 1208 speed = SPEED_1000; 1209 break; 1210 case OCELOT_SPEED_2500: 1211 speed = SPEED_2500; 1212 break; 1213 default: 1214 return; 1215 } 1216 1217 picos_per_byte = (USEC_PER_SEC * 8) / speed; 1218 1219 val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG); 1220 /* MAXLEN_CFG accounts automatically for VLAN. We need to include it 1221 * manually in the bit time calculation, plus the preamble and SFD. 1222 */ 1223 maxlen = val + 2 * VLAN_HLEN; 1224 /* Consider the standard Ethernet overhead of 8 octets preamble+SFD, 1225 * 4 octets FCS, 12 octets IFG. 1226 */ 1227 needed_bit_time_ps = (maxlen + 24) * picos_per_byte; 1228 1229 dev_dbg(ocelot->dev, 1230 "port %d: max frame size %d needs %llu ps at speed %d\n", 1231 port, maxlen, needed_bit_time_ps, speed); 1232 1233 vsc9959_tas_min_gate_lengths(ocelot_port->taprio, min_gate_len); 1234 1235 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1236 u32 max_sdu; 1237 1238 if (min_gate_len[tc] == U64_MAX /* Gate always open */ || 1239 min_gate_len[tc] * PSEC_PER_NSEC > needed_bit_time_ps) { 1240 /* Setting QMAXSDU_CFG to 0 disables oversized frame 1241 * dropping. 1242 */ 1243 max_sdu = 0; 1244 dev_dbg(ocelot->dev, 1245 "port %d tc %d min gate len %llu" 1246 ", sending all frames\n", 1247 port, tc, min_gate_len[tc]); 1248 } else { 1249 /* If traffic class doesn't support a full MTU sized 1250 * frame, make sure to enable oversize frame dropping 1251 * for frames larger than the smallest that would fit. 1252 */ 1253 max_sdu = div_u64(min_gate_len[tc] * PSEC_PER_NSEC, 1254 picos_per_byte); 1255 /* A TC gate may be completely closed, which is a 1256 * special case where all packets are oversized. 1257 * Any limit smaller than 64 octets accomplishes this 1258 */ 1259 if (!max_sdu) 1260 max_sdu = 1; 1261 /* Take L1 overhead into account, but just don't allow 1262 * max_sdu to go negative or to 0. Here we use 20 1263 * because QSYS_MAXSDU_CFG_* already counts the 4 FCS 1264 * octets as part of packet size. 1265 */ 1266 if (max_sdu > 20) 1267 max_sdu -= 20; 1268 dev_info(ocelot->dev, 1269 "port %d tc %d min gate length %llu" 1270 " ns not enough for max frame size %d at %d" 1271 " Mbps, dropping frames over %d" 1272 " octets including FCS\n", 1273 port, tc, min_gate_len[tc], maxlen, speed, 1274 max_sdu); 1275 } 1276 1277 /* ocelot_write_rix is a macro that concatenates 1278 * QSYS_MAXSDU_CFG_* with _RSZ, so we need to spell out 1279 * the writes to each traffic class 1280 */ 1281 switch (tc) { 1282 case 0: 1283 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0, 1284 port); 1285 break; 1286 case 1: 1287 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1, 1288 port); 1289 break; 1290 case 2: 1291 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2, 1292 port); 1293 break; 1294 case 3: 1295 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3, 1296 port); 1297 break; 1298 case 4: 1299 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4, 1300 port); 1301 break; 1302 case 5: 1303 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5, 1304 port); 1305 break; 1306 case 6: 1307 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6, 1308 port); 1309 break; 1310 case 7: 1311 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7, 1312 port); 1313 break; 1314 } 1315 } 1316 1317 ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port); 1318 } 1319 1320 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1321 u32 speed) 1322 { 1323 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1324 u8 tas_speed; 1325 1326 switch (speed) { 1327 case SPEED_10: 1328 tas_speed = OCELOT_SPEED_10; 1329 break; 1330 case SPEED_100: 1331 tas_speed = OCELOT_SPEED_100; 1332 break; 1333 case SPEED_1000: 1334 tas_speed = OCELOT_SPEED_1000; 1335 break; 1336 case SPEED_2500: 1337 tas_speed = OCELOT_SPEED_2500; 1338 break; 1339 default: 1340 tas_speed = OCELOT_SPEED_1000; 1341 break; 1342 } 1343 1344 ocelot_rmw_rix(ocelot, 1345 QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1346 QSYS_TAG_CONFIG_LINK_SPEED_M, 1347 QSYS_TAG_CONFIG, port); 1348 1349 mutex_lock(&ocelot->tas_lock); 1350 1351 if (ocelot_port->taprio) 1352 vsc9959_tas_guard_bands_update(ocelot, port); 1353 1354 mutex_unlock(&ocelot->tas_lock); 1355 } 1356 1357 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1358 u64 cycle_time, 1359 struct timespec64 *new_base_ts) 1360 { 1361 struct timespec64 ts; 1362 ktime_t new_base_time; 1363 ktime_t current_time; 1364 1365 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1366 current_time = timespec64_to_ktime(ts); 1367 new_base_time = base_time; 1368 1369 if (base_time < current_time) { 1370 u64 nr_of_cycles = current_time - base_time; 1371 1372 do_div(nr_of_cycles, cycle_time); 1373 new_base_time += cycle_time * (nr_of_cycles + 1); 1374 } 1375 1376 *new_base_ts = ktime_to_timespec64(new_base_time); 1377 } 1378 1379 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1380 { 1381 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1382 } 1383 1384 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1385 struct tc_taprio_sched_entry *entry) 1386 { 1387 ocelot_write(ocelot, 1388 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1389 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1390 QSYS_GCL_CFG_REG_1); 1391 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1392 } 1393 1394 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1395 struct tc_taprio_qopt_offload *taprio) 1396 { 1397 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1398 struct timespec64 base_ts; 1399 int ret, i; 1400 u32 val; 1401 1402 mutex_lock(&ocelot->tas_lock); 1403 1404 if (!taprio->enable) { 1405 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1406 QSYS_TAG_CONFIG, port); 1407 1408 taprio_offload_free(ocelot_port->taprio); 1409 ocelot_port->taprio = NULL; 1410 1411 vsc9959_tas_guard_bands_update(ocelot, port); 1412 1413 mutex_unlock(&ocelot->tas_lock); 1414 return 0; 1415 } 1416 1417 if (taprio->cycle_time > NSEC_PER_SEC || 1418 taprio->cycle_time_extension >= NSEC_PER_SEC) { 1419 ret = -EINVAL; 1420 goto err; 1421 } 1422 1423 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) { 1424 ret = -ERANGE; 1425 goto err; 1426 } 1427 1428 /* Enable guard band. The switch will schedule frames without taking 1429 * their length into account. Thus we'll always need to enable the 1430 * guard band which reserves the time of a maximum sized frame at the 1431 * end of the time window. 1432 * 1433 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1434 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1435 * operate on the port number. 1436 */ 1437 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1438 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1439 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1440 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1441 QSYS_TAS_PARAM_CFG_CTRL); 1442 1443 /* Hardware errata - Admin config could not be overwritten if 1444 * config is pending, need reset the TAS module 1445 */ 1446 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1447 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) { 1448 ret = -EBUSY; 1449 goto err; 1450 } 1451 1452 ocelot_rmw_rix(ocelot, 1453 QSYS_TAG_CONFIG_ENABLE | 1454 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1455 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1456 QSYS_TAG_CONFIG_ENABLE | 1457 QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1458 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1459 QSYS_TAG_CONFIG, port); 1460 1461 vsc9959_new_base_time(ocelot, taprio->base_time, 1462 taprio->cycle_time, &base_ts); 1463 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1464 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1465 val = upper_32_bits(base_ts.tv_sec); 1466 ocelot_write(ocelot, 1467 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1468 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1469 QSYS_PARAM_CFG_REG_3); 1470 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1471 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1472 1473 for (i = 0; i < taprio->num_entries; i++) 1474 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1475 1476 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1477 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1478 QSYS_TAS_PARAM_CFG_CTRL); 1479 1480 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1481 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1482 10, 100000); 1483 if (ret) 1484 goto err; 1485 1486 ocelot_port->taprio = taprio_offload_get(taprio); 1487 vsc9959_tas_guard_bands_update(ocelot, port); 1488 1489 err: 1490 mutex_unlock(&ocelot->tas_lock); 1491 1492 return ret; 1493 } 1494 1495 static void vsc9959_tas_clock_adjust(struct ocelot *ocelot) 1496 { 1497 struct tc_taprio_qopt_offload *taprio; 1498 struct ocelot_port *ocelot_port; 1499 struct timespec64 base_ts; 1500 int port; 1501 u32 val; 1502 1503 mutex_lock(&ocelot->tas_lock); 1504 1505 for (port = 0; port < ocelot->num_phys_ports; port++) { 1506 ocelot_port = ocelot->ports[port]; 1507 taprio = ocelot_port->taprio; 1508 if (!taprio) 1509 continue; 1510 1511 ocelot_rmw(ocelot, 1512 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port), 1513 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M, 1514 QSYS_TAS_PARAM_CFG_CTRL); 1515 1516 /* Disable time-aware shaper */ 1517 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1518 QSYS_TAG_CONFIG, port); 1519 1520 vsc9959_new_base_time(ocelot, taprio->base_time, 1521 taprio->cycle_time, &base_ts); 1522 1523 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1524 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), 1525 QSYS_PARAM_CFG_REG_2); 1526 val = upper_32_bits(base_ts.tv_sec); 1527 ocelot_rmw(ocelot, 1528 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val), 1529 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M, 1530 QSYS_PARAM_CFG_REG_3); 1531 1532 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1533 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1534 QSYS_TAS_PARAM_CFG_CTRL); 1535 1536 /* Re-enable time-aware shaper */ 1537 ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE, 1538 QSYS_TAG_CONFIG_ENABLE, 1539 QSYS_TAG_CONFIG, port); 1540 } 1541 mutex_unlock(&ocelot->tas_lock); 1542 } 1543 1544 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 1545 struct tc_cbs_qopt_offload *cbs_qopt) 1546 { 1547 struct ocelot *ocelot = ds->priv; 1548 int port_ix = port * 8 + cbs_qopt->queue; 1549 u32 rate, burst; 1550 1551 if (cbs_qopt->queue >= ds->num_tx_queues) 1552 return -EINVAL; 1553 1554 if (!cbs_qopt->enable) { 1555 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 1556 QSYS_CIR_CFG_CIR_BURST(0), 1557 QSYS_CIR_CFG, port_ix); 1558 1559 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 1560 QSYS_SE_CFG, port_ix); 1561 1562 return 0; 1563 } 1564 1565 /* Rate unit is 100 kbps */ 1566 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 1567 /* Avoid using zero rate */ 1568 rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 1569 /* Burst unit is 4kB */ 1570 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 1571 /* Avoid using zero burst size */ 1572 burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 1573 ocelot_write_gix(ocelot, 1574 QSYS_CIR_CFG_CIR_RATE(rate) | 1575 QSYS_CIR_CFG_CIR_BURST(burst), 1576 QSYS_CIR_CFG, 1577 port_ix); 1578 1579 ocelot_rmw_gix(ocelot, 1580 QSYS_SE_CFG_SE_FRM_MODE(0) | 1581 QSYS_SE_CFG_SE_AVB_ENA, 1582 QSYS_SE_CFG_SE_AVB_ENA | 1583 QSYS_SE_CFG_SE_FRM_MODE_M, 1584 QSYS_SE_CFG, 1585 port_ix); 1586 1587 return 0; 1588 } 1589 1590 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1591 enum tc_setup_type type, 1592 void *type_data) 1593 { 1594 struct ocelot *ocelot = ds->priv; 1595 1596 switch (type) { 1597 case TC_SETUP_QDISC_TAPRIO: 1598 return vsc9959_qos_port_tas_set(ocelot, port, type_data); 1599 case TC_SETUP_QDISC_CBS: 1600 return vsc9959_qos_port_cbs_set(ds, port, type_data); 1601 default: 1602 return -EOPNOTSUPP; 1603 } 1604 } 1605 1606 #define VSC9959_PSFP_SFID_MAX 175 1607 #define VSC9959_PSFP_GATE_ID_MAX 183 1608 #define VSC9959_PSFP_POLICER_BASE 63 1609 #define VSC9959_PSFP_POLICER_MAX 383 1610 #define VSC9959_PSFP_GATE_LIST_NUM 4 1611 #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 1612 1613 struct felix_stream { 1614 struct list_head list; 1615 unsigned long id; 1616 bool dummy; 1617 int ports; 1618 int port; 1619 u8 dmac[ETH_ALEN]; 1620 u16 vid; 1621 s8 prio; 1622 u8 sfid_valid; 1623 u8 ssid_valid; 1624 u32 sfid; 1625 u32 ssid; 1626 }; 1627 1628 struct felix_stream_filter { 1629 struct list_head list; 1630 refcount_t refcount; 1631 u32 index; 1632 u8 enable; 1633 int portmask; 1634 u8 sg_valid; 1635 u32 sgid; 1636 u8 fm_valid; 1637 u32 fmid; 1638 u8 prio_valid; 1639 u8 prio; 1640 u32 maxsdu; 1641 }; 1642 1643 struct felix_stream_filter_counters { 1644 u32 match; 1645 u32 not_pass_gate; 1646 u32 not_pass_sdu; 1647 u32 red; 1648 }; 1649 1650 struct felix_stream_gate { 1651 u32 index; 1652 u8 enable; 1653 u8 ipv_valid; 1654 u8 init_ipv; 1655 u64 basetime; 1656 u64 cycletime; 1657 u64 cycletime_ext; 1658 u32 num_entries; 1659 struct action_gate_entry entries[]; 1660 }; 1661 1662 struct felix_stream_gate_entry { 1663 struct list_head list; 1664 refcount_t refcount; 1665 u32 index; 1666 }; 1667 1668 static int vsc9959_stream_identify(struct flow_cls_offload *f, 1669 struct felix_stream *stream) 1670 { 1671 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 1672 struct flow_dissector *dissector = rule->match.dissector; 1673 1674 if (dissector->used_keys & 1675 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 1676 BIT(FLOW_DISSECTOR_KEY_BASIC) | 1677 BIT(FLOW_DISSECTOR_KEY_VLAN) | 1678 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 1679 return -EOPNOTSUPP; 1680 1681 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 1682 struct flow_match_eth_addrs match; 1683 1684 flow_rule_match_eth_addrs(rule, &match); 1685 ether_addr_copy(stream->dmac, match.key->dst); 1686 if (!is_zero_ether_addr(match.mask->src)) 1687 return -EOPNOTSUPP; 1688 } else { 1689 return -EOPNOTSUPP; 1690 } 1691 1692 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 1693 struct flow_match_vlan match; 1694 1695 flow_rule_match_vlan(rule, &match); 1696 if (match.mask->vlan_priority) 1697 stream->prio = match.key->vlan_priority; 1698 else 1699 stream->prio = -1; 1700 1701 if (!match.mask->vlan_id) 1702 return -EOPNOTSUPP; 1703 stream->vid = match.key->vlan_id; 1704 } else { 1705 return -EOPNOTSUPP; 1706 } 1707 1708 stream->id = f->cookie; 1709 1710 return 0; 1711 } 1712 1713 static int vsc9959_mact_stream_set(struct ocelot *ocelot, 1714 struct felix_stream *stream, 1715 struct netlink_ext_ack *extack) 1716 { 1717 enum macaccess_entry_type type; 1718 int ret, sfid, ssid; 1719 u32 vid, dst_idx; 1720 u8 mac[ETH_ALEN]; 1721 1722 ether_addr_copy(mac, stream->dmac); 1723 vid = stream->vid; 1724 1725 /* Stream identification desn't support to add a stream with non 1726 * existent MAC (The MAC entry has not been learned in MAC table). 1727 */ 1728 ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 1729 if (ret) { 1730 if (extack) 1731 NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 1732 return -EOPNOTSUPP; 1733 } 1734 1735 if ((stream->sfid_valid || stream->ssid_valid) && 1736 type == ENTRYTYPE_NORMAL) 1737 type = ENTRYTYPE_LOCKED; 1738 1739 sfid = stream->sfid_valid ? stream->sfid : -1; 1740 ssid = stream->ssid_valid ? stream->ssid : -1; 1741 1742 ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 1743 sfid, ssid); 1744 1745 return ret; 1746 } 1747 1748 static struct felix_stream * 1749 vsc9959_stream_table_lookup(struct list_head *stream_list, 1750 struct felix_stream *stream) 1751 { 1752 struct felix_stream *tmp; 1753 1754 list_for_each_entry(tmp, stream_list, list) 1755 if (ether_addr_equal(tmp->dmac, stream->dmac) && 1756 tmp->vid == stream->vid) 1757 return tmp; 1758 1759 return NULL; 1760 } 1761 1762 static int vsc9959_stream_table_add(struct ocelot *ocelot, 1763 struct list_head *stream_list, 1764 struct felix_stream *stream, 1765 struct netlink_ext_ack *extack) 1766 { 1767 struct felix_stream *stream_entry; 1768 int ret; 1769 1770 stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL); 1771 if (!stream_entry) 1772 return -ENOMEM; 1773 1774 if (!stream->dummy) { 1775 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 1776 if (ret) { 1777 kfree(stream_entry); 1778 return ret; 1779 } 1780 } 1781 1782 list_add_tail(&stream_entry->list, stream_list); 1783 1784 return 0; 1785 } 1786 1787 static struct felix_stream * 1788 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 1789 { 1790 struct felix_stream *tmp; 1791 1792 list_for_each_entry(tmp, stream_list, list) 1793 if (tmp->id == id) 1794 return tmp; 1795 1796 return NULL; 1797 } 1798 1799 static void vsc9959_stream_table_del(struct ocelot *ocelot, 1800 struct felix_stream *stream) 1801 { 1802 if (!stream->dummy) 1803 vsc9959_mact_stream_set(ocelot, stream, NULL); 1804 1805 list_del(&stream->list); 1806 kfree(stream); 1807 } 1808 1809 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 1810 { 1811 return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 1812 } 1813 1814 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 1815 struct felix_stream_filter *sfi) 1816 { 1817 u32 val; 1818 1819 if (sfi->index > VSC9959_PSFP_SFID_MAX) 1820 return -EINVAL; 1821 1822 if (!sfi->enable) { 1823 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1824 ANA_TABLES_SFIDTIDX); 1825 1826 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 1827 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 1828 1829 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1830 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1831 10, 100000); 1832 } 1833 1834 if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 1835 sfi->fmid > VSC9959_PSFP_POLICER_MAX) 1836 return -EINVAL; 1837 1838 ocelot_write(ocelot, 1839 (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 1840 ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 1841 (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 1842 ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 1843 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1844 ANA_TABLES_SFIDTIDX); 1845 1846 ocelot_write(ocelot, 1847 (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 1848 ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 1849 ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 1850 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1851 ANA_TABLES_SFIDACCESS); 1852 1853 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1854 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1855 10, 100000); 1856 } 1857 1858 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) 1859 { 1860 u32 val; 1861 1862 ocelot_rmw(ocelot, 1863 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), 1864 ANA_TABLES_SFIDTIDX_SFID_INDEX_M, 1865 ANA_TABLES_SFIDTIDX); 1866 1867 ocelot_write(ocelot, 1868 ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | 1869 ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, 1870 ANA_TABLES_SFID_MASK); 1871 1872 ocelot_rmw(ocelot, 1873 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1874 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, 1875 ANA_TABLES_SFIDACCESS); 1876 1877 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1878 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1879 10, 100000); 1880 } 1881 1882 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, 1883 struct felix_stream_filter *sfi, 1884 struct list_head *pos) 1885 { 1886 struct felix_stream_filter *sfi_entry; 1887 int ret; 1888 1889 sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL); 1890 if (!sfi_entry) 1891 return -ENOMEM; 1892 1893 refcount_set(&sfi_entry->refcount, 1); 1894 1895 ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 1896 if (ret) { 1897 kfree(sfi_entry); 1898 return ret; 1899 } 1900 1901 vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask); 1902 1903 list_add(&sfi_entry->list, pos); 1904 1905 return 0; 1906 } 1907 1908 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 1909 struct felix_stream_filter *sfi) 1910 { 1911 struct list_head *pos, *q, *last; 1912 struct felix_stream_filter *tmp; 1913 struct ocelot_psfp_list *psfp; 1914 u32 insert = 0; 1915 1916 psfp = &ocelot->psfp; 1917 last = &psfp->sfi_list; 1918 1919 list_for_each_safe(pos, q, &psfp->sfi_list) { 1920 tmp = list_entry(pos, struct felix_stream_filter, list); 1921 if (sfi->sg_valid == tmp->sg_valid && 1922 sfi->fm_valid == tmp->fm_valid && 1923 sfi->portmask == tmp->portmask && 1924 tmp->sgid == sfi->sgid && 1925 tmp->fmid == sfi->fmid) { 1926 sfi->index = tmp->index; 1927 refcount_inc(&tmp->refcount); 1928 return 0; 1929 } 1930 /* Make sure that the index is increasing in order. */ 1931 if (tmp->index == insert) { 1932 last = pos; 1933 insert++; 1934 } 1935 } 1936 sfi->index = insert; 1937 1938 return vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1939 } 1940 1941 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, 1942 struct felix_stream_filter *sfi, 1943 struct felix_stream_filter *sfi2) 1944 { 1945 struct felix_stream_filter *tmp; 1946 struct list_head *pos, *q, *last; 1947 struct ocelot_psfp_list *psfp; 1948 u32 insert = 0; 1949 int ret; 1950 1951 psfp = &ocelot->psfp; 1952 last = &psfp->sfi_list; 1953 1954 list_for_each_safe(pos, q, &psfp->sfi_list) { 1955 tmp = list_entry(pos, struct felix_stream_filter, list); 1956 /* Make sure that the index is increasing in order. */ 1957 if (tmp->index >= insert + 2) 1958 break; 1959 1960 insert = tmp->index + 1; 1961 last = pos; 1962 } 1963 sfi->index = insert; 1964 1965 ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1966 if (ret) 1967 return ret; 1968 1969 sfi2->index = insert + 1; 1970 1971 return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next); 1972 } 1973 1974 static struct felix_stream_filter * 1975 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 1976 { 1977 struct felix_stream_filter *tmp; 1978 1979 list_for_each_entry(tmp, sfi_list, list) 1980 if (tmp->index == index) 1981 return tmp; 1982 1983 return NULL; 1984 } 1985 1986 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 1987 { 1988 struct felix_stream_filter *tmp, *n; 1989 struct ocelot_psfp_list *psfp; 1990 u8 z; 1991 1992 psfp = &ocelot->psfp; 1993 1994 list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 1995 if (tmp->index == index) { 1996 z = refcount_dec_and_test(&tmp->refcount); 1997 if (z) { 1998 tmp->enable = 0; 1999 vsc9959_psfp_sfi_set(ocelot, tmp); 2000 list_del(&tmp->list); 2001 kfree(tmp); 2002 } 2003 break; 2004 } 2005 } 2006 2007 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 2008 struct felix_stream_gate *sgi) 2009 { 2010 sgi->index = entry->hw_index; 2011 sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 2012 sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 2013 sgi->basetime = entry->gate.basetime; 2014 sgi->cycletime = entry->gate.cycletime; 2015 sgi->num_entries = entry->gate.num_entries; 2016 sgi->enable = 1; 2017 2018 memcpy(sgi->entries, entry->gate.entries, 2019 entry->gate.num_entries * sizeof(struct action_gate_entry)); 2020 } 2021 2022 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 2023 { 2024 return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 2025 } 2026 2027 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 2028 struct felix_stream_gate *sgi) 2029 { 2030 struct action_gate_entry *e; 2031 struct timespec64 base_ts; 2032 u32 interval_sum = 0; 2033 u32 val; 2034 int i; 2035 2036 if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 2037 return -EINVAL; 2038 2039 ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 2040 ANA_SG_ACCESS_CTRL); 2041 2042 if (!sgi->enable) { 2043 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 2044 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2045 ANA_SG_CONFIG_REG_3_GATE_ENABLE, 2046 ANA_SG_CONFIG_REG_3); 2047 2048 return 0; 2049 } 2050 2051 if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 2052 sgi->cycletime > NSEC_PER_SEC) 2053 return -EINVAL; 2054 2055 if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 2056 return -EINVAL; 2057 2058 vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 2059 ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 2060 val = lower_32_bits(base_ts.tv_sec); 2061 ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 2062 2063 val = upper_32_bits(base_ts.tv_sec); 2064 ocelot_write(ocelot, 2065 (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 2066 ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 2067 ANA_SG_CONFIG_REG_3_GATE_ENABLE | 2068 ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 2069 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2070 ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 2071 ANA_SG_CONFIG_REG_3); 2072 2073 ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 2074 2075 e = sgi->entries; 2076 for (i = 0; i < sgi->num_entries; i++) { 2077 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 2078 2079 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 2080 (e[i].gate_state ? 2081 ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 2082 ANA_SG_GCL_GS_CONFIG, i); 2083 2084 interval_sum += e[i].interval; 2085 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 2086 } 2087 2088 ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2089 ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2090 ANA_SG_ACCESS_CTRL); 2091 2092 return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 2093 (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 2094 10, 100000); 2095 } 2096 2097 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 2098 struct felix_stream_gate *sgi) 2099 { 2100 struct felix_stream_gate_entry *tmp; 2101 struct ocelot_psfp_list *psfp; 2102 int ret; 2103 2104 psfp = &ocelot->psfp; 2105 2106 list_for_each_entry(tmp, &psfp->sgi_list, list) 2107 if (tmp->index == sgi->index) { 2108 refcount_inc(&tmp->refcount); 2109 return 0; 2110 } 2111 2112 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 2113 if (!tmp) 2114 return -ENOMEM; 2115 2116 ret = vsc9959_psfp_sgi_set(ocelot, sgi); 2117 if (ret) { 2118 kfree(tmp); 2119 return ret; 2120 } 2121 2122 tmp->index = sgi->index; 2123 refcount_set(&tmp->refcount, 1); 2124 list_add_tail(&tmp->list, &psfp->sgi_list); 2125 2126 return 0; 2127 } 2128 2129 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 2130 u32 index) 2131 { 2132 struct felix_stream_gate_entry *tmp, *n; 2133 struct felix_stream_gate sgi = {0}; 2134 struct ocelot_psfp_list *psfp; 2135 u8 z; 2136 2137 psfp = &ocelot->psfp; 2138 2139 list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 2140 if (tmp->index == index) { 2141 z = refcount_dec_and_test(&tmp->refcount); 2142 if (z) { 2143 sgi.index = index; 2144 sgi.enable = 0; 2145 vsc9959_psfp_sgi_set(ocelot, &sgi); 2146 list_del(&tmp->list); 2147 kfree(tmp); 2148 } 2149 break; 2150 } 2151 } 2152 2153 static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index, 2154 struct felix_stream_filter_counters *counters) 2155 { 2156 mutex_lock(&ocelot->stats_lock); 2157 2158 ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index), 2159 SYS_STAT_CFG_STAT_VIEW_M, 2160 SYS_STAT_CFG); 2161 2162 counters->match = ocelot_read_gix(ocelot, SYS_CNT, 0x200); 2163 counters->not_pass_gate = ocelot_read_gix(ocelot, SYS_CNT, 0x201); 2164 counters->not_pass_sdu = ocelot_read_gix(ocelot, SYS_CNT, 0x202); 2165 counters->red = ocelot_read_gix(ocelot, SYS_CNT, 0x203); 2166 2167 /* Clear the PSFP counter. */ 2168 ocelot_write(ocelot, 2169 SYS_STAT_CFG_STAT_VIEW(index) | 2170 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 2171 SYS_STAT_CFG); 2172 2173 mutex_unlock(&ocelot->stats_lock); 2174 } 2175 2176 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, 2177 struct flow_cls_offload *f) 2178 { 2179 struct netlink_ext_ack *extack = f->common.extack; 2180 struct felix_stream_filter old_sfi, *sfi_entry; 2181 struct felix_stream_filter sfi = {0}; 2182 const struct flow_action_entry *a; 2183 struct felix_stream *stream_entry; 2184 struct felix_stream stream = {0}; 2185 struct felix_stream_gate *sgi; 2186 struct ocelot_psfp_list *psfp; 2187 struct ocelot_policer pol; 2188 int ret, i, size; 2189 u64 rate, burst; 2190 u32 index; 2191 2192 psfp = &ocelot->psfp; 2193 2194 ret = vsc9959_stream_identify(f, &stream); 2195 if (ret) { 2196 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 2197 return ret; 2198 } 2199 2200 flow_action_for_each(i, a, &f->rule->action) { 2201 switch (a->id) { 2202 case FLOW_ACTION_GATE: 2203 size = struct_size(sgi, entries, a->gate.num_entries); 2204 sgi = kzalloc(size, GFP_KERNEL); 2205 if (!sgi) { 2206 ret = -ENOMEM; 2207 goto err; 2208 } 2209 vsc9959_psfp_parse_gate(a, sgi); 2210 ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 2211 if (ret) { 2212 kfree(sgi); 2213 goto err; 2214 } 2215 sfi.sg_valid = 1; 2216 sfi.sgid = sgi->index; 2217 kfree(sgi); 2218 break; 2219 case FLOW_ACTION_POLICE: 2220 index = a->hw_index + VSC9959_PSFP_POLICER_BASE; 2221 if (index > VSC9959_PSFP_POLICER_MAX) { 2222 ret = -EINVAL; 2223 goto err; 2224 } 2225 2226 rate = a->police.rate_bytes_ps; 2227 burst = rate * PSCHED_NS2TICKS(a->police.burst); 2228 pol = (struct ocelot_policer) { 2229 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC), 2230 .rate = div_u64(rate, 1000) * 8, 2231 }; 2232 ret = ocelot_vcap_policer_add(ocelot, index, &pol); 2233 if (ret) 2234 goto err; 2235 2236 sfi.fm_valid = 1; 2237 sfi.fmid = index; 2238 sfi.maxsdu = a->police.mtu; 2239 break; 2240 default: 2241 return -EOPNOTSUPP; 2242 } 2243 } 2244 2245 stream.ports = BIT(port); 2246 stream.port = port; 2247 2248 sfi.portmask = stream.ports; 2249 sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 2250 sfi.prio = (sfi.prio_valid ? stream.prio : 0); 2251 sfi.enable = 1; 2252 2253 /* Check if stream is set. */ 2254 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 2255 if (stream_entry) { 2256 if (stream_entry->ports & BIT(port)) { 2257 NL_SET_ERR_MSG_MOD(extack, 2258 "The stream is added on this port"); 2259 ret = -EEXIST; 2260 goto err; 2261 } 2262 2263 if (stream_entry->ports != BIT(stream_entry->port)) { 2264 NL_SET_ERR_MSG_MOD(extack, 2265 "The stream is added on two ports"); 2266 ret = -EEXIST; 2267 goto err; 2268 } 2269 2270 stream_entry->ports |= BIT(port); 2271 stream.ports = stream_entry->ports; 2272 2273 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, 2274 stream_entry->sfid); 2275 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); 2276 2277 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid); 2278 2279 old_sfi.portmask = stream_entry->ports; 2280 sfi.portmask = stream.ports; 2281 2282 if (stream_entry->port > port) { 2283 ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi, 2284 &old_sfi); 2285 stream_entry->dummy = true; 2286 } else { 2287 ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi, 2288 &sfi); 2289 stream.dummy = true; 2290 } 2291 if (ret) 2292 goto err; 2293 2294 stream_entry->sfid = old_sfi.index; 2295 } else { 2296 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 2297 if (ret) 2298 goto err; 2299 } 2300 2301 stream.sfid = sfi.index; 2302 stream.sfid_valid = 1; 2303 ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 2304 &stream, extack); 2305 if (ret) { 2306 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 2307 goto err; 2308 } 2309 2310 return 0; 2311 2312 err: 2313 if (sfi.sg_valid) 2314 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 2315 2316 if (sfi.fm_valid) 2317 ocelot_vcap_policer_del(ocelot, sfi.fmid); 2318 2319 return ret; 2320 } 2321 2322 static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 2323 struct flow_cls_offload *f) 2324 { 2325 struct felix_stream *stream, tmp, *stream_entry; 2326 static struct felix_stream_filter *sfi; 2327 struct ocelot_psfp_list *psfp; 2328 2329 psfp = &ocelot->psfp; 2330 2331 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2332 if (!stream) 2333 return -ENOMEM; 2334 2335 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2336 if (!sfi) 2337 return -ENOMEM; 2338 2339 if (sfi->sg_valid) 2340 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 2341 2342 if (sfi->fm_valid) 2343 ocelot_vcap_policer_del(ocelot, sfi->fmid); 2344 2345 vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 2346 2347 memcpy(&tmp, stream, sizeof(tmp)); 2348 2349 stream->sfid_valid = 0; 2350 vsc9959_stream_table_del(ocelot, stream); 2351 2352 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp); 2353 if (stream_entry) { 2354 stream_entry->ports = BIT(stream_entry->port); 2355 if (stream_entry->dummy) { 2356 stream_entry->dummy = false; 2357 vsc9959_mact_stream_set(ocelot, stream_entry, NULL); 2358 } 2359 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid, 2360 stream_entry->ports); 2361 } 2362 2363 return 0; 2364 } 2365 2366 static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 2367 struct flow_cls_offload *f, 2368 struct flow_stats *stats) 2369 { 2370 struct felix_stream_filter_counters counters; 2371 struct ocelot_psfp_list *psfp; 2372 struct felix_stream *stream; 2373 2374 psfp = &ocelot->psfp; 2375 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2376 if (!stream) 2377 return -ENOMEM; 2378 2379 vsc9959_psfp_counters_get(ocelot, stream->sfid, &counters); 2380 2381 stats->pkts = counters.match; 2382 stats->drops = counters.not_pass_gate + counters.not_pass_sdu + 2383 counters.red; 2384 2385 return 0; 2386 } 2387 2388 static void vsc9959_psfp_init(struct ocelot *ocelot) 2389 { 2390 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2391 2392 INIT_LIST_HEAD(&psfp->stream_list); 2393 INIT_LIST_HEAD(&psfp->sfi_list); 2394 INIT_LIST_HEAD(&psfp->sgi_list); 2395 } 2396 2397 /* When using cut-through forwarding and the egress port runs at a higher data 2398 * rate than the ingress port, the packet currently under transmission would 2399 * suffer an underrun since it would be transmitted faster than it is received. 2400 * The Felix switch implementation of cut-through forwarding does not check in 2401 * hardware whether this condition is satisfied or not, so we must restrict the 2402 * list of ports that have cut-through forwarding enabled on egress to only be 2403 * the ports operating at the lowest link speed within their respective 2404 * forwarding domain. 2405 */ 2406 static void vsc9959_cut_through_fwd(struct ocelot *ocelot) 2407 { 2408 struct felix *felix = ocelot_to_felix(ocelot); 2409 struct dsa_switch *ds = felix->ds; 2410 int port, other_port; 2411 2412 lockdep_assert_held(&ocelot->fwd_domain_lock); 2413 2414 for (port = 0; port < ocelot->num_phys_ports; port++) { 2415 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2416 int min_speed = ocelot_port->speed; 2417 unsigned long mask = 0; 2418 u32 tmp, val = 0; 2419 2420 /* Disable cut-through on ports that are down */ 2421 if (ocelot_port->speed <= 0) 2422 goto set; 2423 2424 if (dsa_is_cpu_port(ds, port)) { 2425 /* Ocelot switches forward from the NPI port towards 2426 * any port, regardless of it being in the NPI port's 2427 * forwarding domain or not. 2428 */ 2429 mask = dsa_user_ports(ds); 2430 } else { 2431 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 2432 mask &= ~BIT(port); 2433 if (ocelot->npi >= 0) 2434 mask |= BIT(ocelot->npi); 2435 else 2436 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 2437 port); 2438 } 2439 2440 /* Calculate the minimum link speed, among the ports that are 2441 * up, of this source port's forwarding domain. 2442 */ 2443 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { 2444 struct ocelot_port *other_ocelot_port; 2445 2446 other_ocelot_port = ocelot->ports[other_port]; 2447 if (other_ocelot_port->speed <= 0) 2448 continue; 2449 2450 if (min_speed > other_ocelot_port->speed) 2451 min_speed = other_ocelot_port->speed; 2452 } 2453 2454 /* Enable cut-through forwarding for all traffic classes. */ 2455 if (ocelot_port->speed == min_speed) 2456 val = GENMASK(7, 0); 2457 2458 set: 2459 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); 2460 if (tmp == val) 2461 continue; 2462 2463 dev_dbg(ocelot->dev, 2464 "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding\n", 2465 port, mask, ocelot_port->speed, min_speed, 2466 val ? "enabling" : "disabling"); 2467 2468 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); 2469 } 2470 } 2471 2472 static const struct ocelot_ops vsc9959_ops = { 2473 .reset = vsc9959_reset, 2474 .wm_enc = vsc9959_wm_enc, 2475 .wm_dec = vsc9959_wm_dec, 2476 .wm_stat = vsc9959_wm_stat, 2477 .port_to_netdev = felix_port_to_netdev, 2478 .netdev_to_port = felix_netdev_to_port, 2479 .psfp_init = vsc9959_psfp_init, 2480 .psfp_filter_add = vsc9959_psfp_filter_add, 2481 .psfp_filter_del = vsc9959_psfp_filter_del, 2482 .psfp_stats_get = vsc9959_psfp_stats_get, 2483 .cut_through_fwd = vsc9959_cut_through_fwd, 2484 .tas_clock_adjust = vsc9959_tas_clock_adjust, 2485 }; 2486 2487 static const struct felix_info felix_info_vsc9959 = { 2488 .target_io_res = vsc9959_target_io_res, 2489 .port_io_res = vsc9959_port_io_res, 2490 .imdio_res = &vsc9959_imdio_res, 2491 .regfields = vsc9959_regfields, 2492 .map = vsc9959_regmap, 2493 .ops = &vsc9959_ops, 2494 .stats_layout = vsc9959_stats_layout, 2495 .vcap = vsc9959_vcap_props, 2496 .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 2497 .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 2498 .vcap_pol_base2 = 0, 2499 .vcap_pol_max2 = 0, 2500 .num_mact_rows = 2048, 2501 .num_ports = VSC9959_NUM_PORTS, 2502 .num_tx_queues = OCELOT_NUM_TC, 2503 .quirk_no_xtr_irq = true, 2504 .ptp_caps = &vsc9959_ptp_caps, 2505 .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2506 .mdio_bus_free = vsc9959_mdio_bus_free, 2507 .phylink_validate = vsc9959_phylink_validate, 2508 .port_modes = vsc9959_port_modes, 2509 .port_setup_tc = vsc9959_port_setup_tc, 2510 .port_sched_speed_set = vsc9959_sched_speed_set, 2511 .tas_guard_bands_update = vsc9959_tas_guard_bands_update, 2512 .init_regmap = ocelot_regmap_init, 2513 }; 2514 2515 static irqreturn_t felix_irq_handler(int irq, void *data) 2516 { 2517 struct ocelot *ocelot = (struct ocelot *)data; 2518 2519 /* The INTB interrupt is used for both PTP TX timestamp interrupt 2520 * and preemption status change interrupt on each port. 2521 * 2522 * - Get txtstamp if have 2523 * - TODO: handle preemption. Without handling it, driver may get 2524 * interrupt storm. 2525 */ 2526 2527 ocelot_get_txtstamp(ocelot); 2528 2529 return IRQ_HANDLED; 2530 } 2531 2532 static int felix_pci_probe(struct pci_dev *pdev, 2533 const struct pci_device_id *id) 2534 { 2535 struct dsa_switch *ds; 2536 struct ocelot *ocelot; 2537 struct felix *felix; 2538 int err; 2539 2540 if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 2541 dev_info(&pdev->dev, "device is disabled, skipping\n"); 2542 return -ENODEV; 2543 } 2544 2545 err = pci_enable_device(pdev); 2546 if (err) { 2547 dev_err(&pdev->dev, "device enable failed\n"); 2548 goto err_pci_enable; 2549 } 2550 2551 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 2552 if (!felix) { 2553 err = -ENOMEM; 2554 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 2555 goto err_alloc_felix; 2556 } 2557 2558 pci_set_drvdata(pdev, felix); 2559 ocelot = &felix->ocelot; 2560 ocelot->dev = &pdev->dev; 2561 ocelot->num_flooding_pgids = OCELOT_NUM_TC; 2562 felix->info = &felix_info_vsc9959; 2563 felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); 2564 felix->imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); 2565 2566 pci_set_master(pdev); 2567 2568 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 2569 &felix_irq_handler, IRQF_ONESHOT, 2570 "felix-intb", ocelot); 2571 if (err) { 2572 dev_err(&pdev->dev, "Failed to request irq\n"); 2573 goto err_alloc_irq; 2574 } 2575 2576 ocelot->ptp = 1; 2577 2578 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 2579 if (!ds) { 2580 err = -ENOMEM; 2581 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 2582 goto err_alloc_ds; 2583 } 2584 2585 ds->dev = &pdev->dev; 2586 ds->num_ports = felix->info->num_ports; 2587 ds->num_tx_queues = felix->info->num_tx_queues; 2588 ds->ops = &felix_switch_ops; 2589 ds->priv = ocelot; 2590 felix->ds = ds; 2591 felix->tag_proto = DSA_TAG_PROTO_OCELOT; 2592 2593 err = dsa_register_switch(ds); 2594 if (err) { 2595 dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n"); 2596 goto err_register_ds; 2597 } 2598 2599 return 0; 2600 2601 err_register_ds: 2602 kfree(ds); 2603 err_alloc_ds: 2604 err_alloc_irq: 2605 kfree(felix); 2606 err_alloc_felix: 2607 pci_disable_device(pdev); 2608 err_pci_enable: 2609 return err; 2610 } 2611 2612 static void felix_pci_remove(struct pci_dev *pdev) 2613 { 2614 struct felix *felix = pci_get_drvdata(pdev); 2615 2616 if (!felix) 2617 return; 2618 2619 dsa_unregister_switch(felix->ds); 2620 2621 kfree(felix->ds); 2622 kfree(felix); 2623 2624 pci_disable_device(pdev); 2625 2626 pci_set_drvdata(pdev, NULL); 2627 } 2628 2629 static void felix_pci_shutdown(struct pci_dev *pdev) 2630 { 2631 struct felix *felix = pci_get_drvdata(pdev); 2632 2633 if (!felix) 2634 return; 2635 2636 dsa_switch_shutdown(felix->ds); 2637 2638 pci_set_drvdata(pdev, NULL); 2639 } 2640 2641 static struct pci_device_id felix_ids[] = { 2642 { 2643 /* NXP LS1028A */ 2644 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 2645 }, 2646 { 0, } 2647 }; 2648 MODULE_DEVICE_TABLE(pci, felix_ids); 2649 2650 static struct pci_driver felix_vsc9959_pci_driver = { 2651 .name = "mscc_felix", 2652 .id_table = felix_ids, 2653 .probe = felix_pci_probe, 2654 .remove = felix_pci_remove, 2655 .shutdown = felix_pci_shutdown, 2656 }; 2657 module_pci_driver(felix_vsc9959_pci_driver); 2658 2659 MODULE_DESCRIPTION("Felix Switch driver"); 2660 MODULE_LICENSE("GPL v2"); 2661