1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright 2017 Microsemi Corporation 3 * Copyright 2018-2019 NXP 4 */ 5 #include <linux/fsl/enetc_mdio.h> 6 #include <soc/mscc/ocelot_qsys.h> 7 #include <soc/mscc/ocelot_vcap.h> 8 #include <soc/mscc/ocelot_ana.h> 9 #include <soc/mscc/ocelot_ptp.h> 10 #include <soc/mscc/ocelot_sys.h> 11 #include <net/tc_act/tc_gate.h> 12 #include <soc/mscc/ocelot.h> 13 #include <linux/dsa/ocelot.h> 14 #include <linux/pcs-lynx.h> 15 #include <net/pkt_sched.h> 16 #include <linux/iopoll.h> 17 #include <linux/mdio.h> 18 #include <linux/pci.h> 19 #include <linux/time.h> 20 #include "felix.h" 21 22 #define VSC9959_NUM_PORTS 6 23 24 #define VSC9959_TAS_GCL_ENTRY_MAX 63 25 #define VSC9959_VCAP_POLICER_BASE 63 26 #define VSC9959_VCAP_POLICER_MAX 383 27 #define VSC9959_SWITCH_PCI_BAR 4 28 #define VSC9959_IMDIO_PCI_BAR 0 29 30 #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ 31 OCELOT_PORT_MODE_QSGMII | \ 32 OCELOT_PORT_MODE_1000BASEX | \ 33 OCELOT_PORT_MODE_2500BASEX | \ 34 OCELOT_PORT_MODE_USXGMII) 35 36 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { 37 VSC9959_PORT_MODE_SERDES, 38 VSC9959_PORT_MODE_SERDES, 39 VSC9959_PORT_MODE_SERDES, 40 VSC9959_PORT_MODE_SERDES, 41 OCELOT_PORT_MODE_INTERNAL, 42 OCELOT_PORT_MODE_INTERNAL, 43 }; 44 45 static const u32 vsc9959_ana_regmap[] = { 46 REG(ANA_ADVLEARN, 0x0089a0), 47 REG(ANA_VLANMASK, 0x0089a4), 48 REG_RESERVED(ANA_PORT_B_DOMAIN), 49 REG(ANA_ANAGEFIL, 0x0089ac), 50 REG(ANA_ANEVENTS, 0x0089b0), 51 REG(ANA_STORMLIMIT_BURST, 0x0089b4), 52 REG(ANA_STORMLIMIT_CFG, 0x0089b8), 53 REG(ANA_ISOLATED_PORTS, 0x0089c8), 54 REG(ANA_COMMUNITY_PORTS, 0x0089cc), 55 REG(ANA_AUTOAGE, 0x0089d0), 56 REG(ANA_MACTOPTIONS, 0x0089d4), 57 REG(ANA_LEARNDISC, 0x0089d8), 58 REG(ANA_AGENCTRL, 0x0089dc), 59 REG(ANA_MIRRORPORTS, 0x0089e0), 60 REG(ANA_EMIRRORPORTS, 0x0089e4), 61 REG(ANA_FLOODING, 0x0089e8), 62 REG(ANA_FLOODING_IPMC, 0x008a08), 63 REG(ANA_SFLOW_CFG, 0x008a0c), 64 REG(ANA_PORT_MODE, 0x008a28), 65 REG(ANA_CUT_THRU_CFG, 0x008a48), 66 REG(ANA_PGID_PGID, 0x008400), 67 REG(ANA_TABLES_ANMOVED, 0x007f1c), 68 REG(ANA_TABLES_MACHDATA, 0x007f20), 69 REG(ANA_TABLES_MACLDATA, 0x007f24), 70 REG(ANA_TABLES_STREAMDATA, 0x007f28), 71 REG(ANA_TABLES_MACACCESS, 0x007f2c), 72 REG(ANA_TABLES_MACTINDX, 0x007f30), 73 REG(ANA_TABLES_VLANACCESS, 0x007f34), 74 REG(ANA_TABLES_VLANTIDX, 0x007f38), 75 REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 76 REG(ANA_TABLES_ISDXTIDX, 0x007f40), 77 REG(ANA_TABLES_ENTRYLIM, 0x007f00), 78 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 79 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 80 REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 81 REG(ANA_TABLES_STREAMTIDX, 0x007f50), 82 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 83 REG(ANA_TABLES_SEQ_MASK, 0x007f58), 84 REG(ANA_TABLES_SFID_MASK, 0x007f5c), 85 REG(ANA_TABLES_SFIDACCESS, 0x007f60), 86 REG(ANA_TABLES_SFIDTIDX, 0x007f64), 87 REG(ANA_MSTI_STATE, 0x008600), 88 REG(ANA_OAM_UPM_LM_CNT, 0x008000), 89 REG(ANA_SG_ACCESS_CTRL, 0x008a64), 90 REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 91 REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 92 REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 93 REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 94 REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 95 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 96 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 97 REG(ANA_SG_STATUS_REG_1, 0x008980), 98 REG(ANA_SG_STATUS_REG_2, 0x008984), 99 REG(ANA_SG_STATUS_REG_3, 0x008988), 100 REG(ANA_PORT_VLAN_CFG, 0x007800), 101 REG(ANA_PORT_DROP_CFG, 0x007804), 102 REG(ANA_PORT_QOS_CFG, 0x007808), 103 REG(ANA_PORT_VCAP_CFG, 0x00780c), 104 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 105 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 106 REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 107 REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 108 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 109 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 110 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 111 REG(ANA_PORT_PORT_CFG, 0x007870), 112 REG(ANA_PORT_POL_CFG, 0x007874), 113 REG(ANA_PORT_PTP_CFG, 0x007878), 114 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 115 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 116 REG(ANA_PORT_SFID_CFG, 0x007884), 117 REG(ANA_PFC_PFC_CFG, 0x008800), 118 REG_RESERVED(ANA_PFC_PFC_TIMER), 119 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 120 REG_RESERVED(ANA_IPT_IPT), 121 REG_RESERVED(ANA_PPT_PPT), 122 REG_RESERVED(ANA_FID_MAP_FID_MAP), 123 REG(ANA_AGGR_CFG, 0x008a68), 124 REG(ANA_CPUQ_CFG, 0x008a6c), 125 REG_RESERVED(ANA_CPUQ_CFG2), 126 REG(ANA_CPUQ_8021_CFG, 0x008a74), 127 REG(ANA_DSCP_CFG, 0x008ab4), 128 REG(ANA_DSCP_REWR_CFG, 0x008bb4), 129 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 130 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 131 REG_RESERVED(ANA_VRAP_CFG), 132 REG_RESERVED(ANA_VRAP_HDR_DATA), 133 REG_RESERVED(ANA_VRAP_HDR_MASK), 134 REG(ANA_DISCARD_CFG, 0x008c40), 135 REG(ANA_FID_CFG, 0x008c44), 136 REG(ANA_POL_PIR_CFG, 0x004000), 137 REG(ANA_POL_CIR_CFG, 0x004004), 138 REG(ANA_POL_MODE_CFG, 0x004008), 139 REG(ANA_POL_PIR_STATE, 0x00400c), 140 REG(ANA_POL_CIR_STATE, 0x004010), 141 REG_RESERVED(ANA_POL_STATE), 142 REG(ANA_POL_FLOWC, 0x008c48), 143 REG(ANA_POL_HYST, 0x008cb4), 144 REG_RESERVED(ANA_POL_MISC_CFG), 145 }; 146 147 static const u32 vsc9959_qs_regmap[] = { 148 REG(QS_XTR_GRP_CFG, 0x000000), 149 REG(QS_XTR_RD, 0x000008), 150 REG(QS_XTR_FRM_PRUNING, 0x000010), 151 REG(QS_XTR_FLUSH, 0x000018), 152 REG(QS_XTR_DATA_PRESENT, 0x00001c), 153 REG(QS_XTR_CFG, 0x000020), 154 REG(QS_INJ_GRP_CFG, 0x000024), 155 REG(QS_INJ_WR, 0x00002c), 156 REG(QS_INJ_CTRL, 0x000034), 157 REG(QS_INJ_STATUS, 0x00003c), 158 REG(QS_INJ_ERR, 0x000040), 159 REG_RESERVED(QS_INH_DBG), 160 }; 161 162 static const u32 vsc9959_vcap_regmap[] = { 163 /* VCAP_CORE_CFG */ 164 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 165 REG(VCAP_CORE_MV_CFG, 0x000004), 166 /* VCAP_CORE_CACHE */ 167 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 168 REG(VCAP_CACHE_MASK_DAT, 0x000108), 169 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 170 REG(VCAP_CACHE_CNT_DAT, 0x000308), 171 REG(VCAP_CACHE_TG_DAT, 0x000388), 172 /* VCAP_CONST */ 173 REG(VCAP_CONST_VCAP_VER, 0x000398), 174 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 175 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 176 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 177 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 178 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 179 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 180 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 181 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 182 REG(VCAP_CONST_IF_CNT, 0x0003bc), 183 }; 184 185 static const u32 vsc9959_qsys_regmap[] = { 186 REG(QSYS_PORT_MODE, 0x00f460), 187 REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 188 REG(QSYS_STAT_CNT_CFG, 0x00f49c), 189 REG(QSYS_EEE_CFG, 0x00f4a0), 190 REG(QSYS_EEE_THRES, 0x00f4b8), 191 REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 192 REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 193 REG(QSYS_SW_STATUS, 0x00f4c4), 194 REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 195 REG_RESERVED(QSYS_PAD_CFG), 196 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 197 REG_RESERVED(QSYS_QMAP), 198 REG_RESERVED(QSYS_ISDX_SGRP), 199 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 200 REG(QSYS_TFRM_MISC, 0x00f50c), 201 REG(QSYS_TFRM_PORT_DLY, 0x00f510), 202 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 203 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 204 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 205 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 206 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 207 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 208 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 209 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 210 REG(QSYS_RED_PROFILE, 0x00f534), 211 REG(QSYS_RES_QOS_MODE, 0x00f574), 212 REG(QSYS_RES_CFG, 0x00c000), 213 REG(QSYS_RES_STAT, 0x00c004), 214 REG(QSYS_EGR_DROP_MODE, 0x00f578), 215 REG(QSYS_EQ_CTRL, 0x00f57c), 216 REG_RESERVED(QSYS_EVENTS_CORE), 217 REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 218 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 219 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 220 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 221 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 222 REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 223 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 224 REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 225 REG(QSYS_PREEMPTION_CFG, 0x00f664), 226 REG(QSYS_CIR_CFG, 0x000000), 227 REG(QSYS_EIR_CFG, 0x000004), 228 REG(QSYS_SE_CFG, 0x000008), 229 REG(QSYS_SE_DWRR_CFG, 0x00000c), 230 REG_RESERVED(QSYS_SE_CONNECT), 231 REG(QSYS_SE_DLB_SENSE, 0x000040), 232 REG(QSYS_CIR_STATE, 0x000044), 233 REG(QSYS_EIR_STATE, 0x000048), 234 REG_RESERVED(QSYS_SE_STATE), 235 REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 236 REG(QSYS_TAG_CONFIG, 0x00f680), 237 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 238 REG(QSYS_PORT_MAX_SDU, 0x00f69c), 239 REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 240 REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 241 REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 242 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 243 REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 244 REG(QSYS_GCL_CFG_REG_1, 0x00f454), 245 REG(QSYS_GCL_CFG_REG_2, 0x00f458), 246 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 247 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 248 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 249 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 250 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 251 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 252 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 253 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 254 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 255 REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 256 REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 257 }; 258 259 static const u32 vsc9959_rew_regmap[] = { 260 REG(REW_PORT_VLAN_CFG, 0x000000), 261 REG(REW_TAG_CFG, 0x000004), 262 REG(REW_PORT_CFG, 0x000008), 263 REG(REW_DSCP_CFG, 0x00000c), 264 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 265 REG(REW_PTP_CFG, 0x000050), 266 REG(REW_PTP_DLY1_CFG, 0x000054), 267 REG(REW_RED_TAG_CFG, 0x000058), 268 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 269 REG(REW_DSCP_REMAP_CFG, 0x000510), 270 REG_RESERVED(REW_STAT_CFG), 271 REG_RESERVED(REW_REW_STICKY), 272 REG_RESERVED(REW_PPT), 273 }; 274 275 static const u32 vsc9959_sys_regmap[] = { 276 REG(SYS_COUNT_RX_OCTETS, 0x000000), 277 REG(SYS_COUNT_RX_UNICAST, 0x000004), 278 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 279 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 280 REG(SYS_COUNT_RX_SHORTS, 0x000010), 281 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 282 REG(SYS_COUNT_RX_JABBERS, 0x000018), 283 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 284 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 285 REG(SYS_COUNT_RX_64, 0x000024), 286 REG(SYS_COUNT_RX_65_127, 0x000028), 287 REG(SYS_COUNT_RX_128_255, 0x00002c), 288 REG(SYS_COUNT_RX_256_511, 0x000030), 289 REG(SYS_COUNT_RX_512_1023, 0x000034), 290 REG(SYS_COUNT_RX_1024_1526, 0x000038), 291 REG(SYS_COUNT_RX_1527_MAX, 0x00003c), 292 REG(SYS_COUNT_RX_PAUSE, 0x000040), 293 REG(SYS_COUNT_RX_CONTROL, 0x000044), 294 REG(SYS_COUNT_RX_LONGS, 0x000048), 295 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), 296 REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), 297 REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), 298 REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), 299 REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), 300 REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), 301 REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), 302 REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), 303 REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), 304 REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), 305 REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), 306 REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), 307 REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), 308 REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), 309 REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), 310 REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), 311 REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), 312 REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), 313 REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), 314 REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), 315 REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), 316 REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), 317 REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), 318 REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), 319 REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), 320 REG(SYS_COUNT_TX_OCTETS, 0x000200), 321 REG(SYS_COUNT_TX_UNICAST, 0x000204), 322 REG(SYS_COUNT_TX_MULTICAST, 0x000208), 323 REG(SYS_COUNT_TX_BROADCAST, 0x00020c), 324 REG(SYS_COUNT_TX_COLLISION, 0x000210), 325 REG(SYS_COUNT_TX_DROPS, 0x000214), 326 REG(SYS_COUNT_TX_PAUSE, 0x000218), 327 REG(SYS_COUNT_TX_64, 0x00021c), 328 REG(SYS_COUNT_TX_65_127, 0x000220), 329 REG(SYS_COUNT_TX_128_255, 0x000224), 330 REG(SYS_COUNT_TX_256_511, 0x000228), 331 REG(SYS_COUNT_TX_512_1023, 0x00022c), 332 REG(SYS_COUNT_TX_1024_1526, 0x000230), 333 REG(SYS_COUNT_TX_1527_MAX, 0x000234), 334 REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238), 335 REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c), 336 REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240), 337 REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244), 338 REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248), 339 REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c), 340 REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250), 341 REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254), 342 REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258), 343 REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c), 344 REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260), 345 REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264), 346 REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268), 347 REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c), 348 REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270), 349 REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274), 350 REG(SYS_COUNT_TX_AGING, 0x000278), 351 REG(SYS_COUNT_DROP_LOCAL, 0x000400), 352 REG(SYS_COUNT_DROP_TAIL, 0x000404), 353 REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408), 354 REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c), 355 REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410), 356 REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414), 357 REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418), 358 REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c), 359 REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420), 360 REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424), 361 REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428), 362 REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c), 363 REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430), 364 REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434), 365 REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438), 366 REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c), 367 REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440), 368 REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444), 369 REG(SYS_RESET_CFG, 0x000e00), 370 REG(SYS_SR_ETYPE_CFG, 0x000e04), 371 REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 372 REG(SYS_PORT_MODE, 0x000e0c), 373 REG(SYS_FRONT_PORT_MODE, 0x000e2c), 374 REG(SYS_FRM_AGING, 0x000e44), 375 REG(SYS_STAT_CFG, 0x000e48), 376 REG(SYS_SW_STATUS, 0x000e4c), 377 REG_RESERVED(SYS_MISC_CFG), 378 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 379 REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 380 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 381 REG(SYS_PAUSE_CFG, 0x000ea0), 382 REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 383 REG(SYS_ATOP, 0x000ec0), 384 REG(SYS_ATOP_TOT_CFG, 0x000edc), 385 REG(SYS_MAC_FC_CFG, 0x000ee0), 386 REG(SYS_MMGT, 0x000ef8), 387 REG_RESERVED(SYS_MMGT_FAST), 388 REG_RESERVED(SYS_EVENTS_DIF), 389 REG_RESERVED(SYS_EVENTS_CORE), 390 REG(SYS_CNT, 0x000000), 391 REG(SYS_PTP_STATUS, 0x000f14), 392 REG(SYS_PTP_TXSTAMP, 0x000f18), 393 REG(SYS_PTP_NXT, 0x000f1c), 394 REG(SYS_PTP_CFG, 0x000f20), 395 REG(SYS_RAM_INIT, 0x000f24), 396 REG_RESERVED(SYS_CM_ADDR), 397 REG_RESERVED(SYS_CM_DATA_WR), 398 REG_RESERVED(SYS_CM_DATA_RD), 399 REG_RESERVED(SYS_CM_OP), 400 REG_RESERVED(SYS_CM_DATA), 401 }; 402 403 static const u32 vsc9959_ptp_regmap[] = { 404 REG(PTP_PIN_CFG, 0x000000), 405 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 406 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 407 REG(PTP_PIN_TOD_NSEC, 0x00000c), 408 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 409 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 410 REG(PTP_CFG_MISC, 0x0000a0), 411 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 412 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 413 }; 414 415 static const u32 vsc9959_gcb_regmap[] = { 416 REG(GCB_SOFT_RST, 0x000004), 417 }; 418 419 static const u32 vsc9959_dev_gmii_regmap[] = { 420 REG(DEV_CLOCK_CFG, 0x0), 421 REG(DEV_PORT_MISC, 0x4), 422 REG(DEV_EVENTS, 0x8), 423 REG(DEV_EEE_CFG, 0xc), 424 REG(DEV_RX_PATH_DELAY, 0x10), 425 REG(DEV_TX_PATH_DELAY, 0x14), 426 REG(DEV_PTP_PREDICT_CFG, 0x18), 427 REG(DEV_MAC_ENA_CFG, 0x1c), 428 REG(DEV_MAC_MODE_CFG, 0x20), 429 REG(DEV_MAC_MAXLEN_CFG, 0x24), 430 REG(DEV_MAC_TAGS_CFG, 0x28), 431 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 432 REG(DEV_MAC_IFG_CFG, 0x30), 433 REG(DEV_MAC_HDX_CFG, 0x34), 434 REG(DEV_MAC_DBG_CFG, 0x38), 435 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 436 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 437 REG(DEV_MAC_STICKY, 0x44), 438 REG_RESERVED(PCS1G_CFG), 439 REG_RESERVED(PCS1G_MODE_CFG), 440 REG_RESERVED(PCS1G_SD_CFG), 441 REG_RESERVED(PCS1G_ANEG_CFG), 442 REG_RESERVED(PCS1G_ANEG_NP_CFG), 443 REG_RESERVED(PCS1G_LB_CFG), 444 REG_RESERVED(PCS1G_DBG_CFG), 445 REG_RESERVED(PCS1G_CDET_CFG), 446 REG_RESERVED(PCS1G_ANEG_STATUS), 447 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 448 REG_RESERVED(PCS1G_LINK_STATUS), 449 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 450 REG_RESERVED(PCS1G_STICKY), 451 REG_RESERVED(PCS1G_DEBUG_STATUS), 452 REG_RESERVED(PCS1G_LPI_CFG), 453 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 454 REG_RESERVED(PCS1G_LPI_STATUS), 455 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 456 REG_RESERVED(PCS1G_TSTPAT_STATUS), 457 REG_RESERVED(DEV_PCS_FX100_CFG), 458 REG_RESERVED(DEV_PCS_FX100_STATUS), 459 }; 460 461 static const u32 *vsc9959_regmap[TARGET_MAX] = { 462 [ANA] = vsc9959_ana_regmap, 463 [QS] = vsc9959_qs_regmap, 464 [QSYS] = vsc9959_qsys_regmap, 465 [REW] = vsc9959_rew_regmap, 466 [SYS] = vsc9959_sys_regmap, 467 [S0] = vsc9959_vcap_regmap, 468 [S1] = vsc9959_vcap_regmap, 469 [S2] = vsc9959_vcap_regmap, 470 [PTP] = vsc9959_ptp_regmap, 471 [GCB] = vsc9959_gcb_regmap, 472 [DEV_GMII] = vsc9959_dev_gmii_regmap, 473 }; 474 475 /* Addresses are relative to the PCI device's base address */ 476 static const struct resource vsc9959_target_io_res[TARGET_MAX] = { 477 [ANA] = { 478 .start = 0x0280000, 479 .end = 0x028ffff, 480 .name = "ana", 481 }, 482 [QS] = { 483 .start = 0x0080000, 484 .end = 0x00800ff, 485 .name = "qs", 486 }, 487 [QSYS] = { 488 .start = 0x0200000, 489 .end = 0x021ffff, 490 .name = "qsys", 491 }, 492 [REW] = { 493 .start = 0x0030000, 494 .end = 0x003ffff, 495 .name = "rew", 496 }, 497 [SYS] = { 498 .start = 0x0010000, 499 .end = 0x001ffff, 500 .name = "sys", 501 }, 502 [S0] = { 503 .start = 0x0040000, 504 .end = 0x00403ff, 505 .name = "s0", 506 }, 507 [S1] = { 508 .start = 0x0050000, 509 .end = 0x00503ff, 510 .name = "s1", 511 }, 512 [S2] = { 513 .start = 0x0060000, 514 .end = 0x00603ff, 515 .name = "s2", 516 }, 517 [PTP] = { 518 .start = 0x0090000, 519 .end = 0x00900cb, 520 .name = "ptp", 521 }, 522 [GCB] = { 523 .start = 0x0070000, 524 .end = 0x00701ff, 525 .name = "devcpu_gcb", 526 }, 527 }; 528 529 static const struct resource vsc9959_port_io_res[] = { 530 { 531 .start = 0x0100000, 532 .end = 0x010ffff, 533 .name = "port0", 534 }, 535 { 536 .start = 0x0110000, 537 .end = 0x011ffff, 538 .name = "port1", 539 }, 540 { 541 .start = 0x0120000, 542 .end = 0x012ffff, 543 .name = "port2", 544 }, 545 { 546 .start = 0x0130000, 547 .end = 0x013ffff, 548 .name = "port3", 549 }, 550 { 551 .start = 0x0140000, 552 .end = 0x014ffff, 553 .name = "port4", 554 }, 555 { 556 .start = 0x0150000, 557 .end = 0x015ffff, 558 .name = "port5", 559 }, 560 }; 561 562 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 563 * SGMII/QSGMII MAC PCS can be found. 564 */ 565 static const struct resource vsc9959_imdio_res = { 566 .start = 0x8030, 567 .end = 0x8040, 568 .name = "imdio", 569 }; 570 571 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 572 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 573 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 574 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 575 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 576 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 577 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 578 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 579 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 580 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 581 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 582 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 583 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 584 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 585 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 586 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 587 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 588 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 589 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 590 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 591 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 592 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 593 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 594 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 595 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 596 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 597 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 598 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 599 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 600 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 601 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 602 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 603 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 604 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 605 /* Replicated per number of ports (7), register size 4 per port */ 606 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 607 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 608 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 609 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 610 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 611 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 612 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 613 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 614 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 615 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 616 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 617 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 618 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 619 }; 620 621 static const struct ocelot_stat_layout vsc9959_stats_layout[OCELOT_NUM_STATS] = { 622 [OCELOT_STAT_RX_OCTETS] = { 623 .name = "rx_octets", 624 .reg = SYS_COUNT_RX_OCTETS, 625 }, 626 [OCELOT_STAT_RX_UNICAST] = { 627 .name = "rx_unicast", 628 .reg = SYS_COUNT_RX_UNICAST, 629 }, 630 [OCELOT_STAT_RX_MULTICAST] = { 631 .name = "rx_multicast", 632 .reg = SYS_COUNT_RX_MULTICAST, 633 }, 634 [OCELOT_STAT_RX_BROADCAST] = { 635 .name = "rx_broadcast", 636 .reg = SYS_COUNT_RX_BROADCAST, 637 }, 638 [OCELOT_STAT_RX_SHORTS] = { 639 .name = "rx_shorts", 640 .reg = SYS_COUNT_RX_SHORTS, 641 }, 642 [OCELOT_STAT_RX_FRAGMENTS] = { 643 .name = "rx_fragments", 644 .reg = SYS_COUNT_RX_FRAGMENTS, 645 }, 646 [OCELOT_STAT_RX_JABBERS] = { 647 .name = "rx_jabbers", 648 .reg = SYS_COUNT_RX_JABBERS, 649 }, 650 [OCELOT_STAT_RX_CRC_ALIGN_ERRS] = { 651 .name = "rx_crc_align_errs", 652 .reg = SYS_COUNT_RX_CRC_ALIGN_ERRS, 653 }, 654 [OCELOT_STAT_RX_SYM_ERRS] = { 655 .name = "rx_sym_errs", 656 .reg = SYS_COUNT_RX_SYM_ERRS, 657 }, 658 [OCELOT_STAT_RX_64] = { 659 .name = "rx_frames_below_65_octets", 660 .reg = SYS_COUNT_RX_64, 661 }, 662 [OCELOT_STAT_RX_65_127] = { 663 .name = "rx_frames_65_to_127_octets", 664 .reg = SYS_COUNT_RX_65_127, 665 }, 666 [OCELOT_STAT_RX_128_255] = { 667 .name = "rx_frames_128_to_255_octets", 668 .reg = SYS_COUNT_RX_128_255, 669 }, 670 [OCELOT_STAT_RX_256_511] = { 671 .name = "rx_frames_256_to_511_octets", 672 .reg = SYS_COUNT_RX_256_511, 673 }, 674 [OCELOT_STAT_RX_512_1023] = { 675 .name = "rx_frames_512_to_1023_octets", 676 .reg = SYS_COUNT_RX_512_1023, 677 }, 678 [OCELOT_STAT_RX_1024_1526] = { 679 .name = "rx_frames_1024_to_1526_octets", 680 .reg = SYS_COUNT_RX_1024_1526, 681 }, 682 [OCELOT_STAT_RX_1527_MAX] = { 683 .name = "rx_frames_over_1526_octets", 684 .reg = SYS_COUNT_RX_1527_MAX, 685 }, 686 [OCELOT_STAT_RX_PAUSE] = { 687 .name = "rx_pause", 688 .reg = SYS_COUNT_RX_PAUSE, 689 }, 690 [OCELOT_STAT_RX_CONTROL] = { 691 .name = "rx_control", 692 .reg = SYS_COUNT_RX_CONTROL, 693 }, 694 [OCELOT_STAT_RX_LONGS] = { 695 .name = "rx_longs", 696 .reg = SYS_COUNT_RX_LONGS, 697 }, 698 [OCELOT_STAT_RX_CLASSIFIED_DROPS] = { 699 .name = "rx_classified_drops", 700 .reg = SYS_COUNT_RX_CLASSIFIED_DROPS, 701 }, 702 [OCELOT_STAT_RX_RED_PRIO_0] = { 703 .name = "rx_red_prio_0", 704 .reg = SYS_COUNT_RX_RED_PRIO_0, 705 }, 706 [OCELOT_STAT_RX_RED_PRIO_1] = { 707 .name = "rx_red_prio_1", 708 .reg = SYS_COUNT_RX_RED_PRIO_1, 709 }, 710 [OCELOT_STAT_RX_RED_PRIO_2] = { 711 .name = "rx_red_prio_2", 712 .reg = SYS_COUNT_RX_RED_PRIO_2, 713 }, 714 [OCELOT_STAT_RX_RED_PRIO_3] = { 715 .name = "rx_red_prio_3", 716 .reg = SYS_COUNT_RX_RED_PRIO_3, 717 }, 718 [OCELOT_STAT_RX_RED_PRIO_4] = { 719 .name = "rx_red_prio_4", 720 .reg = SYS_COUNT_RX_RED_PRIO_4, 721 }, 722 [OCELOT_STAT_RX_RED_PRIO_5] = { 723 .name = "rx_red_prio_5", 724 .reg = SYS_COUNT_RX_RED_PRIO_5, 725 }, 726 [OCELOT_STAT_RX_RED_PRIO_6] = { 727 .name = "rx_red_prio_6", 728 .reg = SYS_COUNT_RX_RED_PRIO_6, 729 }, 730 [OCELOT_STAT_RX_RED_PRIO_7] = { 731 .name = "rx_red_prio_7", 732 .reg = SYS_COUNT_RX_RED_PRIO_7, 733 }, 734 [OCELOT_STAT_RX_YELLOW_PRIO_0] = { 735 .name = "rx_yellow_prio_0", 736 .reg = SYS_COUNT_RX_YELLOW_PRIO_0, 737 }, 738 [OCELOT_STAT_RX_YELLOW_PRIO_1] = { 739 .name = "rx_yellow_prio_1", 740 .reg = SYS_COUNT_RX_YELLOW_PRIO_1, 741 }, 742 [OCELOT_STAT_RX_YELLOW_PRIO_2] = { 743 .name = "rx_yellow_prio_2", 744 .reg = SYS_COUNT_RX_YELLOW_PRIO_2, 745 }, 746 [OCELOT_STAT_RX_YELLOW_PRIO_3] = { 747 .name = "rx_yellow_prio_3", 748 .reg = SYS_COUNT_RX_YELLOW_PRIO_3, 749 }, 750 [OCELOT_STAT_RX_YELLOW_PRIO_4] = { 751 .name = "rx_yellow_prio_4", 752 .reg = SYS_COUNT_RX_YELLOW_PRIO_4, 753 }, 754 [OCELOT_STAT_RX_YELLOW_PRIO_5] = { 755 .name = "rx_yellow_prio_5", 756 .reg = SYS_COUNT_RX_YELLOW_PRIO_5, 757 }, 758 [OCELOT_STAT_RX_YELLOW_PRIO_6] = { 759 .name = "rx_yellow_prio_6", 760 .reg = SYS_COUNT_RX_YELLOW_PRIO_6, 761 }, 762 [OCELOT_STAT_RX_YELLOW_PRIO_7] = { 763 .name = "rx_yellow_prio_7", 764 .reg = SYS_COUNT_RX_YELLOW_PRIO_7, 765 }, 766 [OCELOT_STAT_RX_GREEN_PRIO_0] = { 767 .name = "rx_green_prio_0", 768 .reg = SYS_COUNT_RX_GREEN_PRIO_0, 769 }, 770 [OCELOT_STAT_RX_GREEN_PRIO_1] = { 771 .name = "rx_green_prio_1", 772 .reg = SYS_COUNT_RX_GREEN_PRIO_1, 773 }, 774 [OCELOT_STAT_RX_GREEN_PRIO_2] = { 775 .name = "rx_green_prio_2", 776 .reg = SYS_COUNT_RX_GREEN_PRIO_2, 777 }, 778 [OCELOT_STAT_RX_GREEN_PRIO_3] = { 779 .name = "rx_green_prio_3", 780 .reg = SYS_COUNT_RX_GREEN_PRIO_3, 781 }, 782 [OCELOT_STAT_RX_GREEN_PRIO_4] = { 783 .name = "rx_green_prio_4", 784 .reg = SYS_COUNT_RX_GREEN_PRIO_4, 785 }, 786 [OCELOT_STAT_RX_GREEN_PRIO_5] = { 787 .name = "rx_green_prio_5", 788 .reg = SYS_COUNT_RX_GREEN_PRIO_5, 789 }, 790 [OCELOT_STAT_RX_GREEN_PRIO_6] = { 791 .name = "rx_green_prio_6", 792 .reg = SYS_COUNT_RX_GREEN_PRIO_6, 793 }, 794 [OCELOT_STAT_RX_GREEN_PRIO_7] = { 795 .name = "rx_green_prio_7", 796 .reg = SYS_COUNT_RX_GREEN_PRIO_7, 797 }, 798 [OCELOT_STAT_TX_OCTETS] = { 799 .name = "tx_octets", 800 .reg = SYS_COUNT_TX_OCTETS, 801 }, 802 [OCELOT_STAT_TX_UNICAST] = { 803 .name = "tx_unicast", 804 .reg = SYS_COUNT_TX_UNICAST, 805 }, 806 [OCELOT_STAT_TX_MULTICAST] = { 807 .name = "tx_multicast", 808 .reg = SYS_COUNT_TX_MULTICAST, 809 }, 810 [OCELOT_STAT_TX_BROADCAST] = { 811 .name = "tx_broadcast", 812 .reg = SYS_COUNT_TX_BROADCAST, 813 }, 814 [OCELOT_STAT_TX_COLLISION] = { 815 .name = "tx_collision", 816 .reg = SYS_COUNT_TX_COLLISION, 817 }, 818 [OCELOT_STAT_TX_DROPS] = { 819 .name = "tx_drops", 820 .reg = SYS_COUNT_TX_DROPS, 821 }, 822 [OCELOT_STAT_TX_PAUSE] = { 823 .name = "tx_pause", 824 .reg = SYS_COUNT_TX_PAUSE, 825 }, 826 [OCELOT_STAT_TX_64] = { 827 .name = "tx_frames_below_65_octets", 828 .reg = SYS_COUNT_TX_64, 829 }, 830 [OCELOT_STAT_TX_65_127] = { 831 .name = "tx_frames_65_to_127_octets", 832 .reg = SYS_COUNT_TX_65_127, 833 }, 834 [OCELOT_STAT_TX_128_255] = { 835 .name = "tx_frames_128_255_octets", 836 .reg = SYS_COUNT_TX_128_255, 837 }, 838 [OCELOT_STAT_TX_256_511] = { 839 .name = "tx_frames_256_511_octets", 840 .reg = SYS_COUNT_TX_256_511, 841 }, 842 [OCELOT_STAT_TX_512_1023] = { 843 .name = "tx_frames_512_1023_octets", 844 .reg = SYS_COUNT_TX_512_1023, 845 }, 846 [OCELOT_STAT_TX_1024_1526] = { 847 .name = "tx_frames_1024_1526_octets", 848 .reg = SYS_COUNT_TX_1024_1526, 849 }, 850 [OCELOT_STAT_TX_1527_MAX] = { 851 .name = "tx_frames_over_1526_octets", 852 .reg = SYS_COUNT_TX_1527_MAX, 853 }, 854 [OCELOT_STAT_TX_YELLOW_PRIO_0] = { 855 .name = "tx_yellow_prio_0", 856 .reg = SYS_COUNT_TX_YELLOW_PRIO_0, 857 }, 858 [OCELOT_STAT_TX_YELLOW_PRIO_1] = { 859 .name = "tx_yellow_prio_1", 860 .reg = SYS_COUNT_TX_YELLOW_PRIO_1, 861 }, 862 [OCELOT_STAT_TX_YELLOW_PRIO_2] = { 863 .name = "tx_yellow_prio_2", 864 .reg = SYS_COUNT_TX_YELLOW_PRIO_2, 865 }, 866 [OCELOT_STAT_TX_YELLOW_PRIO_3] = { 867 .name = "tx_yellow_prio_3", 868 .reg = SYS_COUNT_TX_YELLOW_PRIO_3, 869 }, 870 [OCELOT_STAT_TX_YELLOW_PRIO_4] = { 871 .name = "tx_yellow_prio_4", 872 .reg = SYS_COUNT_TX_YELLOW_PRIO_4, 873 }, 874 [OCELOT_STAT_TX_YELLOW_PRIO_5] = { 875 .name = "tx_yellow_prio_5", 876 .reg = SYS_COUNT_TX_YELLOW_PRIO_5, 877 }, 878 [OCELOT_STAT_TX_YELLOW_PRIO_6] = { 879 .name = "tx_yellow_prio_6", 880 .reg = SYS_COUNT_TX_YELLOW_PRIO_6, 881 }, 882 [OCELOT_STAT_TX_YELLOW_PRIO_7] = { 883 .name = "tx_yellow_prio_7", 884 .reg = SYS_COUNT_TX_YELLOW_PRIO_7, 885 }, 886 [OCELOT_STAT_TX_GREEN_PRIO_0] = { 887 .name = "tx_green_prio_0", 888 .reg = SYS_COUNT_TX_GREEN_PRIO_0, 889 }, 890 [OCELOT_STAT_TX_GREEN_PRIO_1] = { 891 .name = "tx_green_prio_1", 892 .reg = SYS_COUNT_TX_GREEN_PRIO_1, 893 }, 894 [OCELOT_STAT_TX_GREEN_PRIO_2] = { 895 .name = "tx_green_prio_2", 896 .reg = SYS_COUNT_TX_GREEN_PRIO_2, 897 }, 898 [OCELOT_STAT_TX_GREEN_PRIO_3] = { 899 .name = "tx_green_prio_3", 900 .reg = SYS_COUNT_TX_GREEN_PRIO_3, 901 }, 902 [OCELOT_STAT_TX_GREEN_PRIO_4] = { 903 .name = "tx_green_prio_4", 904 .reg = SYS_COUNT_TX_GREEN_PRIO_4, 905 }, 906 [OCELOT_STAT_TX_GREEN_PRIO_5] = { 907 .name = "tx_green_prio_5", 908 .reg = SYS_COUNT_TX_GREEN_PRIO_5, 909 }, 910 [OCELOT_STAT_TX_GREEN_PRIO_6] = { 911 .name = "tx_green_prio_6", 912 .reg = SYS_COUNT_TX_GREEN_PRIO_6, 913 }, 914 [OCELOT_STAT_TX_GREEN_PRIO_7] = { 915 .name = "tx_green_prio_7", 916 .reg = SYS_COUNT_TX_GREEN_PRIO_7, 917 }, 918 [OCELOT_STAT_TX_AGED] = { 919 .name = "tx_aged", 920 .reg = SYS_COUNT_TX_AGING, 921 }, 922 [OCELOT_STAT_DROP_LOCAL] = { 923 .name = "drop_local", 924 .reg = SYS_COUNT_DROP_LOCAL, 925 }, 926 [OCELOT_STAT_DROP_TAIL] = { 927 .name = "drop_tail", 928 .reg = SYS_COUNT_DROP_TAIL, 929 }, 930 [OCELOT_STAT_DROP_YELLOW_PRIO_0] = { 931 .name = "drop_yellow_prio_0", 932 .reg = SYS_COUNT_DROP_YELLOW_PRIO_0, 933 }, 934 [OCELOT_STAT_DROP_YELLOW_PRIO_1] = { 935 .name = "drop_yellow_prio_1", 936 .reg = SYS_COUNT_DROP_YELLOW_PRIO_1, 937 }, 938 [OCELOT_STAT_DROP_YELLOW_PRIO_2] = { 939 .name = "drop_yellow_prio_2", 940 .reg = SYS_COUNT_DROP_YELLOW_PRIO_2, 941 }, 942 [OCELOT_STAT_DROP_YELLOW_PRIO_3] = { 943 .name = "drop_yellow_prio_3", 944 .reg = SYS_COUNT_DROP_YELLOW_PRIO_3, 945 }, 946 [OCELOT_STAT_DROP_YELLOW_PRIO_4] = { 947 .name = "drop_yellow_prio_4", 948 .reg = SYS_COUNT_DROP_YELLOW_PRIO_4, 949 }, 950 [OCELOT_STAT_DROP_YELLOW_PRIO_5] = { 951 .name = "drop_yellow_prio_5", 952 .reg = SYS_COUNT_DROP_YELLOW_PRIO_5, 953 }, 954 [OCELOT_STAT_DROP_YELLOW_PRIO_6] = { 955 .name = "drop_yellow_prio_6", 956 .reg = SYS_COUNT_DROP_YELLOW_PRIO_6, 957 }, 958 [OCELOT_STAT_DROP_YELLOW_PRIO_7] = { 959 .name = "drop_yellow_prio_7", 960 .reg = SYS_COUNT_DROP_YELLOW_PRIO_7, 961 }, 962 [OCELOT_STAT_DROP_GREEN_PRIO_0] = { 963 .name = "drop_green_prio_0", 964 .reg = SYS_COUNT_DROP_GREEN_PRIO_0, 965 }, 966 [OCELOT_STAT_DROP_GREEN_PRIO_1] = { 967 .name = "drop_green_prio_1", 968 .reg = SYS_COUNT_DROP_GREEN_PRIO_1, 969 }, 970 [OCELOT_STAT_DROP_GREEN_PRIO_2] = { 971 .name = "drop_green_prio_2", 972 .reg = SYS_COUNT_DROP_GREEN_PRIO_2, 973 }, 974 [OCELOT_STAT_DROP_GREEN_PRIO_3] = { 975 .name = "drop_green_prio_3", 976 .reg = SYS_COUNT_DROP_GREEN_PRIO_3, 977 }, 978 [OCELOT_STAT_DROP_GREEN_PRIO_4] = { 979 .name = "drop_green_prio_4", 980 .reg = SYS_COUNT_DROP_GREEN_PRIO_4, 981 }, 982 [OCELOT_STAT_DROP_GREEN_PRIO_5] = { 983 .name = "drop_green_prio_5", 984 .reg = SYS_COUNT_DROP_GREEN_PRIO_5, 985 }, 986 [OCELOT_STAT_DROP_GREEN_PRIO_6] = { 987 .name = "drop_green_prio_6", 988 .reg = SYS_COUNT_DROP_GREEN_PRIO_6, 989 }, 990 [OCELOT_STAT_DROP_GREEN_PRIO_7] = { 991 .name = "drop_green_prio_7", 992 .reg = SYS_COUNT_DROP_GREEN_PRIO_7, 993 }, 994 }; 995 996 static const struct vcap_field vsc9959_vcap_es0_keys[] = { 997 [VCAP_ES0_EGR_PORT] = { 0, 3}, 998 [VCAP_ES0_IGR_PORT] = { 3, 3}, 999 [VCAP_ES0_RSV] = { 6, 2}, 1000 [VCAP_ES0_L2_MC] = { 8, 1}, 1001 [VCAP_ES0_L2_BC] = { 9, 1}, 1002 [VCAP_ES0_VID] = { 10, 12}, 1003 [VCAP_ES0_DP] = { 22, 1}, 1004 [VCAP_ES0_PCP] = { 23, 3}, 1005 }; 1006 1007 static const struct vcap_field vsc9959_vcap_es0_actions[] = { 1008 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 1009 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 1010 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 1011 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 1012 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 1013 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 1014 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 1015 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 1016 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 1017 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 1018 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 1019 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 1020 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 1021 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 1022 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 1023 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 1024 [VCAP_ES0_ACT_RSV] = { 49, 23}, 1025 [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 1026 }; 1027 1028 static const struct vcap_field vsc9959_vcap_is1_keys[] = { 1029 [VCAP_IS1_HK_TYPE] = { 0, 1}, 1030 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 1031 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 1032 [VCAP_IS1_HK_RSV] = { 10, 9}, 1033 [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 1034 [VCAP_IS1_HK_L2_MC] = { 20, 1}, 1035 [VCAP_IS1_HK_L2_BC] = { 21, 1}, 1036 [VCAP_IS1_HK_IP_MC] = { 22, 1}, 1037 [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 1038 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 1039 [VCAP_IS1_HK_TPID] = { 25, 1}, 1040 [VCAP_IS1_HK_VID] = { 26, 12}, 1041 [VCAP_IS1_HK_DEI] = { 38, 1}, 1042 [VCAP_IS1_HK_PCP] = { 39, 3}, 1043 /* Specific Fields for IS1 Half Key S1_NORMAL */ 1044 [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 1045 [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 1046 [VCAP_IS1_HK_ETYPE] = { 91, 16}, 1047 [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 1048 [VCAP_IS1_HK_IP4] = {108, 1}, 1049 /* Layer-3 Information */ 1050 [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 1051 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 1052 [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 1053 [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 1054 [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 1055 /* Layer-4 Information */ 1056 [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 1057 [VCAP_IS1_HK_TCP] = {151, 1}, 1058 [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 1059 [VCAP_IS1_HK_L4_RNG] = {168, 8}, 1060 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 1061 [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 1062 [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 1063 [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 1064 [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 1065 [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 1066 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 1067 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 1068 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 1069 [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 1070 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 1071 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 1072 [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 1073 [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 1074 [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 1075 [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 1076 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 1077 }; 1078 1079 static const struct vcap_field vsc9959_vcap_is1_actions[] = { 1080 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 1081 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 1082 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 1083 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 1084 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 1085 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 1086 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 1087 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 1088 [VCAP_IS1_ACT_RSV] = { 29, 9}, 1089 /* The fields below are incorrectly shifted by 2 in the manual */ 1090 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 1091 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 1092 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 1093 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 1094 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 1095 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 1096 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 1097 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 1098 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 1099 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 1100 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 1101 }; 1102 1103 static struct vcap_field vsc9959_vcap_is2_keys[] = { 1104 /* Common: 41 bits */ 1105 [VCAP_IS2_TYPE] = { 0, 4}, 1106 [VCAP_IS2_HK_FIRST] = { 4, 1}, 1107 [VCAP_IS2_HK_PAG] = { 5, 8}, 1108 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 1109 [VCAP_IS2_HK_RSV2] = { 20, 1}, 1110 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 1111 [VCAP_IS2_HK_L2_MC] = { 22, 1}, 1112 [VCAP_IS2_HK_L2_BC] = { 23, 1}, 1113 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 1114 [VCAP_IS2_HK_VID] = { 25, 12}, 1115 [VCAP_IS2_HK_DEI] = { 37, 1}, 1116 [VCAP_IS2_HK_PCP] = { 38, 3}, 1117 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 1118 [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 1119 [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 1120 /* MAC_ETYPE (TYPE=000) */ 1121 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 1122 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 1123 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 1124 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 1125 /* MAC_LLC (TYPE=001) */ 1126 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 1127 /* MAC_SNAP (TYPE=010) */ 1128 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 1129 /* MAC_ARP (TYPE=011) */ 1130 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 1131 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 1132 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 1133 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 1134 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 1135 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 1136 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 1137 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 1138 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 1139 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 1140 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 1141 /* IP4_TCP_UDP / IP4_OTHER common */ 1142 [VCAP_IS2_HK_IP4] = { 41, 1}, 1143 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 1144 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 1145 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 1146 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 1147 [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 1148 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 1149 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 1150 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 1151 /* IP4_TCP_UDP (TYPE=100) */ 1152 [VCAP_IS2_HK_TCP] = {119, 1}, 1153 [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 1154 [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 1155 [VCAP_IS2_HK_L4_RNG] = {152, 8}, 1156 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 1157 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 1158 [VCAP_IS2_HK_L4_FIN] = {162, 1}, 1159 [VCAP_IS2_HK_L4_SYN] = {163, 1}, 1160 [VCAP_IS2_HK_L4_RST] = {164, 1}, 1161 [VCAP_IS2_HK_L4_PSH] = {165, 1}, 1162 [VCAP_IS2_HK_L4_ACK] = {166, 1}, 1163 [VCAP_IS2_HK_L4_URG] = {167, 1}, 1164 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 1165 [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 1166 /* IP4_OTHER (TYPE=101) */ 1167 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 1168 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 1169 /* IP6_STD (TYPE=110) */ 1170 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 1171 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 1172 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 1173 /* OAM (TYPE=111) */ 1174 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 1175 [VCAP_IS2_HK_OAM_VER] = {144, 5}, 1176 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 1177 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 1178 [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 1179 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 1180 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 1181 }; 1182 1183 static struct vcap_field vsc9959_vcap_is2_actions[] = { 1184 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 1185 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 1186 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 1187 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 1188 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 1189 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 1190 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 1191 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 1192 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 1193 [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 1194 [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 1195 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 1196 [VCAP_IS2_ACT_RSV] = { 36, 2}, 1197 [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 1198 [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 1199 }; 1200 1201 static struct vcap_props vsc9959_vcap_props[] = { 1202 [VCAP_ES0] = { 1203 .action_type_width = 0, 1204 .action_table = { 1205 [ES0_ACTION_TYPE_NORMAL] = { 1206 .width = 72, /* HIT_STICKY not included */ 1207 .count = 1, 1208 }, 1209 }, 1210 .target = S0, 1211 .keys = vsc9959_vcap_es0_keys, 1212 .actions = vsc9959_vcap_es0_actions, 1213 }, 1214 [VCAP_IS1] = { 1215 .action_type_width = 0, 1216 .action_table = { 1217 [IS1_ACTION_TYPE_NORMAL] = { 1218 .width = 78, /* HIT_STICKY not included */ 1219 .count = 4, 1220 }, 1221 }, 1222 .target = S1, 1223 .keys = vsc9959_vcap_is1_keys, 1224 .actions = vsc9959_vcap_is1_actions, 1225 }, 1226 [VCAP_IS2] = { 1227 .action_type_width = 1, 1228 .action_table = { 1229 [IS2_ACTION_TYPE_NORMAL] = { 1230 .width = 44, 1231 .count = 2 1232 }, 1233 [IS2_ACTION_TYPE_SMAC_SIP] = { 1234 .width = 6, 1235 .count = 4 1236 }, 1237 }, 1238 .target = S2, 1239 .keys = vsc9959_vcap_is2_keys, 1240 .actions = vsc9959_vcap_is2_actions, 1241 }, 1242 }; 1243 1244 static const struct ptp_clock_info vsc9959_ptp_caps = { 1245 .owner = THIS_MODULE, 1246 .name = "felix ptp", 1247 .max_adj = 0x7fffffff, 1248 .n_alarm = 0, 1249 .n_ext_ts = 0, 1250 .n_per_out = OCELOT_PTP_PINS_NUM, 1251 .n_pins = OCELOT_PTP_PINS_NUM, 1252 .pps = 0, 1253 .gettime64 = ocelot_ptp_gettime64, 1254 .settime64 = ocelot_ptp_settime64, 1255 .adjtime = ocelot_ptp_adjtime, 1256 .adjfine = ocelot_ptp_adjfine, 1257 .verify = ocelot_ptp_verify, 1258 .enable = ocelot_ptp_enable, 1259 }; 1260 1261 #define VSC9959_INIT_TIMEOUT 50000 1262 #define VSC9959_GCB_RST_SLEEP 100 1263 #define VSC9959_SYS_RAMINIT_SLEEP 80 1264 1265 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 1266 { 1267 int val; 1268 1269 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 1270 1271 return val; 1272 } 1273 1274 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 1275 { 1276 return ocelot_read(ocelot, SYS_RAM_INIT); 1277 } 1278 1279 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 1280 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 1281 */ 1282 static int vsc9959_reset(struct ocelot *ocelot) 1283 { 1284 int val, err; 1285 1286 /* soft-reset the switch core */ 1287 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 1288 1289 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 1290 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 1291 if (err) { 1292 dev_err(ocelot->dev, "timeout: switch core reset\n"); 1293 return err; 1294 } 1295 1296 /* initialize switch mem ~40us */ 1297 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 1298 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 1299 VSC9959_SYS_RAMINIT_SLEEP, 1300 VSC9959_INIT_TIMEOUT); 1301 if (err) { 1302 dev_err(ocelot->dev, "timeout: switch sram init\n"); 1303 return err; 1304 } 1305 1306 /* enable switch core */ 1307 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 1308 1309 return 0; 1310 } 1311 1312 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port, 1313 unsigned long *supported, 1314 struct phylink_link_state *state) 1315 { 1316 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1317 1318 phylink_set_port_modes(mask); 1319 phylink_set(mask, Autoneg); 1320 phylink_set(mask, Pause); 1321 phylink_set(mask, Asym_Pause); 1322 phylink_set(mask, 10baseT_Half); 1323 phylink_set(mask, 10baseT_Full); 1324 phylink_set(mask, 100baseT_Half); 1325 phylink_set(mask, 100baseT_Full); 1326 phylink_set(mask, 1000baseT_Half); 1327 phylink_set(mask, 1000baseT_Full); 1328 phylink_set(mask, 1000baseX_Full); 1329 1330 if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 1331 state->interface == PHY_INTERFACE_MODE_2500BASEX || 1332 state->interface == PHY_INTERFACE_MODE_USXGMII) { 1333 phylink_set(mask, 2500baseT_Full); 1334 phylink_set(mask, 2500baseX_Full); 1335 } 1336 1337 linkmode_and(supported, supported, mask); 1338 linkmode_and(state->advertising, state->advertising, mask); 1339 } 1340 1341 /* Watermark encode 1342 * Bit 8: Unit; 0:1, 1:16 1343 * Bit 7-0: Value to be multiplied with unit 1344 */ 1345 static u16 vsc9959_wm_enc(u16 value) 1346 { 1347 WARN_ON(value >= 16 * BIT(8)); 1348 1349 if (value >= BIT(8)) 1350 return BIT(8) | (value / 16); 1351 1352 return value; 1353 } 1354 1355 static u16 vsc9959_wm_dec(u16 wm) 1356 { 1357 WARN_ON(wm & ~GENMASK(8, 0)); 1358 1359 if (wm & BIT(8)) 1360 return (wm & GENMASK(7, 0)) * 16; 1361 1362 return wm; 1363 } 1364 1365 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 1366 { 1367 *inuse = (val & GENMASK(23, 12)) >> 12; 1368 *maxuse = val & GENMASK(11, 0); 1369 } 1370 1371 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 1372 { 1373 struct felix *felix = ocelot_to_felix(ocelot); 1374 struct enetc_mdio_priv *mdio_priv; 1375 struct device *dev = ocelot->dev; 1376 void __iomem *imdio_regs; 1377 struct resource res; 1378 struct enetc_hw *hw; 1379 struct mii_bus *bus; 1380 int port; 1381 int rc; 1382 1383 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 1384 sizeof(struct phylink_pcs *), 1385 GFP_KERNEL); 1386 if (!felix->pcs) { 1387 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 1388 return -ENOMEM; 1389 } 1390 1391 memcpy(&res, felix->info->imdio_res, sizeof(res)); 1392 res.flags = IORESOURCE_MEM; 1393 res.start += felix->imdio_base; 1394 res.end += felix->imdio_base; 1395 1396 imdio_regs = devm_ioremap_resource(dev, &res); 1397 if (IS_ERR(imdio_regs)) 1398 return PTR_ERR(imdio_regs); 1399 1400 hw = enetc_hw_alloc(dev, imdio_regs); 1401 if (IS_ERR(hw)) { 1402 dev_err(dev, "failed to allocate ENETC HW structure\n"); 1403 return PTR_ERR(hw); 1404 } 1405 1406 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 1407 if (!bus) 1408 return -ENOMEM; 1409 1410 bus->name = "VSC9959 internal MDIO bus"; 1411 bus->read = enetc_mdio_read; 1412 bus->write = enetc_mdio_write; 1413 bus->parent = dev; 1414 mdio_priv = bus->priv; 1415 mdio_priv->hw = hw; 1416 /* This gets added to imdio_regs, which already maps addresses 1417 * starting with the proper offset. 1418 */ 1419 mdio_priv->mdio_base = 0; 1420 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1421 1422 /* Needed in order to initialize the bus mutex lock */ 1423 rc = mdiobus_register(bus); 1424 if (rc < 0) { 1425 dev_err(dev, "failed to register MDIO bus\n"); 1426 mdiobus_free(bus); 1427 return rc; 1428 } 1429 1430 felix->imdio = bus; 1431 1432 for (port = 0; port < felix->info->num_ports; port++) { 1433 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1434 struct phylink_pcs *phylink_pcs; 1435 struct mdio_device *mdio_device; 1436 1437 if (dsa_is_unused_port(felix->ds, port)) 1438 continue; 1439 1440 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1441 continue; 1442 1443 mdio_device = mdio_device_create(felix->imdio, port); 1444 if (IS_ERR(mdio_device)) 1445 continue; 1446 1447 phylink_pcs = lynx_pcs_create(mdio_device); 1448 if (!phylink_pcs) { 1449 mdio_device_free(mdio_device); 1450 continue; 1451 } 1452 1453 felix->pcs[port] = phylink_pcs; 1454 1455 dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1456 } 1457 1458 return 0; 1459 } 1460 1461 static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1462 { 1463 struct felix *felix = ocelot_to_felix(ocelot); 1464 int port; 1465 1466 for (port = 0; port < ocelot->num_phys_ports; port++) { 1467 struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1468 struct mdio_device *mdio_device; 1469 1470 if (!phylink_pcs) 1471 continue; 1472 1473 mdio_device = lynx_get_mdio_device(phylink_pcs); 1474 mdio_device_free(mdio_device); 1475 lynx_pcs_destroy(phylink_pcs); 1476 } 1477 mdiobus_unregister(felix->imdio); 1478 mdiobus_free(felix->imdio); 1479 } 1480 1481 /* Extract shortest continuous gate open intervals in ns for each traffic class 1482 * of a cyclic tc-taprio schedule. If a gate is always open, the duration is 1483 * considered U64_MAX. If the gate is always closed, it is considered 0. 1484 */ 1485 static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio, 1486 u64 min_gate_len[OCELOT_NUM_TC]) 1487 { 1488 struct tc_taprio_sched_entry *entry; 1489 u64 gate_len[OCELOT_NUM_TC]; 1490 u8 gates_ever_opened = 0; 1491 int tc, i, n; 1492 1493 /* Initialize arrays */ 1494 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1495 min_gate_len[tc] = U64_MAX; 1496 gate_len[tc] = 0; 1497 } 1498 1499 /* If we don't have taprio, consider all gates as permanently open */ 1500 if (!taprio) 1501 return; 1502 1503 n = taprio->num_entries; 1504 1505 /* Walk through the gate list twice to determine the length 1506 * of consecutively open gates for a traffic class, including 1507 * open gates that wrap around. We are just interested in the 1508 * minimum window size, and this doesn't change what the 1509 * minimum is (if the gate never closes, min_gate_len will 1510 * remain U64_MAX). 1511 */ 1512 for (i = 0; i < 2 * n; i++) { 1513 entry = &taprio->entries[i % n]; 1514 1515 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1516 if (entry->gate_mask & BIT(tc)) { 1517 gate_len[tc] += entry->interval; 1518 gates_ever_opened |= BIT(tc); 1519 } else { 1520 /* Gate closes now, record a potential new 1521 * minimum and reinitialize length 1522 */ 1523 if (min_gate_len[tc] > gate_len[tc] && 1524 gate_len[tc]) 1525 min_gate_len[tc] = gate_len[tc]; 1526 gate_len[tc] = 0; 1527 } 1528 } 1529 } 1530 1531 /* min_gate_len[tc] actually tracks minimum *open* gate time, so for 1532 * permanently closed gates, min_gate_len[tc] will still be U64_MAX. 1533 * Therefore they are currently indistinguishable from permanently 1534 * open gates. Overwrite the gate len with 0 when we know they're 1535 * actually permanently closed, i.e. after the loop above. 1536 */ 1537 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 1538 if (!(gates_ever_opened & BIT(tc))) 1539 min_gate_len[tc] = 0; 1540 } 1541 1542 /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the 1543 * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU 1544 * values (the default value is 1518). Also, for traffic class windows smaller 1545 * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame 1546 * dropping, such that these won't hang the port, as they will never be sent. 1547 */ 1548 static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port) 1549 { 1550 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1551 u64 min_gate_len[OCELOT_NUM_TC]; 1552 int speed, picos_per_byte; 1553 u64 needed_bit_time_ps; 1554 u32 val, maxlen; 1555 u8 tas_speed; 1556 int tc; 1557 1558 lockdep_assert_held(&ocelot->tas_lock); 1559 1560 val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port); 1561 tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val); 1562 1563 switch (tas_speed) { 1564 case OCELOT_SPEED_10: 1565 speed = SPEED_10; 1566 break; 1567 case OCELOT_SPEED_100: 1568 speed = SPEED_100; 1569 break; 1570 case OCELOT_SPEED_1000: 1571 speed = SPEED_1000; 1572 break; 1573 case OCELOT_SPEED_2500: 1574 speed = SPEED_2500; 1575 break; 1576 default: 1577 return; 1578 } 1579 1580 picos_per_byte = (USEC_PER_SEC * 8) / speed; 1581 1582 val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG); 1583 /* MAXLEN_CFG accounts automatically for VLAN. We need to include it 1584 * manually in the bit time calculation, plus the preamble and SFD. 1585 */ 1586 maxlen = val + 2 * VLAN_HLEN; 1587 /* Consider the standard Ethernet overhead of 8 octets preamble+SFD, 1588 * 4 octets FCS, 12 octets IFG. 1589 */ 1590 needed_bit_time_ps = (maxlen + 24) * picos_per_byte; 1591 1592 dev_dbg(ocelot->dev, 1593 "port %d: max frame size %d needs %llu ps at speed %d\n", 1594 port, maxlen, needed_bit_time_ps, speed); 1595 1596 vsc9959_tas_min_gate_lengths(ocelot_port->taprio, min_gate_len); 1597 1598 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1599 u32 max_sdu; 1600 1601 if (min_gate_len[tc] == U64_MAX /* Gate always open */ || 1602 min_gate_len[tc] * PSEC_PER_NSEC > needed_bit_time_ps) { 1603 /* Setting QMAXSDU_CFG to 0 disables oversized frame 1604 * dropping. 1605 */ 1606 max_sdu = 0; 1607 dev_dbg(ocelot->dev, 1608 "port %d tc %d min gate len %llu" 1609 ", sending all frames\n", 1610 port, tc, min_gate_len[tc]); 1611 } else { 1612 /* If traffic class doesn't support a full MTU sized 1613 * frame, make sure to enable oversize frame dropping 1614 * for frames larger than the smallest that would fit. 1615 */ 1616 max_sdu = div_u64(min_gate_len[tc] * PSEC_PER_NSEC, 1617 picos_per_byte); 1618 /* A TC gate may be completely closed, which is a 1619 * special case where all packets are oversized. 1620 * Any limit smaller than 64 octets accomplishes this 1621 */ 1622 if (!max_sdu) 1623 max_sdu = 1; 1624 /* Take L1 overhead into account, but just don't allow 1625 * max_sdu to go negative or to 0. Here we use 20 1626 * because QSYS_MAXSDU_CFG_* already counts the 4 FCS 1627 * octets as part of packet size. 1628 */ 1629 if (max_sdu > 20) 1630 max_sdu -= 20; 1631 dev_info(ocelot->dev, 1632 "port %d tc %d min gate length %llu" 1633 " ns not enough for max frame size %d at %d" 1634 " Mbps, dropping frames over %d" 1635 " octets including FCS\n", 1636 port, tc, min_gate_len[tc], maxlen, speed, 1637 max_sdu); 1638 } 1639 1640 /* ocelot_write_rix is a macro that concatenates 1641 * QSYS_MAXSDU_CFG_* with _RSZ, so we need to spell out 1642 * the writes to each traffic class 1643 */ 1644 switch (tc) { 1645 case 0: 1646 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0, 1647 port); 1648 break; 1649 case 1: 1650 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1, 1651 port); 1652 break; 1653 case 2: 1654 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2, 1655 port); 1656 break; 1657 case 3: 1658 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3, 1659 port); 1660 break; 1661 case 4: 1662 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4, 1663 port); 1664 break; 1665 case 5: 1666 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5, 1667 port); 1668 break; 1669 case 6: 1670 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6, 1671 port); 1672 break; 1673 case 7: 1674 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7, 1675 port); 1676 break; 1677 } 1678 } 1679 1680 ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port); 1681 } 1682 1683 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1684 u32 speed) 1685 { 1686 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1687 u8 tas_speed; 1688 1689 switch (speed) { 1690 case SPEED_10: 1691 tas_speed = OCELOT_SPEED_10; 1692 break; 1693 case SPEED_100: 1694 tas_speed = OCELOT_SPEED_100; 1695 break; 1696 case SPEED_1000: 1697 tas_speed = OCELOT_SPEED_1000; 1698 break; 1699 case SPEED_2500: 1700 tas_speed = OCELOT_SPEED_2500; 1701 break; 1702 default: 1703 tas_speed = OCELOT_SPEED_1000; 1704 break; 1705 } 1706 1707 ocelot_rmw_rix(ocelot, 1708 QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1709 QSYS_TAG_CONFIG_LINK_SPEED_M, 1710 QSYS_TAG_CONFIG, port); 1711 1712 mutex_lock(&ocelot->tas_lock); 1713 1714 if (ocelot_port->taprio) 1715 vsc9959_tas_guard_bands_update(ocelot, port); 1716 1717 mutex_unlock(&ocelot->tas_lock); 1718 } 1719 1720 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1721 u64 cycle_time, 1722 struct timespec64 *new_base_ts) 1723 { 1724 struct timespec64 ts; 1725 ktime_t new_base_time; 1726 ktime_t current_time; 1727 1728 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1729 current_time = timespec64_to_ktime(ts); 1730 new_base_time = base_time; 1731 1732 if (base_time < current_time) { 1733 u64 nr_of_cycles = current_time - base_time; 1734 1735 do_div(nr_of_cycles, cycle_time); 1736 new_base_time += cycle_time * (nr_of_cycles + 1); 1737 } 1738 1739 *new_base_ts = ktime_to_timespec64(new_base_time); 1740 } 1741 1742 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1743 { 1744 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1745 } 1746 1747 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1748 struct tc_taprio_sched_entry *entry) 1749 { 1750 ocelot_write(ocelot, 1751 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1752 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1753 QSYS_GCL_CFG_REG_1); 1754 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1755 } 1756 1757 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1758 struct tc_taprio_qopt_offload *taprio) 1759 { 1760 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1761 struct timespec64 base_ts; 1762 int ret, i; 1763 u32 val; 1764 1765 mutex_lock(&ocelot->tas_lock); 1766 1767 if (!taprio->enable) { 1768 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1769 QSYS_TAG_CONFIG, port); 1770 1771 taprio_offload_free(ocelot_port->taprio); 1772 ocelot_port->taprio = NULL; 1773 1774 vsc9959_tas_guard_bands_update(ocelot, port); 1775 1776 mutex_unlock(&ocelot->tas_lock); 1777 return 0; 1778 } 1779 1780 if (taprio->cycle_time > NSEC_PER_SEC || 1781 taprio->cycle_time_extension >= NSEC_PER_SEC) { 1782 ret = -EINVAL; 1783 goto err; 1784 } 1785 1786 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) { 1787 ret = -ERANGE; 1788 goto err; 1789 } 1790 1791 /* Enable guard band. The switch will schedule frames without taking 1792 * their length into account. Thus we'll always need to enable the 1793 * guard band which reserves the time of a maximum sized frame at the 1794 * end of the time window. 1795 * 1796 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1797 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1798 * operate on the port number. 1799 */ 1800 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1801 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1802 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1803 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1804 QSYS_TAS_PARAM_CFG_CTRL); 1805 1806 /* Hardware errata - Admin config could not be overwritten if 1807 * config is pending, need reset the TAS module 1808 */ 1809 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1810 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) { 1811 ret = -EBUSY; 1812 goto err; 1813 } 1814 1815 ocelot_rmw_rix(ocelot, 1816 QSYS_TAG_CONFIG_ENABLE | 1817 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1818 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1819 QSYS_TAG_CONFIG_ENABLE | 1820 QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1821 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1822 QSYS_TAG_CONFIG, port); 1823 1824 vsc9959_new_base_time(ocelot, taprio->base_time, 1825 taprio->cycle_time, &base_ts); 1826 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1827 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1828 val = upper_32_bits(base_ts.tv_sec); 1829 ocelot_write(ocelot, 1830 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1831 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1832 QSYS_PARAM_CFG_REG_3); 1833 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1834 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1835 1836 for (i = 0; i < taprio->num_entries; i++) 1837 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1838 1839 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1840 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1841 QSYS_TAS_PARAM_CFG_CTRL); 1842 1843 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1844 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1845 10, 100000); 1846 if (ret) 1847 goto err; 1848 1849 ocelot_port->taprio = taprio_offload_get(taprio); 1850 vsc9959_tas_guard_bands_update(ocelot, port); 1851 1852 err: 1853 mutex_unlock(&ocelot->tas_lock); 1854 1855 return ret; 1856 } 1857 1858 static void vsc9959_tas_clock_adjust(struct ocelot *ocelot) 1859 { 1860 struct tc_taprio_qopt_offload *taprio; 1861 struct ocelot_port *ocelot_port; 1862 struct timespec64 base_ts; 1863 int port; 1864 u32 val; 1865 1866 mutex_lock(&ocelot->tas_lock); 1867 1868 for (port = 0; port < ocelot->num_phys_ports; port++) { 1869 ocelot_port = ocelot->ports[port]; 1870 taprio = ocelot_port->taprio; 1871 if (!taprio) 1872 continue; 1873 1874 ocelot_rmw(ocelot, 1875 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port), 1876 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M, 1877 QSYS_TAS_PARAM_CFG_CTRL); 1878 1879 /* Disable time-aware shaper */ 1880 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1881 QSYS_TAG_CONFIG, port); 1882 1883 vsc9959_new_base_time(ocelot, taprio->base_time, 1884 taprio->cycle_time, &base_ts); 1885 1886 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1887 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), 1888 QSYS_PARAM_CFG_REG_2); 1889 val = upper_32_bits(base_ts.tv_sec); 1890 ocelot_rmw(ocelot, 1891 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val), 1892 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M, 1893 QSYS_PARAM_CFG_REG_3); 1894 1895 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1896 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1897 QSYS_TAS_PARAM_CFG_CTRL); 1898 1899 /* Re-enable time-aware shaper */ 1900 ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE, 1901 QSYS_TAG_CONFIG_ENABLE, 1902 QSYS_TAG_CONFIG, port); 1903 } 1904 mutex_unlock(&ocelot->tas_lock); 1905 } 1906 1907 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 1908 struct tc_cbs_qopt_offload *cbs_qopt) 1909 { 1910 struct ocelot *ocelot = ds->priv; 1911 int port_ix = port * 8 + cbs_qopt->queue; 1912 u32 rate, burst; 1913 1914 if (cbs_qopt->queue >= ds->num_tx_queues) 1915 return -EINVAL; 1916 1917 if (!cbs_qopt->enable) { 1918 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 1919 QSYS_CIR_CFG_CIR_BURST(0), 1920 QSYS_CIR_CFG, port_ix); 1921 1922 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 1923 QSYS_SE_CFG, port_ix); 1924 1925 return 0; 1926 } 1927 1928 /* Rate unit is 100 kbps */ 1929 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 1930 /* Avoid using zero rate */ 1931 rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 1932 /* Burst unit is 4kB */ 1933 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 1934 /* Avoid using zero burst size */ 1935 burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 1936 ocelot_write_gix(ocelot, 1937 QSYS_CIR_CFG_CIR_RATE(rate) | 1938 QSYS_CIR_CFG_CIR_BURST(burst), 1939 QSYS_CIR_CFG, 1940 port_ix); 1941 1942 ocelot_rmw_gix(ocelot, 1943 QSYS_SE_CFG_SE_FRM_MODE(0) | 1944 QSYS_SE_CFG_SE_AVB_ENA, 1945 QSYS_SE_CFG_SE_AVB_ENA | 1946 QSYS_SE_CFG_SE_FRM_MODE_M, 1947 QSYS_SE_CFG, 1948 port_ix); 1949 1950 return 0; 1951 } 1952 1953 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1954 enum tc_setup_type type, 1955 void *type_data) 1956 { 1957 struct ocelot *ocelot = ds->priv; 1958 1959 switch (type) { 1960 case TC_SETUP_QDISC_TAPRIO: 1961 return vsc9959_qos_port_tas_set(ocelot, port, type_data); 1962 case TC_SETUP_QDISC_CBS: 1963 return vsc9959_qos_port_cbs_set(ds, port, type_data); 1964 default: 1965 return -EOPNOTSUPP; 1966 } 1967 } 1968 1969 #define VSC9959_PSFP_SFID_MAX 175 1970 #define VSC9959_PSFP_GATE_ID_MAX 183 1971 #define VSC9959_PSFP_POLICER_BASE 63 1972 #define VSC9959_PSFP_POLICER_MAX 383 1973 #define VSC9959_PSFP_GATE_LIST_NUM 4 1974 #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 1975 1976 struct felix_stream { 1977 struct list_head list; 1978 unsigned long id; 1979 bool dummy; 1980 int ports; 1981 int port; 1982 u8 dmac[ETH_ALEN]; 1983 u16 vid; 1984 s8 prio; 1985 u8 sfid_valid; 1986 u8 ssid_valid; 1987 u32 sfid; 1988 u32 ssid; 1989 }; 1990 1991 struct felix_stream_filter { 1992 struct list_head list; 1993 refcount_t refcount; 1994 u32 index; 1995 u8 enable; 1996 int portmask; 1997 u8 sg_valid; 1998 u32 sgid; 1999 u8 fm_valid; 2000 u32 fmid; 2001 u8 prio_valid; 2002 u8 prio; 2003 u32 maxsdu; 2004 }; 2005 2006 struct felix_stream_filter_counters { 2007 u32 match; 2008 u32 not_pass_gate; 2009 u32 not_pass_sdu; 2010 u32 red; 2011 }; 2012 2013 struct felix_stream_gate { 2014 u32 index; 2015 u8 enable; 2016 u8 ipv_valid; 2017 u8 init_ipv; 2018 u64 basetime; 2019 u64 cycletime; 2020 u64 cycletime_ext; 2021 u32 num_entries; 2022 struct action_gate_entry entries[]; 2023 }; 2024 2025 struct felix_stream_gate_entry { 2026 struct list_head list; 2027 refcount_t refcount; 2028 u32 index; 2029 }; 2030 2031 static int vsc9959_stream_identify(struct flow_cls_offload *f, 2032 struct felix_stream *stream) 2033 { 2034 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 2035 struct flow_dissector *dissector = rule->match.dissector; 2036 2037 if (dissector->used_keys & 2038 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 2039 BIT(FLOW_DISSECTOR_KEY_BASIC) | 2040 BIT(FLOW_DISSECTOR_KEY_VLAN) | 2041 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 2042 return -EOPNOTSUPP; 2043 2044 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 2045 struct flow_match_eth_addrs match; 2046 2047 flow_rule_match_eth_addrs(rule, &match); 2048 ether_addr_copy(stream->dmac, match.key->dst); 2049 if (!is_zero_ether_addr(match.mask->src)) 2050 return -EOPNOTSUPP; 2051 } else { 2052 return -EOPNOTSUPP; 2053 } 2054 2055 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 2056 struct flow_match_vlan match; 2057 2058 flow_rule_match_vlan(rule, &match); 2059 if (match.mask->vlan_priority) 2060 stream->prio = match.key->vlan_priority; 2061 else 2062 stream->prio = -1; 2063 2064 if (!match.mask->vlan_id) 2065 return -EOPNOTSUPP; 2066 stream->vid = match.key->vlan_id; 2067 } else { 2068 return -EOPNOTSUPP; 2069 } 2070 2071 stream->id = f->cookie; 2072 2073 return 0; 2074 } 2075 2076 static int vsc9959_mact_stream_set(struct ocelot *ocelot, 2077 struct felix_stream *stream, 2078 struct netlink_ext_ack *extack) 2079 { 2080 enum macaccess_entry_type type; 2081 int ret, sfid, ssid; 2082 u32 vid, dst_idx; 2083 u8 mac[ETH_ALEN]; 2084 2085 ether_addr_copy(mac, stream->dmac); 2086 vid = stream->vid; 2087 2088 /* Stream identification desn't support to add a stream with non 2089 * existent MAC (The MAC entry has not been learned in MAC table). 2090 */ 2091 ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 2092 if (ret) { 2093 if (extack) 2094 NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 2095 return -EOPNOTSUPP; 2096 } 2097 2098 if ((stream->sfid_valid || stream->ssid_valid) && 2099 type == ENTRYTYPE_NORMAL) 2100 type = ENTRYTYPE_LOCKED; 2101 2102 sfid = stream->sfid_valid ? stream->sfid : -1; 2103 ssid = stream->ssid_valid ? stream->ssid : -1; 2104 2105 ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 2106 sfid, ssid); 2107 2108 return ret; 2109 } 2110 2111 static struct felix_stream * 2112 vsc9959_stream_table_lookup(struct list_head *stream_list, 2113 struct felix_stream *stream) 2114 { 2115 struct felix_stream *tmp; 2116 2117 list_for_each_entry(tmp, stream_list, list) 2118 if (ether_addr_equal(tmp->dmac, stream->dmac) && 2119 tmp->vid == stream->vid) 2120 return tmp; 2121 2122 return NULL; 2123 } 2124 2125 static int vsc9959_stream_table_add(struct ocelot *ocelot, 2126 struct list_head *stream_list, 2127 struct felix_stream *stream, 2128 struct netlink_ext_ack *extack) 2129 { 2130 struct felix_stream *stream_entry; 2131 int ret; 2132 2133 stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL); 2134 if (!stream_entry) 2135 return -ENOMEM; 2136 2137 if (!stream->dummy) { 2138 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 2139 if (ret) { 2140 kfree(stream_entry); 2141 return ret; 2142 } 2143 } 2144 2145 list_add_tail(&stream_entry->list, stream_list); 2146 2147 return 0; 2148 } 2149 2150 static struct felix_stream * 2151 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 2152 { 2153 struct felix_stream *tmp; 2154 2155 list_for_each_entry(tmp, stream_list, list) 2156 if (tmp->id == id) 2157 return tmp; 2158 2159 return NULL; 2160 } 2161 2162 static void vsc9959_stream_table_del(struct ocelot *ocelot, 2163 struct felix_stream *stream) 2164 { 2165 if (!stream->dummy) 2166 vsc9959_mact_stream_set(ocelot, stream, NULL); 2167 2168 list_del(&stream->list); 2169 kfree(stream); 2170 } 2171 2172 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 2173 { 2174 return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 2175 } 2176 2177 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 2178 struct felix_stream_filter *sfi) 2179 { 2180 u32 val; 2181 2182 if (sfi->index > VSC9959_PSFP_SFID_MAX) 2183 return -EINVAL; 2184 2185 if (!sfi->enable) { 2186 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 2187 ANA_TABLES_SFIDTIDX); 2188 2189 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 2190 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 2191 2192 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 2193 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 2194 10, 100000); 2195 } 2196 2197 if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 2198 sfi->fmid > VSC9959_PSFP_POLICER_MAX) 2199 return -EINVAL; 2200 2201 ocelot_write(ocelot, 2202 (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 2203 ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 2204 (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 2205 ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 2206 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 2207 ANA_TABLES_SFIDTIDX); 2208 2209 ocelot_write(ocelot, 2210 (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 2211 ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 2212 ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 2213 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 2214 ANA_TABLES_SFIDACCESS); 2215 2216 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 2217 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 2218 10, 100000); 2219 } 2220 2221 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) 2222 { 2223 u32 val; 2224 2225 ocelot_rmw(ocelot, 2226 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), 2227 ANA_TABLES_SFIDTIDX_SFID_INDEX_M, 2228 ANA_TABLES_SFIDTIDX); 2229 2230 ocelot_write(ocelot, 2231 ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | 2232 ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, 2233 ANA_TABLES_SFID_MASK); 2234 2235 ocelot_rmw(ocelot, 2236 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 2237 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, 2238 ANA_TABLES_SFIDACCESS); 2239 2240 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 2241 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 2242 10, 100000); 2243 } 2244 2245 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, 2246 struct felix_stream_filter *sfi, 2247 struct list_head *pos) 2248 { 2249 struct felix_stream_filter *sfi_entry; 2250 int ret; 2251 2252 sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL); 2253 if (!sfi_entry) 2254 return -ENOMEM; 2255 2256 refcount_set(&sfi_entry->refcount, 1); 2257 2258 ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 2259 if (ret) { 2260 kfree(sfi_entry); 2261 return ret; 2262 } 2263 2264 vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask); 2265 2266 list_add(&sfi_entry->list, pos); 2267 2268 return 0; 2269 } 2270 2271 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 2272 struct felix_stream_filter *sfi) 2273 { 2274 struct list_head *pos, *q, *last; 2275 struct felix_stream_filter *tmp; 2276 struct ocelot_psfp_list *psfp; 2277 u32 insert = 0; 2278 2279 psfp = &ocelot->psfp; 2280 last = &psfp->sfi_list; 2281 2282 list_for_each_safe(pos, q, &psfp->sfi_list) { 2283 tmp = list_entry(pos, struct felix_stream_filter, list); 2284 if (sfi->sg_valid == tmp->sg_valid && 2285 sfi->fm_valid == tmp->fm_valid && 2286 sfi->portmask == tmp->portmask && 2287 tmp->sgid == sfi->sgid && 2288 tmp->fmid == sfi->fmid) { 2289 sfi->index = tmp->index; 2290 refcount_inc(&tmp->refcount); 2291 return 0; 2292 } 2293 /* Make sure that the index is increasing in order. */ 2294 if (tmp->index == insert) { 2295 last = pos; 2296 insert++; 2297 } 2298 } 2299 sfi->index = insert; 2300 2301 return vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 2302 } 2303 2304 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, 2305 struct felix_stream_filter *sfi, 2306 struct felix_stream_filter *sfi2) 2307 { 2308 struct felix_stream_filter *tmp; 2309 struct list_head *pos, *q, *last; 2310 struct ocelot_psfp_list *psfp; 2311 u32 insert = 0; 2312 int ret; 2313 2314 psfp = &ocelot->psfp; 2315 last = &psfp->sfi_list; 2316 2317 list_for_each_safe(pos, q, &psfp->sfi_list) { 2318 tmp = list_entry(pos, struct felix_stream_filter, list); 2319 /* Make sure that the index is increasing in order. */ 2320 if (tmp->index >= insert + 2) 2321 break; 2322 2323 insert = tmp->index + 1; 2324 last = pos; 2325 } 2326 sfi->index = insert; 2327 2328 ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 2329 if (ret) 2330 return ret; 2331 2332 sfi2->index = insert + 1; 2333 2334 return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next); 2335 } 2336 2337 static struct felix_stream_filter * 2338 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 2339 { 2340 struct felix_stream_filter *tmp; 2341 2342 list_for_each_entry(tmp, sfi_list, list) 2343 if (tmp->index == index) 2344 return tmp; 2345 2346 return NULL; 2347 } 2348 2349 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 2350 { 2351 struct felix_stream_filter *tmp, *n; 2352 struct ocelot_psfp_list *psfp; 2353 u8 z; 2354 2355 psfp = &ocelot->psfp; 2356 2357 list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 2358 if (tmp->index == index) { 2359 z = refcount_dec_and_test(&tmp->refcount); 2360 if (z) { 2361 tmp->enable = 0; 2362 vsc9959_psfp_sfi_set(ocelot, tmp); 2363 list_del(&tmp->list); 2364 kfree(tmp); 2365 } 2366 break; 2367 } 2368 } 2369 2370 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 2371 struct felix_stream_gate *sgi) 2372 { 2373 sgi->index = entry->hw_index; 2374 sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 2375 sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 2376 sgi->basetime = entry->gate.basetime; 2377 sgi->cycletime = entry->gate.cycletime; 2378 sgi->num_entries = entry->gate.num_entries; 2379 sgi->enable = 1; 2380 2381 memcpy(sgi->entries, entry->gate.entries, 2382 entry->gate.num_entries * sizeof(struct action_gate_entry)); 2383 } 2384 2385 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 2386 { 2387 return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 2388 } 2389 2390 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 2391 struct felix_stream_gate *sgi) 2392 { 2393 struct action_gate_entry *e; 2394 struct timespec64 base_ts; 2395 u32 interval_sum = 0; 2396 u32 val; 2397 int i; 2398 2399 if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 2400 return -EINVAL; 2401 2402 ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 2403 ANA_SG_ACCESS_CTRL); 2404 2405 if (!sgi->enable) { 2406 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 2407 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2408 ANA_SG_CONFIG_REG_3_GATE_ENABLE, 2409 ANA_SG_CONFIG_REG_3); 2410 2411 return 0; 2412 } 2413 2414 if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 2415 sgi->cycletime > NSEC_PER_SEC) 2416 return -EINVAL; 2417 2418 if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 2419 return -EINVAL; 2420 2421 vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 2422 ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 2423 val = lower_32_bits(base_ts.tv_sec); 2424 ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 2425 2426 val = upper_32_bits(base_ts.tv_sec); 2427 ocelot_write(ocelot, 2428 (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 2429 ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 2430 ANA_SG_CONFIG_REG_3_GATE_ENABLE | 2431 ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 2432 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2433 ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 2434 ANA_SG_CONFIG_REG_3); 2435 2436 ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 2437 2438 e = sgi->entries; 2439 for (i = 0; i < sgi->num_entries; i++) { 2440 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 2441 2442 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 2443 (e[i].gate_state ? 2444 ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 2445 ANA_SG_GCL_GS_CONFIG, i); 2446 2447 interval_sum += e[i].interval; 2448 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 2449 } 2450 2451 ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2452 ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2453 ANA_SG_ACCESS_CTRL); 2454 2455 return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 2456 (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 2457 10, 100000); 2458 } 2459 2460 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 2461 struct felix_stream_gate *sgi) 2462 { 2463 struct felix_stream_gate_entry *tmp; 2464 struct ocelot_psfp_list *psfp; 2465 int ret; 2466 2467 psfp = &ocelot->psfp; 2468 2469 list_for_each_entry(tmp, &psfp->sgi_list, list) 2470 if (tmp->index == sgi->index) { 2471 refcount_inc(&tmp->refcount); 2472 return 0; 2473 } 2474 2475 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 2476 if (!tmp) 2477 return -ENOMEM; 2478 2479 ret = vsc9959_psfp_sgi_set(ocelot, sgi); 2480 if (ret) { 2481 kfree(tmp); 2482 return ret; 2483 } 2484 2485 tmp->index = sgi->index; 2486 refcount_set(&tmp->refcount, 1); 2487 list_add_tail(&tmp->list, &psfp->sgi_list); 2488 2489 return 0; 2490 } 2491 2492 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 2493 u32 index) 2494 { 2495 struct felix_stream_gate_entry *tmp, *n; 2496 struct felix_stream_gate sgi = {0}; 2497 struct ocelot_psfp_list *psfp; 2498 u8 z; 2499 2500 psfp = &ocelot->psfp; 2501 2502 list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 2503 if (tmp->index == index) { 2504 z = refcount_dec_and_test(&tmp->refcount); 2505 if (z) { 2506 sgi.index = index; 2507 sgi.enable = 0; 2508 vsc9959_psfp_sgi_set(ocelot, &sgi); 2509 list_del(&tmp->list); 2510 kfree(tmp); 2511 } 2512 break; 2513 } 2514 } 2515 2516 static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index, 2517 struct felix_stream_filter_counters *counters) 2518 { 2519 spin_lock(&ocelot->stats_lock); 2520 2521 ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index), 2522 SYS_STAT_CFG_STAT_VIEW_M, 2523 SYS_STAT_CFG); 2524 2525 counters->match = ocelot_read_gix(ocelot, SYS_CNT, 0x200); 2526 counters->not_pass_gate = ocelot_read_gix(ocelot, SYS_CNT, 0x201); 2527 counters->not_pass_sdu = ocelot_read_gix(ocelot, SYS_CNT, 0x202); 2528 counters->red = ocelot_read_gix(ocelot, SYS_CNT, 0x203); 2529 2530 /* Clear the PSFP counter. */ 2531 ocelot_write(ocelot, 2532 SYS_STAT_CFG_STAT_VIEW(index) | 2533 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 2534 SYS_STAT_CFG); 2535 2536 spin_unlock(&ocelot->stats_lock); 2537 } 2538 2539 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, 2540 struct flow_cls_offload *f) 2541 { 2542 struct netlink_ext_ack *extack = f->common.extack; 2543 struct felix_stream_filter old_sfi, *sfi_entry; 2544 struct felix_stream_filter sfi = {0}; 2545 const struct flow_action_entry *a; 2546 struct felix_stream *stream_entry; 2547 struct felix_stream stream = {0}; 2548 struct felix_stream_gate *sgi; 2549 struct ocelot_psfp_list *psfp; 2550 struct ocelot_policer pol; 2551 int ret, i, size; 2552 u64 rate, burst; 2553 u32 index; 2554 2555 psfp = &ocelot->psfp; 2556 2557 ret = vsc9959_stream_identify(f, &stream); 2558 if (ret) { 2559 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 2560 return ret; 2561 } 2562 2563 flow_action_for_each(i, a, &f->rule->action) { 2564 switch (a->id) { 2565 case FLOW_ACTION_GATE: 2566 size = struct_size(sgi, entries, a->gate.num_entries); 2567 sgi = kzalloc(size, GFP_KERNEL); 2568 if (!sgi) { 2569 ret = -ENOMEM; 2570 goto err; 2571 } 2572 vsc9959_psfp_parse_gate(a, sgi); 2573 ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 2574 if (ret) { 2575 kfree(sgi); 2576 goto err; 2577 } 2578 sfi.sg_valid = 1; 2579 sfi.sgid = sgi->index; 2580 kfree(sgi); 2581 break; 2582 case FLOW_ACTION_POLICE: 2583 index = a->hw_index + VSC9959_PSFP_POLICER_BASE; 2584 if (index > VSC9959_PSFP_POLICER_MAX) { 2585 ret = -EINVAL; 2586 goto err; 2587 } 2588 2589 rate = a->police.rate_bytes_ps; 2590 burst = rate * PSCHED_NS2TICKS(a->police.burst); 2591 pol = (struct ocelot_policer) { 2592 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC), 2593 .rate = div_u64(rate, 1000) * 8, 2594 }; 2595 ret = ocelot_vcap_policer_add(ocelot, index, &pol); 2596 if (ret) 2597 goto err; 2598 2599 sfi.fm_valid = 1; 2600 sfi.fmid = index; 2601 sfi.maxsdu = a->police.mtu; 2602 break; 2603 default: 2604 return -EOPNOTSUPP; 2605 } 2606 } 2607 2608 stream.ports = BIT(port); 2609 stream.port = port; 2610 2611 sfi.portmask = stream.ports; 2612 sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 2613 sfi.prio = (sfi.prio_valid ? stream.prio : 0); 2614 sfi.enable = 1; 2615 2616 /* Check if stream is set. */ 2617 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 2618 if (stream_entry) { 2619 if (stream_entry->ports & BIT(port)) { 2620 NL_SET_ERR_MSG_MOD(extack, 2621 "The stream is added on this port"); 2622 ret = -EEXIST; 2623 goto err; 2624 } 2625 2626 if (stream_entry->ports != BIT(stream_entry->port)) { 2627 NL_SET_ERR_MSG_MOD(extack, 2628 "The stream is added on two ports"); 2629 ret = -EEXIST; 2630 goto err; 2631 } 2632 2633 stream_entry->ports |= BIT(port); 2634 stream.ports = stream_entry->ports; 2635 2636 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, 2637 stream_entry->sfid); 2638 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); 2639 2640 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid); 2641 2642 old_sfi.portmask = stream_entry->ports; 2643 sfi.portmask = stream.ports; 2644 2645 if (stream_entry->port > port) { 2646 ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi, 2647 &old_sfi); 2648 stream_entry->dummy = true; 2649 } else { 2650 ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi, 2651 &sfi); 2652 stream.dummy = true; 2653 } 2654 if (ret) 2655 goto err; 2656 2657 stream_entry->sfid = old_sfi.index; 2658 } else { 2659 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 2660 if (ret) 2661 goto err; 2662 } 2663 2664 stream.sfid = sfi.index; 2665 stream.sfid_valid = 1; 2666 ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 2667 &stream, extack); 2668 if (ret) { 2669 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 2670 goto err; 2671 } 2672 2673 return 0; 2674 2675 err: 2676 if (sfi.sg_valid) 2677 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 2678 2679 if (sfi.fm_valid) 2680 ocelot_vcap_policer_del(ocelot, sfi.fmid); 2681 2682 return ret; 2683 } 2684 2685 static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 2686 struct flow_cls_offload *f) 2687 { 2688 struct felix_stream *stream, tmp, *stream_entry; 2689 static struct felix_stream_filter *sfi; 2690 struct ocelot_psfp_list *psfp; 2691 2692 psfp = &ocelot->psfp; 2693 2694 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2695 if (!stream) 2696 return -ENOMEM; 2697 2698 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2699 if (!sfi) 2700 return -ENOMEM; 2701 2702 if (sfi->sg_valid) 2703 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 2704 2705 if (sfi->fm_valid) 2706 ocelot_vcap_policer_del(ocelot, sfi->fmid); 2707 2708 vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 2709 2710 memcpy(&tmp, stream, sizeof(tmp)); 2711 2712 stream->sfid_valid = 0; 2713 vsc9959_stream_table_del(ocelot, stream); 2714 2715 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp); 2716 if (stream_entry) { 2717 stream_entry->ports = BIT(stream_entry->port); 2718 if (stream_entry->dummy) { 2719 stream_entry->dummy = false; 2720 vsc9959_mact_stream_set(ocelot, stream_entry, NULL); 2721 } 2722 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid, 2723 stream_entry->ports); 2724 } 2725 2726 return 0; 2727 } 2728 2729 static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 2730 struct flow_cls_offload *f, 2731 struct flow_stats *stats) 2732 { 2733 struct felix_stream_filter_counters counters; 2734 struct ocelot_psfp_list *psfp; 2735 struct felix_stream *stream; 2736 2737 psfp = &ocelot->psfp; 2738 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2739 if (!stream) 2740 return -ENOMEM; 2741 2742 vsc9959_psfp_counters_get(ocelot, stream->sfid, &counters); 2743 2744 stats->pkts = counters.match; 2745 stats->drops = counters.not_pass_gate + counters.not_pass_sdu + 2746 counters.red; 2747 2748 return 0; 2749 } 2750 2751 static void vsc9959_psfp_init(struct ocelot *ocelot) 2752 { 2753 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2754 2755 INIT_LIST_HEAD(&psfp->stream_list); 2756 INIT_LIST_HEAD(&psfp->sfi_list); 2757 INIT_LIST_HEAD(&psfp->sgi_list); 2758 } 2759 2760 /* When using cut-through forwarding and the egress port runs at a higher data 2761 * rate than the ingress port, the packet currently under transmission would 2762 * suffer an underrun since it would be transmitted faster than it is received. 2763 * The Felix switch implementation of cut-through forwarding does not check in 2764 * hardware whether this condition is satisfied or not, so we must restrict the 2765 * list of ports that have cut-through forwarding enabled on egress to only be 2766 * the ports operating at the lowest link speed within their respective 2767 * forwarding domain. 2768 */ 2769 static void vsc9959_cut_through_fwd(struct ocelot *ocelot) 2770 { 2771 struct felix *felix = ocelot_to_felix(ocelot); 2772 struct dsa_switch *ds = felix->ds; 2773 int port, other_port; 2774 2775 lockdep_assert_held(&ocelot->fwd_domain_lock); 2776 2777 for (port = 0; port < ocelot->num_phys_ports; port++) { 2778 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2779 int min_speed = ocelot_port->speed; 2780 unsigned long mask = 0; 2781 u32 tmp, val = 0; 2782 2783 /* Disable cut-through on ports that are down */ 2784 if (ocelot_port->speed <= 0) 2785 goto set; 2786 2787 if (dsa_is_cpu_port(ds, port)) { 2788 /* Ocelot switches forward from the NPI port towards 2789 * any port, regardless of it being in the NPI port's 2790 * forwarding domain or not. 2791 */ 2792 mask = dsa_user_ports(ds); 2793 } else { 2794 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 2795 mask &= ~BIT(port); 2796 if (ocelot->npi >= 0) 2797 mask |= BIT(ocelot->npi); 2798 else 2799 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 2800 port); 2801 } 2802 2803 /* Calculate the minimum link speed, among the ports that are 2804 * up, of this source port's forwarding domain. 2805 */ 2806 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { 2807 struct ocelot_port *other_ocelot_port; 2808 2809 other_ocelot_port = ocelot->ports[other_port]; 2810 if (other_ocelot_port->speed <= 0) 2811 continue; 2812 2813 if (min_speed > other_ocelot_port->speed) 2814 min_speed = other_ocelot_port->speed; 2815 } 2816 2817 /* Enable cut-through forwarding for all traffic classes. */ 2818 if (ocelot_port->speed == min_speed) 2819 val = GENMASK(7, 0); 2820 2821 set: 2822 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); 2823 if (tmp == val) 2824 continue; 2825 2826 dev_dbg(ocelot->dev, 2827 "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding\n", 2828 port, mask, ocelot_port->speed, min_speed, 2829 val ? "enabling" : "disabling"); 2830 2831 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); 2832 } 2833 } 2834 2835 static const struct ocelot_ops vsc9959_ops = { 2836 .reset = vsc9959_reset, 2837 .wm_enc = vsc9959_wm_enc, 2838 .wm_dec = vsc9959_wm_dec, 2839 .wm_stat = vsc9959_wm_stat, 2840 .port_to_netdev = felix_port_to_netdev, 2841 .netdev_to_port = felix_netdev_to_port, 2842 .psfp_init = vsc9959_psfp_init, 2843 .psfp_filter_add = vsc9959_psfp_filter_add, 2844 .psfp_filter_del = vsc9959_psfp_filter_del, 2845 .psfp_stats_get = vsc9959_psfp_stats_get, 2846 .cut_through_fwd = vsc9959_cut_through_fwd, 2847 .tas_clock_adjust = vsc9959_tas_clock_adjust, 2848 }; 2849 2850 static const struct felix_info felix_info_vsc9959 = { 2851 .target_io_res = vsc9959_target_io_res, 2852 .port_io_res = vsc9959_port_io_res, 2853 .imdio_res = &vsc9959_imdio_res, 2854 .regfields = vsc9959_regfields, 2855 .map = vsc9959_regmap, 2856 .ops = &vsc9959_ops, 2857 .stats_layout = vsc9959_stats_layout, 2858 .vcap = vsc9959_vcap_props, 2859 .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 2860 .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 2861 .vcap_pol_base2 = 0, 2862 .vcap_pol_max2 = 0, 2863 .num_mact_rows = 2048, 2864 .num_ports = VSC9959_NUM_PORTS, 2865 .num_tx_queues = OCELOT_NUM_TC, 2866 .quirk_no_xtr_irq = true, 2867 .ptp_caps = &vsc9959_ptp_caps, 2868 .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2869 .mdio_bus_free = vsc9959_mdio_bus_free, 2870 .phylink_validate = vsc9959_phylink_validate, 2871 .port_modes = vsc9959_port_modes, 2872 .port_setup_tc = vsc9959_port_setup_tc, 2873 .port_sched_speed_set = vsc9959_sched_speed_set, 2874 .tas_guard_bands_update = vsc9959_tas_guard_bands_update, 2875 .init_regmap = ocelot_regmap_init, 2876 }; 2877 2878 static irqreturn_t felix_irq_handler(int irq, void *data) 2879 { 2880 struct ocelot *ocelot = (struct ocelot *)data; 2881 2882 /* The INTB interrupt is used for both PTP TX timestamp interrupt 2883 * and preemption status change interrupt on each port. 2884 * 2885 * - Get txtstamp if have 2886 * - TODO: handle preemption. Without handling it, driver may get 2887 * interrupt storm. 2888 */ 2889 2890 ocelot_get_txtstamp(ocelot); 2891 2892 return IRQ_HANDLED; 2893 } 2894 2895 static int felix_pci_probe(struct pci_dev *pdev, 2896 const struct pci_device_id *id) 2897 { 2898 struct dsa_switch *ds; 2899 struct ocelot *ocelot; 2900 struct felix *felix; 2901 int err; 2902 2903 if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 2904 dev_info(&pdev->dev, "device is disabled, skipping\n"); 2905 return -ENODEV; 2906 } 2907 2908 err = pci_enable_device(pdev); 2909 if (err) { 2910 dev_err(&pdev->dev, "device enable failed\n"); 2911 goto err_pci_enable; 2912 } 2913 2914 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 2915 if (!felix) { 2916 err = -ENOMEM; 2917 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 2918 goto err_alloc_felix; 2919 } 2920 2921 pci_set_drvdata(pdev, felix); 2922 ocelot = &felix->ocelot; 2923 ocelot->dev = &pdev->dev; 2924 ocelot->num_flooding_pgids = OCELOT_NUM_TC; 2925 felix->info = &felix_info_vsc9959; 2926 felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); 2927 felix->imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); 2928 2929 pci_set_master(pdev); 2930 2931 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 2932 &felix_irq_handler, IRQF_ONESHOT, 2933 "felix-intb", ocelot); 2934 if (err) { 2935 dev_err(&pdev->dev, "Failed to request irq\n"); 2936 goto err_alloc_irq; 2937 } 2938 2939 ocelot->ptp = 1; 2940 2941 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 2942 if (!ds) { 2943 err = -ENOMEM; 2944 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 2945 goto err_alloc_ds; 2946 } 2947 2948 ds->dev = &pdev->dev; 2949 ds->num_ports = felix->info->num_ports; 2950 ds->num_tx_queues = felix->info->num_tx_queues; 2951 ds->ops = &felix_switch_ops; 2952 ds->priv = ocelot; 2953 felix->ds = ds; 2954 felix->tag_proto = DSA_TAG_PROTO_OCELOT; 2955 2956 err = dsa_register_switch(ds); 2957 if (err) { 2958 dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n"); 2959 goto err_register_ds; 2960 } 2961 2962 return 0; 2963 2964 err_register_ds: 2965 kfree(ds); 2966 err_alloc_ds: 2967 err_alloc_irq: 2968 kfree(felix); 2969 err_alloc_felix: 2970 pci_disable_device(pdev); 2971 err_pci_enable: 2972 return err; 2973 } 2974 2975 static void felix_pci_remove(struct pci_dev *pdev) 2976 { 2977 struct felix *felix = pci_get_drvdata(pdev); 2978 2979 if (!felix) 2980 return; 2981 2982 dsa_unregister_switch(felix->ds); 2983 2984 kfree(felix->ds); 2985 kfree(felix); 2986 2987 pci_disable_device(pdev); 2988 2989 pci_set_drvdata(pdev, NULL); 2990 } 2991 2992 static void felix_pci_shutdown(struct pci_dev *pdev) 2993 { 2994 struct felix *felix = pci_get_drvdata(pdev); 2995 2996 if (!felix) 2997 return; 2998 2999 dsa_switch_shutdown(felix->ds); 3000 3001 pci_set_drvdata(pdev, NULL); 3002 } 3003 3004 static struct pci_device_id felix_ids[] = { 3005 { 3006 /* NXP LS1028A */ 3007 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 3008 }, 3009 { 0, } 3010 }; 3011 MODULE_DEVICE_TABLE(pci, felix_ids); 3012 3013 static struct pci_driver felix_vsc9959_pci_driver = { 3014 .name = "mscc_felix", 3015 .id_table = felix_ids, 3016 .probe = felix_pci_probe, 3017 .remove = felix_pci_remove, 3018 .shutdown = felix_pci_shutdown, 3019 }; 3020 module_pci_driver(felix_vsc9959_pci_driver); 3021 3022 MODULE_DESCRIPTION("Felix Switch driver"); 3023 MODULE_LICENSE("GPL v2"); 3024