xref: /openbmc/linux/drivers/net/dsa/ocelot/felix_vsc9959.c (revision 0760aad038b5a032c31ea124feed63d88627d2f1) 
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright 2017 Microsemi Corporation
3  * Copyright 2018-2019 NXP Semiconductors
4  */
5 #include <linux/fsl/enetc_mdio.h>
6 #include <soc/mscc/ocelot_qsys.h>
7 #include <soc/mscc/ocelot_vcap.h>
8 #include <soc/mscc/ocelot_ptp.h>
9 #include <soc/mscc/ocelot_sys.h>
10 #include <soc/mscc/ocelot.h>
11 #include <linux/packing.h>
12 #include <linux/pcs-lynx.h>
13 #include <net/pkt_sched.h>
14 #include <linux/iopoll.h>
15 #include <linux/mdio.h>
16 #include <linux/pci.h>
17 #include "felix.h"
18 
19 #define VSC9959_VCAP_IS2_CNT		1024
20 #define VSC9959_VCAP_IS2_ENTRY_WIDTH	376
21 #define VSC9959_VCAP_PORT_CNT		6
22 #define VSC9959_TAS_GCL_ENTRY_MAX	63
23 
24 static const u32 vsc9959_ana_regmap[] = {
25 	REG(ANA_ADVLEARN,			0x0089a0),
26 	REG(ANA_VLANMASK,			0x0089a4),
27 	REG_RESERVED(ANA_PORT_B_DOMAIN),
28 	REG(ANA_ANAGEFIL,			0x0089ac),
29 	REG(ANA_ANEVENTS,			0x0089b0),
30 	REG(ANA_STORMLIMIT_BURST,		0x0089b4),
31 	REG(ANA_STORMLIMIT_CFG,			0x0089b8),
32 	REG(ANA_ISOLATED_PORTS,			0x0089c8),
33 	REG(ANA_COMMUNITY_PORTS,		0x0089cc),
34 	REG(ANA_AUTOAGE,			0x0089d0),
35 	REG(ANA_MACTOPTIONS,			0x0089d4),
36 	REG(ANA_LEARNDISC,			0x0089d8),
37 	REG(ANA_AGENCTRL,			0x0089dc),
38 	REG(ANA_MIRRORPORTS,			0x0089e0),
39 	REG(ANA_EMIRRORPORTS,			0x0089e4),
40 	REG(ANA_FLOODING,			0x0089e8),
41 	REG(ANA_FLOODING_IPMC,			0x008a08),
42 	REG(ANA_SFLOW_CFG,			0x008a0c),
43 	REG(ANA_PORT_MODE,			0x008a28),
44 	REG(ANA_CUT_THRU_CFG,			0x008a48),
45 	REG(ANA_PGID_PGID,			0x008400),
46 	REG(ANA_TABLES_ANMOVED,			0x007f1c),
47 	REG(ANA_TABLES_MACHDATA,		0x007f20),
48 	REG(ANA_TABLES_MACLDATA,		0x007f24),
49 	REG(ANA_TABLES_STREAMDATA,		0x007f28),
50 	REG(ANA_TABLES_MACACCESS,		0x007f2c),
51 	REG(ANA_TABLES_MACTINDX,		0x007f30),
52 	REG(ANA_TABLES_VLANACCESS,		0x007f34),
53 	REG(ANA_TABLES_VLANTIDX,		0x007f38),
54 	REG(ANA_TABLES_ISDXACCESS,		0x007f3c),
55 	REG(ANA_TABLES_ISDXTIDX,		0x007f40),
56 	REG(ANA_TABLES_ENTRYLIM,		0x007f00),
57 	REG(ANA_TABLES_PTP_ID_HIGH,		0x007f44),
58 	REG(ANA_TABLES_PTP_ID_LOW,		0x007f48),
59 	REG(ANA_TABLES_STREAMACCESS,		0x007f4c),
60 	REG(ANA_TABLES_STREAMTIDX,		0x007f50),
61 	REG(ANA_TABLES_SEQ_HISTORY,		0x007f54),
62 	REG(ANA_TABLES_SEQ_MASK,		0x007f58),
63 	REG(ANA_TABLES_SFID_MASK,		0x007f5c),
64 	REG(ANA_TABLES_SFIDACCESS,		0x007f60),
65 	REG(ANA_TABLES_SFIDTIDX,		0x007f64),
66 	REG(ANA_MSTI_STATE,			0x008600),
67 	REG(ANA_OAM_UPM_LM_CNT,			0x008000),
68 	REG(ANA_SG_ACCESS_CTRL,			0x008a64),
69 	REG(ANA_SG_CONFIG_REG_1,		0x007fb0),
70 	REG(ANA_SG_CONFIG_REG_2,		0x007fb4),
71 	REG(ANA_SG_CONFIG_REG_3,		0x007fb8),
72 	REG(ANA_SG_CONFIG_REG_4,		0x007fbc),
73 	REG(ANA_SG_CONFIG_REG_5,		0x007fc0),
74 	REG(ANA_SG_GCL_GS_CONFIG,		0x007f80),
75 	REG(ANA_SG_GCL_TI_CONFIG,		0x007f90),
76 	REG(ANA_SG_STATUS_REG_1,		0x008980),
77 	REG(ANA_SG_STATUS_REG_2,		0x008984),
78 	REG(ANA_SG_STATUS_REG_3,		0x008988),
79 	REG(ANA_PORT_VLAN_CFG,			0x007800),
80 	REG(ANA_PORT_DROP_CFG,			0x007804),
81 	REG(ANA_PORT_QOS_CFG,			0x007808),
82 	REG(ANA_PORT_VCAP_CFG,			0x00780c),
83 	REG(ANA_PORT_VCAP_S1_KEY_CFG,		0x007810),
84 	REG(ANA_PORT_VCAP_S2_CFG,		0x00781c),
85 	REG(ANA_PORT_PCP_DEI_MAP,		0x007820),
86 	REG(ANA_PORT_CPU_FWD_CFG,		0x007860),
87 	REG(ANA_PORT_CPU_FWD_BPDU_CFG,		0x007864),
88 	REG(ANA_PORT_CPU_FWD_GARP_CFG,		0x007868),
89 	REG(ANA_PORT_CPU_FWD_CCM_CFG,		0x00786c),
90 	REG(ANA_PORT_PORT_CFG,			0x007870),
91 	REG(ANA_PORT_POL_CFG,			0x007874),
92 	REG(ANA_PORT_PTP_CFG,			0x007878),
93 	REG(ANA_PORT_PTP_DLY1_CFG,		0x00787c),
94 	REG(ANA_PORT_PTP_DLY2_CFG,		0x007880),
95 	REG(ANA_PORT_SFID_CFG,			0x007884),
96 	REG(ANA_PFC_PFC_CFG,			0x008800),
97 	REG_RESERVED(ANA_PFC_PFC_TIMER),
98 	REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
99 	REG_RESERVED(ANA_IPT_IPT),
100 	REG_RESERVED(ANA_PPT_PPT),
101 	REG_RESERVED(ANA_FID_MAP_FID_MAP),
102 	REG(ANA_AGGR_CFG,			0x008a68),
103 	REG(ANA_CPUQ_CFG,			0x008a6c),
104 	REG_RESERVED(ANA_CPUQ_CFG2),
105 	REG(ANA_CPUQ_8021_CFG,			0x008a74),
106 	REG(ANA_DSCP_CFG,			0x008ab4),
107 	REG(ANA_DSCP_REWR_CFG,			0x008bb4),
108 	REG(ANA_VCAP_RNG_TYPE_CFG,		0x008bf4),
109 	REG(ANA_VCAP_RNG_VAL_CFG,		0x008c14),
110 	REG_RESERVED(ANA_VRAP_CFG),
111 	REG_RESERVED(ANA_VRAP_HDR_DATA),
112 	REG_RESERVED(ANA_VRAP_HDR_MASK),
113 	REG(ANA_DISCARD_CFG,			0x008c40),
114 	REG(ANA_FID_CFG,			0x008c44),
115 	REG(ANA_POL_PIR_CFG,			0x004000),
116 	REG(ANA_POL_CIR_CFG,			0x004004),
117 	REG(ANA_POL_MODE_CFG,			0x004008),
118 	REG(ANA_POL_PIR_STATE,			0x00400c),
119 	REG(ANA_POL_CIR_STATE,			0x004010),
120 	REG_RESERVED(ANA_POL_STATE),
121 	REG(ANA_POL_FLOWC,			0x008c48),
122 	REG(ANA_POL_HYST,			0x008cb4),
123 	REG_RESERVED(ANA_POL_MISC_CFG),
124 };
125 
126 static const u32 vsc9959_qs_regmap[] = {
127 	REG(QS_XTR_GRP_CFG,			0x000000),
128 	REG(QS_XTR_RD,				0x000008),
129 	REG(QS_XTR_FRM_PRUNING,			0x000010),
130 	REG(QS_XTR_FLUSH,			0x000018),
131 	REG(QS_XTR_DATA_PRESENT,		0x00001c),
132 	REG(QS_XTR_CFG,				0x000020),
133 	REG(QS_INJ_GRP_CFG,			0x000024),
134 	REG(QS_INJ_WR,				0x00002c),
135 	REG(QS_INJ_CTRL,			0x000034),
136 	REG(QS_INJ_STATUS,			0x00003c),
137 	REG(QS_INJ_ERR,				0x000040),
138 	REG_RESERVED(QS_INH_DBG),
139 };
140 
141 static const u32 vsc9959_s2_regmap[] = {
142 	REG(S2_CORE_UPDATE_CTRL,		0x000000),
143 	REG(S2_CORE_MV_CFG,			0x000004),
144 	REG(S2_CACHE_ENTRY_DAT,			0x000008),
145 	REG(S2_CACHE_MASK_DAT,			0x000108),
146 	REG(S2_CACHE_ACTION_DAT,		0x000208),
147 	REG(S2_CACHE_CNT_DAT,			0x000308),
148 	REG(S2_CACHE_TG_DAT,			0x000388),
149 };
150 
151 static const u32 vsc9959_qsys_regmap[] = {
152 	REG(QSYS_PORT_MODE,			0x00f460),
153 	REG(QSYS_SWITCH_PORT_MODE,		0x00f480),
154 	REG(QSYS_STAT_CNT_CFG,			0x00f49c),
155 	REG(QSYS_EEE_CFG,			0x00f4a0),
156 	REG(QSYS_EEE_THRES,			0x00f4b8),
157 	REG(QSYS_IGR_NO_SHARING,		0x00f4bc),
158 	REG(QSYS_EGR_NO_SHARING,		0x00f4c0),
159 	REG(QSYS_SW_STATUS,			0x00f4c4),
160 	REG(QSYS_EXT_CPU_CFG,			0x00f4e0),
161 	REG_RESERVED(QSYS_PAD_CFG),
162 	REG(QSYS_CPU_GROUP_MAP,			0x00f4e8),
163 	REG_RESERVED(QSYS_QMAP),
164 	REG_RESERVED(QSYS_ISDX_SGRP),
165 	REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
166 	REG(QSYS_TFRM_MISC,			0x00f50c),
167 	REG(QSYS_TFRM_PORT_DLY,			0x00f510),
168 	REG(QSYS_TFRM_TIMER_CFG_1,		0x00f514),
169 	REG(QSYS_TFRM_TIMER_CFG_2,		0x00f518),
170 	REG(QSYS_TFRM_TIMER_CFG_3,		0x00f51c),
171 	REG(QSYS_TFRM_TIMER_CFG_4,		0x00f520),
172 	REG(QSYS_TFRM_TIMER_CFG_5,		0x00f524),
173 	REG(QSYS_TFRM_TIMER_CFG_6,		0x00f528),
174 	REG(QSYS_TFRM_TIMER_CFG_7,		0x00f52c),
175 	REG(QSYS_TFRM_TIMER_CFG_8,		0x00f530),
176 	REG(QSYS_RED_PROFILE,			0x00f534),
177 	REG(QSYS_RES_QOS_MODE,			0x00f574),
178 	REG(QSYS_RES_CFG,			0x00c000),
179 	REG(QSYS_RES_STAT,			0x00c004),
180 	REG(QSYS_EGR_DROP_MODE,			0x00f578),
181 	REG(QSYS_EQ_CTRL,			0x00f57c),
182 	REG_RESERVED(QSYS_EVENTS_CORE),
183 	REG(QSYS_QMAXSDU_CFG_0,			0x00f584),
184 	REG(QSYS_QMAXSDU_CFG_1,			0x00f5a0),
185 	REG(QSYS_QMAXSDU_CFG_2,			0x00f5bc),
186 	REG(QSYS_QMAXSDU_CFG_3,			0x00f5d8),
187 	REG(QSYS_QMAXSDU_CFG_4,			0x00f5f4),
188 	REG(QSYS_QMAXSDU_CFG_5,			0x00f610),
189 	REG(QSYS_QMAXSDU_CFG_6,			0x00f62c),
190 	REG(QSYS_QMAXSDU_CFG_7,			0x00f648),
191 	REG(QSYS_PREEMPTION_CFG,		0x00f664),
192 	REG(QSYS_CIR_CFG,			0x000000),
193 	REG(QSYS_EIR_CFG,			0x000004),
194 	REG(QSYS_SE_CFG,			0x000008),
195 	REG(QSYS_SE_DWRR_CFG,			0x00000c),
196 	REG_RESERVED(QSYS_SE_CONNECT),
197 	REG(QSYS_SE_DLB_SENSE,			0x000040),
198 	REG(QSYS_CIR_STATE,			0x000044),
199 	REG(QSYS_EIR_STATE,			0x000048),
200 	REG_RESERVED(QSYS_SE_STATE),
201 	REG(QSYS_HSCH_MISC_CFG,			0x00f67c),
202 	REG(QSYS_TAG_CONFIG,			0x00f680),
203 	REG(QSYS_TAS_PARAM_CFG_CTRL,		0x00f698),
204 	REG(QSYS_PORT_MAX_SDU,			0x00f69c),
205 	REG(QSYS_PARAM_CFG_REG_1,		0x00f440),
206 	REG(QSYS_PARAM_CFG_REG_2,		0x00f444),
207 	REG(QSYS_PARAM_CFG_REG_3,		0x00f448),
208 	REG(QSYS_PARAM_CFG_REG_4,		0x00f44c),
209 	REG(QSYS_PARAM_CFG_REG_5,		0x00f450),
210 	REG(QSYS_GCL_CFG_REG_1,			0x00f454),
211 	REG(QSYS_GCL_CFG_REG_2,			0x00f458),
212 	REG(QSYS_PARAM_STATUS_REG_1,		0x00f400),
213 	REG(QSYS_PARAM_STATUS_REG_2,		0x00f404),
214 	REG(QSYS_PARAM_STATUS_REG_3,		0x00f408),
215 	REG(QSYS_PARAM_STATUS_REG_4,		0x00f40c),
216 	REG(QSYS_PARAM_STATUS_REG_5,		0x00f410),
217 	REG(QSYS_PARAM_STATUS_REG_6,		0x00f414),
218 	REG(QSYS_PARAM_STATUS_REG_7,		0x00f418),
219 	REG(QSYS_PARAM_STATUS_REG_8,		0x00f41c),
220 	REG(QSYS_PARAM_STATUS_REG_9,		0x00f420),
221 	REG(QSYS_GCL_STATUS_REG_1,		0x00f424),
222 	REG(QSYS_GCL_STATUS_REG_2,		0x00f428),
223 };
224 
225 static const u32 vsc9959_rew_regmap[] = {
226 	REG(REW_PORT_VLAN_CFG,			0x000000),
227 	REG(REW_TAG_CFG,			0x000004),
228 	REG(REW_PORT_CFG,			0x000008),
229 	REG(REW_DSCP_CFG,			0x00000c),
230 	REG(REW_PCP_DEI_QOS_MAP_CFG,		0x000010),
231 	REG(REW_PTP_CFG,			0x000050),
232 	REG(REW_PTP_DLY1_CFG,			0x000054),
233 	REG(REW_RED_TAG_CFG,			0x000058),
234 	REG(REW_DSCP_REMAP_DP1_CFG,		0x000410),
235 	REG(REW_DSCP_REMAP_CFG,			0x000510),
236 	REG_RESERVED(REW_STAT_CFG),
237 	REG_RESERVED(REW_REW_STICKY),
238 	REG_RESERVED(REW_PPT),
239 };
240 
241 static const u32 vsc9959_sys_regmap[] = {
242 	REG(SYS_COUNT_RX_OCTETS,		0x000000),
243 	REG(SYS_COUNT_RX_MULTICAST,		0x000008),
244 	REG(SYS_COUNT_RX_SHORTS,		0x000010),
245 	REG(SYS_COUNT_RX_FRAGMENTS,		0x000014),
246 	REG(SYS_COUNT_RX_JABBERS,		0x000018),
247 	REG(SYS_COUNT_RX_64,			0x000024),
248 	REG(SYS_COUNT_RX_65_127,		0x000028),
249 	REG(SYS_COUNT_RX_128_255,		0x00002c),
250 	REG(SYS_COUNT_RX_256_1023,		0x000030),
251 	REG(SYS_COUNT_RX_1024_1526,		0x000034),
252 	REG(SYS_COUNT_RX_1527_MAX,		0x000038),
253 	REG(SYS_COUNT_RX_LONGS,			0x000044),
254 	REG(SYS_COUNT_TX_OCTETS,		0x000200),
255 	REG(SYS_COUNT_TX_COLLISION,		0x000210),
256 	REG(SYS_COUNT_TX_DROPS,			0x000214),
257 	REG(SYS_COUNT_TX_64,			0x00021c),
258 	REG(SYS_COUNT_TX_65_127,		0x000220),
259 	REG(SYS_COUNT_TX_128_511,		0x000224),
260 	REG(SYS_COUNT_TX_512_1023,		0x000228),
261 	REG(SYS_COUNT_TX_1024_1526,		0x00022c),
262 	REG(SYS_COUNT_TX_1527_MAX,		0x000230),
263 	REG(SYS_COUNT_TX_AGING,			0x000278),
264 	REG(SYS_RESET_CFG,			0x000e00),
265 	REG(SYS_SR_ETYPE_CFG,			0x000e04),
266 	REG(SYS_VLAN_ETYPE_CFG,			0x000e08),
267 	REG(SYS_PORT_MODE,			0x000e0c),
268 	REG(SYS_FRONT_PORT_MODE,		0x000e2c),
269 	REG(SYS_FRM_AGING,			0x000e44),
270 	REG(SYS_STAT_CFG,			0x000e48),
271 	REG(SYS_SW_STATUS,			0x000e4c),
272 	REG_RESERVED(SYS_MISC_CFG),
273 	REG(SYS_REW_MAC_HIGH_CFG,		0x000e6c),
274 	REG(SYS_REW_MAC_LOW_CFG,		0x000e84),
275 	REG(SYS_TIMESTAMP_OFFSET,		0x000e9c),
276 	REG(SYS_PAUSE_CFG,			0x000ea0),
277 	REG(SYS_PAUSE_TOT_CFG,			0x000ebc),
278 	REG(SYS_ATOP,				0x000ec0),
279 	REG(SYS_ATOP_TOT_CFG,			0x000edc),
280 	REG(SYS_MAC_FC_CFG,			0x000ee0),
281 	REG(SYS_MMGT,				0x000ef8),
282 	REG_RESERVED(SYS_MMGT_FAST),
283 	REG_RESERVED(SYS_EVENTS_DIF),
284 	REG_RESERVED(SYS_EVENTS_CORE),
285 	REG_RESERVED(SYS_CNT),
286 	REG(SYS_PTP_STATUS,			0x000f14),
287 	REG(SYS_PTP_TXSTAMP,			0x000f18),
288 	REG(SYS_PTP_NXT,			0x000f1c),
289 	REG(SYS_PTP_CFG,			0x000f20),
290 	REG(SYS_RAM_INIT,			0x000f24),
291 	REG_RESERVED(SYS_CM_ADDR),
292 	REG_RESERVED(SYS_CM_DATA_WR),
293 	REG_RESERVED(SYS_CM_DATA_RD),
294 	REG_RESERVED(SYS_CM_OP),
295 	REG_RESERVED(SYS_CM_DATA),
296 };
297 
298 static const u32 vsc9959_ptp_regmap[] = {
299 	REG(PTP_PIN_CFG,                   0x000000),
300 	REG(PTP_PIN_TOD_SEC_MSB,           0x000004),
301 	REG(PTP_PIN_TOD_SEC_LSB,           0x000008),
302 	REG(PTP_PIN_TOD_NSEC,              0x00000c),
303 	REG(PTP_PIN_WF_HIGH_PERIOD,        0x000014),
304 	REG(PTP_PIN_WF_LOW_PERIOD,         0x000018),
305 	REG(PTP_CFG_MISC,                  0x0000a0),
306 	REG(PTP_CLK_CFG_ADJ_CFG,           0x0000a4),
307 	REG(PTP_CLK_CFG_ADJ_FREQ,          0x0000a8),
308 };
309 
310 static const u32 vsc9959_gcb_regmap[] = {
311 	REG(GCB_SOFT_RST,			0x000004),
312 };
313 
314 static const u32 vsc9959_dev_gmii_regmap[] = {
315 	REG(DEV_CLOCK_CFG,			0x0),
316 	REG(DEV_PORT_MISC,			0x4),
317 	REG(DEV_EVENTS,				0x8),
318 	REG(DEV_EEE_CFG,			0xc),
319 	REG(DEV_RX_PATH_DELAY,			0x10),
320 	REG(DEV_TX_PATH_DELAY,			0x14),
321 	REG(DEV_PTP_PREDICT_CFG,		0x18),
322 	REG(DEV_MAC_ENA_CFG,			0x1c),
323 	REG(DEV_MAC_MODE_CFG,			0x20),
324 	REG(DEV_MAC_MAXLEN_CFG,			0x24),
325 	REG(DEV_MAC_TAGS_CFG,			0x28),
326 	REG(DEV_MAC_ADV_CHK_CFG,		0x2c),
327 	REG(DEV_MAC_IFG_CFG,			0x30),
328 	REG(DEV_MAC_HDX_CFG,			0x34),
329 	REG(DEV_MAC_DBG_CFG,			0x38),
330 	REG(DEV_MAC_FC_MAC_LOW_CFG,		0x3c),
331 	REG(DEV_MAC_FC_MAC_HIGH_CFG,		0x40),
332 	REG(DEV_MAC_STICKY,			0x44),
333 	REG_RESERVED(PCS1G_CFG),
334 	REG_RESERVED(PCS1G_MODE_CFG),
335 	REG_RESERVED(PCS1G_SD_CFG),
336 	REG_RESERVED(PCS1G_ANEG_CFG),
337 	REG_RESERVED(PCS1G_ANEG_NP_CFG),
338 	REG_RESERVED(PCS1G_LB_CFG),
339 	REG_RESERVED(PCS1G_DBG_CFG),
340 	REG_RESERVED(PCS1G_CDET_CFG),
341 	REG_RESERVED(PCS1G_ANEG_STATUS),
342 	REG_RESERVED(PCS1G_ANEG_NP_STATUS),
343 	REG_RESERVED(PCS1G_LINK_STATUS),
344 	REG_RESERVED(PCS1G_LINK_DOWN_CNT),
345 	REG_RESERVED(PCS1G_STICKY),
346 	REG_RESERVED(PCS1G_DEBUG_STATUS),
347 	REG_RESERVED(PCS1G_LPI_CFG),
348 	REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
349 	REG_RESERVED(PCS1G_LPI_STATUS),
350 	REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
351 	REG_RESERVED(PCS1G_TSTPAT_STATUS),
352 	REG_RESERVED(DEV_PCS_FX100_CFG),
353 	REG_RESERVED(DEV_PCS_FX100_STATUS),
354 };
355 
356 static const u32 *vsc9959_regmap[TARGET_MAX] = {
357 	[ANA]	= vsc9959_ana_regmap,
358 	[QS]	= vsc9959_qs_regmap,
359 	[QSYS]	= vsc9959_qsys_regmap,
360 	[REW]	= vsc9959_rew_regmap,
361 	[SYS]	= vsc9959_sys_regmap,
362 	[S2]	= vsc9959_s2_regmap,
363 	[PTP]	= vsc9959_ptp_regmap,
364 	[GCB]	= vsc9959_gcb_regmap,
365 	[DEV_GMII] = vsc9959_dev_gmii_regmap,
366 };
367 
368 /* Addresses are relative to the PCI device's base address */
369 static const struct resource vsc9959_target_io_res[TARGET_MAX] = {
370 	[ANA] = {
371 		.start	= 0x0280000,
372 		.end	= 0x028ffff,
373 		.name	= "ana",
374 	},
375 	[QS] = {
376 		.start	= 0x0080000,
377 		.end	= 0x00800ff,
378 		.name	= "qs",
379 	},
380 	[QSYS] = {
381 		.start	= 0x0200000,
382 		.end	= 0x021ffff,
383 		.name	= "qsys",
384 	},
385 	[REW] = {
386 		.start	= 0x0030000,
387 		.end	= 0x003ffff,
388 		.name	= "rew",
389 	},
390 	[SYS] = {
391 		.start	= 0x0010000,
392 		.end	= 0x001ffff,
393 		.name	= "sys",
394 	},
395 	[S2] = {
396 		.start	= 0x0060000,
397 		.end	= 0x00603ff,
398 		.name	= "s2",
399 	},
400 	[PTP] = {
401 		.start	= 0x0090000,
402 		.end	= 0x00900cb,
403 		.name	= "ptp",
404 	},
405 	[GCB] = {
406 		.start	= 0x0070000,
407 		.end	= 0x00701ff,
408 		.name	= "devcpu_gcb",
409 	},
410 };
411 
412 static const struct resource vsc9959_port_io_res[] = {
413 	{
414 		.start	= 0x0100000,
415 		.end	= 0x010ffff,
416 		.name	= "port0",
417 	},
418 	{
419 		.start	= 0x0110000,
420 		.end	= 0x011ffff,
421 		.name	= "port1",
422 	},
423 	{
424 		.start	= 0x0120000,
425 		.end	= 0x012ffff,
426 		.name	= "port2",
427 	},
428 	{
429 		.start	= 0x0130000,
430 		.end	= 0x013ffff,
431 		.name	= "port3",
432 	},
433 	{
434 		.start	= 0x0140000,
435 		.end	= 0x014ffff,
436 		.name	= "port4",
437 	},
438 	{
439 		.start	= 0x0150000,
440 		.end	= 0x015ffff,
441 		.name	= "port5",
442 	},
443 };
444 
445 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
446  * SGMII/QSGMII MAC PCS can be found.
447  */
448 static const struct resource vsc9959_imdio_res = {
449 	.start		= 0x8030,
450 	.end		= 0x8040,
451 	.name		= "imdio",
452 };
453 
454 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
455 	[ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
456 	[ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
457 	[ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
458 	[ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
459 	[ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
460 	[ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
461 	[ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
462 	[ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
463 	[ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
464 	[ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
465 	[ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
466 	[ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
467 	[ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
468 	[ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
469 	[ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
470 	[ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
471 	[ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
472 	[ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
473 	[ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
474 	[ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
475 	[ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
476 	[ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
477 	[ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
478 	[ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
479 	[ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
480 	[ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
481 	[ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
482 	[ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
483 	[ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
484 	[ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
485 	[ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
486 	[SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
487 	[GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
488 	/* Replicated per number of ports (7), register size 4 per port */
489 	[QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4),
490 	[QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4),
491 	[QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4),
492 	[QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4),
493 	[QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),
494 	[QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
495 	[SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4),
496 	[SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4),
497 	[SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),
498 	[SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
499 	[SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4),
500 	[SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4),
501 	[SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
502 };
503 
504 static const struct ocelot_stat_layout vsc9959_stats_layout[] = {
505 	{ .offset = 0x00,	.name = "rx_octets", },
506 	{ .offset = 0x01,	.name = "rx_unicast", },
507 	{ .offset = 0x02,	.name = "rx_multicast", },
508 	{ .offset = 0x03,	.name = "rx_broadcast", },
509 	{ .offset = 0x04,	.name = "rx_shorts", },
510 	{ .offset = 0x05,	.name = "rx_fragments", },
511 	{ .offset = 0x06,	.name = "rx_jabbers", },
512 	{ .offset = 0x07,	.name = "rx_crc_align_errs", },
513 	{ .offset = 0x08,	.name = "rx_sym_errs", },
514 	{ .offset = 0x09,	.name = "rx_frames_below_65_octets", },
515 	{ .offset = 0x0A,	.name = "rx_frames_65_to_127_octets", },
516 	{ .offset = 0x0B,	.name = "rx_frames_128_to_255_octets", },
517 	{ .offset = 0x0C,	.name = "rx_frames_256_to_511_octets", },
518 	{ .offset = 0x0D,	.name = "rx_frames_512_to_1023_octets", },
519 	{ .offset = 0x0E,	.name = "rx_frames_1024_to_1526_octets", },
520 	{ .offset = 0x0F,	.name = "rx_frames_over_1526_octets", },
521 	{ .offset = 0x10,	.name = "rx_pause", },
522 	{ .offset = 0x11,	.name = "rx_control", },
523 	{ .offset = 0x12,	.name = "rx_longs", },
524 	{ .offset = 0x13,	.name = "rx_classified_drops", },
525 	{ .offset = 0x14,	.name = "rx_red_prio_0", },
526 	{ .offset = 0x15,	.name = "rx_red_prio_1", },
527 	{ .offset = 0x16,	.name = "rx_red_prio_2", },
528 	{ .offset = 0x17,	.name = "rx_red_prio_3", },
529 	{ .offset = 0x18,	.name = "rx_red_prio_4", },
530 	{ .offset = 0x19,	.name = "rx_red_prio_5", },
531 	{ .offset = 0x1A,	.name = "rx_red_prio_6", },
532 	{ .offset = 0x1B,	.name = "rx_red_prio_7", },
533 	{ .offset = 0x1C,	.name = "rx_yellow_prio_0", },
534 	{ .offset = 0x1D,	.name = "rx_yellow_prio_1", },
535 	{ .offset = 0x1E,	.name = "rx_yellow_prio_2", },
536 	{ .offset = 0x1F,	.name = "rx_yellow_prio_3", },
537 	{ .offset = 0x20,	.name = "rx_yellow_prio_4", },
538 	{ .offset = 0x21,	.name = "rx_yellow_prio_5", },
539 	{ .offset = 0x22,	.name = "rx_yellow_prio_6", },
540 	{ .offset = 0x23,	.name = "rx_yellow_prio_7", },
541 	{ .offset = 0x24,	.name = "rx_green_prio_0", },
542 	{ .offset = 0x25,	.name = "rx_green_prio_1", },
543 	{ .offset = 0x26,	.name = "rx_green_prio_2", },
544 	{ .offset = 0x27,	.name = "rx_green_prio_3", },
545 	{ .offset = 0x28,	.name = "rx_green_prio_4", },
546 	{ .offset = 0x29,	.name = "rx_green_prio_5", },
547 	{ .offset = 0x2A,	.name = "rx_green_prio_6", },
548 	{ .offset = 0x2B,	.name = "rx_green_prio_7", },
549 	{ .offset = 0x80,	.name = "tx_octets", },
550 	{ .offset = 0x81,	.name = "tx_unicast", },
551 	{ .offset = 0x82,	.name = "tx_multicast", },
552 	{ .offset = 0x83,	.name = "tx_broadcast", },
553 	{ .offset = 0x84,	.name = "tx_collision", },
554 	{ .offset = 0x85,	.name = "tx_drops", },
555 	{ .offset = 0x86,	.name = "tx_pause", },
556 	{ .offset = 0x87,	.name = "tx_frames_below_65_octets", },
557 	{ .offset = 0x88,	.name = "tx_frames_65_to_127_octets", },
558 	{ .offset = 0x89,	.name = "tx_frames_128_255_octets", },
559 	{ .offset = 0x8B,	.name = "tx_frames_256_511_octets", },
560 	{ .offset = 0x8C,	.name = "tx_frames_1024_1526_octets", },
561 	{ .offset = 0x8D,	.name = "tx_frames_over_1526_octets", },
562 	{ .offset = 0x8E,	.name = "tx_yellow_prio_0", },
563 	{ .offset = 0x8F,	.name = "tx_yellow_prio_1", },
564 	{ .offset = 0x90,	.name = "tx_yellow_prio_2", },
565 	{ .offset = 0x91,	.name = "tx_yellow_prio_3", },
566 	{ .offset = 0x92,	.name = "tx_yellow_prio_4", },
567 	{ .offset = 0x93,	.name = "tx_yellow_prio_5", },
568 	{ .offset = 0x94,	.name = "tx_yellow_prio_6", },
569 	{ .offset = 0x95,	.name = "tx_yellow_prio_7", },
570 	{ .offset = 0x96,	.name = "tx_green_prio_0", },
571 	{ .offset = 0x97,	.name = "tx_green_prio_1", },
572 	{ .offset = 0x98,	.name = "tx_green_prio_2", },
573 	{ .offset = 0x99,	.name = "tx_green_prio_3", },
574 	{ .offset = 0x9A,	.name = "tx_green_prio_4", },
575 	{ .offset = 0x9B,	.name = "tx_green_prio_5", },
576 	{ .offset = 0x9C,	.name = "tx_green_prio_6", },
577 	{ .offset = 0x9D,	.name = "tx_green_prio_7", },
578 	{ .offset = 0x9E,	.name = "tx_aged", },
579 	{ .offset = 0x100,	.name = "drop_local", },
580 	{ .offset = 0x101,	.name = "drop_tail", },
581 	{ .offset = 0x102,	.name = "drop_yellow_prio_0", },
582 	{ .offset = 0x103,	.name = "drop_yellow_prio_1", },
583 	{ .offset = 0x104,	.name = "drop_yellow_prio_2", },
584 	{ .offset = 0x105,	.name = "drop_yellow_prio_3", },
585 	{ .offset = 0x106,	.name = "drop_yellow_prio_4", },
586 	{ .offset = 0x107,	.name = "drop_yellow_prio_5", },
587 	{ .offset = 0x108,	.name = "drop_yellow_prio_6", },
588 	{ .offset = 0x109,	.name = "drop_yellow_prio_7", },
589 	{ .offset = 0x10A,	.name = "drop_green_prio_0", },
590 	{ .offset = 0x10B,	.name = "drop_green_prio_1", },
591 	{ .offset = 0x10C,	.name = "drop_green_prio_2", },
592 	{ .offset = 0x10D,	.name = "drop_green_prio_3", },
593 	{ .offset = 0x10E,	.name = "drop_green_prio_4", },
594 	{ .offset = 0x10F,	.name = "drop_green_prio_5", },
595 	{ .offset = 0x110,	.name = "drop_green_prio_6", },
596 	{ .offset = 0x111,	.name = "drop_green_prio_7", },
597 };
598 
599 static struct vcap_field vsc9959_vcap_is2_keys[] = {
600 	/* Common: 41 bits */
601 	[VCAP_IS2_TYPE]				= {  0,   4},
602 	[VCAP_IS2_HK_FIRST]			= {  4,   1},
603 	[VCAP_IS2_HK_PAG]			= {  5,   8},
604 	[VCAP_IS2_HK_IGR_PORT_MASK]		= { 13,   7},
605 	[VCAP_IS2_HK_RSV2]			= { 20,   1},
606 	[VCAP_IS2_HK_HOST_MATCH]		= { 21,   1},
607 	[VCAP_IS2_HK_L2_MC]			= { 22,   1},
608 	[VCAP_IS2_HK_L2_BC]			= { 23,   1},
609 	[VCAP_IS2_HK_VLAN_TAGGED]		= { 24,   1},
610 	[VCAP_IS2_HK_VID]			= { 25,  12},
611 	[VCAP_IS2_HK_DEI]			= { 37,   1},
612 	[VCAP_IS2_HK_PCP]			= { 38,   3},
613 	/* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
614 	[VCAP_IS2_HK_L2_DMAC]			= { 41,  48},
615 	[VCAP_IS2_HK_L2_SMAC]			= { 89,  48},
616 	/* MAC_ETYPE (TYPE=000) */
617 	[VCAP_IS2_HK_MAC_ETYPE_ETYPE]		= {137,  16},
618 	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0]	= {153,  16},
619 	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1]	= {169,   8},
620 	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2]	= {177,   3},
621 	/* MAC_LLC (TYPE=001) */
622 	[VCAP_IS2_HK_MAC_LLC_L2_LLC]		= {137,  40},
623 	/* MAC_SNAP (TYPE=010) */
624 	[VCAP_IS2_HK_MAC_SNAP_L2_SNAP]		= {137,  40},
625 	/* MAC_ARP (TYPE=011) */
626 	[VCAP_IS2_HK_MAC_ARP_SMAC]		= { 41,  48},
627 	[VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK]	= { 89,   1},
628 	[VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK]	= { 90,   1},
629 	[VCAP_IS2_HK_MAC_ARP_LEN_OK]		= { 91,   1},
630 	[VCAP_IS2_HK_MAC_ARP_TARGET_MATCH]	= { 92,   1},
631 	[VCAP_IS2_HK_MAC_ARP_SENDER_MATCH]	= { 93,   1},
632 	[VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN]	= { 94,   1},
633 	[VCAP_IS2_HK_MAC_ARP_OPCODE]		= { 95,   2},
634 	[VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP]	= { 97,  32},
635 	[VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP]	= {129,  32},
636 	[VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP]	= {161,   1},
637 	/* IP4_TCP_UDP / IP4_OTHER common */
638 	[VCAP_IS2_HK_IP4]			= { 41,   1},
639 	[VCAP_IS2_HK_L3_FRAGMENT]		= { 42,   1},
640 	[VCAP_IS2_HK_L3_FRAG_OFS_GT0]		= { 43,   1},
641 	[VCAP_IS2_HK_L3_OPTIONS]		= { 44,   1},
642 	[VCAP_IS2_HK_IP4_L3_TTL_GT0]		= { 45,   1},
643 	[VCAP_IS2_HK_L3_TOS]			= { 46,   8},
644 	[VCAP_IS2_HK_L3_IP4_DIP]		= { 54,  32},
645 	[VCAP_IS2_HK_L3_IP4_SIP]		= { 86,  32},
646 	[VCAP_IS2_HK_DIP_EQ_SIP]		= {118,   1},
647 	/* IP4_TCP_UDP (TYPE=100) */
648 	[VCAP_IS2_HK_TCP]			= {119,   1},
649 	[VCAP_IS2_HK_L4_SPORT]			= {120,  16},
650 	[VCAP_IS2_HK_L4_DPORT]			= {136,  16},
651 	[VCAP_IS2_HK_L4_RNG]			= {152,   8},
652 	[VCAP_IS2_HK_L4_SPORT_EQ_DPORT]		= {160,   1},
653 	[VCAP_IS2_HK_L4_SEQUENCE_EQ0]		= {161,   1},
654 	[VCAP_IS2_HK_L4_URG]			= {162,   1},
655 	[VCAP_IS2_HK_L4_ACK]			= {163,   1},
656 	[VCAP_IS2_HK_L4_PSH]			= {164,   1},
657 	[VCAP_IS2_HK_L4_RST]			= {165,   1},
658 	[VCAP_IS2_HK_L4_SYN]			= {166,   1},
659 	[VCAP_IS2_HK_L4_FIN]			= {167,   1},
660 	[VCAP_IS2_HK_L4_1588_DOM]		= {168,   8},
661 	[VCAP_IS2_HK_L4_1588_VER]		= {176,   4},
662 	/* IP4_OTHER (TYPE=101) */
663 	[VCAP_IS2_HK_IP4_L3_PROTO]		= {119,   8},
664 	[VCAP_IS2_HK_L3_PAYLOAD]		= {127,  56},
665 	/* IP6_STD (TYPE=110) */
666 	[VCAP_IS2_HK_IP6_L3_TTL_GT0]		= { 41,   1},
667 	[VCAP_IS2_HK_L3_IP6_SIP]		= { 42, 128},
668 	[VCAP_IS2_HK_IP6_L3_PROTO]		= {170,   8},
669 	/* OAM (TYPE=111) */
670 	[VCAP_IS2_HK_OAM_MEL_FLAGS]		= {137,   7},
671 	[VCAP_IS2_HK_OAM_VER]			= {144,   5},
672 	[VCAP_IS2_HK_OAM_OPCODE]		= {149,   8},
673 	[VCAP_IS2_HK_OAM_FLAGS]			= {157,   8},
674 	[VCAP_IS2_HK_OAM_MEPID]			= {165,  16},
675 	[VCAP_IS2_HK_OAM_CCM_CNTS_EQ0]		= {181,   1},
676 	[VCAP_IS2_HK_OAM_IS_Y1731]		= {182,   1},
677 };
678 
679 static struct vcap_field vsc9959_vcap_is2_actions[] = {
680 	[VCAP_IS2_ACT_HIT_ME_ONCE]		= {  0,  1},
681 	[VCAP_IS2_ACT_CPU_COPY_ENA]		= {  1,  1},
682 	[VCAP_IS2_ACT_CPU_QU_NUM]		= {  2,  3},
683 	[VCAP_IS2_ACT_MASK_MODE]		= {  5,  2},
684 	[VCAP_IS2_ACT_MIRROR_ENA]		= {  7,  1},
685 	[VCAP_IS2_ACT_LRN_DIS]			= {  8,  1},
686 	[VCAP_IS2_ACT_POLICE_ENA]		= {  9,  1},
687 	[VCAP_IS2_ACT_POLICE_IDX]		= { 10,  9},
688 	[VCAP_IS2_ACT_POLICE_VCAP_ONLY]		= { 19,  1},
689 	[VCAP_IS2_ACT_PORT_MASK]		= { 20, 11},
690 	[VCAP_IS2_ACT_REW_OP]			= { 31,  9},
691 	[VCAP_IS2_ACT_SMAC_REPLACE_ENA]		= { 40,  1},
692 	[VCAP_IS2_ACT_RSV]			= { 41,  2},
693 	[VCAP_IS2_ACT_ACL_ID]			= { 43,  6},
694 	[VCAP_IS2_ACT_HIT_CNT]			= { 49, 32},
695 };
696 
697 static const struct vcap_props vsc9959_vcap_props[] = {
698 	[VCAP_IS2] = {
699 		.tg_width = 2,
700 		.sw_count = 4,
701 		.entry_count = VSC9959_VCAP_IS2_CNT,
702 		.entry_width = VSC9959_VCAP_IS2_ENTRY_WIDTH,
703 		.action_count = VSC9959_VCAP_IS2_CNT +
704 				VSC9959_VCAP_PORT_CNT + 2,
705 		.action_width = 89,
706 		.action_type_width = 1,
707 		.action_table = {
708 			[IS2_ACTION_TYPE_NORMAL] = {
709 				.width = 44,
710 				.count = 2
711 			},
712 			[IS2_ACTION_TYPE_SMAC_SIP] = {
713 				.width = 6,
714 				.count = 4
715 			},
716 		},
717 		.counter_words = 4,
718 		.counter_width = 32,
719 	},
720 };
721 
722 #define VSC9959_INIT_TIMEOUT			50000
723 #define VSC9959_GCB_RST_SLEEP			100
724 #define VSC9959_SYS_RAMINIT_SLEEP		80
725 
726 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
727 {
728 	int val;
729 
730 	regmap_field_read(ocelot->regfields[GCB_SOFT_RST_SWC_RST], &val);
731 
732 	return val;
733 }
734 
735 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
736 {
737 	return ocelot_read(ocelot, SYS_RAM_INIT);
738 }
739 
740 static int vsc9959_reset(struct ocelot *ocelot)
741 {
742 	int val, err;
743 
744 	/* soft-reset the switch core */
745 	regmap_field_write(ocelot->regfields[GCB_SOFT_RST_SWC_RST], 1);
746 
747 	err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
748 				 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
749 	if (err) {
750 		dev_err(ocelot->dev, "timeout: switch core reset\n");
751 		return err;
752 	}
753 
754 	/* initialize switch mem ~40us */
755 	ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
756 	err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
757 				 VSC9959_SYS_RAMINIT_SLEEP,
758 				 VSC9959_INIT_TIMEOUT);
759 	if (err) {
760 		dev_err(ocelot->dev, "timeout: switch sram init\n");
761 		return err;
762 	}
763 
764 	/* enable switch core */
765 	regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
766 
767 	return 0;
768 }
769 
770 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port,
771 				     unsigned long *supported,
772 				     struct phylink_link_state *state)
773 {
774 	struct ocelot_port *ocelot_port = ocelot->ports[port];
775 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
776 
777 	if (state->interface != PHY_INTERFACE_MODE_NA &&
778 	    state->interface != ocelot_port->phy_mode) {
779 		bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
780 		return;
781 	}
782 
783 	phylink_set_port_modes(mask);
784 	phylink_set(mask, Autoneg);
785 	phylink_set(mask, Pause);
786 	phylink_set(mask, Asym_Pause);
787 	phylink_set(mask, 10baseT_Half);
788 	phylink_set(mask, 10baseT_Full);
789 	phylink_set(mask, 100baseT_Half);
790 	phylink_set(mask, 100baseT_Full);
791 	phylink_set(mask, 1000baseT_Half);
792 	phylink_set(mask, 1000baseT_Full);
793 
794 	if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
795 	    state->interface == PHY_INTERFACE_MODE_2500BASEX ||
796 	    state->interface == PHY_INTERFACE_MODE_USXGMII) {
797 		phylink_set(mask, 2500baseT_Full);
798 		phylink_set(mask, 2500baseX_Full);
799 	}
800 
801 	bitmap_and(supported, supported, mask,
802 		   __ETHTOOL_LINK_MODE_MASK_NBITS);
803 	bitmap_and(state->advertising, state->advertising, mask,
804 		   __ETHTOOL_LINK_MODE_MASK_NBITS);
805 }
806 
807 static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port,
808 					phy_interface_t phy_mode)
809 {
810 	switch (phy_mode) {
811 	case PHY_INTERFACE_MODE_INTERNAL:
812 		if (port != 4 && port != 5)
813 			return -ENOTSUPP;
814 		return 0;
815 	case PHY_INTERFACE_MODE_SGMII:
816 	case PHY_INTERFACE_MODE_QSGMII:
817 	case PHY_INTERFACE_MODE_USXGMII:
818 	case PHY_INTERFACE_MODE_2500BASEX:
819 		/* Not supported on internal to-CPU ports */
820 		if (port == 4 || port == 5)
821 			return -ENOTSUPP;
822 		return 0;
823 	default:
824 		return -ENOTSUPP;
825 	}
826 }
827 
828 /* Watermark encode
829  * Bit 8:   Unit; 0:1, 1:16
830  * Bit 7-0: Value to be multiplied with unit
831  */
832 static u16 vsc9959_wm_enc(u16 value)
833 {
834 	if (value >= BIT(8))
835 		return BIT(8) | (value / 16);
836 
837 	return value;
838 }
839 
840 static const struct ocelot_ops vsc9959_ops = {
841 	.reset			= vsc9959_reset,
842 	.wm_enc			= vsc9959_wm_enc,
843 };
844 
845 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
846 {
847 	struct felix *felix = ocelot_to_felix(ocelot);
848 	struct enetc_mdio_priv *mdio_priv;
849 	struct device *dev = ocelot->dev;
850 	void __iomem *imdio_regs;
851 	struct resource res;
852 	struct enetc_hw *hw;
853 	struct mii_bus *bus;
854 	int port;
855 	int rc;
856 
857 	felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
858 				  sizeof(struct lynx_pcs *),
859 				  GFP_KERNEL);
860 	if (!felix->pcs) {
861 		dev_err(dev, "failed to allocate array for PCS PHYs\n");
862 		return -ENOMEM;
863 	}
864 
865 	memcpy(&res, felix->info->imdio_res, sizeof(res));
866 	res.flags = IORESOURCE_MEM;
867 	res.start += felix->imdio_base;
868 	res.end += felix->imdio_base;
869 
870 	imdio_regs = devm_ioremap_resource(dev, &res);
871 	if (IS_ERR(imdio_regs)) {
872 		dev_err(dev, "failed to map internal MDIO registers\n");
873 		return PTR_ERR(imdio_regs);
874 	}
875 
876 	hw = enetc_hw_alloc(dev, imdio_regs);
877 	if (IS_ERR(hw)) {
878 		dev_err(dev, "failed to allocate ENETC HW structure\n");
879 		return PTR_ERR(hw);
880 	}
881 
882 	bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
883 	if (!bus)
884 		return -ENOMEM;
885 
886 	bus->name = "VSC9959 internal MDIO bus";
887 	bus->read = enetc_mdio_read;
888 	bus->write = enetc_mdio_write;
889 	bus->parent = dev;
890 	mdio_priv = bus->priv;
891 	mdio_priv->hw = hw;
892 	/* This gets added to imdio_regs, which already maps addresses
893 	 * starting with the proper offset.
894 	 */
895 	mdio_priv->mdio_base = 0;
896 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
897 
898 	/* Needed in order to initialize the bus mutex lock */
899 	rc = mdiobus_register(bus);
900 	if (rc < 0) {
901 		dev_err(dev, "failed to register MDIO bus\n");
902 		return rc;
903 	}
904 
905 	felix->imdio = bus;
906 
907 	for (port = 0; port < felix->info->num_ports; port++) {
908 		struct ocelot_port *ocelot_port = ocelot->ports[port];
909 		struct mdio_device *pcs;
910 		struct lynx_pcs *lynx;
911 
912 		if (dsa_is_unused_port(felix->ds, port))
913 			continue;
914 
915 		if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
916 			continue;
917 
918 		pcs = mdio_device_create(felix->imdio, port);
919 		if (IS_ERR(pcs))
920 			continue;
921 
922 		lynx = lynx_pcs_create(pcs);
923 		if (!lynx) {
924 			mdio_device_free(pcs);
925 			continue;
926 		}
927 
928 		felix->pcs[port] = lynx;
929 
930 		dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
931 	}
932 
933 	return 0;
934 }
935 
936 void vsc9959_mdio_bus_free(struct ocelot *ocelot)
937 {
938 	struct felix *felix = ocelot_to_felix(ocelot);
939 	int port;
940 
941 	for (port = 0; port < ocelot->num_phys_ports; port++) {
942 		struct lynx_pcs *pcs = felix->pcs[port];
943 
944 		if (!pcs)
945 			continue;
946 
947 		mdio_device_free(pcs->mdio);
948 		lynx_pcs_destroy(pcs);
949 	}
950 	mdiobus_unregister(felix->imdio);
951 }
952 
953 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
954 				    u32 speed)
955 {
956 	ocelot_rmw_rix(ocelot,
957 		       QSYS_TAG_CONFIG_LINK_SPEED(speed),
958 		       QSYS_TAG_CONFIG_LINK_SPEED_M,
959 		       QSYS_TAG_CONFIG, port);
960 }
961 
962 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
963 				  u64 cycle_time,
964 				  struct timespec64 *new_base_ts)
965 {
966 	struct timespec64 ts;
967 	ktime_t new_base_time;
968 	ktime_t current_time;
969 
970 	ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
971 	current_time = timespec64_to_ktime(ts);
972 	new_base_time = base_time;
973 
974 	if (base_time < current_time) {
975 		u64 nr_of_cycles = current_time - base_time;
976 
977 		do_div(nr_of_cycles, cycle_time);
978 		new_base_time += cycle_time * (nr_of_cycles + 1);
979 	}
980 
981 	*new_base_ts = ktime_to_timespec64(new_base_time);
982 }
983 
984 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
985 {
986 	return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
987 }
988 
989 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
990 				struct tc_taprio_sched_entry *entry)
991 {
992 	ocelot_write(ocelot,
993 		     QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
994 		     QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
995 		     QSYS_GCL_CFG_REG_1);
996 	ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
997 }
998 
999 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1000 				    struct tc_taprio_qopt_offload *taprio)
1001 {
1002 	struct timespec64 base_ts;
1003 	int ret, i;
1004 	u32 val;
1005 
1006 	if (!taprio->enable) {
1007 		ocelot_rmw_rix(ocelot,
1008 			       QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF),
1009 			       QSYS_TAG_CONFIG_ENABLE |
1010 			       QSYS_TAG_CONFIG_INIT_GATE_STATE_M,
1011 			       QSYS_TAG_CONFIG, port);
1012 
1013 		return 0;
1014 	}
1015 
1016 	if (taprio->cycle_time > NSEC_PER_SEC ||
1017 	    taprio->cycle_time_extension >= NSEC_PER_SEC)
1018 		return -EINVAL;
1019 
1020 	if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX)
1021 		return -ERANGE;
1022 
1023 	ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1024 		   QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1025 		   QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1026 		   QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1027 		   QSYS_TAS_PARAM_CFG_CTRL);
1028 
1029 	/* Hardware errata -  Admin config could not be overwritten if
1030 	 * config is pending, need reset the TAS module
1031 	 */
1032 	val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1033 	if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING)
1034 		return  -EBUSY;
1035 
1036 	ocelot_rmw_rix(ocelot,
1037 		       QSYS_TAG_CONFIG_ENABLE |
1038 		       QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1039 		       QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1040 		       QSYS_TAG_CONFIG_ENABLE |
1041 		       QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1042 		       QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1043 		       QSYS_TAG_CONFIG, port);
1044 
1045 	vsc9959_new_base_time(ocelot, taprio->base_time,
1046 			      taprio->cycle_time, &base_ts);
1047 	ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1048 	ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1049 	val = upper_32_bits(base_ts.tv_sec);
1050 	ocelot_write(ocelot,
1051 		     QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1052 		     QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1053 		     QSYS_PARAM_CFG_REG_3);
1054 	ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1055 	ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1056 
1057 	for (i = 0; i < taprio->num_entries; i++)
1058 		vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1059 
1060 	ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1061 		   QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1062 		   QSYS_TAS_PARAM_CFG_CTRL);
1063 
1064 	ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1065 				 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
1066 				 10, 100000);
1067 
1068 	return ret;
1069 }
1070 
1071 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
1072 				    struct tc_cbs_qopt_offload *cbs_qopt)
1073 {
1074 	struct ocelot *ocelot = ds->priv;
1075 	int port_ix = port * 8 + cbs_qopt->queue;
1076 	u32 rate, burst;
1077 
1078 	if (cbs_qopt->queue >= ds->num_tx_queues)
1079 		return -EINVAL;
1080 
1081 	if (!cbs_qopt->enable) {
1082 		ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
1083 				 QSYS_CIR_CFG_CIR_BURST(0),
1084 				 QSYS_CIR_CFG, port_ix);
1085 
1086 		ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
1087 			       QSYS_SE_CFG, port_ix);
1088 
1089 		return 0;
1090 	}
1091 
1092 	/* Rate unit is 100 kbps */
1093 	rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
1094 	/* Avoid using zero rate */
1095 	rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
1096 	/* Burst unit is 4kB */
1097 	burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1098 	/* Avoid using zero burst size */
1099 	burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
1100 	ocelot_write_gix(ocelot,
1101 			 QSYS_CIR_CFG_CIR_RATE(rate) |
1102 			 QSYS_CIR_CFG_CIR_BURST(burst),
1103 			 QSYS_CIR_CFG,
1104 			 port_ix);
1105 
1106 	ocelot_rmw_gix(ocelot,
1107 		       QSYS_SE_CFG_SE_FRM_MODE(0) |
1108 		       QSYS_SE_CFG_SE_AVB_ENA,
1109 		       QSYS_SE_CFG_SE_AVB_ENA |
1110 		       QSYS_SE_CFG_SE_FRM_MODE_M,
1111 		       QSYS_SE_CFG,
1112 		       port_ix);
1113 
1114 	return 0;
1115 }
1116 
1117 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
1118 				 enum tc_setup_type type,
1119 				 void *type_data)
1120 {
1121 	struct ocelot *ocelot = ds->priv;
1122 
1123 	switch (type) {
1124 	case TC_SETUP_QDISC_TAPRIO:
1125 		return vsc9959_qos_port_tas_set(ocelot, port, type_data);
1126 	case TC_SETUP_QDISC_CBS:
1127 		return vsc9959_qos_port_cbs_set(ds, port, type_data);
1128 	default:
1129 		return -EOPNOTSUPP;
1130 	}
1131 }
1132 
1133 static void vsc9959_xmit_template_populate(struct ocelot *ocelot, int port)
1134 {
1135 	struct ocelot_port *ocelot_port = ocelot->ports[port];
1136 	u8 *template = ocelot_port->xmit_template;
1137 	u64 bypass, dest, src;
1138 
1139 	/* Set the source port as the CPU port module and not the
1140 	 * NPI port
1141 	 */
1142 	src = ocelot->num_phys_ports;
1143 	dest = BIT(port);
1144 	bypass = true;
1145 
1146 	packing(template, &bypass, 127, 127, OCELOT_TAG_LEN, PACK, 0);
1147 	packing(template, &dest,    68,  56, OCELOT_TAG_LEN, PACK, 0);
1148 	packing(template, &src,     46,  43, OCELOT_TAG_LEN, PACK, 0);
1149 }
1150 
1151 static const struct felix_info felix_info_vsc9959 = {
1152 	.target_io_res		= vsc9959_target_io_res,
1153 	.port_io_res		= vsc9959_port_io_res,
1154 	.imdio_res		= &vsc9959_imdio_res,
1155 	.regfields		= vsc9959_regfields,
1156 	.map			= vsc9959_regmap,
1157 	.ops			= &vsc9959_ops,
1158 	.stats_layout		= vsc9959_stats_layout,
1159 	.num_stats		= ARRAY_SIZE(vsc9959_stats_layout),
1160 	.vcap_is2_keys		= vsc9959_vcap_is2_keys,
1161 	.vcap_is2_actions	= vsc9959_vcap_is2_actions,
1162 	.vcap			= vsc9959_vcap_props,
1163 	.shared_queue_sz	= 128 * 1024,
1164 	.num_mact_rows		= 2048,
1165 	.num_ports		= 6,
1166 	.num_tx_queues		= FELIX_NUM_TC,
1167 	.switch_pci_bar		= 4,
1168 	.imdio_pci_bar		= 0,
1169 	.mdio_bus_alloc		= vsc9959_mdio_bus_alloc,
1170 	.mdio_bus_free		= vsc9959_mdio_bus_free,
1171 	.phylink_validate	= vsc9959_phylink_validate,
1172 	.prevalidate_phy_mode	= vsc9959_prevalidate_phy_mode,
1173 	.port_setup_tc          = vsc9959_port_setup_tc,
1174 	.port_sched_speed_set   = vsc9959_sched_speed_set,
1175 	.xmit_template_populate	= vsc9959_xmit_template_populate,
1176 };
1177 
1178 static irqreturn_t felix_irq_handler(int irq, void *data)
1179 {
1180 	struct ocelot *ocelot = (struct ocelot *)data;
1181 
1182 	/* The INTB interrupt is used for both PTP TX timestamp interrupt
1183 	 * and preemption status change interrupt on each port.
1184 	 *
1185 	 * - Get txtstamp if have
1186 	 * - TODO: handle preemption. Without handling it, driver may get
1187 	 *   interrupt storm.
1188 	 */
1189 
1190 	ocelot_get_txtstamp(ocelot);
1191 
1192 	return IRQ_HANDLED;
1193 }
1194 
1195 static int felix_pci_probe(struct pci_dev *pdev,
1196 			   const struct pci_device_id *id)
1197 {
1198 	struct dsa_switch *ds;
1199 	struct ocelot *ocelot;
1200 	struct felix *felix;
1201 	int err;
1202 
1203 	if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) {
1204 		dev_info(&pdev->dev, "device is disabled, skipping\n");
1205 		return -ENODEV;
1206 	}
1207 
1208 	err = pci_enable_device(pdev);
1209 	if (err) {
1210 		dev_err(&pdev->dev, "device enable failed\n");
1211 		goto err_pci_enable;
1212 	}
1213 
1214 	/* set up for high or low dma */
1215 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1216 	if (err) {
1217 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1218 		if (err) {
1219 			dev_err(&pdev->dev,
1220 				"DMA configuration failed: 0x%x\n", err);
1221 			goto err_dma;
1222 		}
1223 	}
1224 
1225 	felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
1226 	if (!felix) {
1227 		err = -ENOMEM;
1228 		dev_err(&pdev->dev, "Failed to allocate driver memory\n");
1229 		goto err_alloc_felix;
1230 	}
1231 
1232 	pci_set_drvdata(pdev, felix);
1233 	ocelot = &felix->ocelot;
1234 	ocelot->dev = &pdev->dev;
1235 	felix->info = &felix_info_vsc9959;
1236 	felix->switch_base = pci_resource_start(pdev,
1237 						felix->info->switch_pci_bar);
1238 	felix->imdio_base = pci_resource_start(pdev,
1239 					       felix->info->imdio_pci_bar);
1240 
1241 	pci_set_master(pdev);
1242 
1243 	err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL,
1244 					&felix_irq_handler, IRQF_ONESHOT,
1245 					"felix-intb", ocelot);
1246 	if (err) {
1247 		dev_err(&pdev->dev, "Failed to request irq\n");
1248 		goto err_alloc_irq;
1249 	}
1250 
1251 	ocelot->ptp = 1;
1252 
1253 	ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
1254 	if (!ds) {
1255 		err = -ENOMEM;
1256 		dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
1257 		goto err_alloc_ds;
1258 	}
1259 
1260 	ds->dev = &pdev->dev;
1261 	ds->num_ports = felix->info->num_ports;
1262 	ds->num_tx_queues = felix->info->num_tx_queues;
1263 	ds->ops = &felix_switch_ops;
1264 	ds->priv = ocelot;
1265 	felix->ds = ds;
1266 
1267 	err = dsa_register_switch(ds);
1268 	if (err) {
1269 		dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err);
1270 		goto err_register_ds;
1271 	}
1272 
1273 	return 0;
1274 
1275 err_register_ds:
1276 	kfree(ds);
1277 err_alloc_ds:
1278 err_alloc_irq:
1279 err_alloc_felix:
1280 	kfree(felix);
1281 err_dma:
1282 	pci_disable_device(pdev);
1283 err_pci_enable:
1284 	return err;
1285 }
1286 
1287 static void felix_pci_remove(struct pci_dev *pdev)
1288 {
1289 	struct felix *felix;
1290 
1291 	felix = pci_get_drvdata(pdev);
1292 
1293 	dsa_unregister_switch(felix->ds);
1294 
1295 	kfree(felix->ds);
1296 	kfree(felix);
1297 
1298 	pci_disable_device(pdev);
1299 }
1300 
1301 static struct pci_device_id felix_ids[] = {
1302 	{
1303 		/* NXP LS1028A */
1304 		PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
1305 	},
1306 	{ 0, }
1307 };
1308 MODULE_DEVICE_TABLE(pci, felix_ids);
1309 
1310 struct pci_driver felix_vsc9959_pci_driver = {
1311 	.name		= "mscc_felix",
1312 	.id_table	= felix_ids,
1313 	.probe		= felix_pci_probe,
1314 	.remove		= felix_pci_remove,
1315 };
1316