156051948SVladimir Oltean // SPDX-License-Identifier: (GPL-2.0 OR MIT) 256051948SVladimir Oltean /* Copyright 2017 Microsemi Corporation 356051948SVladimir Oltean * Copyright 2018-2019 NXP Semiconductors 456051948SVladimir Oltean */ 5bdeced75SVladimir Oltean #include <linux/fsl/enetc_mdio.h> 607d985eeSVladimir Oltean #include <soc/mscc/ocelot_vcap.h> 756051948SVladimir Oltean #include <soc/mscc/ocelot_sys.h> 856051948SVladimir Oltean #include <soc/mscc/ocelot.h> 956051948SVladimir Oltean #include <linux/iopoll.h> 1056051948SVladimir Oltean #include <linux/pci.h> 1156051948SVladimir Oltean #include "felix.h" 1256051948SVladimir Oltean 1307d985eeSVladimir Oltean #define VSC9959_VCAP_IS2_CNT 1024 1407d985eeSVladimir Oltean #define VSC9959_VCAP_IS2_ENTRY_WIDTH 376 1507d985eeSVladimir Oltean #define VSC9959_VCAP_PORT_CNT 6 1607d985eeSVladimir Oltean 17bdeced75SVladimir Oltean /* TODO: should find a better place for these */ 18bdeced75SVladimir Oltean #define USXGMII_BMCR_RESET BIT(15) 19bdeced75SVladimir Oltean #define USXGMII_BMCR_AN_EN BIT(12) 20bdeced75SVladimir Oltean #define USXGMII_BMCR_RST_AN BIT(9) 21bdeced75SVladimir Oltean #define USXGMII_BMSR_LNKS(status) (((status) & GENMASK(2, 2)) >> 2) 22bdeced75SVladimir Oltean #define USXGMII_BMSR_AN_CMPL(status) (((status) & GENMASK(5, 5)) >> 5) 23bdeced75SVladimir Oltean #define USXGMII_ADVERTISE_LNKS(x) (((x) << 15) & BIT(15)) 24bdeced75SVladimir Oltean #define USXGMII_ADVERTISE_FDX BIT(12) 25bdeced75SVladimir Oltean #define USXGMII_ADVERTISE_SPEED(x) (((x) << 9) & GENMASK(11, 9)) 26bdeced75SVladimir Oltean #define USXGMII_LPA_LNKS(lpa) ((lpa) >> 15) 27bdeced75SVladimir Oltean #define USXGMII_LPA_DUPLEX(lpa) (((lpa) & GENMASK(12, 12)) >> 12) 28bdeced75SVladimir Oltean #define USXGMII_LPA_SPEED(lpa) (((lpa) & GENMASK(11, 9)) >> 9) 29bdeced75SVladimir Oltean 30bdeced75SVladimir Oltean enum usxgmii_speed { 31bdeced75SVladimir Oltean USXGMII_SPEED_10 = 0, 32bdeced75SVladimir Oltean USXGMII_SPEED_100 = 1, 33bdeced75SVladimir Oltean USXGMII_SPEED_1000 = 2, 34bdeced75SVladimir Oltean USXGMII_SPEED_2500 = 4, 35bdeced75SVladimir Oltean }; 36bdeced75SVladimir Oltean 3756051948SVladimir Oltean static const u32 vsc9959_ana_regmap[] = { 3856051948SVladimir Oltean REG(ANA_ADVLEARN, 0x0089a0), 3956051948SVladimir Oltean REG(ANA_VLANMASK, 0x0089a4), 4056051948SVladimir Oltean REG_RESERVED(ANA_PORT_B_DOMAIN), 4156051948SVladimir Oltean REG(ANA_ANAGEFIL, 0x0089ac), 4256051948SVladimir Oltean REG(ANA_ANEVENTS, 0x0089b0), 4356051948SVladimir Oltean REG(ANA_STORMLIMIT_BURST, 0x0089b4), 4456051948SVladimir Oltean REG(ANA_STORMLIMIT_CFG, 0x0089b8), 4556051948SVladimir Oltean REG(ANA_ISOLATED_PORTS, 0x0089c8), 4656051948SVladimir Oltean REG(ANA_COMMUNITY_PORTS, 0x0089cc), 4756051948SVladimir Oltean REG(ANA_AUTOAGE, 0x0089d0), 4856051948SVladimir Oltean REG(ANA_MACTOPTIONS, 0x0089d4), 4956051948SVladimir Oltean REG(ANA_LEARNDISC, 0x0089d8), 5056051948SVladimir Oltean REG(ANA_AGENCTRL, 0x0089dc), 5156051948SVladimir Oltean REG(ANA_MIRRORPORTS, 0x0089e0), 5256051948SVladimir Oltean REG(ANA_EMIRRORPORTS, 0x0089e4), 5356051948SVladimir Oltean REG(ANA_FLOODING, 0x0089e8), 5456051948SVladimir Oltean REG(ANA_FLOODING_IPMC, 0x008a08), 5556051948SVladimir Oltean REG(ANA_SFLOW_CFG, 0x008a0c), 5656051948SVladimir Oltean REG(ANA_PORT_MODE, 0x008a28), 5756051948SVladimir Oltean REG(ANA_CUT_THRU_CFG, 0x008a48), 5856051948SVladimir Oltean REG(ANA_PGID_PGID, 0x008400), 5956051948SVladimir Oltean REG(ANA_TABLES_ANMOVED, 0x007f1c), 6056051948SVladimir Oltean REG(ANA_TABLES_MACHDATA, 0x007f20), 6156051948SVladimir Oltean REG(ANA_TABLES_MACLDATA, 0x007f24), 6256051948SVladimir Oltean REG(ANA_TABLES_STREAMDATA, 0x007f28), 6356051948SVladimir Oltean REG(ANA_TABLES_MACACCESS, 0x007f2c), 6456051948SVladimir Oltean REG(ANA_TABLES_MACTINDX, 0x007f30), 6556051948SVladimir Oltean REG(ANA_TABLES_VLANACCESS, 0x007f34), 6656051948SVladimir Oltean REG(ANA_TABLES_VLANTIDX, 0x007f38), 6756051948SVladimir Oltean REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 6856051948SVladimir Oltean REG(ANA_TABLES_ISDXTIDX, 0x007f40), 6956051948SVladimir Oltean REG(ANA_TABLES_ENTRYLIM, 0x007f00), 7056051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 7156051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 7256051948SVladimir Oltean REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 7356051948SVladimir Oltean REG(ANA_TABLES_STREAMTIDX, 0x007f50), 7456051948SVladimir Oltean REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 7556051948SVladimir Oltean REG(ANA_TABLES_SEQ_MASK, 0x007f58), 7656051948SVladimir Oltean REG(ANA_TABLES_SFID_MASK, 0x007f5c), 7756051948SVladimir Oltean REG(ANA_TABLES_SFIDACCESS, 0x007f60), 7856051948SVladimir Oltean REG(ANA_TABLES_SFIDTIDX, 0x007f64), 7956051948SVladimir Oltean REG(ANA_MSTI_STATE, 0x008600), 8056051948SVladimir Oltean REG(ANA_OAM_UPM_LM_CNT, 0x008000), 8156051948SVladimir Oltean REG(ANA_SG_ACCESS_CTRL, 0x008a64), 8256051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 8356051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 8456051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 8556051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 8656051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 8756051948SVladimir Oltean REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 8856051948SVladimir Oltean REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 8956051948SVladimir Oltean REG(ANA_SG_STATUS_REG_1, 0x008980), 9056051948SVladimir Oltean REG(ANA_SG_STATUS_REG_2, 0x008984), 9156051948SVladimir Oltean REG(ANA_SG_STATUS_REG_3, 0x008988), 9256051948SVladimir Oltean REG(ANA_PORT_VLAN_CFG, 0x007800), 9356051948SVladimir Oltean REG(ANA_PORT_DROP_CFG, 0x007804), 9456051948SVladimir Oltean REG(ANA_PORT_QOS_CFG, 0x007808), 9556051948SVladimir Oltean REG(ANA_PORT_VCAP_CFG, 0x00780c), 9656051948SVladimir Oltean REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 9756051948SVladimir Oltean REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 9856051948SVladimir Oltean REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 9956051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 10056051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 10156051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 10256051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 10356051948SVladimir Oltean REG(ANA_PORT_PORT_CFG, 0x007870), 10456051948SVladimir Oltean REG(ANA_PORT_POL_CFG, 0x007874), 10556051948SVladimir Oltean REG(ANA_PORT_PTP_CFG, 0x007878), 10656051948SVladimir Oltean REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 10756051948SVladimir Oltean REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 10856051948SVladimir Oltean REG(ANA_PORT_SFID_CFG, 0x007884), 10956051948SVladimir Oltean REG(ANA_PFC_PFC_CFG, 0x008800), 11056051948SVladimir Oltean REG_RESERVED(ANA_PFC_PFC_TIMER), 11156051948SVladimir Oltean REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 11256051948SVladimir Oltean REG_RESERVED(ANA_IPT_IPT), 11356051948SVladimir Oltean REG_RESERVED(ANA_PPT_PPT), 11456051948SVladimir Oltean REG_RESERVED(ANA_FID_MAP_FID_MAP), 11556051948SVladimir Oltean REG(ANA_AGGR_CFG, 0x008a68), 11656051948SVladimir Oltean REG(ANA_CPUQ_CFG, 0x008a6c), 11756051948SVladimir Oltean REG_RESERVED(ANA_CPUQ_CFG2), 11856051948SVladimir Oltean REG(ANA_CPUQ_8021_CFG, 0x008a74), 11956051948SVladimir Oltean REG(ANA_DSCP_CFG, 0x008ab4), 12056051948SVladimir Oltean REG(ANA_DSCP_REWR_CFG, 0x008bb4), 12156051948SVladimir Oltean REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 12256051948SVladimir Oltean REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 12356051948SVladimir Oltean REG_RESERVED(ANA_VRAP_CFG), 12456051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_DATA), 12556051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_MASK), 12656051948SVladimir Oltean REG(ANA_DISCARD_CFG, 0x008c40), 12756051948SVladimir Oltean REG(ANA_FID_CFG, 0x008c44), 12856051948SVladimir Oltean REG(ANA_POL_PIR_CFG, 0x004000), 12956051948SVladimir Oltean REG(ANA_POL_CIR_CFG, 0x004004), 13056051948SVladimir Oltean REG(ANA_POL_MODE_CFG, 0x004008), 13156051948SVladimir Oltean REG(ANA_POL_PIR_STATE, 0x00400c), 13256051948SVladimir Oltean REG(ANA_POL_CIR_STATE, 0x004010), 13356051948SVladimir Oltean REG_RESERVED(ANA_POL_STATE), 13456051948SVladimir Oltean REG(ANA_POL_FLOWC, 0x008c48), 13556051948SVladimir Oltean REG(ANA_POL_HYST, 0x008cb4), 13656051948SVladimir Oltean REG_RESERVED(ANA_POL_MISC_CFG), 13756051948SVladimir Oltean }; 13856051948SVladimir Oltean 13956051948SVladimir Oltean static const u32 vsc9959_qs_regmap[] = { 14056051948SVladimir Oltean REG(QS_XTR_GRP_CFG, 0x000000), 14156051948SVladimir Oltean REG(QS_XTR_RD, 0x000008), 14256051948SVladimir Oltean REG(QS_XTR_FRM_PRUNING, 0x000010), 14356051948SVladimir Oltean REG(QS_XTR_FLUSH, 0x000018), 14456051948SVladimir Oltean REG(QS_XTR_DATA_PRESENT, 0x00001c), 14556051948SVladimir Oltean REG(QS_XTR_CFG, 0x000020), 14656051948SVladimir Oltean REG(QS_INJ_GRP_CFG, 0x000024), 14756051948SVladimir Oltean REG(QS_INJ_WR, 0x00002c), 14856051948SVladimir Oltean REG(QS_INJ_CTRL, 0x000034), 14956051948SVladimir Oltean REG(QS_INJ_STATUS, 0x00003c), 15056051948SVladimir Oltean REG(QS_INJ_ERR, 0x000040), 15156051948SVladimir Oltean REG_RESERVED(QS_INH_DBG), 15256051948SVladimir Oltean }; 15356051948SVladimir Oltean 15456051948SVladimir Oltean static const u32 vsc9959_s2_regmap[] = { 15556051948SVladimir Oltean REG(S2_CORE_UPDATE_CTRL, 0x000000), 15656051948SVladimir Oltean REG(S2_CORE_MV_CFG, 0x000004), 15756051948SVladimir Oltean REG(S2_CACHE_ENTRY_DAT, 0x000008), 15856051948SVladimir Oltean REG(S2_CACHE_MASK_DAT, 0x000108), 15956051948SVladimir Oltean REG(S2_CACHE_ACTION_DAT, 0x000208), 16056051948SVladimir Oltean REG(S2_CACHE_CNT_DAT, 0x000308), 16156051948SVladimir Oltean REG(S2_CACHE_TG_DAT, 0x000388), 16256051948SVladimir Oltean }; 16356051948SVladimir Oltean 16456051948SVladimir Oltean static const u32 vsc9959_qsys_regmap[] = { 16556051948SVladimir Oltean REG(QSYS_PORT_MODE, 0x00f460), 16656051948SVladimir Oltean REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 16756051948SVladimir Oltean REG(QSYS_STAT_CNT_CFG, 0x00f49c), 16856051948SVladimir Oltean REG(QSYS_EEE_CFG, 0x00f4a0), 16956051948SVladimir Oltean REG(QSYS_EEE_THRES, 0x00f4b8), 17056051948SVladimir Oltean REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 17156051948SVladimir Oltean REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 17256051948SVladimir Oltean REG(QSYS_SW_STATUS, 0x00f4c4), 17356051948SVladimir Oltean REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 17456051948SVladimir Oltean REG_RESERVED(QSYS_PAD_CFG), 17556051948SVladimir Oltean REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 17656051948SVladimir Oltean REG_RESERVED(QSYS_QMAP), 17756051948SVladimir Oltean REG_RESERVED(QSYS_ISDX_SGRP), 17856051948SVladimir Oltean REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 17956051948SVladimir Oltean REG(QSYS_TFRM_MISC, 0x00f50c), 18056051948SVladimir Oltean REG(QSYS_TFRM_PORT_DLY, 0x00f510), 18156051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 18256051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 18356051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 18456051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 18556051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 18656051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 18756051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 18856051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 18956051948SVladimir Oltean REG(QSYS_RED_PROFILE, 0x00f534), 19056051948SVladimir Oltean REG(QSYS_RES_QOS_MODE, 0x00f574), 19156051948SVladimir Oltean REG(QSYS_RES_CFG, 0x00c000), 19256051948SVladimir Oltean REG(QSYS_RES_STAT, 0x00c004), 19356051948SVladimir Oltean REG(QSYS_EGR_DROP_MODE, 0x00f578), 19456051948SVladimir Oltean REG(QSYS_EQ_CTRL, 0x00f57c), 19556051948SVladimir Oltean REG_RESERVED(QSYS_EVENTS_CORE), 19656051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 19756051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 19856051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 19956051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 20056051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 20156051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 20256051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 20356051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 20456051948SVladimir Oltean REG(QSYS_PREEMPTION_CFG, 0x00f664), 20556051948SVladimir Oltean REG_RESERVED(QSYS_CIR_CFG), 20656051948SVladimir Oltean REG(QSYS_EIR_CFG, 0x000004), 20756051948SVladimir Oltean REG(QSYS_SE_CFG, 0x000008), 20856051948SVladimir Oltean REG(QSYS_SE_DWRR_CFG, 0x00000c), 20956051948SVladimir Oltean REG_RESERVED(QSYS_SE_CONNECT), 21056051948SVladimir Oltean REG(QSYS_SE_DLB_SENSE, 0x000040), 21156051948SVladimir Oltean REG(QSYS_CIR_STATE, 0x000044), 21256051948SVladimir Oltean REG(QSYS_EIR_STATE, 0x000048), 21356051948SVladimir Oltean REG_RESERVED(QSYS_SE_STATE), 21456051948SVladimir Oltean REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 21556051948SVladimir Oltean REG(QSYS_TAG_CONFIG, 0x00f680), 21656051948SVladimir Oltean REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 21756051948SVladimir Oltean REG(QSYS_PORT_MAX_SDU, 0x00f69c), 21856051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 21956051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 22056051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 22156051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 22256051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 22356051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_1, 0x00f454), 22456051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_2, 0x00f458), 22556051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 22656051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 22756051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 22856051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 22956051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 23056051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 23156051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 23256051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 23356051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 23456051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 23556051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 23656051948SVladimir Oltean }; 23756051948SVladimir Oltean 23856051948SVladimir Oltean static const u32 vsc9959_rew_regmap[] = { 23956051948SVladimir Oltean REG(REW_PORT_VLAN_CFG, 0x000000), 24056051948SVladimir Oltean REG(REW_TAG_CFG, 0x000004), 24156051948SVladimir Oltean REG(REW_PORT_CFG, 0x000008), 24256051948SVladimir Oltean REG(REW_DSCP_CFG, 0x00000c), 24356051948SVladimir Oltean REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 24456051948SVladimir Oltean REG(REW_PTP_CFG, 0x000050), 24556051948SVladimir Oltean REG(REW_PTP_DLY1_CFG, 0x000054), 24656051948SVladimir Oltean REG(REW_RED_TAG_CFG, 0x000058), 24756051948SVladimir Oltean REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 24856051948SVladimir Oltean REG(REW_DSCP_REMAP_CFG, 0x000510), 24956051948SVladimir Oltean REG_RESERVED(REW_STAT_CFG), 25056051948SVladimir Oltean REG_RESERVED(REW_REW_STICKY), 25156051948SVladimir Oltean REG_RESERVED(REW_PPT), 25256051948SVladimir Oltean }; 25356051948SVladimir Oltean 25456051948SVladimir Oltean static const u32 vsc9959_sys_regmap[] = { 25556051948SVladimir Oltean REG(SYS_COUNT_RX_OCTETS, 0x000000), 25656051948SVladimir Oltean REG(SYS_COUNT_RX_MULTICAST, 0x000008), 25756051948SVladimir Oltean REG(SYS_COUNT_RX_SHORTS, 0x000010), 25856051948SVladimir Oltean REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 25956051948SVladimir Oltean REG(SYS_COUNT_RX_JABBERS, 0x000018), 26056051948SVladimir Oltean REG(SYS_COUNT_RX_64, 0x000024), 26156051948SVladimir Oltean REG(SYS_COUNT_RX_65_127, 0x000028), 26256051948SVladimir Oltean REG(SYS_COUNT_RX_128_255, 0x00002c), 26356051948SVladimir Oltean REG(SYS_COUNT_RX_256_1023, 0x000030), 26456051948SVladimir Oltean REG(SYS_COUNT_RX_1024_1526, 0x000034), 26556051948SVladimir Oltean REG(SYS_COUNT_RX_1527_MAX, 0x000038), 26656051948SVladimir Oltean REG(SYS_COUNT_RX_LONGS, 0x000044), 26756051948SVladimir Oltean REG(SYS_COUNT_TX_OCTETS, 0x000200), 26856051948SVladimir Oltean REG(SYS_COUNT_TX_COLLISION, 0x000210), 26956051948SVladimir Oltean REG(SYS_COUNT_TX_DROPS, 0x000214), 27056051948SVladimir Oltean REG(SYS_COUNT_TX_64, 0x00021c), 27156051948SVladimir Oltean REG(SYS_COUNT_TX_65_127, 0x000220), 27256051948SVladimir Oltean REG(SYS_COUNT_TX_128_511, 0x000224), 27356051948SVladimir Oltean REG(SYS_COUNT_TX_512_1023, 0x000228), 27456051948SVladimir Oltean REG(SYS_COUNT_TX_1024_1526, 0x00022c), 27556051948SVladimir Oltean REG(SYS_COUNT_TX_1527_MAX, 0x000230), 27656051948SVladimir Oltean REG(SYS_COUNT_TX_AGING, 0x000278), 27756051948SVladimir Oltean REG(SYS_RESET_CFG, 0x000e00), 27856051948SVladimir Oltean REG(SYS_SR_ETYPE_CFG, 0x000e04), 27956051948SVladimir Oltean REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 28056051948SVladimir Oltean REG(SYS_PORT_MODE, 0x000e0c), 28156051948SVladimir Oltean REG(SYS_FRONT_PORT_MODE, 0x000e2c), 28256051948SVladimir Oltean REG(SYS_FRM_AGING, 0x000e44), 28356051948SVladimir Oltean REG(SYS_STAT_CFG, 0x000e48), 28456051948SVladimir Oltean REG(SYS_SW_STATUS, 0x000e4c), 28556051948SVladimir Oltean REG_RESERVED(SYS_MISC_CFG), 28656051948SVladimir Oltean REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 28756051948SVladimir Oltean REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 28856051948SVladimir Oltean REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 28956051948SVladimir Oltean REG(SYS_PAUSE_CFG, 0x000ea0), 29056051948SVladimir Oltean REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 29156051948SVladimir Oltean REG(SYS_ATOP, 0x000ec0), 29256051948SVladimir Oltean REG(SYS_ATOP_TOT_CFG, 0x000edc), 29356051948SVladimir Oltean REG(SYS_MAC_FC_CFG, 0x000ee0), 29456051948SVladimir Oltean REG(SYS_MMGT, 0x000ef8), 29556051948SVladimir Oltean REG_RESERVED(SYS_MMGT_FAST), 29656051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_DIF), 29756051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_CORE), 29856051948SVladimir Oltean REG_RESERVED(SYS_CNT), 29956051948SVladimir Oltean REG(SYS_PTP_STATUS, 0x000f14), 30056051948SVladimir Oltean REG(SYS_PTP_TXSTAMP, 0x000f18), 30156051948SVladimir Oltean REG(SYS_PTP_NXT, 0x000f1c), 30256051948SVladimir Oltean REG(SYS_PTP_CFG, 0x000f20), 30356051948SVladimir Oltean REG(SYS_RAM_INIT, 0x000f24), 30456051948SVladimir Oltean REG_RESERVED(SYS_CM_ADDR), 30556051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_WR), 30656051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_RD), 30756051948SVladimir Oltean REG_RESERVED(SYS_CM_OP), 30856051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA), 30956051948SVladimir Oltean }; 31056051948SVladimir Oltean 3115df66c48SYangbo Lu static const u32 vsc9959_ptp_regmap[] = { 3125df66c48SYangbo Lu REG(PTP_PIN_CFG, 0x000000), 3135df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 3145df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 3155df66c48SYangbo Lu REG(PTP_PIN_TOD_NSEC, 0x00000c), 3165df66c48SYangbo Lu REG(PTP_CFG_MISC, 0x0000a0), 3175df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 3185df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 3195df66c48SYangbo Lu }; 3205df66c48SYangbo Lu 32156051948SVladimir Oltean static const u32 vsc9959_gcb_regmap[] = { 32256051948SVladimir Oltean REG(GCB_SOFT_RST, 0x000004), 32356051948SVladimir Oltean }; 32456051948SVladimir Oltean 32556051948SVladimir Oltean static const u32 *vsc9959_regmap[] = { 32656051948SVladimir Oltean [ANA] = vsc9959_ana_regmap, 32756051948SVladimir Oltean [QS] = vsc9959_qs_regmap, 32856051948SVladimir Oltean [QSYS] = vsc9959_qsys_regmap, 32956051948SVladimir Oltean [REW] = vsc9959_rew_regmap, 33056051948SVladimir Oltean [SYS] = vsc9959_sys_regmap, 33156051948SVladimir Oltean [S2] = vsc9959_s2_regmap, 3325df66c48SYangbo Lu [PTP] = vsc9959_ptp_regmap, 33356051948SVladimir Oltean [GCB] = vsc9959_gcb_regmap, 33456051948SVladimir Oltean }; 33556051948SVladimir Oltean 336*b4024c9eSClaudiu Manoil /* Addresses are relative to the PCI device's base address */ 337*b4024c9eSClaudiu Manoil static const struct resource vsc9959_target_io_res[] = { 33856051948SVladimir Oltean [ANA] = { 33956051948SVladimir Oltean .start = 0x0280000, 34056051948SVladimir Oltean .end = 0x028ffff, 34156051948SVladimir Oltean .name = "ana", 34256051948SVladimir Oltean }, 34356051948SVladimir Oltean [QS] = { 34456051948SVladimir Oltean .start = 0x0080000, 34556051948SVladimir Oltean .end = 0x00800ff, 34656051948SVladimir Oltean .name = "qs", 34756051948SVladimir Oltean }, 34856051948SVladimir Oltean [QSYS] = { 34956051948SVladimir Oltean .start = 0x0200000, 35056051948SVladimir Oltean .end = 0x021ffff, 35156051948SVladimir Oltean .name = "qsys", 35256051948SVladimir Oltean }, 35356051948SVladimir Oltean [REW] = { 35456051948SVladimir Oltean .start = 0x0030000, 35556051948SVladimir Oltean .end = 0x003ffff, 35656051948SVladimir Oltean .name = "rew", 35756051948SVladimir Oltean }, 35856051948SVladimir Oltean [SYS] = { 35956051948SVladimir Oltean .start = 0x0010000, 36056051948SVladimir Oltean .end = 0x001ffff, 36156051948SVladimir Oltean .name = "sys", 36256051948SVladimir Oltean }, 36356051948SVladimir Oltean [S2] = { 36456051948SVladimir Oltean .start = 0x0060000, 36556051948SVladimir Oltean .end = 0x00603ff, 36656051948SVladimir Oltean .name = "s2", 36756051948SVladimir Oltean }, 3685df66c48SYangbo Lu [PTP] = { 3695df66c48SYangbo Lu .start = 0x0090000, 3705df66c48SYangbo Lu .end = 0x00900cb, 3715df66c48SYangbo Lu .name = "ptp", 3725df66c48SYangbo Lu }, 37356051948SVladimir Oltean [GCB] = { 37456051948SVladimir Oltean .start = 0x0070000, 37556051948SVladimir Oltean .end = 0x00701ff, 37656051948SVladimir Oltean .name = "devcpu_gcb", 37756051948SVladimir Oltean }, 37856051948SVladimir Oltean }; 37956051948SVladimir Oltean 380*b4024c9eSClaudiu Manoil static const struct resource vsc9959_port_io_res[] = { 38156051948SVladimir Oltean { 38256051948SVladimir Oltean .start = 0x0100000, 38356051948SVladimir Oltean .end = 0x010ffff, 38456051948SVladimir Oltean .name = "port0", 38556051948SVladimir Oltean }, 38656051948SVladimir Oltean { 38756051948SVladimir Oltean .start = 0x0110000, 38856051948SVladimir Oltean .end = 0x011ffff, 38956051948SVladimir Oltean .name = "port1", 39056051948SVladimir Oltean }, 39156051948SVladimir Oltean { 39256051948SVladimir Oltean .start = 0x0120000, 39356051948SVladimir Oltean .end = 0x012ffff, 39456051948SVladimir Oltean .name = "port2", 39556051948SVladimir Oltean }, 39656051948SVladimir Oltean { 39756051948SVladimir Oltean .start = 0x0130000, 39856051948SVladimir Oltean .end = 0x013ffff, 39956051948SVladimir Oltean .name = "port3", 40056051948SVladimir Oltean }, 40156051948SVladimir Oltean { 40256051948SVladimir Oltean .start = 0x0140000, 40356051948SVladimir Oltean .end = 0x014ffff, 40456051948SVladimir Oltean .name = "port4", 40556051948SVladimir Oltean }, 40656051948SVladimir Oltean { 40756051948SVladimir Oltean .start = 0x0150000, 40856051948SVladimir Oltean .end = 0x015ffff, 40956051948SVladimir Oltean .name = "port5", 41056051948SVladimir Oltean }, 41156051948SVladimir Oltean }; 41256051948SVladimir Oltean 413bdeced75SVladimir Oltean /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 414bdeced75SVladimir Oltean * SGMII/QSGMII MAC PCS can be found. 415bdeced75SVladimir Oltean */ 416*b4024c9eSClaudiu Manoil static const struct resource vsc9959_imdio_res = { 417bdeced75SVladimir Oltean .start = 0x8030, 418bdeced75SVladimir Oltean .end = 0x8040, 419bdeced75SVladimir Oltean .name = "imdio", 420bdeced75SVladimir Oltean }; 421bdeced75SVladimir Oltean 42256051948SVladimir Oltean static const struct reg_field vsc9959_regfields[] = { 42356051948SVladimir Oltean [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 42456051948SVladimir Oltean [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 42556051948SVladimir Oltean [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 42656051948SVladimir Oltean [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 42756051948SVladimir Oltean [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 42856051948SVladimir Oltean [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 42956051948SVladimir Oltean [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 43056051948SVladimir Oltean [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 43156051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 43256051948SVladimir Oltean [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 43356051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 43456051948SVladimir Oltean [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 43556051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 43656051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 43756051948SVladimir Oltean [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 43856051948SVladimir Oltean [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 43956051948SVladimir Oltean [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 44056051948SVladimir Oltean [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 44156051948SVladimir Oltean [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 44256051948SVladimir Oltean [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 44356051948SVladimir Oltean [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 44456051948SVladimir Oltean [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 44556051948SVladimir Oltean [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 44656051948SVladimir Oltean [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 44756051948SVladimir Oltean [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 44856051948SVladimir Oltean [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 44956051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 45056051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 45156051948SVladimir Oltean [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 45256051948SVladimir Oltean [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 45356051948SVladimir Oltean [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 45456051948SVladimir Oltean [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 45556051948SVladimir Oltean [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 45656051948SVladimir Oltean }; 45756051948SVladimir Oltean 45856051948SVladimir Oltean static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 45956051948SVladimir Oltean { .offset = 0x00, .name = "rx_octets", }, 46056051948SVladimir Oltean { .offset = 0x01, .name = "rx_unicast", }, 46156051948SVladimir Oltean { .offset = 0x02, .name = "rx_multicast", }, 46256051948SVladimir Oltean { .offset = 0x03, .name = "rx_broadcast", }, 46356051948SVladimir Oltean { .offset = 0x04, .name = "rx_shorts", }, 46456051948SVladimir Oltean { .offset = 0x05, .name = "rx_fragments", }, 46556051948SVladimir Oltean { .offset = 0x06, .name = "rx_jabbers", }, 46656051948SVladimir Oltean { .offset = 0x07, .name = "rx_crc_align_errs", }, 46756051948SVladimir Oltean { .offset = 0x08, .name = "rx_sym_errs", }, 46856051948SVladimir Oltean { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 46956051948SVladimir Oltean { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 47056051948SVladimir Oltean { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 47156051948SVladimir Oltean { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 47256051948SVladimir Oltean { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 47356051948SVladimir Oltean { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 47456051948SVladimir Oltean { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 47556051948SVladimir Oltean { .offset = 0x10, .name = "rx_pause", }, 47656051948SVladimir Oltean { .offset = 0x11, .name = "rx_control", }, 47756051948SVladimir Oltean { .offset = 0x12, .name = "rx_longs", }, 47856051948SVladimir Oltean { .offset = 0x13, .name = "rx_classified_drops", }, 47956051948SVladimir Oltean { .offset = 0x14, .name = "rx_red_prio_0", }, 48056051948SVladimir Oltean { .offset = 0x15, .name = "rx_red_prio_1", }, 48156051948SVladimir Oltean { .offset = 0x16, .name = "rx_red_prio_2", }, 48256051948SVladimir Oltean { .offset = 0x17, .name = "rx_red_prio_3", }, 48356051948SVladimir Oltean { .offset = 0x18, .name = "rx_red_prio_4", }, 48456051948SVladimir Oltean { .offset = 0x19, .name = "rx_red_prio_5", }, 48556051948SVladimir Oltean { .offset = 0x1A, .name = "rx_red_prio_6", }, 48656051948SVladimir Oltean { .offset = 0x1B, .name = "rx_red_prio_7", }, 48756051948SVladimir Oltean { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 48856051948SVladimir Oltean { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 48956051948SVladimir Oltean { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 49056051948SVladimir Oltean { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 49156051948SVladimir Oltean { .offset = 0x20, .name = "rx_yellow_prio_4", }, 49256051948SVladimir Oltean { .offset = 0x21, .name = "rx_yellow_prio_5", }, 49356051948SVladimir Oltean { .offset = 0x22, .name = "rx_yellow_prio_6", }, 49456051948SVladimir Oltean { .offset = 0x23, .name = "rx_yellow_prio_7", }, 49556051948SVladimir Oltean { .offset = 0x24, .name = "rx_green_prio_0", }, 49656051948SVladimir Oltean { .offset = 0x25, .name = "rx_green_prio_1", }, 49756051948SVladimir Oltean { .offset = 0x26, .name = "rx_green_prio_2", }, 49856051948SVladimir Oltean { .offset = 0x27, .name = "rx_green_prio_3", }, 49956051948SVladimir Oltean { .offset = 0x28, .name = "rx_green_prio_4", }, 50056051948SVladimir Oltean { .offset = 0x29, .name = "rx_green_prio_5", }, 50156051948SVladimir Oltean { .offset = 0x2A, .name = "rx_green_prio_6", }, 50256051948SVladimir Oltean { .offset = 0x2B, .name = "rx_green_prio_7", }, 50356051948SVladimir Oltean { .offset = 0x80, .name = "tx_octets", }, 50456051948SVladimir Oltean { .offset = 0x81, .name = "tx_unicast", }, 50556051948SVladimir Oltean { .offset = 0x82, .name = "tx_multicast", }, 50656051948SVladimir Oltean { .offset = 0x83, .name = "tx_broadcast", }, 50756051948SVladimir Oltean { .offset = 0x84, .name = "tx_collision", }, 50856051948SVladimir Oltean { .offset = 0x85, .name = "tx_drops", }, 50956051948SVladimir Oltean { .offset = 0x86, .name = "tx_pause", }, 51056051948SVladimir Oltean { .offset = 0x87, .name = "tx_frames_below_65_octets", }, 51156051948SVladimir Oltean { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, 51256051948SVladimir Oltean { .offset = 0x89, .name = "tx_frames_128_255_octets", }, 51356051948SVladimir Oltean { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, 51456051948SVladimir Oltean { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, 51556051948SVladimir Oltean { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, 51656051948SVladimir Oltean { .offset = 0x8E, .name = "tx_yellow_prio_0", }, 51756051948SVladimir Oltean { .offset = 0x8F, .name = "tx_yellow_prio_1", }, 51856051948SVladimir Oltean { .offset = 0x90, .name = "tx_yellow_prio_2", }, 51956051948SVladimir Oltean { .offset = 0x91, .name = "tx_yellow_prio_3", }, 52056051948SVladimir Oltean { .offset = 0x92, .name = "tx_yellow_prio_4", }, 52156051948SVladimir Oltean { .offset = 0x93, .name = "tx_yellow_prio_5", }, 52256051948SVladimir Oltean { .offset = 0x94, .name = "tx_yellow_prio_6", }, 52356051948SVladimir Oltean { .offset = 0x95, .name = "tx_yellow_prio_7", }, 52456051948SVladimir Oltean { .offset = 0x96, .name = "tx_green_prio_0", }, 52556051948SVladimir Oltean { .offset = 0x97, .name = "tx_green_prio_1", }, 52656051948SVladimir Oltean { .offset = 0x98, .name = "tx_green_prio_2", }, 52756051948SVladimir Oltean { .offset = 0x99, .name = "tx_green_prio_3", }, 52856051948SVladimir Oltean { .offset = 0x9A, .name = "tx_green_prio_4", }, 52956051948SVladimir Oltean { .offset = 0x9B, .name = "tx_green_prio_5", }, 53056051948SVladimir Oltean { .offset = 0x9C, .name = "tx_green_prio_6", }, 53156051948SVladimir Oltean { .offset = 0x9D, .name = "tx_green_prio_7", }, 53256051948SVladimir Oltean { .offset = 0x9E, .name = "tx_aged", }, 53356051948SVladimir Oltean { .offset = 0x100, .name = "drop_local", }, 53456051948SVladimir Oltean { .offset = 0x101, .name = "drop_tail", }, 53556051948SVladimir Oltean { .offset = 0x102, .name = "drop_yellow_prio_0", }, 53656051948SVladimir Oltean { .offset = 0x103, .name = "drop_yellow_prio_1", }, 53756051948SVladimir Oltean { .offset = 0x104, .name = "drop_yellow_prio_2", }, 53856051948SVladimir Oltean { .offset = 0x105, .name = "drop_yellow_prio_3", }, 53956051948SVladimir Oltean { .offset = 0x106, .name = "drop_yellow_prio_4", }, 54056051948SVladimir Oltean { .offset = 0x107, .name = "drop_yellow_prio_5", }, 54156051948SVladimir Oltean { .offset = 0x108, .name = "drop_yellow_prio_6", }, 54256051948SVladimir Oltean { .offset = 0x109, .name = "drop_yellow_prio_7", }, 54356051948SVladimir Oltean { .offset = 0x10A, .name = "drop_green_prio_0", }, 54456051948SVladimir Oltean { .offset = 0x10B, .name = "drop_green_prio_1", }, 54556051948SVladimir Oltean { .offset = 0x10C, .name = "drop_green_prio_2", }, 54656051948SVladimir Oltean { .offset = 0x10D, .name = "drop_green_prio_3", }, 54756051948SVladimir Oltean { .offset = 0x10E, .name = "drop_green_prio_4", }, 54856051948SVladimir Oltean { .offset = 0x10F, .name = "drop_green_prio_5", }, 54956051948SVladimir Oltean { .offset = 0x110, .name = "drop_green_prio_6", }, 55056051948SVladimir Oltean { .offset = 0x111, .name = "drop_green_prio_7", }, 55156051948SVladimir Oltean }; 55256051948SVladimir Oltean 55307d985eeSVladimir Oltean struct vcap_field vsc9959_vcap_is2_keys[] = { 55407d985eeSVladimir Oltean /* Common: 41 bits */ 55507d985eeSVladimir Oltean [VCAP_IS2_TYPE] = { 0, 4}, 55607d985eeSVladimir Oltean [VCAP_IS2_HK_FIRST] = { 4, 1}, 55707d985eeSVladimir Oltean [VCAP_IS2_HK_PAG] = { 5, 8}, 55807d985eeSVladimir Oltean [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 55907d985eeSVladimir Oltean [VCAP_IS2_HK_RSV2] = { 20, 1}, 56007d985eeSVladimir Oltean [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 56107d985eeSVladimir Oltean [VCAP_IS2_HK_L2_MC] = { 22, 1}, 56207d985eeSVladimir Oltean [VCAP_IS2_HK_L2_BC] = { 23, 1}, 56307d985eeSVladimir Oltean [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 56407d985eeSVladimir Oltean [VCAP_IS2_HK_VID] = { 25, 12}, 56507d985eeSVladimir Oltean [VCAP_IS2_HK_DEI] = { 37, 1}, 56607d985eeSVladimir Oltean [VCAP_IS2_HK_PCP] = { 38, 3}, 56707d985eeSVladimir Oltean /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 56807d985eeSVladimir Oltean [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 56907d985eeSVladimir Oltean [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 57007d985eeSVladimir Oltean /* MAC_ETYPE (TYPE=000) */ 57107d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 57207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 57307d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 57407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 57507d985eeSVladimir Oltean /* MAC_LLC (TYPE=001) */ 57607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 57707d985eeSVladimir Oltean /* MAC_SNAP (TYPE=010) */ 57807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 57907d985eeSVladimir Oltean /* MAC_ARP (TYPE=011) */ 58007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 58107d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 58207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 58307d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 58407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 58507d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 58607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 58707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 58807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 58907d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 59007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 59107d985eeSVladimir Oltean /* IP4_TCP_UDP / IP4_OTHER common */ 59207d985eeSVladimir Oltean [VCAP_IS2_HK_IP4] = { 41, 1}, 59307d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 59407d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 59507d985eeSVladimir Oltean [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 59607d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 59707d985eeSVladimir Oltean [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 59807d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 59907d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 60007d985eeSVladimir Oltean [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 60107d985eeSVladimir Oltean /* IP4_TCP_UDP (TYPE=100) */ 60207d985eeSVladimir Oltean [VCAP_IS2_HK_TCP] = {119, 1}, 60307d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SPORT] = {120, 16}, 60407d985eeSVladimir Oltean [VCAP_IS2_HK_L4_DPORT] = {136, 16}, 60507d985eeSVladimir Oltean [VCAP_IS2_HK_L4_RNG] = {152, 8}, 60607d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 60707d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 60807d985eeSVladimir Oltean [VCAP_IS2_HK_L4_URG] = {162, 1}, 60907d985eeSVladimir Oltean [VCAP_IS2_HK_L4_ACK] = {163, 1}, 61007d985eeSVladimir Oltean [VCAP_IS2_HK_L4_PSH] = {164, 1}, 61107d985eeSVladimir Oltean [VCAP_IS2_HK_L4_RST] = {165, 1}, 61207d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SYN] = {166, 1}, 61307d985eeSVladimir Oltean [VCAP_IS2_HK_L4_FIN] = {167, 1}, 61407d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 61507d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 61607d985eeSVladimir Oltean /* IP4_OTHER (TYPE=101) */ 61707d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 61807d985eeSVladimir Oltean [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 61907d985eeSVladimir Oltean /* IP6_STD (TYPE=110) */ 62007d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 62107d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 62207d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 62307d985eeSVladimir Oltean /* OAM (TYPE=111) */ 62407d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 62507d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_VER] = {144, 5}, 62607d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 62707d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 62807d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 62907d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 63007d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 63107d985eeSVladimir Oltean }; 63207d985eeSVladimir Oltean 63307d985eeSVladimir Oltean struct vcap_field vsc9959_vcap_is2_actions[] = { 63407d985eeSVladimir Oltean [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 63507d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 63607d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 63707d985eeSVladimir Oltean [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 63807d985eeSVladimir Oltean [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 63907d985eeSVladimir Oltean [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 64007d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 64107d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 64207d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 64307d985eeSVladimir Oltean [VCAP_IS2_ACT_PORT_MASK] = { 20, 11}, 64407d985eeSVladimir Oltean [VCAP_IS2_ACT_REW_OP] = { 31, 9}, 64507d985eeSVladimir Oltean [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1}, 64607d985eeSVladimir Oltean [VCAP_IS2_ACT_RSV] = { 41, 2}, 64707d985eeSVladimir Oltean [VCAP_IS2_ACT_ACL_ID] = { 43, 6}, 64807d985eeSVladimir Oltean [VCAP_IS2_ACT_HIT_CNT] = { 49, 32}, 64907d985eeSVladimir Oltean }; 65007d985eeSVladimir Oltean 65107d985eeSVladimir Oltean static const struct vcap_props vsc9959_vcap_props[] = { 65207d985eeSVladimir Oltean [VCAP_IS2] = { 65307d985eeSVladimir Oltean .tg_width = 2, 65407d985eeSVladimir Oltean .sw_count = 4, 65507d985eeSVladimir Oltean .entry_count = VSC9959_VCAP_IS2_CNT, 65607d985eeSVladimir Oltean .entry_width = VSC9959_VCAP_IS2_ENTRY_WIDTH, 65707d985eeSVladimir Oltean .action_count = VSC9959_VCAP_IS2_CNT + 65807d985eeSVladimir Oltean VSC9959_VCAP_PORT_CNT + 2, 65907d985eeSVladimir Oltean .action_width = 89, 66007d985eeSVladimir Oltean .action_type_width = 1, 66107d985eeSVladimir Oltean .action_table = { 66207d985eeSVladimir Oltean [IS2_ACTION_TYPE_NORMAL] = { 66307d985eeSVladimir Oltean .width = 44, 66407d985eeSVladimir Oltean .count = 2 66507d985eeSVladimir Oltean }, 66607d985eeSVladimir Oltean [IS2_ACTION_TYPE_SMAC_SIP] = { 66707d985eeSVladimir Oltean .width = 6, 66807d985eeSVladimir Oltean .count = 4 66907d985eeSVladimir Oltean }, 67007d985eeSVladimir Oltean }, 67107d985eeSVladimir Oltean .counter_words = 4, 67207d985eeSVladimir Oltean .counter_width = 32, 67307d985eeSVladimir Oltean }, 67407d985eeSVladimir Oltean }; 67507d985eeSVladimir Oltean 67656051948SVladimir Oltean #define VSC9959_INIT_TIMEOUT 50000 67756051948SVladimir Oltean #define VSC9959_GCB_RST_SLEEP 100 67856051948SVladimir Oltean #define VSC9959_SYS_RAMINIT_SLEEP 80 67956051948SVladimir Oltean 68056051948SVladimir Oltean static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 68156051948SVladimir Oltean { 68256051948SVladimir Oltean int val; 68356051948SVladimir Oltean 68456051948SVladimir Oltean regmap_field_read(ocelot->regfields[GCB_SOFT_RST_SWC_RST], &val); 68556051948SVladimir Oltean 68656051948SVladimir Oltean return val; 68756051948SVladimir Oltean } 68856051948SVladimir Oltean 68956051948SVladimir Oltean static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 69056051948SVladimir Oltean { 69156051948SVladimir Oltean return ocelot_read(ocelot, SYS_RAM_INIT); 69256051948SVladimir Oltean } 69356051948SVladimir Oltean 69456051948SVladimir Oltean static int vsc9959_reset(struct ocelot *ocelot) 69556051948SVladimir Oltean { 69656051948SVladimir Oltean int val, err; 69756051948SVladimir Oltean 69856051948SVladimir Oltean /* soft-reset the switch core */ 69956051948SVladimir Oltean regmap_field_write(ocelot->regfields[GCB_SOFT_RST_SWC_RST], 1); 70056051948SVladimir Oltean 70156051948SVladimir Oltean err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 70256051948SVladimir Oltean VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 70356051948SVladimir Oltean if (err) { 70456051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch core reset\n"); 70556051948SVladimir Oltean return err; 70656051948SVladimir Oltean } 70756051948SVladimir Oltean 70856051948SVladimir Oltean /* initialize switch mem ~40us */ 70956051948SVladimir Oltean ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 71056051948SVladimir Oltean err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 71156051948SVladimir Oltean VSC9959_SYS_RAMINIT_SLEEP, 71256051948SVladimir Oltean VSC9959_INIT_TIMEOUT); 71356051948SVladimir Oltean if (err) { 71456051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch sram init\n"); 71556051948SVladimir Oltean return err; 71656051948SVladimir Oltean } 71756051948SVladimir Oltean 71856051948SVladimir Oltean /* enable switch core */ 71956051948SVladimir Oltean regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 72056051948SVladimir Oltean 72156051948SVladimir Oltean return 0; 72256051948SVladimir Oltean } 72356051948SVladimir Oltean 724bdeced75SVladimir Oltean static void vsc9959_pcs_an_restart_sgmii(struct phy_device *pcs) 725bdeced75SVladimir Oltean { 726bdeced75SVladimir Oltean phy_set_bits(pcs, MII_BMCR, BMCR_ANRESTART); 727bdeced75SVladimir Oltean } 728bdeced75SVladimir Oltean 729bdeced75SVladimir Oltean static void vsc9959_pcs_an_restart_usxgmii(struct phy_device *pcs) 730bdeced75SVladimir Oltean { 731bdeced75SVladimir Oltean phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_BMCR, 732bdeced75SVladimir Oltean USXGMII_BMCR_RESET | 733bdeced75SVladimir Oltean USXGMII_BMCR_AN_EN | 734bdeced75SVladimir Oltean USXGMII_BMCR_RST_AN); 735bdeced75SVladimir Oltean } 736bdeced75SVladimir Oltean 737bdeced75SVladimir Oltean static void vsc9959_pcs_an_restart(struct ocelot *ocelot, int port) 738bdeced75SVladimir Oltean { 739bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 740bdeced75SVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 741bdeced75SVladimir Oltean 742bdeced75SVladimir Oltean if (!pcs) 743bdeced75SVladimir Oltean return; 744bdeced75SVladimir Oltean 745bdeced75SVladimir Oltean switch (pcs->interface) { 746bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 747bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 748bdeced75SVladimir Oltean vsc9959_pcs_an_restart_sgmii(pcs); 749bdeced75SVladimir Oltean break; 750bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 751bdeced75SVladimir Oltean vsc9959_pcs_an_restart_usxgmii(pcs); 752bdeced75SVladimir Oltean break; 753bdeced75SVladimir Oltean default: 754bdeced75SVladimir Oltean dev_err(ocelot->dev, "Invalid PCS interface type %s\n", 755bdeced75SVladimir Oltean phy_modes(pcs->interface)); 756bdeced75SVladimir Oltean break; 757bdeced75SVladimir Oltean } 758bdeced75SVladimir Oltean } 759bdeced75SVladimir Oltean 760bdeced75SVladimir Oltean /* We enable SGMII AN only when the PHY has managed = "in-band-status" in the 761bdeced75SVladimir Oltean * device tree. If we are in MLO_AN_PHY mode, we program directly state->speed 762bdeced75SVladimir Oltean * into the PCS, which is retrieved out-of-band over MDIO. This also has the 763bdeced75SVladimir Oltean * benefit of working with SGMII fixed-links, like downstream switches, where 764bdeced75SVladimir Oltean * both link partners attempt to operate as AN slaves and therefore AN never 765bdeced75SVladimir Oltean * completes. But it also has the disadvantage that some PHY chips don't pass 766bdeced75SVladimir Oltean * traffic if SGMII AN is enabled but not completed (acknowledged by us), so 767bdeced75SVladimir Oltean * setting MLO_AN_INBAND is actually required for those. 768bdeced75SVladimir Oltean */ 769bdeced75SVladimir Oltean static void vsc9959_pcs_init_sgmii(struct phy_device *pcs, 770bdeced75SVladimir Oltean unsigned int link_an_mode, 771bdeced75SVladimir Oltean const struct phylink_link_state *state) 772bdeced75SVladimir Oltean { 773bdeced75SVladimir Oltean if (link_an_mode == MLO_AN_INBAND) { 7748c6123e1SAlex Marginean int bmsr, bmcr; 7758c6123e1SAlex Marginean 7768c6123e1SAlex Marginean /* Some PHYs like VSC8234 don't like it when AN restarts on 7778c6123e1SAlex Marginean * their system side and they restart line side AN too, going 7788c6123e1SAlex Marginean * into an endless link up/down loop. Don't restart PCS AN if 7798c6123e1SAlex Marginean * link is up already. 7808c6123e1SAlex Marginean * We do check that AN is enabled just in case this is the 1st 7818c6123e1SAlex Marginean * call, PCS detects a carrier but AN is disabled from power on 7828c6123e1SAlex Marginean * or by boot loader. 7838c6123e1SAlex Marginean */ 7848c6123e1SAlex Marginean bmcr = phy_read(pcs, MII_BMCR); 7858c6123e1SAlex Marginean if (bmcr < 0) 7868c6123e1SAlex Marginean return; 7878c6123e1SAlex Marginean 7888c6123e1SAlex Marginean bmsr = phy_read(pcs, MII_BMSR); 7898c6123e1SAlex Marginean if (bmsr < 0) 7908c6123e1SAlex Marginean return; 7918c6123e1SAlex Marginean 7928c6123e1SAlex Marginean if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_LSTATUS)) 7938c6123e1SAlex Marginean return; 7948c6123e1SAlex Marginean 795bdeced75SVladimir Oltean /* SGMII spec requires tx_config_Reg[15:0] to be exactly 0x4001 796bdeced75SVladimir Oltean * for the MAC PCS in order to acknowledge the AN. 797bdeced75SVladimir Oltean */ 798bdeced75SVladimir Oltean phy_write(pcs, MII_ADVERTISE, ADVERTISE_SGMII | 799bdeced75SVladimir Oltean ADVERTISE_LPACK); 800bdeced75SVladimir Oltean 801bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_IF_MODE, 802bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_SGMII_EN | 803bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_USE_SGMII_AN); 804bdeced75SVladimir Oltean 805bdeced75SVladimir Oltean /* Adjust link timer for SGMII */ 806bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_LINK_TIMER1, 807bdeced75SVladimir Oltean ENETC_PCS_LINK_TIMER1_VAL); 808bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_LINK_TIMER2, 809bdeced75SVladimir Oltean ENETC_PCS_LINK_TIMER2_VAL); 810bdeced75SVladimir Oltean 811bdeced75SVladimir Oltean phy_write(pcs, MII_BMCR, BMCR_ANRESTART | BMCR_ANENABLE); 812bdeced75SVladimir Oltean } else { 813bdeced75SVladimir Oltean int speed; 814bdeced75SVladimir Oltean 815bdeced75SVladimir Oltean if (state->duplex == DUPLEX_HALF) { 816bdeced75SVladimir Oltean phydev_err(pcs, "Half duplex not supported\n"); 817bdeced75SVladimir Oltean return; 818bdeced75SVladimir Oltean } 819bdeced75SVladimir Oltean switch (state->speed) { 820bdeced75SVladimir Oltean case SPEED_1000: 821bdeced75SVladimir Oltean speed = ENETC_PCS_SPEED_1000; 822bdeced75SVladimir Oltean break; 823bdeced75SVladimir Oltean case SPEED_100: 824bdeced75SVladimir Oltean speed = ENETC_PCS_SPEED_100; 825bdeced75SVladimir Oltean break; 826bdeced75SVladimir Oltean case SPEED_10: 827bdeced75SVladimir Oltean speed = ENETC_PCS_SPEED_10; 828bdeced75SVladimir Oltean break; 829bdeced75SVladimir Oltean case SPEED_UNKNOWN: 830bdeced75SVladimir Oltean /* Silently don't do anything */ 831bdeced75SVladimir Oltean return; 832bdeced75SVladimir Oltean default: 833bdeced75SVladimir Oltean phydev_err(pcs, "Invalid PCS speed %d\n", state->speed); 834bdeced75SVladimir Oltean return; 835bdeced75SVladimir Oltean } 836bdeced75SVladimir Oltean 837bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_IF_MODE, 838bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_SGMII_EN | 839bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_SGMII_SPEED(speed)); 840bdeced75SVladimir Oltean 841bdeced75SVladimir Oltean /* Yes, not a mistake: speed is given by IF_MODE. */ 842bdeced75SVladimir Oltean phy_write(pcs, MII_BMCR, BMCR_RESET | 843bdeced75SVladimir Oltean BMCR_SPEED1000 | 844bdeced75SVladimir Oltean BMCR_FULLDPLX); 845bdeced75SVladimir Oltean } 846bdeced75SVladimir Oltean } 847bdeced75SVladimir Oltean 848bdeced75SVladimir Oltean /* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane 849bdeced75SVladimir Oltean * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have 850bdeced75SVladimir Oltean * auto-negotiation of any link parameters. Electrically it is compatible with 851bdeced75SVladimir Oltean * a single lane of XAUI. 852bdeced75SVladimir Oltean * The hardware reference manual wants to call this mode SGMII, but it isn't 853bdeced75SVladimir Oltean * really, since the fundamental features of SGMII: 854bdeced75SVladimir Oltean * - Downgrading the link speed by duplicating symbols 855bdeced75SVladimir Oltean * - Auto-negotiation 856bdeced75SVladimir Oltean * are not there. 857bdeced75SVladimir Oltean * The speed is configured at 1000 in the IF_MODE and BMCR MDIO registers 858bdeced75SVladimir Oltean * because the clock frequency is actually given by a PLL configured in the 859bdeced75SVladimir Oltean * Reset Configuration Word (RCW). 860bdeced75SVladimir Oltean * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o 861bdeced75SVladimir Oltean * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a 862bdeced75SVladimir Oltean * lower link speed on line side, the system-side interface remains fixed at 863bdeced75SVladimir Oltean * 2500 Mbps and we do rate adaptation through pause frames. 864bdeced75SVladimir Oltean */ 865bdeced75SVladimir Oltean static void vsc9959_pcs_init_2500basex(struct phy_device *pcs, 866bdeced75SVladimir Oltean unsigned int link_an_mode, 867bdeced75SVladimir Oltean const struct phylink_link_state *state) 868bdeced75SVladimir Oltean { 869bdeced75SVladimir Oltean if (link_an_mode == MLO_AN_INBAND) { 870bdeced75SVladimir Oltean phydev_err(pcs, "AN not supported on 3.125GHz SerDes lane\n"); 871bdeced75SVladimir Oltean return; 872bdeced75SVladimir Oltean } 873bdeced75SVladimir Oltean 874bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_IF_MODE, 875bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_SGMII_EN | 876bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500)); 877bdeced75SVladimir Oltean 878bdeced75SVladimir Oltean phy_write(pcs, MII_BMCR, BMCR_SPEED1000 | 879bdeced75SVladimir Oltean BMCR_FULLDPLX | 880bdeced75SVladimir Oltean BMCR_RESET); 881bdeced75SVladimir Oltean } 882bdeced75SVladimir Oltean 883bdeced75SVladimir Oltean static void vsc9959_pcs_init_usxgmii(struct phy_device *pcs, 884bdeced75SVladimir Oltean unsigned int link_an_mode, 885bdeced75SVladimir Oltean const struct phylink_link_state *state) 886bdeced75SVladimir Oltean { 887bdeced75SVladimir Oltean if (link_an_mode != MLO_AN_INBAND) { 888bdeced75SVladimir Oltean phydev_err(pcs, "USXGMII only supports in-band AN for now\n"); 889bdeced75SVladimir Oltean return; 890bdeced75SVladimir Oltean } 891bdeced75SVladimir Oltean 892bdeced75SVladimir Oltean /* Configure device ability for the USXGMII Replicator */ 893bdeced75SVladimir Oltean phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_ADVERTISE, 894bdeced75SVladimir Oltean USXGMII_ADVERTISE_SPEED(USXGMII_SPEED_2500) | 895bdeced75SVladimir Oltean USXGMII_ADVERTISE_LNKS(1) | 896bdeced75SVladimir Oltean ADVERTISE_SGMII | 897bdeced75SVladimir Oltean ADVERTISE_LPACK | 898bdeced75SVladimir Oltean USXGMII_ADVERTISE_FDX); 899bdeced75SVladimir Oltean } 900bdeced75SVladimir Oltean 901bdeced75SVladimir Oltean static void vsc9959_pcs_init(struct ocelot *ocelot, int port, 902bdeced75SVladimir Oltean unsigned int link_an_mode, 903bdeced75SVladimir Oltean const struct phylink_link_state *state) 904bdeced75SVladimir Oltean { 905bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 906bdeced75SVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 907bdeced75SVladimir Oltean 908bdeced75SVladimir Oltean if (!pcs) 909bdeced75SVladimir Oltean return; 910bdeced75SVladimir Oltean 911bdeced75SVladimir Oltean /* The PCS does not implement the BMSR register fully, so capability 912bdeced75SVladimir Oltean * detection via genphy_read_abilities does not work. Since we can get 913bdeced75SVladimir Oltean * the PHY config word from the LPA register though, there is still 914bdeced75SVladimir Oltean * value in using the generic phy_resolve_aneg_linkmode function. So 915bdeced75SVladimir Oltean * populate the supported and advertising link modes manually here. 916bdeced75SVladimir Oltean */ 917bdeced75SVladimir Oltean linkmode_set_bit_array(phy_basic_ports_array, 918bdeced75SVladimir Oltean ARRAY_SIZE(phy_basic_ports_array), 919bdeced75SVladimir Oltean pcs->supported); 920bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, pcs->supported); 921bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pcs->supported); 922bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, pcs->supported); 923bdeced75SVladimir Oltean if (pcs->interface == PHY_INTERFACE_MODE_2500BASEX || 924bdeced75SVladimir Oltean pcs->interface == PHY_INTERFACE_MODE_USXGMII) 925bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 926bdeced75SVladimir Oltean pcs->supported); 927bdeced75SVladimir Oltean if (pcs->interface != PHY_INTERFACE_MODE_2500BASEX) 928bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 929bdeced75SVladimir Oltean pcs->supported); 930bdeced75SVladimir Oltean phy_advertise_supported(pcs); 931bdeced75SVladimir Oltean 932bdeced75SVladimir Oltean switch (pcs->interface) { 933bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 934bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 935bdeced75SVladimir Oltean vsc9959_pcs_init_sgmii(pcs, link_an_mode, state); 936bdeced75SVladimir Oltean break; 937bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 938bdeced75SVladimir Oltean vsc9959_pcs_init_2500basex(pcs, link_an_mode, state); 939bdeced75SVladimir Oltean break; 940bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 941bdeced75SVladimir Oltean vsc9959_pcs_init_usxgmii(pcs, link_an_mode, state); 942bdeced75SVladimir Oltean break; 943bdeced75SVladimir Oltean default: 944bdeced75SVladimir Oltean dev_err(ocelot->dev, "Unsupported link mode %s\n", 945bdeced75SVladimir Oltean phy_modes(pcs->interface)); 946bdeced75SVladimir Oltean } 947bdeced75SVladimir Oltean } 948bdeced75SVladimir Oltean 949bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_resolve(struct phy_device *pcs, 950bdeced75SVladimir Oltean struct phylink_link_state *state) 951bdeced75SVladimir Oltean { 952bdeced75SVladimir Oltean state->an_complete = pcs->autoneg_complete; 953bdeced75SVladimir Oltean state->an_enabled = pcs->autoneg; 954bdeced75SVladimir Oltean state->link = pcs->link; 955bdeced75SVladimir Oltean state->duplex = pcs->duplex; 956bdeced75SVladimir Oltean state->speed = pcs->speed; 957bdeced75SVladimir Oltean /* SGMII AN does not negotiate flow control, but that's ok, 958bdeced75SVladimir Oltean * since phylink already knows that, and does: 959bdeced75SVladimir Oltean * link_state.pause |= pl->phy_state.pause; 960bdeced75SVladimir Oltean */ 961bdeced75SVladimir Oltean state->pause = MLO_PAUSE_NONE; 962bdeced75SVladimir Oltean 963bdeced75SVladimir Oltean phydev_dbg(pcs, 964bdeced75SVladimir Oltean "mode=%s/%s/%s adv=%*pb lpa=%*pb link=%u an_enabled=%u an_complete=%u\n", 965bdeced75SVladimir Oltean phy_modes(pcs->interface), 966bdeced75SVladimir Oltean phy_speed_to_str(pcs->speed), 967bdeced75SVladimir Oltean phy_duplex_to_str(pcs->duplex), 968bdeced75SVladimir Oltean __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->advertising, 969bdeced75SVladimir Oltean __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->lp_advertising, 970bdeced75SVladimir Oltean pcs->link, pcs->autoneg, pcs->autoneg_complete); 971bdeced75SVladimir Oltean } 972bdeced75SVladimir Oltean 973bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_sgmii(struct phy_device *pcs, 974bdeced75SVladimir Oltean struct phylink_link_state *state) 975bdeced75SVladimir Oltean { 976bdeced75SVladimir Oltean int err; 977bdeced75SVladimir Oltean 978bdeced75SVladimir Oltean err = genphy_update_link(pcs); 979bdeced75SVladimir Oltean if (err < 0) 980bdeced75SVladimir Oltean return; 981bdeced75SVladimir Oltean 982bdeced75SVladimir Oltean if (pcs->autoneg_complete) { 983bdeced75SVladimir Oltean u16 lpa = phy_read(pcs, MII_LPA); 984bdeced75SVladimir Oltean 985bdeced75SVladimir Oltean mii_lpa_to_linkmode_lpa_sgmii(pcs->lp_advertising, lpa); 986bdeced75SVladimir Oltean 987bdeced75SVladimir Oltean phy_resolve_aneg_linkmode(pcs); 988bdeced75SVladimir Oltean } 989bdeced75SVladimir Oltean } 990bdeced75SVladimir Oltean 991bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_2500basex(struct phy_device *pcs, 992bdeced75SVladimir Oltean struct phylink_link_state *state) 993bdeced75SVladimir Oltean { 994bdeced75SVladimir Oltean int err; 995bdeced75SVladimir Oltean 996bdeced75SVladimir Oltean err = genphy_update_link(pcs); 997bdeced75SVladimir Oltean if (err < 0) 998bdeced75SVladimir Oltean return; 999bdeced75SVladimir Oltean 1000bdeced75SVladimir Oltean pcs->speed = SPEED_2500; 1001bdeced75SVladimir Oltean pcs->asym_pause = true; 1002bdeced75SVladimir Oltean pcs->pause = true; 1003bdeced75SVladimir Oltean } 1004bdeced75SVladimir Oltean 1005bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_usxgmii(struct phy_device *pcs, 1006bdeced75SVladimir Oltean struct phylink_link_state *state) 1007bdeced75SVladimir Oltean { 1008bdeced75SVladimir Oltean int status, lpa; 1009bdeced75SVladimir Oltean 1010bdeced75SVladimir Oltean status = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_BMSR); 1011bdeced75SVladimir Oltean if (status < 0) 1012bdeced75SVladimir Oltean return; 1013bdeced75SVladimir Oltean 1014bdeced75SVladimir Oltean pcs->autoneg = true; 1015bdeced75SVladimir Oltean pcs->autoneg_complete = USXGMII_BMSR_AN_CMPL(status); 1016bdeced75SVladimir Oltean pcs->link = USXGMII_BMSR_LNKS(status); 1017bdeced75SVladimir Oltean 1018bdeced75SVladimir Oltean if (!pcs->link || !pcs->autoneg_complete) 1019bdeced75SVladimir Oltean return; 1020bdeced75SVladimir Oltean 1021bdeced75SVladimir Oltean lpa = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_LPA); 1022bdeced75SVladimir Oltean if (lpa < 0) 1023bdeced75SVladimir Oltean return; 1024bdeced75SVladimir Oltean 1025bdeced75SVladimir Oltean switch (USXGMII_LPA_SPEED(lpa)) { 1026bdeced75SVladimir Oltean case USXGMII_SPEED_10: 1027bdeced75SVladimir Oltean pcs->speed = SPEED_10; 1028bdeced75SVladimir Oltean break; 1029bdeced75SVladimir Oltean case USXGMII_SPEED_100: 1030bdeced75SVladimir Oltean pcs->speed = SPEED_100; 1031bdeced75SVladimir Oltean break; 1032bdeced75SVladimir Oltean case USXGMII_SPEED_1000: 1033bdeced75SVladimir Oltean pcs->speed = SPEED_1000; 1034bdeced75SVladimir Oltean break; 1035bdeced75SVladimir Oltean case USXGMII_SPEED_2500: 1036bdeced75SVladimir Oltean pcs->speed = SPEED_2500; 1037bdeced75SVladimir Oltean break; 1038bdeced75SVladimir Oltean default: 1039bdeced75SVladimir Oltean break; 1040bdeced75SVladimir Oltean } 1041bdeced75SVladimir Oltean 1042bdeced75SVladimir Oltean if (USXGMII_LPA_DUPLEX(lpa)) 1043bdeced75SVladimir Oltean pcs->duplex = DUPLEX_FULL; 1044bdeced75SVladimir Oltean else 1045bdeced75SVladimir Oltean pcs->duplex = DUPLEX_HALF; 1046bdeced75SVladimir Oltean } 1047bdeced75SVladimir Oltean 1048bdeced75SVladimir Oltean static void vsc9959_pcs_link_state(struct ocelot *ocelot, int port, 1049bdeced75SVladimir Oltean struct phylink_link_state *state) 1050bdeced75SVladimir Oltean { 1051bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1052bdeced75SVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 1053bdeced75SVladimir Oltean 1054bdeced75SVladimir Oltean if (!pcs) 1055bdeced75SVladimir Oltean return; 1056bdeced75SVladimir Oltean 1057bdeced75SVladimir Oltean pcs->speed = SPEED_UNKNOWN; 1058bdeced75SVladimir Oltean pcs->duplex = DUPLEX_UNKNOWN; 1059bdeced75SVladimir Oltean pcs->pause = 0; 1060bdeced75SVladimir Oltean pcs->asym_pause = 0; 1061bdeced75SVladimir Oltean 1062bdeced75SVladimir Oltean switch (pcs->interface) { 1063bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 1064bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 1065bdeced75SVladimir Oltean vsc9959_pcs_link_state_sgmii(pcs, state); 1066bdeced75SVladimir Oltean break; 1067bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 1068bdeced75SVladimir Oltean vsc9959_pcs_link_state_2500basex(pcs, state); 1069bdeced75SVladimir Oltean break; 1070bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 1071bdeced75SVladimir Oltean vsc9959_pcs_link_state_usxgmii(pcs, state); 1072bdeced75SVladimir Oltean break; 1073bdeced75SVladimir Oltean default: 1074bdeced75SVladimir Oltean return; 1075bdeced75SVladimir Oltean } 1076bdeced75SVladimir Oltean 1077bdeced75SVladimir Oltean vsc9959_pcs_link_state_resolve(pcs, state); 1078bdeced75SVladimir Oltean } 1079bdeced75SVladimir Oltean 1080bdeced75SVladimir Oltean static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port, 1081bdeced75SVladimir Oltean phy_interface_t phy_mode) 1082bdeced75SVladimir Oltean { 1083bdeced75SVladimir Oltean switch (phy_mode) { 108428a134f5SVladimir Oltean case PHY_INTERFACE_MODE_INTERNAL: 1085bdeced75SVladimir Oltean if (port != 4 && port != 5) 1086bdeced75SVladimir Oltean return -ENOTSUPP; 1087bdeced75SVladimir Oltean return 0; 1088bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 1089bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 1090bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 1091bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 1092bdeced75SVladimir Oltean /* Not supported on internal to-CPU ports */ 1093bdeced75SVladimir Oltean if (port == 4 || port == 5) 1094bdeced75SVladimir Oltean return -ENOTSUPP; 1095bdeced75SVladimir Oltean return 0; 1096bdeced75SVladimir Oltean default: 1097bdeced75SVladimir Oltean return -ENOTSUPP; 1098bdeced75SVladimir Oltean } 1099bdeced75SVladimir Oltean } 1100bdeced75SVladimir Oltean 110156051948SVladimir Oltean static const struct ocelot_ops vsc9959_ops = { 110256051948SVladimir Oltean .reset = vsc9959_reset, 110356051948SVladimir Oltean }; 110456051948SVladimir Oltean 1105bdeced75SVladimir Oltean static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 1106bdeced75SVladimir Oltean { 1107bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1108bdeced75SVladimir Oltean struct enetc_mdio_priv *mdio_priv; 1109bdeced75SVladimir Oltean struct device *dev = ocelot->dev; 1110bdeced75SVladimir Oltean resource_size_t imdio_base; 1111bdeced75SVladimir Oltean void __iomem *imdio_regs; 1112*b4024c9eSClaudiu Manoil struct resource res; 1113bdeced75SVladimir Oltean struct enetc_hw *hw; 1114bdeced75SVladimir Oltean struct mii_bus *bus; 1115bdeced75SVladimir Oltean int port; 1116bdeced75SVladimir Oltean int rc; 1117bdeced75SVladimir Oltean 1118bdeced75SVladimir Oltean felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 1119bdeced75SVladimir Oltean sizeof(struct phy_device *), 1120bdeced75SVladimir Oltean GFP_KERNEL); 1121bdeced75SVladimir Oltean if (!felix->pcs) { 1122bdeced75SVladimir Oltean dev_err(dev, "failed to allocate array for PCS PHYs\n"); 1123bdeced75SVladimir Oltean return -ENOMEM; 1124bdeced75SVladimir Oltean } 1125bdeced75SVladimir Oltean 1126bdeced75SVladimir Oltean imdio_base = pci_resource_start(felix->pdev, 1127bdeced75SVladimir Oltean felix->info->imdio_pci_bar); 1128bdeced75SVladimir Oltean 1129*b4024c9eSClaudiu Manoil memcpy(&res, felix->info->imdio_res, sizeof(res)); 1130*b4024c9eSClaudiu Manoil res.flags = IORESOURCE_MEM; 1131*b4024c9eSClaudiu Manoil res.start += imdio_base; 1132*b4024c9eSClaudiu Manoil res.end += imdio_base; 1133bdeced75SVladimir Oltean 1134*b4024c9eSClaudiu Manoil imdio_regs = devm_ioremap_resource(dev, &res); 1135bdeced75SVladimir Oltean if (IS_ERR(imdio_regs)) { 1136bdeced75SVladimir Oltean dev_err(dev, "failed to map internal MDIO registers\n"); 1137bdeced75SVladimir Oltean return PTR_ERR(imdio_regs); 1138bdeced75SVladimir Oltean } 1139bdeced75SVladimir Oltean 1140bdeced75SVladimir Oltean hw = enetc_hw_alloc(dev, imdio_regs); 1141bdeced75SVladimir Oltean if (IS_ERR(hw)) { 1142bdeced75SVladimir Oltean dev_err(dev, "failed to allocate ENETC HW structure\n"); 1143bdeced75SVladimir Oltean return PTR_ERR(hw); 1144bdeced75SVladimir Oltean } 1145bdeced75SVladimir Oltean 1146bdeced75SVladimir Oltean bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv)); 1147bdeced75SVladimir Oltean if (!bus) 1148bdeced75SVladimir Oltean return -ENOMEM; 1149bdeced75SVladimir Oltean 1150bdeced75SVladimir Oltean bus->name = "VSC9959 internal MDIO bus"; 1151bdeced75SVladimir Oltean bus->read = enetc_mdio_read; 1152bdeced75SVladimir Oltean bus->write = enetc_mdio_write; 1153bdeced75SVladimir Oltean bus->parent = dev; 1154bdeced75SVladimir Oltean mdio_priv = bus->priv; 1155bdeced75SVladimir Oltean mdio_priv->hw = hw; 1156bdeced75SVladimir Oltean /* This gets added to imdio_regs, which already maps addresses 1157bdeced75SVladimir Oltean * starting with the proper offset. 1158bdeced75SVladimir Oltean */ 1159bdeced75SVladimir Oltean mdio_priv->mdio_base = 0; 1160bdeced75SVladimir Oltean snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1161bdeced75SVladimir Oltean 1162bdeced75SVladimir Oltean /* Needed in order to initialize the bus mutex lock */ 1163bdeced75SVladimir Oltean rc = mdiobus_register(bus); 1164bdeced75SVladimir Oltean if (rc < 0) { 1165bdeced75SVladimir Oltean dev_err(dev, "failed to register MDIO bus\n"); 1166bdeced75SVladimir Oltean return rc; 1167bdeced75SVladimir Oltean } 1168bdeced75SVladimir Oltean 1169bdeced75SVladimir Oltean felix->imdio = bus; 1170bdeced75SVladimir Oltean 1171bdeced75SVladimir Oltean for (port = 0; port < felix->info->num_ports; port++) { 1172bdeced75SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 1173bdeced75SVladimir Oltean struct phy_device *pcs; 1174bdeced75SVladimir Oltean bool is_c45 = false; 1175bdeced75SVladimir Oltean 1176bdeced75SVladimir Oltean if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_USXGMII) 1177bdeced75SVladimir Oltean is_c45 = true; 1178bdeced75SVladimir Oltean 1179bdeced75SVladimir Oltean pcs = get_phy_device(felix->imdio, port, is_c45); 1180bdeced75SVladimir Oltean if (IS_ERR(pcs)) 1181bdeced75SVladimir Oltean continue; 1182bdeced75SVladimir Oltean 1183bdeced75SVladimir Oltean pcs->interface = ocelot_port->phy_mode; 1184bdeced75SVladimir Oltean felix->pcs[port] = pcs; 1185bdeced75SVladimir Oltean 1186bdeced75SVladimir Oltean dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1187bdeced75SVladimir Oltean } 1188bdeced75SVladimir Oltean 1189bdeced75SVladimir Oltean return 0; 1190bdeced75SVladimir Oltean } 1191bdeced75SVladimir Oltean 1192bdeced75SVladimir Oltean static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1193bdeced75SVladimir Oltean { 1194bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1195bdeced75SVladimir Oltean int port; 1196bdeced75SVladimir Oltean 1197bdeced75SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) { 1198bdeced75SVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 1199bdeced75SVladimir Oltean 1200bdeced75SVladimir Oltean if (!pcs) 1201bdeced75SVladimir Oltean continue; 1202bdeced75SVladimir Oltean 1203bdeced75SVladimir Oltean put_device(&pcs->mdio.dev); 1204bdeced75SVladimir Oltean } 1205bdeced75SVladimir Oltean mdiobus_unregister(felix->imdio); 1206bdeced75SVladimir Oltean } 1207bdeced75SVladimir Oltean 120856051948SVladimir Oltean struct felix_info felix_info_vsc9959 = { 120956051948SVladimir Oltean .target_io_res = vsc9959_target_io_res, 121056051948SVladimir Oltean .port_io_res = vsc9959_port_io_res, 1211bdeced75SVladimir Oltean .imdio_res = &vsc9959_imdio_res, 121256051948SVladimir Oltean .regfields = vsc9959_regfields, 121356051948SVladimir Oltean .map = vsc9959_regmap, 121456051948SVladimir Oltean .ops = &vsc9959_ops, 121556051948SVladimir Oltean .stats_layout = vsc9959_stats_layout, 121656051948SVladimir Oltean .num_stats = ARRAY_SIZE(vsc9959_stats_layout), 121707d985eeSVladimir Oltean .vcap_is2_keys = vsc9959_vcap_is2_keys, 121807d985eeSVladimir Oltean .vcap_is2_actions = vsc9959_vcap_is2_actions, 121907d985eeSVladimir Oltean .vcap = vsc9959_vcap_props, 122056051948SVladimir Oltean .shared_queue_sz = 128 * 1024, 122121ce7f3eSVladimir Oltean .num_mact_rows = 2048, 122256051948SVladimir Oltean .num_ports = 6, 1223bdeced75SVladimir Oltean .switch_pci_bar = 4, 1224bdeced75SVladimir Oltean .imdio_pci_bar = 0, 1225bdeced75SVladimir Oltean .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 1226bdeced75SVladimir Oltean .mdio_bus_free = vsc9959_mdio_bus_free, 1227bdeced75SVladimir Oltean .pcs_init = vsc9959_pcs_init, 1228bdeced75SVladimir Oltean .pcs_an_restart = vsc9959_pcs_an_restart, 1229bdeced75SVladimir Oltean .pcs_link_state = vsc9959_pcs_link_state, 1230bdeced75SVladimir Oltean .prevalidate_phy_mode = vsc9959_prevalidate_phy_mode, 123156051948SVladimir Oltean }; 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