156051948SVladimir Oltean // SPDX-License-Identifier: (GPL-2.0 OR MIT) 256051948SVladimir Oltean /* Copyright 2017 Microsemi Corporation 33c9cfb52SVladimir Oltean * Copyright 2018-2019 NXP 456051948SVladimir Oltean */ 5bdeced75SVladimir Oltean #include <linux/fsl/enetc_mdio.h> 6de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_qsys.h> 707d985eeSVladimir Oltean #include <soc/mscc/ocelot_vcap.h> 87d4b564dSXiaoliang Yang #include <soc/mscc/ocelot_ana.h> 9de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_ptp.h> 1056051948SVladimir Oltean #include <soc/mscc/ocelot_sys.h> 1123ae3a78SXiaoliang Yang #include <net/tc_act/tc_gate.h> 1256051948SVladimir Oltean #include <soc/mscc/ocelot.h> 1340d3f295SVladimir Oltean #include <linux/dsa/ocelot.h> 14588d0550SIoana Ciornei #include <linux/pcs-lynx.h> 15de143c0eSXiaoliang Yang #include <net/pkt_sched.h> 1656051948SVladimir Oltean #include <linux/iopoll.h> 1716659b81SMichael Walle #include <linux/mdio.h> 1856051948SVladimir Oltean #include <linux/pci.h> 1956051948SVladimir Oltean #include "felix.h" 2056051948SVladimir Oltean 21*acf242fcSColin Foster #define VSC9959_NUM_PORTS 6 22*acf242fcSColin Foster 23de143c0eSXiaoliang Yang #define VSC9959_TAS_GCL_ENTRY_MAX 63 2477043c37SXiaoliang Yang #define VSC9959_VCAP_POLICER_BASE 63 2577043c37SXiaoliang Yang #define VSC9959_VCAP_POLICER_MAX 383 26c9910484SColin Foster #define VSC9959_SWITCH_PCI_BAR 4 27c9910484SColin Foster #define VSC9959_IMDIO_PCI_BAR 0 28de143c0eSXiaoliang Yang 29*acf242fcSColin Foster #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ 30*acf242fcSColin Foster OCELOT_PORT_MODE_QSGMII | \ 31*acf242fcSColin Foster OCELOT_PORT_MODE_2500BASEX | \ 32*acf242fcSColin Foster OCELOT_PORT_MODE_USXGMII) 33*acf242fcSColin Foster 34*acf242fcSColin Foster static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { 35*acf242fcSColin Foster VSC9959_PORT_MODE_SERDES, 36*acf242fcSColin Foster VSC9959_PORT_MODE_SERDES, 37*acf242fcSColin Foster VSC9959_PORT_MODE_SERDES, 38*acf242fcSColin Foster VSC9959_PORT_MODE_SERDES, 39*acf242fcSColin Foster OCELOT_PORT_MODE_INTERNAL, 40*acf242fcSColin Foster }; 41*acf242fcSColin Foster 4256051948SVladimir Oltean static const u32 vsc9959_ana_regmap[] = { 4356051948SVladimir Oltean REG(ANA_ADVLEARN, 0x0089a0), 4456051948SVladimir Oltean REG(ANA_VLANMASK, 0x0089a4), 4556051948SVladimir Oltean REG_RESERVED(ANA_PORT_B_DOMAIN), 4656051948SVladimir Oltean REG(ANA_ANAGEFIL, 0x0089ac), 4756051948SVladimir Oltean REG(ANA_ANEVENTS, 0x0089b0), 4856051948SVladimir Oltean REG(ANA_STORMLIMIT_BURST, 0x0089b4), 4956051948SVladimir Oltean REG(ANA_STORMLIMIT_CFG, 0x0089b8), 5056051948SVladimir Oltean REG(ANA_ISOLATED_PORTS, 0x0089c8), 5156051948SVladimir Oltean REG(ANA_COMMUNITY_PORTS, 0x0089cc), 5256051948SVladimir Oltean REG(ANA_AUTOAGE, 0x0089d0), 5356051948SVladimir Oltean REG(ANA_MACTOPTIONS, 0x0089d4), 5456051948SVladimir Oltean REG(ANA_LEARNDISC, 0x0089d8), 5556051948SVladimir Oltean REG(ANA_AGENCTRL, 0x0089dc), 5656051948SVladimir Oltean REG(ANA_MIRRORPORTS, 0x0089e0), 5756051948SVladimir Oltean REG(ANA_EMIRRORPORTS, 0x0089e4), 5856051948SVladimir Oltean REG(ANA_FLOODING, 0x0089e8), 5956051948SVladimir Oltean REG(ANA_FLOODING_IPMC, 0x008a08), 6056051948SVladimir Oltean REG(ANA_SFLOW_CFG, 0x008a0c), 6156051948SVladimir Oltean REG(ANA_PORT_MODE, 0x008a28), 6256051948SVladimir Oltean REG(ANA_CUT_THRU_CFG, 0x008a48), 6356051948SVladimir Oltean REG(ANA_PGID_PGID, 0x008400), 6456051948SVladimir Oltean REG(ANA_TABLES_ANMOVED, 0x007f1c), 6556051948SVladimir Oltean REG(ANA_TABLES_MACHDATA, 0x007f20), 6656051948SVladimir Oltean REG(ANA_TABLES_MACLDATA, 0x007f24), 6756051948SVladimir Oltean REG(ANA_TABLES_STREAMDATA, 0x007f28), 6856051948SVladimir Oltean REG(ANA_TABLES_MACACCESS, 0x007f2c), 6956051948SVladimir Oltean REG(ANA_TABLES_MACTINDX, 0x007f30), 7056051948SVladimir Oltean REG(ANA_TABLES_VLANACCESS, 0x007f34), 7156051948SVladimir Oltean REG(ANA_TABLES_VLANTIDX, 0x007f38), 7256051948SVladimir Oltean REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 7356051948SVladimir Oltean REG(ANA_TABLES_ISDXTIDX, 0x007f40), 7456051948SVladimir Oltean REG(ANA_TABLES_ENTRYLIM, 0x007f00), 7556051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 7656051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 7756051948SVladimir Oltean REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 7856051948SVladimir Oltean REG(ANA_TABLES_STREAMTIDX, 0x007f50), 7956051948SVladimir Oltean REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 8056051948SVladimir Oltean REG(ANA_TABLES_SEQ_MASK, 0x007f58), 8156051948SVladimir Oltean REG(ANA_TABLES_SFID_MASK, 0x007f5c), 8256051948SVladimir Oltean REG(ANA_TABLES_SFIDACCESS, 0x007f60), 8356051948SVladimir Oltean REG(ANA_TABLES_SFIDTIDX, 0x007f64), 8456051948SVladimir Oltean REG(ANA_MSTI_STATE, 0x008600), 8556051948SVladimir Oltean REG(ANA_OAM_UPM_LM_CNT, 0x008000), 8656051948SVladimir Oltean REG(ANA_SG_ACCESS_CTRL, 0x008a64), 8756051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 8856051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 8956051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 9056051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 9156051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 9256051948SVladimir Oltean REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 9356051948SVladimir Oltean REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 9456051948SVladimir Oltean REG(ANA_SG_STATUS_REG_1, 0x008980), 9556051948SVladimir Oltean REG(ANA_SG_STATUS_REG_2, 0x008984), 9656051948SVladimir Oltean REG(ANA_SG_STATUS_REG_3, 0x008988), 9756051948SVladimir Oltean REG(ANA_PORT_VLAN_CFG, 0x007800), 9856051948SVladimir Oltean REG(ANA_PORT_DROP_CFG, 0x007804), 9956051948SVladimir Oltean REG(ANA_PORT_QOS_CFG, 0x007808), 10056051948SVladimir Oltean REG(ANA_PORT_VCAP_CFG, 0x00780c), 10156051948SVladimir Oltean REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 10256051948SVladimir Oltean REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 10356051948SVladimir Oltean REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 10456051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 10556051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 10656051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 10756051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 10856051948SVladimir Oltean REG(ANA_PORT_PORT_CFG, 0x007870), 10956051948SVladimir Oltean REG(ANA_PORT_POL_CFG, 0x007874), 11056051948SVladimir Oltean REG(ANA_PORT_PTP_CFG, 0x007878), 11156051948SVladimir Oltean REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 11256051948SVladimir Oltean REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 11356051948SVladimir Oltean REG(ANA_PORT_SFID_CFG, 0x007884), 11456051948SVladimir Oltean REG(ANA_PFC_PFC_CFG, 0x008800), 11556051948SVladimir Oltean REG_RESERVED(ANA_PFC_PFC_TIMER), 11656051948SVladimir Oltean REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 11756051948SVladimir Oltean REG_RESERVED(ANA_IPT_IPT), 11856051948SVladimir Oltean REG_RESERVED(ANA_PPT_PPT), 11956051948SVladimir Oltean REG_RESERVED(ANA_FID_MAP_FID_MAP), 12056051948SVladimir Oltean REG(ANA_AGGR_CFG, 0x008a68), 12156051948SVladimir Oltean REG(ANA_CPUQ_CFG, 0x008a6c), 12256051948SVladimir Oltean REG_RESERVED(ANA_CPUQ_CFG2), 12356051948SVladimir Oltean REG(ANA_CPUQ_8021_CFG, 0x008a74), 12456051948SVladimir Oltean REG(ANA_DSCP_CFG, 0x008ab4), 12556051948SVladimir Oltean REG(ANA_DSCP_REWR_CFG, 0x008bb4), 12656051948SVladimir Oltean REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 12756051948SVladimir Oltean REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 12856051948SVladimir Oltean REG_RESERVED(ANA_VRAP_CFG), 12956051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_DATA), 13056051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_MASK), 13156051948SVladimir Oltean REG(ANA_DISCARD_CFG, 0x008c40), 13256051948SVladimir Oltean REG(ANA_FID_CFG, 0x008c44), 13356051948SVladimir Oltean REG(ANA_POL_PIR_CFG, 0x004000), 13456051948SVladimir Oltean REG(ANA_POL_CIR_CFG, 0x004004), 13556051948SVladimir Oltean REG(ANA_POL_MODE_CFG, 0x004008), 13656051948SVladimir Oltean REG(ANA_POL_PIR_STATE, 0x00400c), 13756051948SVladimir Oltean REG(ANA_POL_CIR_STATE, 0x004010), 13856051948SVladimir Oltean REG_RESERVED(ANA_POL_STATE), 13956051948SVladimir Oltean REG(ANA_POL_FLOWC, 0x008c48), 14056051948SVladimir Oltean REG(ANA_POL_HYST, 0x008cb4), 14156051948SVladimir Oltean REG_RESERVED(ANA_POL_MISC_CFG), 14256051948SVladimir Oltean }; 14356051948SVladimir Oltean 14456051948SVladimir Oltean static const u32 vsc9959_qs_regmap[] = { 14556051948SVladimir Oltean REG(QS_XTR_GRP_CFG, 0x000000), 14656051948SVladimir Oltean REG(QS_XTR_RD, 0x000008), 14756051948SVladimir Oltean REG(QS_XTR_FRM_PRUNING, 0x000010), 14856051948SVladimir Oltean REG(QS_XTR_FLUSH, 0x000018), 14956051948SVladimir Oltean REG(QS_XTR_DATA_PRESENT, 0x00001c), 15056051948SVladimir Oltean REG(QS_XTR_CFG, 0x000020), 15156051948SVladimir Oltean REG(QS_INJ_GRP_CFG, 0x000024), 15256051948SVladimir Oltean REG(QS_INJ_WR, 0x00002c), 15356051948SVladimir Oltean REG(QS_INJ_CTRL, 0x000034), 15456051948SVladimir Oltean REG(QS_INJ_STATUS, 0x00003c), 15556051948SVladimir Oltean REG(QS_INJ_ERR, 0x000040), 15656051948SVladimir Oltean REG_RESERVED(QS_INH_DBG), 15756051948SVladimir Oltean }; 15856051948SVladimir Oltean 159c1c3993eSVladimir Oltean static const u32 vsc9959_vcap_regmap[] = { 160c1c3993eSVladimir Oltean /* VCAP_CORE_CFG */ 161c1c3993eSVladimir Oltean REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 162c1c3993eSVladimir Oltean REG(VCAP_CORE_MV_CFG, 0x000004), 163c1c3993eSVladimir Oltean /* VCAP_CORE_CACHE */ 164c1c3993eSVladimir Oltean REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 165c1c3993eSVladimir Oltean REG(VCAP_CACHE_MASK_DAT, 0x000108), 166c1c3993eSVladimir Oltean REG(VCAP_CACHE_ACTION_DAT, 0x000208), 167c1c3993eSVladimir Oltean REG(VCAP_CACHE_CNT_DAT, 0x000308), 168c1c3993eSVladimir Oltean REG(VCAP_CACHE_TG_DAT, 0x000388), 16920968054SVladimir Oltean /* VCAP_CONST */ 17020968054SVladimir Oltean REG(VCAP_CONST_VCAP_VER, 0x000398), 17120968054SVladimir Oltean REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 17220968054SVladimir Oltean REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 17320968054SVladimir Oltean REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 17420968054SVladimir Oltean REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 17520968054SVladimir Oltean REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 17620968054SVladimir Oltean REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 17720968054SVladimir Oltean REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 17820968054SVladimir Oltean REG(VCAP_CONST_CORE_CNT, 0x0003b8), 17920968054SVladimir Oltean REG(VCAP_CONST_IF_CNT, 0x0003bc), 18056051948SVladimir Oltean }; 18156051948SVladimir Oltean 18256051948SVladimir Oltean static const u32 vsc9959_qsys_regmap[] = { 18356051948SVladimir Oltean REG(QSYS_PORT_MODE, 0x00f460), 18456051948SVladimir Oltean REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 18556051948SVladimir Oltean REG(QSYS_STAT_CNT_CFG, 0x00f49c), 18656051948SVladimir Oltean REG(QSYS_EEE_CFG, 0x00f4a0), 18756051948SVladimir Oltean REG(QSYS_EEE_THRES, 0x00f4b8), 18856051948SVladimir Oltean REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 18956051948SVladimir Oltean REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 19056051948SVladimir Oltean REG(QSYS_SW_STATUS, 0x00f4c4), 19156051948SVladimir Oltean REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 19256051948SVladimir Oltean REG_RESERVED(QSYS_PAD_CFG), 19356051948SVladimir Oltean REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 19456051948SVladimir Oltean REG_RESERVED(QSYS_QMAP), 19556051948SVladimir Oltean REG_RESERVED(QSYS_ISDX_SGRP), 19656051948SVladimir Oltean REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 19756051948SVladimir Oltean REG(QSYS_TFRM_MISC, 0x00f50c), 19856051948SVladimir Oltean REG(QSYS_TFRM_PORT_DLY, 0x00f510), 19956051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 20056051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 20156051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 20256051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 20356051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 20456051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 20556051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 20656051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 20756051948SVladimir Oltean REG(QSYS_RED_PROFILE, 0x00f534), 20856051948SVladimir Oltean REG(QSYS_RES_QOS_MODE, 0x00f574), 20956051948SVladimir Oltean REG(QSYS_RES_CFG, 0x00c000), 21056051948SVladimir Oltean REG(QSYS_RES_STAT, 0x00c004), 21156051948SVladimir Oltean REG(QSYS_EGR_DROP_MODE, 0x00f578), 21256051948SVladimir Oltean REG(QSYS_EQ_CTRL, 0x00f57c), 21356051948SVladimir Oltean REG_RESERVED(QSYS_EVENTS_CORE), 21456051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 21556051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 21656051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 21756051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 21856051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 21956051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 22056051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 22156051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 22256051948SVladimir Oltean REG(QSYS_PREEMPTION_CFG, 0x00f664), 2230fbabf87SXiaoliang Yang REG(QSYS_CIR_CFG, 0x000000), 22456051948SVladimir Oltean REG(QSYS_EIR_CFG, 0x000004), 22556051948SVladimir Oltean REG(QSYS_SE_CFG, 0x000008), 22656051948SVladimir Oltean REG(QSYS_SE_DWRR_CFG, 0x00000c), 22756051948SVladimir Oltean REG_RESERVED(QSYS_SE_CONNECT), 22856051948SVladimir Oltean REG(QSYS_SE_DLB_SENSE, 0x000040), 22956051948SVladimir Oltean REG(QSYS_CIR_STATE, 0x000044), 23056051948SVladimir Oltean REG(QSYS_EIR_STATE, 0x000048), 23156051948SVladimir Oltean REG_RESERVED(QSYS_SE_STATE), 23256051948SVladimir Oltean REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 23356051948SVladimir Oltean REG(QSYS_TAG_CONFIG, 0x00f680), 23456051948SVladimir Oltean REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 23556051948SVladimir Oltean REG(QSYS_PORT_MAX_SDU, 0x00f69c), 23656051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 23756051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 23856051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 23956051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 24056051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 24156051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_1, 0x00f454), 24256051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_2, 0x00f458), 24356051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 24456051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 24556051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 24656051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 24756051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 24856051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 24956051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 25056051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 25156051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 25256051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 25356051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 25456051948SVladimir Oltean }; 25556051948SVladimir Oltean 25656051948SVladimir Oltean static const u32 vsc9959_rew_regmap[] = { 25756051948SVladimir Oltean REG(REW_PORT_VLAN_CFG, 0x000000), 25856051948SVladimir Oltean REG(REW_TAG_CFG, 0x000004), 25956051948SVladimir Oltean REG(REW_PORT_CFG, 0x000008), 26056051948SVladimir Oltean REG(REW_DSCP_CFG, 0x00000c), 26156051948SVladimir Oltean REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 26256051948SVladimir Oltean REG(REW_PTP_CFG, 0x000050), 26356051948SVladimir Oltean REG(REW_PTP_DLY1_CFG, 0x000054), 26456051948SVladimir Oltean REG(REW_RED_TAG_CFG, 0x000058), 26556051948SVladimir Oltean REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 26656051948SVladimir Oltean REG(REW_DSCP_REMAP_CFG, 0x000510), 26756051948SVladimir Oltean REG_RESERVED(REW_STAT_CFG), 26856051948SVladimir Oltean REG_RESERVED(REW_REW_STICKY), 26956051948SVladimir Oltean REG_RESERVED(REW_PPT), 27056051948SVladimir Oltean }; 27156051948SVladimir Oltean 27256051948SVladimir Oltean static const u32 vsc9959_sys_regmap[] = { 27356051948SVladimir Oltean REG(SYS_COUNT_RX_OCTETS, 0x000000), 27456051948SVladimir Oltean REG(SYS_COUNT_RX_MULTICAST, 0x000008), 27556051948SVladimir Oltean REG(SYS_COUNT_RX_SHORTS, 0x000010), 27656051948SVladimir Oltean REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 27756051948SVladimir Oltean REG(SYS_COUNT_RX_JABBERS, 0x000018), 27856051948SVladimir Oltean REG(SYS_COUNT_RX_64, 0x000024), 27956051948SVladimir Oltean REG(SYS_COUNT_RX_65_127, 0x000028), 28056051948SVladimir Oltean REG(SYS_COUNT_RX_128_255, 0x00002c), 28156051948SVladimir Oltean REG(SYS_COUNT_RX_256_1023, 0x000030), 28256051948SVladimir Oltean REG(SYS_COUNT_RX_1024_1526, 0x000034), 28356051948SVladimir Oltean REG(SYS_COUNT_RX_1527_MAX, 0x000038), 28456051948SVladimir Oltean REG(SYS_COUNT_RX_LONGS, 0x000044), 28556051948SVladimir Oltean REG(SYS_COUNT_TX_OCTETS, 0x000200), 28656051948SVladimir Oltean REG(SYS_COUNT_TX_COLLISION, 0x000210), 28756051948SVladimir Oltean REG(SYS_COUNT_TX_DROPS, 0x000214), 28856051948SVladimir Oltean REG(SYS_COUNT_TX_64, 0x00021c), 28956051948SVladimir Oltean REG(SYS_COUNT_TX_65_127, 0x000220), 29056051948SVladimir Oltean REG(SYS_COUNT_TX_128_511, 0x000224), 29156051948SVladimir Oltean REG(SYS_COUNT_TX_512_1023, 0x000228), 29256051948SVladimir Oltean REG(SYS_COUNT_TX_1024_1526, 0x00022c), 29356051948SVladimir Oltean REG(SYS_COUNT_TX_1527_MAX, 0x000230), 29456051948SVladimir Oltean REG(SYS_COUNT_TX_AGING, 0x000278), 29556051948SVladimir Oltean REG(SYS_RESET_CFG, 0x000e00), 29656051948SVladimir Oltean REG(SYS_SR_ETYPE_CFG, 0x000e04), 29756051948SVladimir Oltean REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 29856051948SVladimir Oltean REG(SYS_PORT_MODE, 0x000e0c), 29956051948SVladimir Oltean REG(SYS_FRONT_PORT_MODE, 0x000e2c), 30056051948SVladimir Oltean REG(SYS_FRM_AGING, 0x000e44), 30156051948SVladimir Oltean REG(SYS_STAT_CFG, 0x000e48), 30256051948SVladimir Oltean REG(SYS_SW_STATUS, 0x000e4c), 30356051948SVladimir Oltean REG_RESERVED(SYS_MISC_CFG), 30456051948SVladimir Oltean REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 30556051948SVladimir Oltean REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 30656051948SVladimir Oltean REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 30756051948SVladimir Oltean REG(SYS_PAUSE_CFG, 0x000ea0), 30856051948SVladimir Oltean REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 30956051948SVladimir Oltean REG(SYS_ATOP, 0x000ec0), 31056051948SVladimir Oltean REG(SYS_ATOP_TOT_CFG, 0x000edc), 31156051948SVladimir Oltean REG(SYS_MAC_FC_CFG, 0x000ee0), 31256051948SVladimir Oltean REG(SYS_MMGT, 0x000ef8), 31356051948SVladimir Oltean REG_RESERVED(SYS_MMGT_FAST), 31456051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_DIF), 31556051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_CORE), 3167d4b564dSXiaoliang Yang REG(SYS_CNT, 0x000000), 31756051948SVladimir Oltean REG(SYS_PTP_STATUS, 0x000f14), 31856051948SVladimir Oltean REG(SYS_PTP_TXSTAMP, 0x000f18), 31956051948SVladimir Oltean REG(SYS_PTP_NXT, 0x000f1c), 32056051948SVladimir Oltean REG(SYS_PTP_CFG, 0x000f20), 32156051948SVladimir Oltean REG(SYS_RAM_INIT, 0x000f24), 32256051948SVladimir Oltean REG_RESERVED(SYS_CM_ADDR), 32356051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_WR), 32456051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_RD), 32556051948SVladimir Oltean REG_RESERVED(SYS_CM_OP), 32656051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA), 32756051948SVladimir Oltean }; 32856051948SVladimir Oltean 3295df66c48SYangbo Lu static const u32 vsc9959_ptp_regmap[] = { 3305df66c48SYangbo Lu REG(PTP_PIN_CFG, 0x000000), 3315df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 3325df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 3335df66c48SYangbo Lu REG(PTP_PIN_TOD_NSEC, 0x00000c), 33494aca082SYangbo Lu REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 33594aca082SYangbo Lu REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 3365df66c48SYangbo Lu REG(PTP_CFG_MISC, 0x0000a0), 3375df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 3385df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 3395df66c48SYangbo Lu }; 3405df66c48SYangbo Lu 34156051948SVladimir Oltean static const u32 vsc9959_gcb_regmap[] = { 34256051948SVladimir Oltean REG(GCB_SOFT_RST, 0x000004), 34356051948SVladimir Oltean }; 34456051948SVladimir Oltean 34591c724cfSVladimir Oltean static const u32 vsc9959_dev_gmii_regmap[] = { 34691c724cfSVladimir Oltean REG(DEV_CLOCK_CFG, 0x0), 34791c724cfSVladimir Oltean REG(DEV_PORT_MISC, 0x4), 34891c724cfSVladimir Oltean REG(DEV_EVENTS, 0x8), 34991c724cfSVladimir Oltean REG(DEV_EEE_CFG, 0xc), 35091c724cfSVladimir Oltean REG(DEV_RX_PATH_DELAY, 0x10), 35191c724cfSVladimir Oltean REG(DEV_TX_PATH_DELAY, 0x14), 35291c724cfSVladimir Oltean REG(DEV_PTP_PREDICT_CFG, 0x18), 35391c724cfSVladimir Oltean REG(DEV_MAC_ENA_CFG, 0x1c), 35491c724cfSVladimir Oltean REG(DEV_MAC_MODE_CFG, 0x20), 35591c724cfSVladimir Oltean REG(DEV_MAC_MAXLEN_CFG, 0x24), 35691c724cfSVladimir Oltean REG(DEV_MAC_TAGS_CFG, 0x28), 35791c724cfSVladimir Oltean REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 35891c724cfSVladimir Oltean REG(DEV_MAC_IFG_CFG, 0x30), 35991c724cfSVladimir Oltean REG(DEV_MAC_HDX_CFG, 0x34), 36091c724cfSVladimir Oltean REG(DEV_MAC_DBG_CFG, 0x38), 36191c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 36291c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 36391c724cfSVladimir Oltean REG(DEV_MAC_STICKY, 0x44), 36491c724cfSVladimir Oltean REG_RESERVED(PCS1G_CFG), 36591c724cfSVladimir Oltean REG_RESERVED(PCS1G_MODE_CFG), 36691c724cfSVladimir Oltean REG_RESERVED(PCS1G_SD_CFG), 36791c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_CFG), 36891c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_CFG), 36991c724cfSVladimir Oltean REG_RESERVED(PCS1G_LB_CFG), 37091c724cfSVladimir Oltean REG_RESERVED(PCS1G_DBG_CFG), 37191c724cfSVladimir Oltean REG_RESERVED(PCS1G_CDET_CFG), 37291c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_STATUS), 37391c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_STATUS), 37491c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_STATUS), 37591c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_DOWN_CNT), 37691c724cfSVladimir Oltean REG_RESERVED(PCS1G_STICKY), 37791c724cfSVladimir Oltean REG_RESERVED(PCS1G_DEBUG_STATUS), 37891c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_CFG), 37991c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 38091c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_STATUS), 38191c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 38291c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_STATUS), 38391c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_CFG), 38491c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_STATUS), 38591c724cfSVladimir Oltean }; 38691c724cfSVladimir Oltean 38791c724cfSVladimir Oltean static const u32 *vsc9959_regmap[TARGET_MAX] = { 38856051948SVladimir Oltean [ANA] = vsc9959_ana_regmap, 38956051948SVladimir Oltean [QS] = vsc9959_qs_regmap, 39056051948SVladimir Oltean [QSYS] = vsc9959_qsys_regmap, 39156051948SVladimir Oltean [REW] = vsc9959_rew_regmap, 39256051948SVladimir Oltean [SYS] = vsc9959_sys_regmap, 393e3aea296SVladimir Oltean [S0] = vsc9959_vcap_regmap, 394a61e365dSVladimir Oltean [S1] = vsc9959_vcap_regmap, 395c1c3993eSVladimir Oltean [S2] = vsc9959_vcap_regmap, 3965df66c48SYangbo Lu [PTP] = vsc9959_ptp_regmap, 39756051948SVladimir Oltean [GCB] = vsc9959_gcb_regmap, 39891c724cfSVladimir Oltean [DEV_GMII] = vsc9959_dev_gmii_regmap, 39956051948SVladimir Oltean }; 40056051948SVladimir Oltean 401b4024c9eSClaudiu Manoil /* Addresses are relative to the PCI device's base address */ 40291c724cfSVladimir Oltean static const struct resource vsc9959_target_io_res[TARGET_MAX] = { 40356051948SVladimir Oltean [ANA] = { 40456051948SVladimir Oltean .start = 0x0280000, 40556051948SVladimir Oltean .end = 0x028ffff, 40656051948SVladimir Oltean .name = "ana", 40756051948SVladimir Oltean }, 40856051948SVladimir Oltean [QS] = { 40956051948SVladimir Oltean .start = 0x0080000, 41056051948SVladimir Oltean .end = 0x00800ff, 41156051948SVladimir Oltean .name = "qs", 41256051948SVladimir Oltean }, 41356051948SVladimir Oltean [QSYS] = { 41456051948SVladimir Oltean .start = 0x0200000, 41556051948SVladimir Oltean .end = 0x021ffff, 41656051948SVladimir Oltean .name = "qsys", 41756051948SVladimir Oltean }, 41856051948SVladimir Oltean [REW] = { 41956051948SVladimir Oltean .start = 0x0030000, 42056051948SVladimir Oltean .end = 0x003ffff, 42156051948SVladimir Oltean .name = "rew", 42256051948SVladimir Oltean }, 42356051948SVladimir Oltean [SYS] = { 42456051948SVladimir Oltean .start = 0x0010000, 42556051948SVladimir Oltean .end = 0x001ffff, 42656051948SVladimir Oltean .name = "sys", 42756051948SVladimir Oltean }, 428e3aea296SVladimir Oltean [S0] = { 429e3aea296SVladimir Oltean .start = 0x0040000, 430e3aea296SVladimir Oltean .end = 0x00403ff, 431e3aea296SVladimir Oltean .name = "s0", 432e3aea296SVladimir Oltean }, 433a61e365dSVladimir Oltean [S1] = { 434a61e365dSVladimir Oltean .start = 0x0050000, 435a61e365dSVladimir Oltean .end = 0x00503ff, 436a61e365dSVladimir Oltean .name = "s1", 437a61e365dSVladimir Oltean }, 43856051948SVladimir Oltean [S2] = { 43956051948SVladimir Oltean .start = 0x0060000, 44056051948SVladimir Oltean .end = 0x00603ff, 44156051948SVladimir Oltean .name = "s2", 44256051948SVladimir Oltean }, 4435df66c48SYangbo Lu [PTP] = { 4445df66c48SYangbo Lu .start = 0x0090000, 4455df66c48SYangbo Lu .end = 0x00900cb, 4465df66c48SYangbo Lu .name = "ptp", 4475df66c48SYangbo Lu }, 44856051948SVladimir Oltean [GCB] = { 44956051948SVladimir Oltean .start = 0x0070000, 45056051948SVladimir Oltean .end = 0x00701ff, 45156051948SVladimir Oltean .name = "devcpu_gcb", 45256051948SVladimir Oltean }, 45356051948SVladimir Oltean }; 45456051948SVladimir Oltean 455b4024c9eSClaudiu Manoil static const struct resource vsc9959_port_io_res[] = { 45656051948SVladimir Oltean { 45756051948SVladimir Oltean .start = 0x0100000, 45856051948SVladimir Oltean .end = 0x010ffff, 45956051948SVladimir Oltean .name = "port0", 46056051948SVladimir Oltean }, 46156051948SVladimir Oltean { 46256051948SVladimir Oltean .start = 0x0110000, 46356051948SVladimir Oltean .end = 0x011ffff, 46456051948SVladimir Oltean .name = "port1", 46556051948SVladimir Oltean }, 46656051948SVladimir Oltean { 46756051948SVladimir Oltean .start = 0x0120000, 46856051948SVladimir Oltean .end = 0x012ffff, 46956051948SVladimir Oltean .name = "port2", 47056051948SVladimir Oltean }, 47156051948SVladimir Oltean { 47256051948SVladimir Oltean .start = 0x0130000, 47356051948SVladimir Oltean .end = 0x013ffff, 47456051948SVladimir Oltean .name = "port3", 47556051948SVladimir Oltean }, 47656051948SVladimir Oltean { 47756051948SVladimir Oltean .start = 0x0140000, 47856051948SVladimir Oltean .end = 0x014ffff, 47956051948SVladimir Oltean .name = "port4", 48056051948SVladimir Oltean }, 48156051948SVladimir Oltean { 48256051948SVladimir Oltean .start = 0x0150000, 48356051948SVladimir Oltean .end = 0x015ffff, 48456051948SVladimir Oltean .name = "port5", 48556051948SVladimir Oltean }, 48656051948SVladimir Oltean }; 48756051948SVladimir Oltean 488bdeced75SVladimir Oltean /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 489bdeced75SVladimir Oltean * SGMII/QSGMII MAC PCS can be found. 490bdeced75SVladimir Oltean */ 491b4024c9eSClaudiu Manoil static const struct resource vsc9959_imdio_res = { 492bdeced75SVladimir Oltean .start = 0x8030, 493bdeced75SVladimir Oltean .end = 0x8040, 494bdeced75SVladimir Oltean .name = "imdio", 495bdeced75SVladimir Oltean }; 496bdeced75SVladimir Oltean 4972789658fSMaxim Kochetkov static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 49856051948SVladimir Oltean [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 49956051948SVladimir Oltean [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 50056051948SVladimir Oltean [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 50156051948SVladimir Oltean [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 50256051948SVladimir Oltean [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 50356051948SVladimir Oltean [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 50456051948SVladimir Oltean [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 50556051948SVladimir Oltean [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 50656051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 50756051948SVladimir Oltean [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 50856051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 50956051948SVladimir Oltean [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 51056051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 51156051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 51256051948SVladimir Oltean [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 51356051948SVladimir Oltean [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 51456051948SVladimir Oltean [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 51556051948SVladimir Oltean [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 51656051948SVladimir Oltean [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 51756051948SVladimir Oltean [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 51856051948SVladimir Oltean [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 51956051948SVladimir Oltean [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 52056051948SVladimir Oltean [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 52156051948SVladimir Oltean [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 52256051948SVladimir Oltean [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 52356051948SVladimir Oltean [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 52456051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 52556051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 52656051948SVladimir Oltean [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 52756051948SVladimir Oltean [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 52856051948SVladimir Oltean [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 52956051948SVladimir Oltean [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 53056051948SVladimir Oltean [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 531886e1387SVladimir Oltean /* Replicated per number of ports (7), register size 4 per port */ 532886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 533886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 534886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 535886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 536886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 537886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 538886e1387SVladimir Oltean [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 539886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 540886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 541886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 542541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 543541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 544541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 54556051948SVladimir Oltean }; 54656051948SVladimir Oltean 54756051948SVladimir Oltean static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 54856051948SVladimir Oltean { .offset = 0x00, .name = "rx_octets", }, 54956051948SVladimir Oltean { .offset = 0x01, .name = "rx_unicast", }, 55056051948SVladimir Oltean { .offset = 0x02, .name = "rx_multicast", }, 55156051948SVladimir Oltean { .offset = 0x03, .name = "rx_broadcast", }, 55256051948SVladimir Oltean { .offset = 0x04, .name = "rx_shorts", }, 55356051948SVladimir Oltean { .offset = 0x05, .name = "rx_fragments", }, 55456051948SVladimir Oltean { .offset = 0x06, .name = "rx_jabbers", }, 55556051948SVladimir Oltean { .offset = 0x07, .name = "rx_crc_align_errs", }, 55656051948SVladimir Oltean { .offset = 0x08, .name = "rx_sym_errs", }, 55756051948SVladimir Oltean { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 55856051948SVladimir Oltean { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 55956051948SVladimir Oltean { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 56056051948SVladimir Oltean { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 56156051948SVladimir Oltean { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 56256051948SVladimir Oltean { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 56356051948SVladimir Oltean { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 56456051948SVladimir Oltean { .offset = 0x10, .name = "rx_pause", }, 56556051948SVladimir Oltean { .offset = 0x11, .name = "rx_control", }, 56656051948SVladimir Oltean { .offset = 0x12, .name = "rx_longs", }, 56756051948SVladimir Oltean { .offset = 0x13, .name = "rx_classified_drops", }, 56856051948SVladimir Oltean { .offset = 0x14, .name = "rx_red_prio_0", }, 56956051948SVladimir Oltean { .offset = 0x15, .name = "rx_red_prio_1", }, 57056051948SVladimir Oltean { .offset = 0x16, .name = "rx_red_prio_2", }, 57156051948SVladimir Oltean { .offset = 0x17, .name = "rx_red_prio_3", }, 57256051948SVladimir Oltean { .offset = 0x18, .name = "rx_red_prio_4", }, 57356051948SVladimir Oltean { .offset = 0x19, .name = "rx_red_prio_5", }, 57456051948SVladimir Oltean { .offset = 0x1A, .name = "rx_red_prio_6", }, 57556051948SVladimir Oltean { .offset = 0x1B, .name = "rx_red_prio_7", }, 57656051948SVladimir Oltean { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 57756051948SVladimir Oltean { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 57856051948SVladimir Oltean { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 57956051948SVladimir Oltean { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 58056051948SVladimir Oltean { .offset = 0x20, .name = "rx_yellow_prio_4", }, 58156051948SVladimir Oltean { .offset = 0x21, .name = "rx_yellow_prio_5", }, 58256051948SVladimir Oltean { .offset = 0x22, .name = "rx_yellow_prio_6", }, 58356051948SVladimir Oltean { .offset = 0x23, .name = "rx_yellow_prio_7", }, 58456051948SVladimir Oltean { .offset = 0x24, .name = "rx_green_prio_0", }, 58556051948SVladimir Oltean { .offset = 0x25, .name = "rx_green_prio_1", }, 58656051948SVladimir Oltean { .offset = 0x26, .name = "rx_green_prio_2", }, 58756051948SVladimir Oltean { .offset = 0x27, .name = "rx_green_prio_3", }, 58856051948SVladimir Oltean { .offset = 0x28, .name = "rx_green_prio_4", }, 58956051948SVladimir Oltean { .offset = 0x29, .name = "rx_green_prio_5", }, 59056051948SVladimir Oltean { .offset = 0x2A, .name = "rx_green_prio_6", }, 59156051948SVladimir Oltean { .offset = 0x2B, .name = "rx_green_prio_7", }, 59256051948SVladimir Oltean { .offset = 0x80, .name = "tx_octets", }, 59356051948SVladimir Oltean { .offset = 0x81, .name = "tx_unicast", }, 59456051948SVladimir Oltean { .offset = 0x82, .name = "tx_multicast", }, 59556051948SVladimir Oltean { .offset = 0x83, .name = "tx_broadcast", }, 59656051948SVladimir Oltean { .offset = 0x84, .name = "tx_collision", }, 59756051948SVladimir Oltean { .offset = 0x85, .name = "tx_drops", }, 59856051948SVladimir Oltean { .offset = 0x86, .name = "tx_pause", }, 59956051948SVladimir Oltean { .offset = 0x87, .name = "tx_frames_below_65_octets", }, 60056051948SVladimir Oltean { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, 60156051948SVladimir Oltean { .offset = 0x89, .name = "tx_frames_128_255_octets", }, 60256051948SVladimir Oltean { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, 60356051948SVladimir Oltean { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, 60456051948SVladimir Oltean { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, 60556051948SVladimir Oltean { .offset = 0x8E, .name = "tx_yellow_prio_0", }, 60656051948SVladimir Oltean { .offset = 0x8F, .name = "tx_yellow_prio_1", }, 60756051948SVladimir Oltean { .offset = 0x90, .name = "tx_yellow_prio_2", }, 60856051948SVladimir Oltean { .offset = 0x91, .name = "tx_yellow_prio_3", }, 60956051948SVladimir Oltean { .offset = 0x92, .name = "tx_yellow_prio_4", }, 61056051948SVladimir Oltean { .offset = 0x93, .name = "tx_yellow_prio_5", }, 61156051948SVladimir Oltean { .offset = 0x94, .name = "tx_yellow_prio_6", }, 61256051948SVladimir Oltean { .offset = 0x95, .name = "tx_yellow_prio_7", }, 61356051948SVladimir Oltean { .offset = 0x96, .name = "tx_green_prio_0", }, 61456051948SVladimir Oltean { .offset = 0x97, .name = "tx_green_prio_1", }, 61556051948SVladimir Oltean { .offset = 0x98, .name = "tx_green_prio_2", }, 61656051948SVladimir Oltean { .offset = 0x99, .name = "tx_green_prio_3", }, 61756051948SVladimir Oltean { .offset = 0x9A, .name = "tx_green_prio_4", }, 61856051948SVladimir Oltean { .offset = 0x9B, .name = "tx_green_prio_5", }, 61956051948SVladimir Oltean { .offset = 0x9C, .name = "tx_green_prio_6", }, 62056051948SVladimir Oltean { .offset = 0x9D, .name = "tx_green_prio_7", }, 62156051948SVladimir Oltean { .offset = 0x9E, .name = "tx_aged", }, 62256051948SVladimir Oltean { .offset = 0x100, .name = "drop_local", }, 62356051948SVladimir Oltean { .offset = 0x101, .name = "drop_tail", }, 62456051948SVladimir Oltean { .offset = 0x102, .name = "drop_yellow_prio_0", }, 62556051948SVladimir Oltean { .offset = 0x103, .name = "drop_yellow_prio_1", }, 62656051948SVladimir Oltean { .offset = 0x104, .name = "drop_yellow_prio_2", }, 62756051948SVladimir Oltean { .offset = 0x105, .name = "drop_yellow_prio_3", }, 62856051948SVladimir Oltean { .offset = 0x106, .name = "drop_yellow_prio_4", }, 62956051948SVladimir Oltean { .offset = 0x107, .name = "drop_yellow_prio_5", }, 63056051948SVladimir Oltean { .offset = 0x108, .name = "drop_yellow_prio_6", }, 63156051948SVladimir Oltean { .offset = 0x109, .name = "drop_yellow_prio_7", }, 63256051948SVladimir Oltean { .offset = 0x10A, .name = "drop_green_prio_0", }, 63356051948SVladimir Oltean { .offset = 0x10B, .name = "drop_green_prio_1", }, 63456051948SVladimir Oltean { .offset = 0x10C, .name = "drop_green_prio_2", }, 63556051948SVladimir Oltean { .offset = 0x10D, .name = "drop_green_prio_3", }, 63656051948SVladimir Oltean { .offset = 0x10E, .name = "drop_green_prio_4", }, 63756051948SVladimir Oltean { .offset = 0x10F, .name = "drop_green_prio_5", }, 63856051948SVladimir Oltean { .offset = 0x110, .name = "drop_green_prio_6", }, 63956051948SVladimir Oltean { .offset = 0x111, .name = "drop_green_prio_7", }, 64056051948SVladimir Oltean }; 64156051948SVladimir Oltean 642e3aea296SVladimir Oltean static const struct vcap_field vsc9959_vcap_es0_keys[] = { 643e3aea296SVladimir Oltean [VCAP_ES0_EGR_PORT] = { 0, 3}, 644e3aea296SVladimir Oltean [VCAP_ES0_IGR_PORT] = { 3, 3}, 645e3aea296SVladimir Oltean [VCAP_ES0_RSV] = { 6, 2}, 646e3aea296SVladimir Oltean [VCAP_ES0_L2_MC] = { 8, 1}, 647e3aea296SVladimir Oltean [VCAP_ES0_L2_BC] = { 9, 1}, 648e3aea296SVladimir Oltean [VCAP_ES0_VID] = { 10, 12}, 649e3aea296SVladimir Oltean [VCAP_ES0_DP] = { 22, 1}, 650e3aea296SVladimir Oltean [VCAP_ES0_PCP] = { 23, 3}, 651e3aea296SVladimir Oltean }; 652e3aea296SVladimir Oltean 653e3aea296SVladimir Oltean static const struct vcap_field vsc9959_vcap_es0_actions[] = { 654e3aea296SVladimir Oltean [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 655e3aea296SVladimir Oltean [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 656e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 657e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 658e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 659e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 660e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 661e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 662e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 663e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 664e3aea296SVladimir Oltean [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 665e3aea296SVladimir Oltean [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 666e3aea296SVladimir Oltean [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 667e3aea296SVladimir Oltean [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 668e3aea296SVladimir Oltean [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 669e3aea296SVladimir Oltean [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 670e3aea296SVladimir Oltean [VCAP_ES0_ACT_RSV] = { 49, 23}, 671e3aea296SVladimir Oltean [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 672e3aea296SVladimir Oltean }; 673e3aea296SVladimir Oltean 674a61e365dSVladimir Oltean static const struct vcap_field vsc9959_vcap_is1_keys[] = { 675a61e365dSVladimir Oltean [VCAP_IS1_HK_TYPE] = { 0, 1}, 676a61e365dSVladimir Oltean [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 677a61e365dSVladimir Oltean [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 678a61e365dSVladimir Oltean [VCAP_IS1_HK_RSV] = { 10, 9}, 679a61e365dSVladimir Oltean [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 680a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_MC] = { 20, 1}, 681a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_BC] = { 21, 1}, 682a61e365dSVladimir Oltean [VCAP_IS1_HK_IP_MC] = { 22, 1}, 683a61e365dSVladimir Oltean [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 684a61e365dSVladimir Oltean [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 685a61e365dSVladimir Oltean [VCAP_IS1_HK_TPID] = { 25, 1}, 686a61e365dSVladimir Oltean [VCAP_IS1_HK_VID] = { 26, 12}, 687a61e365dSVladimir Oltean [VCAP_IS1_HK_DEI] = { 38, 1}, 688a61e365dSVladimir Oltean [VCAP_IS1_HK_PCP] = { 39, 3}, 689a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_NORMAL */ 690a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 691a61e365dSVladimir Oltean [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 692a61e365dSVladimir Oltean [VCAP_IS1_HK_ETYPE] = { 91, 16}, 693a61e365dSVladimir Oltean [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 694a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4] = {108, 1}, 695a61e365dSVladimir Oltean /* Layer-3 Information */ 696a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 697a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 698a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 699a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 700a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 701a61e365dSVladimir Oltean /* Layer-4 Information */ 702a61e365dSVladimir Oltean [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 703a61e365dSVladimir Oltean [VCAP_IS1_HK_TCP] = {151, 1}, 704a61e365dSVladimir Oltean [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 705a61e365dSVladimir Oltean [VCAP_IS1_HK_L4_RNG] = {168, 8}, 706a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 707a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 708a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 709a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 710a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 711a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 712a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 713a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 714a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 715a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 716a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 717a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 718a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 719a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 720a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 721a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 722a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 723a61e365dSVladimir Oltean }; 724a61e365dSVladimir Oltean 725a61e365dSVladimir Oltean static const struct vcap_field vsc9959_vcap_is1_actions[] = { 726a61e365dSVladimir Oltean [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 727a61e365dSVladimir Oltean [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 728a61e365dSVladimir Oltean [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 729a61e365dSVladimir Oltean [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 730a61e365dSVladimir Oltean [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 731a61e365dSVladimir Oltean [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 732a61e365dSVladimir Oltean [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 733a61e365dSVladimir Oltean [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 734a61e365dSVladimir Oltean [VCAP_IS1_ACT_RSV] = { 29, 9}, 73575944fdaSXiaoliang Yang /* The fields below are incorrectly shifted by 2 in the manual */ 736a61e365dSVladimir Oltean [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 737a61e365dSVladimir Oltean [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 738a61e365dSVladimir Oltean [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 739a61e365dSVladimir Oltean [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 740a61e365dSVladimir Oltean [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 741a61e365dSVladimir Oltean [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 742a61e365dSVladimir Oltean [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 743a61e365dSVladimir Oltean [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 744a61e365dSVladimir Oltean [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 745a61e365dSVladimir Oltean [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 746a61e365dSVladimir Oltean [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 747a61e365dSVladimir Oltean }; 748a61e365dSVladimir Oltean 7493ab4ceb6SVladimir Oltean static struct vcap_field vsc9959_vcap_is2_keys[] = { 75007d985eeSVladimir Oltean /* Common: 41 bits */ 75107d985eeSVladimir Oltean [VCAP_IS2_TYPE] = { 0, 4}, 75207d985eeSVladimir Oltean [VCAP_IS2_HK_FIRST] = { 4, 1}, 75307d985eeSVladimir Oltean [VCAP_IS2_HK_PAG] = { 5, 8}, 75407d985eeSVladimir Oltean [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 75507d985eeSVladimir Oltean [VCAP_IS2_HK_RSV2] = { 20, 1}, 75607d985eeSVladimir Oltean [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 75707d985eeSVladimir Oltean [VCAP_IS2_HK_L2_MC] = { 22, 1}, 75807d985eeSVladimir Oltean [VCAP_IS2_HK_L2_BC] = { 23, 1}, 75907d985eeSVladimir Oltean [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 76007d985eeSVladimir Oltean [VCAP_IS2_HK_VID] = { 25, 12}, 76107d985eeSVladimir Oltean [VCAP_IS2_HK_DEI] = { 37, 1}, 76207d985eeSVladimir Oltean [VCAP_IS2_HK_PCP] = { 38, 3}, 76307d985eeSVladimir Oltean /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 76407d985eeSVladimir Oltean [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 76507d985eeSVladimir Oltean [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 76607d985eeSVladimir Oltean /* MAC_ETYPE (TYPE=000) */ 76707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 76807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 76907d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 77007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 77107d985eeSVladimir Oltean /* MAC_LLC (TYPE=001) */ 77207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 77307d985eeSVladimir Oltean /* MAC_SNAP (TYPE=010) */ 77407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 77507d985eeSVladimir Oltean /* MAC_ARP (TYPE=011) */ 77607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 77707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 77807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 77907d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 78007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 78107d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 78207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 78307d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 78407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 78507d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 78607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 78707d985eeSVladimir Oltean /* IP4_TCP_UDP / IP4_OTHER common */ 78807d985eeSVladimir Oltean [VCAP_IS2_HK_IP4] = { 41, 1}, 78907d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 79007d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 79107d985eeSVladimir Oltean [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 79207d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 79307d985eeSVladimir Oltean [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 79407d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 79507d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 79607d985eeSVladimir Oltean [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 79707d985eeSVladimir Oltean /* IP4_TCP_UDP (TYPE=100) */ 79807d985eeSVladimir Oltean [VCAP_IS2_HK_TCP] = {119, 1}, 7998b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 8008b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 80107d985eeSVladimir Oltean [VCAP_IS2_HK_L4_RNG] = {152, 8}, 80207d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 80307d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 8048b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_FIN] = {162, 1}, 8058b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_SYN] = {163, 1}, 8068b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_RST] = {164, 1}, 8078b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_PSH] = {165, 1}, 8088b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_ACK] = {166, 1}, 8098b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_URG] = {167, 1}, 81007d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 81107d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 81207d985eeSVladimir Oltean /* IP4_OTHER (TYPE=101) */ 81307d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 81407d985eeSVladimir Oltean [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 81507d985eeSVladimir Oltean /* IP6_STD (TYPE=110) */ 81607d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 81707d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 81807d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 81907d985eeSVladimir Oltean /* OAM (TYPE=111) */ 82007d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 82107d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_VER] = {144, 5}, 82207d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 82307d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 82407d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 82507d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 82607d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 82707d985eeSVladimir Oltean }; 82807d985eeSVladimir Oltean 8293ab4ceb6SVladimir Oltean static struct vcap_field vsc9959_vcap_is2_actions[] = { 83007d985eeSVladimir Oltean [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 83107d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 83207d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 83307d985eeSVladimir Oltean [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 83407d985eeSVladimir Oltean [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 83507d985eeSVladimir Oltean [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 83607d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 83707d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 83807d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 839460e985eSVladimir Oltean [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 840460e985eSVladimir Oltean [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 841460e985eSVladimir Oltean [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 842460e985eSVladimir Oltean [VCAP_IS2_ACT_RSV] = { 36, 2}, 843460e985eSVladimir Oltean [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 844460e985eSVladimir Oltean [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 84507d985eeSVladimir Oltean }; 84607d985eeSVladimir Oltean 84720968054SVladimir Oltean static struct vcap_props vsc9959_vcap_props[] = { 848e3aea296SVladimir Oltean [VCAP_ES0] = { 849e3aea296SVladimir Oltean .action_type_width = 0, 850e3aea296SVladimir Oltean .action_table = { 851e3aea296SVladimir Oltean [ES0_ACTION_TYPE_NORMAL] = { 852e3aea296SVladimir Oltean .width = 72, /* HIT_STICKY not included */ 853e3aea296SVladimir Oltean .count = 1, 854e3aea296SVladimir Oltean }, 855e3aea296SVladimir Oltean }, 856e3aea296SVladimir Oltean .target = S0, 857e3aea296SVladimir Oltean .keys = vsc9959_vcap_es0_keys, 858e3aea296SVladimir Oltean .actions = vsc9959_vcap_es0_actions, 859e3aea296SVladimir Oltean }, 860a61e365dSVladimir Oltean [VCAP_IS1] = { 861a61e365dSVladimir Oltean .action_type_width = 0, 862a61e365dSVladimir Oltean .action_table = { 863a61e365dSVladimir Oltean [IS1_ACTION_TYPE_NORMAL] = { 864a61e365dSVladimir Oltean .width = 78, /* HIT_STICKY not included */ 865a61e365dSVladimir Oltean .count = 4, 866a61e365dSVladimir Oltean }, 867a61e365dSVladimir Oltean }, 868a61e365dSVladimir Oltean .target = S1, 869a61e365dSVladimir Oltean .keys = vsc9959_vcap_is1_keys, 870a61e365dSVladimir Oltean .actions = vsc9959_vcap_is1_actions, 871a61e365dSVladimir Oltean }, 87207d985eeSVladimir Oltean [VCAP_IS2] = { 87307d985eeSVladimir Oltean .action_type_width = 1, 87407d985eeSVladimir Oltean .action_table = { 87507d985eeSVladimir Oltean [IS2_ACTION_TYPE_NORMAL] = { 87607d985eeSVladimir Oltean .width = 44, 87707d985eeSVladimir Oltean .count = 2 87807d985eeSVladimir Oltean }, 87907d985eeSVladimir Oltean [IS2_ACTION_TYPE_SMAC_SIP] = { 88007d985eeSVladimir Oltean .width = 6, 88107d985eeSVladimir Oltean .count = 4 88207d985eeSVladimir Oltean }, 88307d985eeSVladimir Oltean }, 884c1c3993eSVladimir Oltean .target = S2, 885c1c3993eSVladimir Oltean .keys = vsc9959_vcap_is2_keys, 886c1c3993eSVladimir Oltean .actions = vsc9959_vcap_is2_actions, 88707d985eeSVladimir Oltean }, 88807d985eeSVladimir Oltean }; 88907d985eeSVladimir Oltean 8902ac7c6c5SVladimir Oltean static const struct ptp_clock_info vsc9959_ptp_caps = { 8912ac7c6c5SVladimir Oltean .owner = THIS_MODULE, 8922ac7c6c5SVladimir Oltean .name = "felix ptp", 8932ac7c6c5SVladimir Oltean .max_adj = 0x7fffffff, 8942ac7c6c5SVladimir Oltean .n_alarm = 0, 8952ac7c6c5SVladimir Oltean .n_ext_ts = 0, 8962ac7c6c5SVladimir Oltean .n_per_out = OCELOT_PTP_PINS_NUM, 8972ac7c6c5SVladimir Oltean .n_pins = OCELOT_PTP_PINS_NUM, 8982ac7c6c5SVladimir Oltean .pps = 0, 8992ac7c6c5SVladimir Oltean .gettime64 = ocelot_ptp_gettime64, 9002ac7c6c5SVladimir Oltean .settime64 = ocelot_ptp_settime64, 9012ac7c6c5SVladimir Oltean .adjtime = ocelot_ptp_adjtime, 9022ac7c6c5SVladimir Oltean .adjfine = ocelot_ptp_adjfine, 9032ac7c6c5SVladimir Oltean .verify = ocelot_ptp_verify, 9042ac7c6c5SVladimir Oltean .enable = ocelot_ptp_enable, 9052ac7c6c5SVladimir Oltean }; 9062ac7c6c5SVladimir Oltean 90756051948SVladimir Oltean #define VSC9959_INIT_TIMEOUT 50000 90856051948SVladimir Oltean #define VSC9959_GCB_RST_SLEEP 100 90956051948SVladimir Oltean #define VSC9959_SYS_RAMINIT_SLEEP 80 91056051948SVladimir Oltean 91156051948SVladimir Oltean static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 91256051948SVladimir Oltean { 91356051948SVladimir Oltean int val; 91456051948SVladimir Oltean 91575cea9cbSVladimir Oltean ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 91656051948SVladimir Oltean 91756051948SVladimir Oltean return val; 91856051948SVladimir Oltean } 91956051948SVladimir Oltean 92056051948SVladimir Oltean static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 92156051948SVladimir Oltean { 92256051948SVladimir Oltean return ocelot_read(ocelot, SYS_RAM_INIT); 92356051948SVladimir Oltean } 92456051948SVladimir Oltean 925c129fc55SVladimir Oltean /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 926c129fc55SVladimir Oltean * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 927c129fc55SVladimir Oltean */ 92856051948SVladimir Oltean static int vsc9959_reset(struct ocelot *ocelot) 92956051948SVladimir Oltean { 93056051948SVladimir Oltean int val, err; 93156051948SVladimir Oltean 93256051948SVladimir Oltean /* soft-reset the switch core */ 93375cea9cbSVladimir Oltean ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 93456051948SVladimir Oltean 93556051948SVladimir Oltean err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 93656051948SVladimir Oltean VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 93756051948SVladimir Oltean if (err) { 93856051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch core reset\n"); 93956051948SVladimir Oltean return err; 94056051948SVladimir Oltean } 94156051948SVladimir Oltean 94256051948SVladimir Oltean /* initialize switch mem ~40us */ 94356051948SVladimir Oltean ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 94456051948SVladimir Oltean err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 94556051948SVladimir Oltean VSC9959_SYS_RAMINIT_SLEEP, 94656051948SVladimir Oltean VSC9959_INIT_TIMEOUT); 94756051948SVladimir Oltean if (err) { 94856051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch sram init\n"); 94956051948SVladimir Oltean return err; 95056051948SVladimir Oltean } 95156051948SVladimir Oltean 95256051948SVladimir Oltean /* enable switch core */ 95375cea9cbSVladimir Oltean ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 95456051948SVladimir Oltean 95556051948SVladimir Oltean return 0; 95656051948SVladimir Oltean } 95756051948SVladimir Oltean 958375e1314SVladimir Oltean static void vsc9959_phylink_validate(struct ocelot *ocelot, int port, 959375e1314SVladimir Oltean unsigned long *supported, 960375e1314SVladimir Oltean struct phylink_link_state *state) 961375e1314SVladimir Oltean { 962375e1314SVladimir Oltean __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 963375e1314SVladimir Oltean 964375e1314SVladimir Oltean phylink_set_port_modes(mask); 965375e1314SVladimir Oltean phylink_set(mask, Autoneg); 966375e1314SVladimir Oltean phylink_set(mask, Pause); 967375e1314SVladimir Oltean phylink_set(mask, Asym_Pause); 968375e1314SVladimir Oltean phylink_set(mask, 10baseT_Half); 969375e1314SVladimir Oltean phylink_set(mask, 10baseT_Full); 970375e1314SVladimir Oltean phylink_set(mask, 100baseT_Half); 971375e1314SVladimir Oltean phylink_set(mask, 100baseT_Full); 972375e1314SVladimir Oltean phylink_set(mask, 1000baseT_Half); 973375e1314SVladimir Oltean phylink_set(mask, 1000baseT_Full); 974375e1314SVladimir Oltean 975375e1314SVladimir Oltean if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 976375e1314SVladimir Oltean state->interface == PHY_INTERFACE_MODE_2500BASEX || 977375e1314SVladimir Oltean state->interface == PHY_INTERFACE_MODE_USXGMII) { 978375e1314SVladimir Oltean phylink_set(mask, 2500baseT_Full); 979375e1314SVladimir Oltean phylink_set(mask, 2500baseX_Full); 980375e1314SVladimir Oltean } 981375e1314SVladimir Oltean 9824973056cSSean Anderson linkmode_and(supported, supported, mask); 9834973056cSSean Anderson linkmode_and(state->advertising, state->advertising, mask); 984375e1314SVladimir Oltean } 985375e1314SVladimir Oltean 986aa92d836SMaxim Kochetkov /* Watermark encode 987aa92d836SMaxim Kochetkov * Bit 8: Unit; 0:1, 1:16 988aa92d836SMaxim Kochetkov * Bit 7-0: Value to be multiplied with unit 989aa92d836SMaxim Kochetkov */ 990aa92d836SMaxim Kochetkov static u16 vsc9959_wm_enc(u16 value) 991aa92d836SMaxim Kochetkov { 99201326493SVladimir Oltean WARN_ON(value >= 16 * BIT(8)); 99301326493SVladimir Oltean 994aa92d836SMaxim Kochetkov if (value >= BIT(8)) 995aa92d836SMaxim Kochetkov return BIT(8) | (value / 16); 996aa92d836SMaxim Kochetkov 997aa92d836SMaxim Kochetkov return value; 998aa92d836SMaxim Kochetkov } 999aa92d836SMaxim Kochetkov 1000703b7621SVladimir Oltean static u16 vsc9959_wm_dec(u16 wm) 1001703b7621SVladimir Oltean { 1002703b7621SVladimir Oltean WARN_ON(wm & ~GENMASK(8, 0)); 1003703b7621SVladimir Oltean 1004703b7621SVladimir Oltean if (wm & BIT(8)) 1005703b7621SVladimir Oltean return (wm & GENMASK(7, 0)) * 16; 1006703b7621SVladimir Oltean 1007703b7621SVladimir Oltean return wm; 1008703b7621SVladimir Oltean } 1009703b7621SVladimir Oltean 1010703b7621SVladimir Oltean static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 1011703b7621SVladimir Oltean { 1012703b7621SVladimir Oltean *inuse = (val & GENMASK(23, 12)) >> 12; 1013703b7621SVladimir Oltean *maxuse = val & GENMASK(11, 0); 1014703b7621SVladimir Oltean } 1015703b7621SVladimir Oltean 1016bdeced75SVladimir Oltean static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 1017bdeced75SVladimir Oltean { 1018bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1019bdeced75SVladimir Oltean struct enetc_mdio_priv *mdio_priv; 1020bdeced75SVladimir Oltean struct device *dev = ocelot->dev; 1021bdeced75SVladimir Oltean void __iomem *imdio_regs; 1022b4024c9eSClaudiu Manoil struct resource res; 1023bdeced75SVladimir Oltean struct enetc_hw *hw; 1024bdeced75SVladimir Oltean struct mii_bus *bus; 1025bdeced75SVladimir Oltean int port; 1026bdeced75SVladimir Oltean int rc; 1027bdeced75SVladimir Oltean 1028bdeced75SVladimir Oltean felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 1029e7026f15SColin Foster sizeof(struct phylink_pcs *), 1030bdeced75SVladimir Oltean GFP_KERNEL); 1031bdeced75SVladimir Oltean if (!felix->pcs) { 1032bdeced75SVladimir Oltean dev_err(dev, "failed to allocate array for PCS PHYs\n"); 1033bdeced75SVladimir Oltean return -ENOMEM; 1034bdeced75SVladimir Oltean } 1035bdeced75SVladimir Oltean 1036b4024c9eSClaudiu Manoil memcpy(&res, felix->info->imdio_res, sizeof(res)); 1037b4024c9eSClaudiu Manoil res.flags = IORESOURCE_MEM; 1038375e1314SVladimir Oltean res.start += felix->imdio_base; 1039375e1314SVladimir Oltean res.end += felix->imdio_base; 1040bdeced75SVladimir Oltean 1041b4024c9eSClaudiu Manoil imdio_regs = devm_ioremap_resource(dev, &res); 1042a180be79SGuobin Huang if (IS_ERR(imdio_regs)) 1043bdeced75SVladimir Oltean return PTR_ERR(imdio_regs); 1044bdeced75SVladimir Oltean 1045bdeced75SVladimir Oltean hw = enetc_hw_alloc(dev, imdio_regs); 1046bdeced75SVladimir Oltean if (IS_ERR(hw)) { 1047bdeced75SVladimir Oltean dev_err(dev, "failed to allocate ENETC HW structure\n"); 1048bdeced75SVladimir Oltean return PTR_ERR(hw); 1049bdeced75SVladimir Oltean } 1050bdeced75SVladimir Oltean 1051209bdb7eSVladimir Oltean bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 1052bdeced75SVladimir Oltean if (!bus) 1053bdeced75SVladimir Oltean return -ENOMEM; 1054bdeced75SVladimir Oltean 1055bdeced75SVladimir Oltean bus->name = "VSC9959 internal MDIO bus"; 1056bdeced75SVladimir Oltean bus->read = enetc_mdio_read; 1057bdeced75SVladimir Oltean bus->write = enetc_mdio_write; 1058bdeced75SVladimir Oltean bus->parent = dev; 1059bdeced75SVladimir Oltean mdio_priv = bus->priv; 1060bdeced75SVladimir Oltean mdio_priv->hw = hw; 1061bdeced75SVladimir Oltean /* This gets added to imdio_regs, which already maps addresses 1062bdeced75SVladimir Oltean * starting with the proper offset. 1063bdeced75SVladimir Oltean */ 1064bdeced75SVladimir Oltean mdio_priv->mdio_base = 0; 1065bdeced75SVladimir Oltean snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1066bdeced75SVladimir Oltean 1067bdeced75SVladimir Oltean /* Needed in order to initialize the bus mutex lock */ 1068bdeced75SVladimir Oltean rc = mdiobus_register(bus); 1069bdeced75SVladimir Oltean if (rc < 0) { 1070bdeced75SVladimir Oltean dev_err(dev, "failed to register MDIO bus\n"); 1071209bdb7eSVladimir Oltean mdiobus_free(bus); 1072bdeced75SVladimir Oltean return rc; 1073bdeced75SVladimir Oltean } 1074bdeced75SVladimir Oltean 1075bdeced75SVladimir Oltean felix->imdio = bus; 1076bdeced75SVladimir Oltean 1077bdeced75SVladimir Oltean for (port = 0; port < felix->info->num_ports; port++) { 1078bdeced75SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 1079e7026f15SColin Foster struct phylink_pcs *phylink_pcs; 108061f0d0c3SColin Foster struct mdio_device *mdio_device; 1081bdeced75SVladimir Oltean 1082588d0550SIoana Ciornei if (dsa_is_unused_port(felix->ds, port)) 1083588d0550SIoana Ciornei continue; 1084bdeced75SVladimir Oltean 1085588d0550SIoana Ciornei if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1086588d0550SIoana Ciornei continue; 1087588d0550SIoana Ciornei 108861f0d0c3SColin Foster mdio_device = mdio_device_create(felix->imdio, port); 108961f0d0c3SColin Foster if (IS_ERR(mdio_device)) 1090bdeced75SVladimir Oltean continue; 1091bdeced75SVladimir Oltean 109261f0d0c3SColin Foster phylink_pcs = lynx_pcs_create(mdio_device); 1093e7026f15SColin Foster if (!phylink_pcs) { 109461f0d0c3SColin Foster mdio_device_free(mdio_device); 1095588d0550SIoana Ciornei continue; 1096588d0550SIoana Ciornei } 1097588d0550SIoana Ciornei 1098e7026f15SColin Foster felix->pcs[port] = phylink_pcs; 1099bdeced75SVladimir Oltean 1100bdeced75SVladimir Oltean dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1101bdeced75SVladimir Oltean } 1102bdeced75SVladimir Oltean 1103bdeced75SVladimir Oltean return 0; 1104bdeced75SVladimir Oltean } 1105bdeced75SVladimir Oltean 1106ccfdbab5SVladimir Oltean static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1107bdeced75SVladimir Oltean { 1108bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1109bdeced75SVladimir Oltean int port; 1110bdeced75SVladimir Oltean 1111bdeced75SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) { 1112e7026f15SColin Foster struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1113e7026f15SColin Foster struct mdio_device *mdio_device; 1114bdeced75SVladimir Oltean 1115e7026f15SColin Foster if (!phylink_pcs) 1116bdeced75SVladimir Oltean continue; 1117bdeced75SVladimir Oltean 1118e7026f15SColin Foster mdio_device = lynx_get_mdio_device(phylink_pcs); 1119e7026f15SColin Foster mdio_device_free(mdio_device); 1120e7026f15SColin Foster lynx_pcs_destroy(phylink_pcs); 1121bdeced75SVladimir Oltean } 1122bdeced75SVladimir Oltean mdiobus_unregister(felix->imdio); 1123209bdb7eSVladimir Oltean mdiobus_free(felix->imdio); 1124bdeced75SVladimir Oltean } 1125bdeced75SVladimir Oltean 1126de143c0eSXiaoliang Yang static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1127de143c0eSXiaoliang Yang u32 speed) 1128de143c0eSXiaoliang Yang { 1129dba1e466SXiaoliang Yang u8 tas_speed; 1130dba1e466SXiaoliang Yang 1131dba1e466SXiaoliang Yang switch (speed) { 1132dba1e466SXiaoliang Yang case SPEED_10: 1133dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_10; 1134dba1e466SXiaoliang Yang break; 1135dba1e466SXiaoliang Yang case SPEED_100: 1136dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_100; 1137dba1e466SXiaoliang Yang break; 1138dba1e466SXiaoliang Yang case SPEED_1000: 1139dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_1000; 1140dba1e466SXiaoliang Yang break; 1141dba1e466SXiaoliang Yang case SPEED_2500: 1142dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_2500; 1143dba1e466SXiaoliang Yang break; 1144dba1e466SXiaoliang Yang default: 1145dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_1000; 1146dba1e466SXiaoliang Yang break; 1147dba1e466SXiaoliang Yang } 1148dba1e466SXiaoliang Yang 1149de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1150dba1e466SXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1151de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED_M, 1152de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1153de143c0eSXiaoliang Yang } 1154de143c0eSXiaoliang Yang 1155de143c0eSXiaoliang Yang static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1156de143c0eSXiaoliang Yang u64 cycle_time, 1157de143c0eSXiaoliang Yang struct timespec64 *new_base_ts) 1158de143c0eSXiaoliang Yang { 1159de143c0eSXiaoliang Yang struct timespec64 ts; 1160de143c0eSXiaoliang Yang ktime_t new_base_time; 1161de143c0eSXiaoliang Yang ktime_t current_time; 1162de143c0eSXiaoliang Yang 1163de143c0eSXiaoliang Yang ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1164de143c0eSXiaoliang Yang current_time = timespec64_to_ktime(ts); 1165de143c0eSXiaoliang Yang new_base_time = base_time; 1166de143c0eSXiaoliang Yang 1167de143c0eSXiaoliang Yang if (base_time < current_time) { 1168de143c0eSXiaoliang Yang u64 nr_of_cycles = current_time - base_time; 1169de143c0eSXiaoliang Yang 1170de143c0eSXiaoliang Yang do_div(nr_of_cycles, cycle_time); 1171de143c0eSXiaoliang Yang new_base_time += cycle_time * (nr_of_cycles + 1); 1172de143c0eSXiaoliang Yang } 1173de143c0eSXiaoliang Yang 1174de143c0eSXiaoliang Yang *new_base_ts = ktime_to_timespec64(new_base_time); 1175de143c0eSXiaoliang Yang } 1176de143c0eSXiaoliang Yang 1177de143c0eSXiaoliang Yang static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1178de143c0eSXiaoliang Yang { 1179de143c0eSXiaoliang Yang return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1180de143c0eSXiaoliang Yang } 1181de143c0eSXiaoliang Yang 1182de143c0eSXiaoliang Yang static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1183de143c0eSXiaoliang Yang struct tc_taprio_sched_entry *entry) 1184de143c0eSXiaoliang Yang { 1185de143c0eSXiaoliang Yang ocelot_write(ocelot, 1186de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1187de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1188de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1); 1189de143c0eSXiaoliang Yang ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1190de143c0eSXiaoliang Yang } 1191de143c0eSXiaoliang Yang 1192de143c0eSXiaoliang Yang static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1193de143c0eSXiaoliang Yang struct tc_taprio_qopt_offload *taprio) 1194de143c0eSXiaoliang Yang { 1195de143c0eSXiaoliang Yang struct timespec64 base_ts; 1196de143c0eSXiaoliang Yang int ret, i; 1197de143c0eSXiaoliang Yang u32 val; 1198de143c0eSXiaoliang Yang 1199de143c0eSXiaoliang Yang if (!taprio->enable) { 1200de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1201de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF), 1202de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1203de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE_M, 1204de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1205de143c0eSXiaoliang Yang 1206de143c0eSXiaoliang Yang return 0; 1207de143c0eSXiaoliang Yang } 1208de143c0eSXiaoliang Yang 1209de143c0eSXiaoliang Yang if (taprio->cycle_time > NSEC_PER_SEC || 1210de143c0eSXiaoliang Yang taprio->cycle_time_extension >= NSEC_PER_SEC) 1211de143c0eSXiaoliang Yang return -EINVAL; 1212de143c0eSXiaoliang Yang 1213de143c0eSXiaoliang Yang if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) 1214de143c0eSXiaoliang Yang return -ERANGE; 1215de143c0eSXiaoliang Yang 1216297c4de6SMichael Walle /* Enable guard band. The switch will schedule frames without taking 1217297c4de6SMichael Walle * their length into account. Thus we'll always need to enable the 1218297c4de6SMichael Walle * guard band which reserves the time of a maximum sized frame at the 1219297c4de6SMichael Walle * end of the time window. 1220297c4de6SMichael Walle * 1221297c4de6SMichael Walle * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1222297c4de6SMichael Walle * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1223297c4de6SMichael Walle * operate on the port number. 1224316bcffeSXiaoliang Yang */ 1225297c4de6SMichael Walle ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1226297c4de6SMichael Walle QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1227de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1228de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1229de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 1230de143c0eSXiaoliang Yang 1231de143c0eSXiaoliang Yang /* Hardware errata - Admin config could not be overwritten if 1232de143c0eSXiaoliang Yang * config is pending, need reset the TAS module 1233de143c0eSXiaoliang Yang */ 1234de143c0eSXiaoliang Yang val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1235de143c0eSXiaoliang Yang if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) 1236de143c0eSXiaoliang Yang return -EBUSY; 1237de143c0eSXiaoliang Yang 1238de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1239de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1240de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1241de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1242de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1243de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1244de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1245de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1246de143c0eSXiaoliang Yang 1247de143c0eSXiaoliang Yang vsc9959_new_base_time(ocelot, taprio->base_time, 1248de143c0eSXiaoliang Yang taprio->cycle_time, &base_ts); 1249de143c0eSXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1250de143c0eSXiaoliang Yang ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1251de143c0eSXiaoliang Yang val = upper_32_bits(base_ts.tv_sec); 1252de143c0eSXiaoliang Yang ocelot_write(ocelot, 1253de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1254de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1255de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3); 1256de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1257de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1258de143c0eSXiaoliang Yang 1259de143c0eSXiaoliang Yang for (i = 0; i < taprio->num_entries; i++) 1260de143c0eSXiaoliang Yang vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1261de143c0eSXiaoliang Yang 1262de143c0eSXiaoliang Yang ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1263de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1264de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 1265de143c0eSXiaoliang Yang 1266de143c0eSXiaoliang Yang ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1267de143c0eSXiaoliang Yang !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1268de143c0eSXiaoliang Yang 10, 100000); 1269de143c0eSXiaoliang Yang 1270de143c0eSXiaoliang Yang return ret; 1271de143c0eSXiaoliang Yang } 1272de143c0eSXiaoliang Yang 12730fbabf87SXiaoliang Yang static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 12740fbabf87SXiaoliang Yang struct tc_cbs_qopt_offload *cbs_qopt) 12750fbabf87SXiaoliang Yang { 12760fbabf87SXiaoliang Yang struct ocelot *ocelot = ds->priv; 12770fbabf87SXiaoliang Yang int port_ix = port * 8 + cbs_qopt->queue; 12780fbabf87SXiaoliang Yang u32 rate, burst; 12790fbabf87SXiaoliang Yang 12800fbabf87SXiaoliang Yang if (cbs_qopt->queue >= ds->num_tx_queues) 12810fbabf87SXiaoliang Yang return -EINVAL; 12820fbabf87SXiaoliang Yang 12830fbabf87SXiaoliang Yang if (!cbs_qopt->enable) { 12840fbabf87SXiaoliang Yang ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 12850fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(0), 12860fbabf87SXiaoliang Yang QSYS_CIR_CFG, port_ix); 12870fbabf87SXiaoliang Yang 12880fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 12890fbabf87SXiaoliang Yang QSYS_SE_CFG, port_ix); 12900fbabf87SXiaoliang Yang 12910fbabf87SXiaoliang Yang return 0; 12920fbabf87SXiaoliang Yang } 12930fbabf87SXiaoliang Yang 12940fbabf87SXiaoliang Yang /* Rate unit is 100 kbps */ 12950fbabf87SXiaoliang Yang rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 12960fbabf87SXiaoliang Yang /* Avoid using zero rate */ 12970fbabf87SXiaoliang Yang rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 12980fbabf87SXiaoliang Yang /* Burst unit is 4kB */ 12990fbabf87SXiaoliang Yang burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 13000fbabf87SXiaoliang Yang /* Avoid using zero burst size */ 1301b014d043SColin Ian King burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 13020fbabf87SXiaoliang Yang ocelot_write_gix(ocelot, 13030fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_RATE(rate) | 13040fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(burst), 13050fbabf87SXiaoliang Yang QSYS_CIR_CFG, 13060fbabf87SXiaoliang Yang port_ix); 13070fbabf87SXiaoliang Yang 13080fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot, 13090fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE(0) | 13100fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA, 13110fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA | 13120fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE_M, 13130fbabf87SXiaoliang Yang QSYS_SE_CFG, 13140fbabf87SXiaoliang Yang port_ix); 13150fbabf87SXiaoliang Yang 13160fbabf87SXiaoliang Yang return 0; 13170fbabf87SXiaoliang Yang } 13180fbabf87SXiaoliang Yang 1319de143c0eSXiaoliang Yang static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1320de143c0eSXiaoliang Yang enum tc_setup_type type, 1321de143c0eSXiaoliang Yang void *type_data) 1322de143c0eSXiaoliang Yang { 1323de143c0eSXiaoliang Yang struct ocelot *ocelot = ds->priv; 1324de143c0eSXiaoliang Yang 1325de143c0eSXiaoliang Yang switch (type) { 1326de143c0eSXiaoliang Yang case TC_SETUP_QDISC_TAPRIO: 1327de143c0eSXiaoliang Yang return vsc9959_qos_port_tas_set(ocelot, port, type_data); 13280fbabf87SXiaoliang Yang case TC_SETUP_QDISC_CBS: 13290fbabf87SXiaoliang Yang return vsc9959_qos_port_cbs_set(ds, port, type_data); 1330de143c0eSXiaoliang Yang default: 1331de143c0eSXiaoliang Yang return -EOPNOTSUPP; 1332de143c0eSXiaoliang Yang } 1333de143c0eSXiaoliang Yang } 1334de143c0eSXiaoliang Yang 13357d4b564dSXiaoliang Yang #define VSC9959_PSFP_SFID_MAX 175 13367d4b564dSXiaoliang Yang #define VSC9959_PSFP_GATE_ID_MAX 183 133776c13edeSXiaoliang Yang #define VSC9959_PSFP_POLICER_BASE 63 13387d4b564dSXiaoliang Yang #define VSC9959_PSFP_POLICER_MAX 383 133923ae3a78SXiaoliang Yang #define VSC9959_PSFP_GATE_LIST_NUM 4 134023ae3a78SXiaoliang Yang #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 13417d4b564dSXiaoliang Yang 13427d4b564dSXiaoliang Yang struct felix_stream { 13437d4b564dSXiaoliang Yang struct list_head list; 13447d4b564dSXiaoliang Yang unsigned long id; 1345a7e13edfSXiaoliang Yang bool dummy; 1346a7e13edfSXiaoliang Yang int ports; 1347a7e13edfSXiaoliang Yang int port; 13487d4b564dSXiaoliang Yang u8 dmac[ETH_ALEN]; 13497d4b564dSXiaoliang Yang u16 vid; 13507d4b564dSXiaoliang Yang s8 prio; 13517d4b564dSXiaoliang Yang u8 sfid_valid; 13527d4b564dSXiaoliang Yang u8 ssid_valid; 13537d4b564dSXiaoliang Yang u32 sfid; 13547d4b564dSXiaoliang Yang u32 ssid; 13557d4b564dSXiaoliang Yang }; 13567d4b564dSXiaoliang Yang 13577d4b564dSXiaoliang Yang struct felix_stream_filter { 13587d4b564dSXiaoliang Yang struct list_head list; 13597d4b564dSXiaoliang Yang refcount_t refcount; 13607d4b564dSXiaoliang Yang u32 index; 13617d4b564dSXiaoliang Yang u8 enable; 1362a7e13edfSXiaoliang Yang int portmask; 13637d4b564dSXiaoliang Yang u8 sg_valid; 13647d4b564dSXiaoliang Yang u32 sgid; 13657d4b564dSXiaoliang Yang u8 fm_valid; 13667d4b564dSXiaoliang Yang u32 fmid; 13677d4b564dSXiaoliang Yang u8 prio_valid; 13687d4b564dSXiaoliang Yang u8 prio; 13697d4b564dSXiaoliang Yang u32 maxsdu; 13707d4b564dSXiaoliang Yang }; 13717d4b564dSXiaoliang Yang 13727d4b564dSXiaoliang Yang struct felix_stream_filter_counters { 13737d4b564dSXiaoliang Yang u32 match; 13747d4b564dSXiaoliang Yang u32 not_pass_gate; 13757d4b564dSXiaoliang Yang u32 not_pass_sdu; 13767d4b564dSXiaoliang Yang u32 red; 13777d4b564dSXiaoliang Yang }; 13787d4b564dSXiaoliang Yang 137923ae3a78SXiaoliang Yang struct felix_stream_gate { 138023ae3a78SXiaoliang Yang u32 index; 138123ae3a78SXiaoliang Yang u8 enable; 138223ae3a78SXiaoliang Yang u8 ipv_valid; 138323ae3a78SXiaoliang Yang u8 init_ipv; 138423ae3a78SXiaoliang Yang u64 basetime; 138523ae3a78SXiaoliang Yang u64 cycletime; 138623ae3a78SXiaoliang Yang u64 cycletime_ext; 138723ae3a78SXiaoliang Yang u32 num_entries; 1388dcad856fSkernel test robot struct action_gate_entry entries[]; 138923ae3a78SXiaoliang Yang }; 139023ae3a78SXiaoliang Yang 139123ae3a78SXiaoliang Yang struct felix_stream_gate_entry { 139223ae3a78SXiaoliang Yang struct list_head list; 139323ae3a78SXiaoliang Yang refcount_t refcount; 139423ae3a78SXiaoliang Yang u32 index; 139523ae3a78SXiaoliang Yang }; 139623ae3a78SXiaoliang Yang 13977d4b564dSXiaoliang Yang static int vsc9959_stream_identify(struct flow_cls_offload *f, 13987d4b564dSXiaoliang Yang struct felix_stream *stream) 13997d4b564dSXiaoliang Yang { 14007d4b564dSXiaoliang Yang struct flow_rule *rule = flow_cls_offload_flow_rule(f); 14017d4b564dSXiaoliang Yang struct flow_dissector *dissector = rule->match.dissector; 14027d4b564dSXiaoliang Yang 14037d4b564dSXiaoliang Yang if (dissector->used_keys & 14047d4b564dSXiaoliang Yang ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 14057d4b564dSXiaoliang Yang BIT(FLOW_DISSECTOR_KEY_BASIC) | 14067d4b564dSXiaoliang Yang BIT(FLOW_DISSECTOR_KEY_VLAN) | 14077d4b564dSXiaoliang Yang BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 14087d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14097d4b564dSXiaoliang Yang 14107d4b564dSXiaoliang Yang if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 14117d4b564dSXiaoliang Yang struct flow_match_eth_addrs match; 14127d4b564dSXiaoliang Yang 14137d4b564dSXiaoliang Yang flow_rule_match_eth_addrs(rule, &match); 14147d4b564dSXiaoliang Yang ether_addr_copy(stream->dmac, match.key->dst); 14157d4b564dSXiaoliang Yang if (!is_zero_ether_addr(match.mask->src)) 14167d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14177d4b564dSXiaoliang Yang } else { 14187d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14197d4b564dSXiaoliang Yang } 14207d4b564dSXiaoliang Yang 14217d4b564dSXiaoliang Yang if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 14227d4b564dSXiaoliang Yang struct flow_match_vlan match; 14237d4b564dSXiaoliang Yang 14247d4b564dSXiaoliang Yang flow_rule_match_vlan(rule, &match); 14257d4b564dSXiaoliang Yang if (match.mask->vlan_priority) 14267d4b564dSXiaoliang Yang stream->prio = match.key->vlan_priority; 14277d4b564dSXiaoliang Yang else 14287d4b564dSXiaoliang Yang stream->prio = -1; 14297d4b564dSXiaoliang Yang 14307d4b564dSXiaoliang Yang if (!match.mask->vlan_id) 14317d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14327d4b564dSXiaoliang Yang stream->vid = match.key->vlan_id; 14337d4b564dSXiaoliang Yang } else { 14347d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14357d4b564dSXiaoliang Yang } 14367d4b564dSXiaoliang Yang 14377d4b564dSXiaoliang Yang stream->id = f->cookie; 14387d4b564dSXiaoliang Yang 14397d4b564dSXiaoliang Yang return 0; 14407d4b564dSXiaoliang Yang } 14417d4b564dSXiaoliang Yang 14427d4b564dSXiaoliang Yang static int vsc9959_mact_stream_set(struct ocelot *ocelot, 14437d4b564dSXiaoliang Yang struct felix_stream *stream, 14447d4b564dSXiaoliang Yang struct netlink_ext_ack *extack) 14457d4b564dSXiaoliang Yang { 14467d4b564dSXiaoliang Yang enum macaccess_entry_type type; 14477d4b564dSXiaoliang Yang int ret, sfid, ssid; 14487d4b564dSXiaoliang Yang u32 vid, dst_idx; 14497d4b564dSXiaoliang Yang u8 mac[ETH_ALEN]; 14507d4b564dSXiaoliang Yang 14517d4b564dSXiaoliang Yang ether_addr_copy(mac, stream->dmac); 14527d4b564dSXiaoliang Yang vid = stream->vid; 14537d4b564dSXiaoliang Yang 14547d4b564dSXiaoliang Yang /* Stream identification desn't support to add a stream with non 14557d4b564dSXiaoliang Yang * existent MAC (The MAC entry has not been learned in MAC table). 14567d4b564dSXiaoliang Yang */ 14577d4b564dSXiaoliang Yang ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 14587d4b564dSXiaoliang Yang if (ret) { 14597d4b564dSXiaoliang Yang if (extack) 14607d4b564dSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 14617d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14627d4b564dSXiaoliang Yang } 14637d4b564dSXiaoliang Yang 14647d4b564dSXiaoliang Yang if ((stream->sfid_valid || stream->ssid_valid) && 14657d4b564dSXiaoliang Yang type == ENTRYTYPE_NORMAL) 14667d4b564dSXiaoliang Yang type = ENTRYTYPE_LOCKED; 14677d4b564dSXiaoliang Yang 14687d4b564dSXiaoliang Yang sfid = stream->sfid_valid ? stream->sfid : -1; 14697d4b564dSXiaoliang Yang ssid = stream->ssid_valid ? stream->ssid : -1; 14707d4b564dSXiaoliang Yang 14717d4b564dSXiaoliang Yang ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 14727d4b564dSXiaoliang Yang sfid, ssid); 14737d4b564dSXiaoliang Yang 14747d4b564dSXiaoliang Yang return ret; 14757d4b564dSXiaoliang Yang } 14767d4b564dSXiaoliang Yang 14777d4b564dSXiaoliang Yang static struct felix_stream * 14787d4b564dSXiaoliang Yang vsc9959_stream_table_lookup(struct list_head *stream_list, 14797d4b564dSXiaoliang Yang struct felix_stream *stream) 14807d4b564dSXiaoliang Yang { 14817d4b564dSXiaoliang Yang struct felix_stream *tmp; 14827d4b564dSXiaoliang Yang 14837d4b564dSXiaoliang Yang list_for_each_entry(tmp, stream_list, list) 14847d4b564dSXiaoliang Yang if (ether_addr_equal(tmp->dmac, stream->dmac) && 14857d4b564dSXiaoliang Yang tmp->vid == stream->vid) 14867d4b564dSXiaoliang Yang return tmp; 14877d4b564dSXiaoliang Yang 14887d4b564dSXiaoliang Yang return NULL; 14897d4b564dSXiaoliang Yang } 14907d4b564dSXiaoliang Yang 14917d4b564dSXiaoliang Yang static int vsc9959_stream_table_add(struct ocelot *ocelot, 14927d4b564dSXiaoliang Yang struct list_head *stream_list, 14937d4b564dSXiaoliang Yang struct felix_stream *stream, 14947d4b564dSXiaoliang Yang struct netlink_ext_ack *extack) 14957d4b564dSXiaoliang Yang { 14967d4b564dSXiaoliang Yang struct felix_stream *stream_entry; 14977d4b564dSXiaoliang Yang int ret; 14987d4b564dSXiaoliang Yang 1499e44aecc7SYihao Han stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL); 15007d4b564dSXiaoliang Yang if (!stream_entry) 15017d4b564dSXiaoliang Yang return -ENOMEM; 15027d4b564dSXiaoliang Yang 1503a7e13edfSXiaoliang Yang if (!stream->dummy) { 15047d4b564dSXiaoliang Yang ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 15057d4b564dSXiaoliang Yang if (ret) { 15067d4b564dSXiaoliang Yang kfree(stream_entry); 15077d4b564dSXiaoliang Yang return ret; 15087d4b564dSXiaoliang Yang } 1509a7e13edfSXiaoliang Yang } 15107d4b564dSXiaoliang Yang 15117d4b564dSXiaoliang Yang list_add_tail(&stream_entry->list, stream_list); 15127d4b564dSXiaoliang Yang 15137d4b564dSXiaoliang Yang return 0; 15147d4b564dSXiaoliang Yang } 15157d4b564dSXiaoliang Yang 15167d4b564dSXiaoliang Yang static struct felix_stream * 15177d4b564dSXiaoliang Yang vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 15187d4b564dSXiaoliang Yang { 15197d4b564dSXiaoliang Yang struct felix_stream *tmp; 15207d4b564dSXiaoliang Yang 15217d4b564dSXiaoliang Yang list_for_each_entry(tmp, stream_list, list) 15227d4b564dSXiaoliang Yang if (tmp->id == id) 15237d4b564dSXiaoliang Yang return tmp; 15247d4b564dSXiaoliang Yang 15257d4b564dSXiaoliang Yang return NULL; 15267d4b564dSXiaoliang Yang } 15277d4b564dSXiaoliang Yang 15287d4b564dSXiaoliang Yang static void vsc9959_stream_table_del(struct ocelot *ocelot, 15297d4b564dSXiaoliang Yang struct felix_stream *stream) 15307d4b564dSXiaoliang Yang { 1531a7e13edfSXiaoliang Yang if (!stream->dummy) 15327d4b564dSXiaoliang Yang vsc9959_mact_stream_set(ocelot, stream, NULL); 15337d4b564dSXiaoliang Yang 15347d4b564dSXiaoliang Yang list_del(&stream->list); 15357d4b564dSXiaoliang Yang kfree(stream); 15367d4b564dSXiaoliang Yang } 15377d4b564dSXiaoliang Yang 15387d4b564dSXiaoliang Yang static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 15397d4b564dSXiaoliang Yang { 15407d4b564dSXiaoliang Yang return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 15417d4b564dSXiaoliang Yang } 15427d4b564dSXiaoliang Yang 15437d4b564dSXiaoliang Yang static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 15447d4b564dSXiaoliang Yang struct felix_stream_filter *sfi) 15457d4b564dSXiaoliang Yang { 15467d4b564dSXiaoliang Yang u32 val; 15477d4b564dSXiaoliang Yang 15487d4b564dSXiaoliang Yang if (sfi->index > VSC9959_PSFP_SFID_MAX) 15497d4b564dSXiaoliang Yang return -EINVAL; 15507d4b564dSXiaoliang Yang 15517d4b564dSXiaoliang Yang if (!sfi->enable) { 15527d4b564dSXiaoliang Yang ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 15537d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX); 15547d4b564dSXiaoliang Yang 15557d4b564dSXiaoliang Yang val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 15567d4b564dSXiaoliang Yang ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 15577d4b564dSXiaoliang Yang 15587d4b564dSXiaoliang Yang return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 15597d4b564dSXiaoliang Yang (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 15607d4b564dSXiaoliang Yang 10, 100000); 15617d4b564dSXiaoliang Yang } 15627d4b564dSXiaoliang Yang 15637d4b564dSXiaoliang Yang if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 15647d4b564dSXiaoliang Yang sfi->fmid > VSC9959_PSFP_POLICER_MAX) 15657d4b564dSXiaoliang Yang return -EINVAL; 15667d4b564dSXiaoliang Yang 15677d4b564dSXiaoliang Yang ocelot_write(ocelot, 15687d4b564dSXiaoliang Yang (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 15697d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 15707d4b564dSXiaoliang Yang (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 15717d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 15727d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 15737d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX); 15747d4b564dSXiaoliang Yang 15757d4b564dSXiaoliang Yang ocelot_write(ocelot, 15767d4b564dSXiaoliang Yang (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 15777d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 15787d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 15797d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 15807d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS); 15817d4b564dSXiaoliang Yang 15827d4b564dSXiaoliang Yang return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 15837d4b564dSXiaoliang Yang (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 15847d4b564dSXiaoliang Yang 10, 100000); 15857d4b564dSXiaoliang Yang } 15867d4b564dSXiaoliang Yang 1587a7e13edfSXiaoliang Yang static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) 15887d4b564dSXiaoliang Yang { 1589a7e13edfSXiaoliang Yang u32 val; 1590a7e13edfSXiaoliang Yang 1591a7e13edfSXiaoliang Yang ocelot_rmw(ocelot, 1592a7e13edfSXiaoliang Yang ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), 1593a7e13edfSXiaoliang Yang ANA_TABLES_SFIDTIDX_SFID_INDEX_M, 1594a7e13edfSXiaoliang Yang ANA_TABLES_SFIDTIDX); 1595a7e13edfSXiaoliang Yang 1596a7e13edfSXiaoliang Yang ocelot_write(ocelot, 1597a7e13edfSXiaoliang Yang ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | 1598a7e13edfSXiaoliang Yang ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, 1599a7e13edfSXiaoliang Yang ANA_TABLES_SFID_MASK); 1600a7e13edfSXiaoliang Yang 1601a7e13edfSXiaoliang Yang ocelot_rmw(ocelot, 1602a7e13edfSXiaoliang Yang ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1603a7e13edfSXiaoliang Yang ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, 1604a7e13edfSXiaoliang Yang ANA_TABLES_SFIDACCESS); 1605a7e13edfSXiaoliang Yang 1606a7e13edfSXiaoliang Yang return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1607a7e13edfSXiaoliang Yang (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1608a7e13edfSXiaoliang Yang 10, 100000); 1609a7e13edfSXiaoliang Yang } 1610a7e13edfSXiaoliang Yang 1611a7e13edfSXiaoliang Yang static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, 1612a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi, 1613a7e13edfSXiaoliang Yang struct list_head *pos) 1614a7e13edfSXiaoliang Yang { 1615a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi_entry; 16167d4b564dSXiaoliang Yang int ret; 16177d4b564dSXiaoliang Yang 1618e44aecc7SYihao Han sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL); 16197d4b564dSXiaoliang Yang if (!sfi_entry) 16207d4b564dSXiaoliang Yang return -ENOMEM; 16217d4b564dSXiaoliang Yang 16227d4b564dSXiaoliang Yang refcount_set(&sfi_entry->refcount, 1); 16237d4b564dSXiaoliang Yang 16247d4b564dSXiaoliang Yang ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 16257d4b564dSXiaoliang Yang if (ret) { 16267d4b564dSXiaoliang Yang kfree(sfi_entry); 16277d4b564dSXiaoliang Yang return ret; 16287d4b564dSXiaoliang Yang } 16297d4b564dSXiaoliang Yang 1630a7e13edfSXiaoliang Yang vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask); 1631a7e13edfSXiaoliang Yang 1632a7e13edfSXiaoliang Yang list_add(&sfi_entry->list, pos); 16337d4b564dSXiaoliang Yang 16347d4b564dSXiaoliang Yang return 0; 16357d4b564dSXiaoliang Yang } 16367d4b564dSXiaoliang Yang 1637a7e13edfSXiaoliang Yang static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 1638a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi) 1639a7e13edfSXiaoliang Yang { 1640a7e13edfSXiaoliang Yang struct list_head *pos, *q, *last; 1641a7e13edfSXiaoliang Yang struct felix_stream_filter *tmp; 1642a7e13edfSXiaoliang Yang struct ocelot_psfp_list *psfp; 1643a7e13edfSXiaoliang Yang u32 insert = 0; 1644a7e13edfSXiaoliang Yang 1645a7e13edfSXiaoliang Yang psfp = &ocelot->psfp; 1646a7e13edfSXiaoliang Yang last = &psfp->sfi_list; 1647a7e13edfSXiaoliang Yang 1648a7e13edfSXiaoliang Yang list_for_each_safe(pos, q, &psfp->sfi_list) { 1649a7e13edfSXiaoliang Yang tmp = list_entry(pos, struct felix_stream_filter, list); 1650a7e13edfSXiaoliang Yang if (sfi->sg_valid == tmp->sg_valid && 1651a7e13edfSXiaoliang Yang sfi->fm_valid == tmp->fm_valid && 1652a7e13edfSXiaoliang Yang sfi->portmask == tmp->portmask && 1653a7e13edfSXiaoliang Yang tmp->sgid == sfi->sgid && 1654a7e13edfSXiaoliang Yang tmp->fmid == sfi->fmid) { 1655a7e13edfSXiaoliang Yang sfi->index = tmp->index; 1656a7e13edfSXiaoliang Yang refcount_inc(&tmp->refcount); 1657a7e13edfSXiaoliang Yang return 0; 1658a7e13edfSXiaoliang Yang } 1659a7e13edfSXiaoliang Yang /* Make sure that the index is increasing in order. */ 1660a7e13edfSXiaoliang Yang if (tmp->index == insert) { 1661a7e13edfSXiaoliang Yang last = pos; 1662a7e13edfSXiaoliang Yang insert++; 1663a7e13edfSXiaoliang Yang } 1664a7e13edfSXiaoliang Yang } 1665a7e13edfSXiaoliang Yang sfi->index = insert; 1666a7e13edfSXiaoliang Yang 1667a7e13edfSXiaoliang Yang return vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1668a7e13edfSXiaoliang Yang } 1669a7e13edfSXiaoliang Yang 1670a7e13edfSXiaoliang Yang static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, 1671a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi, 1672a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi2) 1673a7e13edfSXiaoliang Yang { 1674a7e13edfSXiaoliang Yang struct felix_stream_filter *tmp; 1675a7e13edfSXiaoliang Yang struct list_head *pos, *q, *last; 1676a7e13edfSXiaoliang Yang struct ocelot_psfp_list *psfp; 1677a7e13edfSXiaoliang Yang u32 insert = 0; 1678a7e13edfSXiaoliang Yang int ret; 1679a7e13edfSXiaoliang Yang 1680a7e13edfSXiaoliang Yang psfp = &ocelot->psfp; 1681a7e13edfSXiaoliang Yang last = &psfp->sfi_list; 1682a7e13edfSXiaoliang Yang 1683a7e13edfSXiaoliang Yang list_for_each_safe(pos, q, &psfp->sfi_list) { 1684a7e13edfSXiaoliang Yang tmp = list_entry(pos, struct felix_stream_filter, list); 1685a7e13edfSXiaoliang Yang /* Make sure that the index is increasing in order. */ 1686a7e13edfSXiaoliang Yang if (tmp->index >= insert + 2) 1687a7e13edfSXiaoliang Yang break; 1688a7e13edfSXiaoliang Yang 1689a7e13edfSXiaoliang Yang insert = tmp->index + 1; 1690a7e13edfSXiaoliang Yang last = pos; 1691a7e13edfSXiaoliang Yang } 1692a7e13edfSXiaoliang Yang sfi->index = insert; 1693a7e13edfSXiaoliang Yang 1694a7e13edfSXiaoliang Yang ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1695a7e13edfSXiaoliang Yang if (ret) 1696a7e13edfSXiaoliang Yang return ret; 1697a7e13edfSXiaoliang Yang 1698a7e13edfSXiaoliang Yang sfi2->index = insert + 1; 1699a7e13edfSXiaoliang Yang 1700a7e13edfSXiaoliang Yang return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next); 1701a7e13edfSXiaoliang Yang } 1702a7e13edfSXiaoliang Yang 170323ae3a78SXiaoliang Yang static struct felix_stream_filter * 170423ae3a78SXiaoliang Yang vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 170523ae3a78SXiaoliang Yang { 170623ae3a78SXiaoliang Yang struct felix_stream_filter *tmp; 170723ae3a78SXiaoliang Yang 170823ae3a78SXiaoliang Yang list_for_each_entry(tmp, sfi_list, list) 170923ae3a78SXiaoliang Yang if (tmp->index == index) 171023ae3a78SXiaoliang Yang return tmp; 171123ae3a78SXiaoliang Yang 171223ae3a78SXiaoliang Yang return NULL; 171323ae3a78SXiaoliang Yang } 171423ae3a78SXiaoliang Yang 17157d4b564dSXiaoliang Yang static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 17167d4b564dSXiaoliang Yang { 17177d4b564dSXiaoliang Yang struct felix_stream_filter *tmp, *n; 17187d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 17197d4b564dSXiaoliang Yang u8 z; 17207d4b564dSXiaoliang Yang 17217d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 17227d4b564dSXiaoliang Yang 17237d4b564dSXiaoliang Yang list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 17247d4b564dSXiaoliang Yang if (tmp->index == index) { 17257d4b564dSXiaoliang Yang z = refcount_dec_and_test(&tmp->refcount); 17267d4b564dSXiaoliang Yang if (z) { 17277d4b564dSXiaoliang Yang tmp->enable = 0; 17287d4b564dSXiaoliang Yang vsc9959_psfp_sfi_set(ocelot, tmp); 17297d4b564dSXiaoliang Yang list_del(&tmp->list); 17307d4b564dSXiaoliang Yang kfree(tmp); 17317d4b564dSXiaoliang Yang } 17327d4b564dSXiaoliang Yang break; 17337d4b564dSXiaoliang Yang } 17347d4b564dSXiaoliang Yang } 17357d4b564dSXiaoliang Yang 173623ae3a78SXiaoliang Yang static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 173723ae3a78SXiaoliang Yang struct felix_stream_gate *sgi) 173823ae3a78SXiaoliang Yang { 17395a995900SBaowen Zheng sgi->index = entry->hw_index; 174023ae3a78SXiaoliang Yang sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 174123ae3a78SXiaoliang Yang sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 174223ae3a78SXiaoliang Yang sgi->basetime = entry->gate.basetime; 174323ae3a78SXiaoliang Yang sgi->cycletime = entry->gate.cycletime; 174423ae3a78SXiaoliang Yang sgi->num_entries = entry->gate.num_entries; 174523ae3a78SXiaoliang Yang sgi->enable = 1; 174623ae3a78SXiaoliang Yang 174723ae3a78SXiaoliang Yang memcpy(sgi->entries, entry->gate.entries, 174823ae3a78SXiaoliang Yang entry->gate.num_entries * sizeof(struct action_gate_entry)); 174923ae3a78SXiaoliang Yang } 175023ae3a78SXiaoliang Yang 175123ae3a78SXiaoliang Yang static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 175223ae3a78SXiaoliang Yang { 175323ae3a78SXiaoliang Yang return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 175423ae3a78SXiaoliang Yang } 175523ae3a78SXiaoliang Yang 175623ae3a78SXiaoliang Yang static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 175723ae3a78SXiaoliang Yang struct felix_stream_gate *sgi) 175823ae3a78SXiaoliang Yang { 175923ae3a78SXiaoliang Yang struct action_gate_entry *e; 176023ae3a78SXiaoliang Yang struct timespec64 base_ts; 176123ae3a78SXiaoliang Yang u32 interval_sum = 0; 176223ae3a78SXiaoliang Yang u32 val; 176323ae3a78SXiaoliang Yang int i; 176423ae3a78SXiaoliang Yang 176523ae3a78SXiaoliang Yang if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 176623ae3a78SXiaoliang Yang return -EINVAL; 176723ae3a78SXiaoliang Yang 176823ae3a78SXiaoliang Yang ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 176923ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL); 177023ae3a78SXiaoliang Yang 177123ae3a78SXiaoliang Yang if (!sgi->enable) { 177223ae3a78SXiaoliang Yang ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 177323ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 177423ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_GATE_ENABLE, 177523ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3); 177623ae3a78SXiaoliang Yang 177723ae3a78SXiaoliang Yang return 0; 177823ae3a78SXiaoliang Yang } 177923ae3a78SXiaoliang Yang 178023ae3a78SXiaoliang Yang if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 178123ae3a78SXiaoliang Yang sgi->cycletime > NSEC_PER_SEC) 178223ae3a78SXiaoliang Yang return -EINVAL; 178323ae3a78SXiaoliang Yang 178423ae3a78SXiaoliang Yang if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 178523ae3a78SXiaoliang Yang return -EINVAL; 178623ae3a78SXiaoliang Yang 178723ae3a78SXiaoliang Yang vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 178823ae3a78SXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 178923ae3a78SXiaoliang Yang val = lower_32_bits(base_ts.tv_sec); 179023ae3a78SXiaoliang Yang ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 179123ae3a78SXiaoliang Yang 179223ae3a78SXiaoliang Yang val = upper_32_bits(base_ts.tv_sec); 179323ae3a78SXiaoliang Yang ocelot_write(ocelot, 179423ae3a78SXiaoliang Yang (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 179523ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 179623ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_GATE_ENABLE | 179723ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 179823ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 179923ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 180023ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3); 180123ae3a78SXiaoliang Yang 180223ae3a78SXiaoliang Yang ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 180323ae3a78SXiaoliang Yang 180423ae3a78SXiaoliang Yang e = sgi->entries; 180523ae3a78SXiaoliang Yang for (i = 0; i < sgi->num_entries; i++) { 180623ae3a78SXiaoliang Yang u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 180723ae3a78SXiaoliang Yang 180823ae3a78SXiaoliang Yang ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 180923ae3a78SXiaoliang Yang (e[i].gate_state ? 181023ae3a78SXiaoliang Yang ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 181123ae3a78SXiaoliang Yang ANA_SG_GCL_GS_CONFIG, i); 181223ae3a78SXiaoliang Yang 181323ae3a78SXiaoliang Yang interval_sum += e[i].interval; 181423ae3a78SXiaoliang Yang ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 181523ae3a78SXiaoliang Yang } 181623ae3a78SXiaoliang Yang 181723ae3a78SXiaoliang Yang ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 181823ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 181923ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL); 182023ae3a78SXiaoliang Yang 182123ae3a78SXiaoliang Yang return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 182223ae3a78SXiaoliang Yang (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 182323ae3a78SXiaoliang Yang 10, 100000); 182423ae3a78SXiaoliang Yang } 182523ae3a78SXiaoliang Yang 182623ae3a78SXiaoliang Yang static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 182723ae3a78SXiaoliang Yang struct felix_stream_gate *sgi) 182823ae3a78SXiaoliang Yang { 182923ae3a78SXiaoliang Yang struct felix_stream_gate_entry *tmp; 183023ae3a78SXiaoliang Yang struct ocelot_psfp_list *psfp; 183123ae3a78SXiaoliang Yang int ret; 183223ae3a78SXiaoliang Yang 183323ae3a78SXiaoliang Yang psfp = &ocelot->psfp; 183423ae3a78SXiaoliang Yang 183523ae3a78SXiaoliang Yang list_for_each_entry(tmp, &psfp->sgi_list, list) 183623ae3a78SXiaoliang Yang if (tmp->index == sgi->index) { 183723ae3a78SXiaoliang Yang refcount_inc(&tmp->refcount); 183823ae3a78SXiaoliang Yang return 0; 183923ae3a78SXiaoliang Yang } 184023ae3a78SXiaoliang Yang 184123ae3a78SXiaoliang Yang tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 184223ae3a78SXiaoliang Yang if (!tmp) 184323ae3a78SXiaoliang Yang return -ENOMEM; 184423ae3a78SXiaoliang Yang 184523ae3a78SXiaoliang Yang ret = vsc9959_psfp_sgi_set(ocelot, sgi); 184623ae3a78SXiaoliang Yang if (ret) { 184723ae3a78SXiaoliang Yang kfree(tmp); 184823ae3a78SXiaoliang Yang return ret; 184923ae3a78SXiaoliang Yang } 185023ae3a78SXiaoliang Yang 185123ae3a78SXiaoliang Yang tmp->index = sgi->index; 185223ae3a78SXiaoliang Yang refcount_set(&tmp->refcount, 1); 185323ae3a78SXiaoliang Yang list_add_tail(&tmp->list, &psfp->sgi_list); 185423ae3a78SXiaoliang Yang 185523ae3a78SXiaoliang Yang return 0; 185623ae3a78SXiaoliang Yang } 185723ae3a78SXiaoliang Yang 185823ae3a78SXiaoliang Yang static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 185923ae3a78SXiaoliang Yang u32 index) 186023ae3a78SXiaoliang Yang { 186123ae3a78SXiaoliang Yang struct felix_stream_gate_entry *tmp, *n; 186223ae3a78SXiaoliang Yang struct felix_stream_gate sgi = {0}; 186323ae3a78SXiaoliang Yang struct ocelot_psfp_list *psfp; 186423ae3a78SXiaoliang Yang u8 z; 186523ae3a78SXiaoliang Yang 186623ae3a78SXiaoliang Yang psfp = &ocelot->psfp; 186723ae3a78SXiaoliang Yang 186823ae3a78SXiaoliang Yang list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 186923ae3a78SXiaoliang Yang if (tmp->index == index) { 187023ae3a78SXiaoliang Yang z = refcount_dec_and_test(&tmp->refcount); 187123ae3a78SXiaoliang Yang if (z) { 187223ae3a78SXiaoliang Yang sgi.index = index; 187323ae3a78SXiaoliang Yang sgi.enable = 0; 187423ae3a78SXiaoliang Yang vsc9959_psfp_sgi_set(ocelot, &sgi); 187523ae3a78SXiaoliang Yang list_del(&tmp->list); 187623ae3a78SXiaoliang Yang kfree(tmp); 187723ae3a78SXiaoliang Yang } 187823ae3a78SXiaoliang Yang break; 187923ae3a78SXiaoliang Yang } 188023ae3a78SXiaoliang Yang } 188123ae3a78SXiaoliang Yang 18827d4b564dSXiaoliang Yang static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index, 18837d4b564dSXiaoliang Yang struct felix_stream_filter_counters *counters) 18847d4b564dSXiaoliang Yang { 18857d4b564dSXiaoliang Yang ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index), 18867d4b564dSXiaoliang Yang SYS_STAT_CFG_STAT_VIEW_M, 18877d4b564dSXiaoliang Yang SYS_STAT_CFG); 18887d4b564dSXiaoliang Yang 18897d4b564dSXiaoliang Yang counters->match = ocelot_read_gix(ocelot, SYS_CNT, 0x200); 18907d4b564dSXiaoliang Yang counters->not_pass_gate = ocelot_read_gix(ocelot, SYS_CNT, 0x201); 18917d4b564dSXiaoliang Yang counters->not_pass_sdu = ocelot_read_gix(ocelot, SYS_CNT, 0x202); 18927d4b564dSXiaoliang Yang counters->red = ocelot_read_gix(ocelot, SYS_CNT, 0x203); 18937d4b564dSXiaoliang Yang 18947d4b564dSXiaoliang Yang /* Clear the PSFP counter. */ 18957d4b564dSXiaoliang Yang ocelot_write(ocelot, 18967d4b564dSXiaoliang Yang SYS_STAT_CFG_STAT_VIEW(index) | 18977d4b564dSXiaoliang Yang SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 18987d4b564dSXiaoliang Yang SYS_STAT_CFG); 18997d4b564dSXiaoliang Yang } 19007d4b564dSXiaoliang Yang 1901a7e13edfSXiaoliang Yang static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, 19027d4b564dSXiaoliang Yang struct flow_cls_offload *f) 19037d4b564dSXiaoliang Yang { 19047d4b564dSXiaoliang Yang struct netlink_ext_ack *extack = f->common.extack; 1905a7e13edfSXiaoliang Yang struct felix_stream_filter old_sfi, *sfi_entry; 19067d4b564dSXiaoliang Yang struct felix_stream_filter sfi = {0}; 19077d4b564dSXiaoliang Yang const struct flow_action_entry *a; 19087d4b564dSXiaoliang Yang struct felix_stream *stream_entry; 19097d4b564dSXiaoliang Yang struct felix_stream stream = {0}; 191023ae3a78SXiaoliang Yang struct felix_stream_gate *sgi; 19117d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 191276c13edeSXiaoliang Yang struct ocelot_policer pol; 191323ae3a78SXiaoliang Yang int ret, i, size; 191476c13edeSXiaoliang Yang u64 rate, burst; 191576c13edeSXiaoliang Yang u32 index; 19167d4b564dSXiaoliang Yang 19177d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 19187d4b564dSXiaoliang Yang 19197d4b564dSXiaoliang Yang ret = vsc9959_stream_identify(f, &stream); 19207d4b564dSXiaoliang Yang if (ret) { 19217d4b564dSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 19227d4b564dSXiaoliang Yang return ret; 19237d4b564dSXiaoliang Yang } 19247d4b564dSXiaoliang Yang 19257d4b564dSXiaoliang Yang flow_action_for_each(i, a, &f->rule->action) { 19267d4b564dSXiaoliang Yang switch (a->id) { 19277d4b564dSXiaoliang Yang case FLOW_ACTION_GATE: 192823ae3a78SXiaoliang Yang size = struct_size(sgi, entries, a->gate.num_entries); 192923ae3a78SXiaoliang Yang sgi = kzalloc(size, GFP_KERNEL); 193023ae3a78SXiaoliang Yang vsc9959_psfp_parse_gate(a, sgi); 193123ae3a78SXiaoliang Yang ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 193223ae3a78SXiaoliang Yang if (ret) { 193323ae3a78SXiaoliang Yang kfree(sgi); 193476c13edeSXiaoliang Yang goto err; 193523ae3a78SXiaoliang Yang } 193623ae3a78SXiaoliang Yang sfi.sg_valid = 1; 193723ae3a78SXiaoliang Yang sfi.sgid = sgi->index; 193823ae3a78SXiaoliang Yang kfree(sgi); 193923ae3a78SXiaoliang Yang break; 19407d4b564dSXiaoliang Yang case FLOW_ACTION_POLICE: 19415a995900SBaowen Zheng index = a->hw_index + VSC9959_PSFP_POLICER_BASE; 194276c13edeSXiaoliang Yang if (index > VSC9959_PSFP_POLICER_MAX) { 194376c13edeSXiaoliang Yang ret = -EINVAL; 194476c13edeSXiaoliang Yang goto err; 194576c13edeSXiaoliang Yang } 194676c13edeSXiaoliang Yang 194776c13edeSXiaoliang Yang rate = a->police.rate_bytes_ps; 194876c13edeSXiaoliang Yang burst = rate * PSCHED_NS2TICKS(a->police.burst); 194976c13edeSXiaoliang Yang pol = (struct ocelot_policer) { 195076c13edeSXiaoliang Yang .burst = div_u64(burst, PSCHED_TICKS_PER_SEC), 195176c13edeSXiaoliang Yang .rate = div_u64(rate, 1000) * 8, 195276c13edeSXiaoliang Yang }; 195376c13edeSXiaoliang Yang ret = ocelot_vcap_policer_add(ocelot, index, &pol); 195476c13edeSXiaoliang Yang if (ret) 195576c13edeSXiaoliang Yang goto err; 195676c13edeSXiaoliang Yang 195776c13edeSXiaoliang Yang sfi.fm_valid = 1; 195876c13edeSXiaoliang Yang sfi.fmid = index; 195976c13edeSXiaoliang Yang sfi.maxsdu = a->police.mtu; 196076c13edeSXiaoliang Yang break; 19617d4b564dSXiaoliang Yang default: 19627d4b564dSXiaoliang Yang return -EOPNOTSUPP; 19637d4b564dSXiaoliang Yang } 19647d4b564dSXiaoliang Yang } 19657d4b564dSXiaoliang Yang 1966a7e13edfSXiaoliang Yang stream.ports = BIT(port); 1967a7e13edfSXiaoliang Yang stream.port = port; 19687d4b564dSXiaoliang Yang 1969a7e13edfSXiaoliang Yang sfi.portmask = stream.ports; 19707d4b564dSXiaoliang Yang sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 19717d4b564dSXiaoliang Yang sfi.prio = (sfi.prio_valid ? stream.prio : 0); 19727d4b564dSXiaoliang Yang sfi.enable = 1; 19737d4b564dSXiaoliang Yang 1974a7e13edfSXiaoliang Yang /* Check if stream is set. */ 1975a7e13edfSXiaoliang Yang stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 1976a7e13edfSXiaoliang Yang if (stream_entry) { 1977a7e13edfSXiaoliang Yang if (stream_entry->ports & BIT(port)) { 1978a7e13edfSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, 1979a7e13edfSXiaoliang Yang "The stream is added on this port"); 1980a7e13edfSXiaoliang Yang ret = -EEXIST; 1981a7e13edfSXiaoliang Yang goto err; 1982a7e13edfSXiaoliang Yang } 1983a7e13edfSXiaoliang Yang 1984a7e13edfSXiaoliang Yang if (stream_entry->ports != BIT(stream_entry->port)) { 1985a7e13edfSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, 1986a7e13edfSXiaoliang Yang "The stream is added on two ports"); 1987a7e13edfSXiaoliang Yang ret = -EEXIST; 1988a7e13edfSXiaoliang Yang goto err; 1989a7e13edfSXiaoliang Yang } 1990a7e13edfSXiaoliang Yang 1991a7e13edfSXiaoliang Yang stream_entry->ports |= BIT(port); 1992a7e13edfSXiaoliang Yang stream.ports = stream_entry->ports; 1993a7e13edfSXiaoliang Yang 1994a7e13edfSXiaoliang Yang sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, 1995a7e13edfSXiaoliang Yang stream_entry->sfid); 1996a7e13edfSXiaoliang Yang memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); 1997a7e13edfSXiaoliang Yang 1998a7e13edfSXiaoliang Yang vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid); 1999a7e13edfSXiaoliang Yang 2000a7e13edfSXiaoliang Yang old_sfi.portmask = stream_entry->ports; 2001a7e13edfSXiaoliang Yang sfi.portmask = stream.ports; 2002a7e13edfSXiaoliang Yang 2003a7e13edfSXiaoliang Yang if (stream_entry->port > port) { 2004a7e13edfSXiaoliang Yang ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi, 2005a7e13edfSXiaoliang Yang &old_sfi); 2006a7e13edfSXiaoliang Yang stream_entry->dummy = true; 2007a7e13edfSXiaoliang Yang } else { 2008a7e13edfSXiaoliang Yang ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi, 2009a7e13edfSXiaoliang Yang &sfi); 2010a7e13edfSXiaoliang Yang stream.dummy = true; 2011a7e13edfSXiaoliang Yang } 2012a7e13edfSXiaoliang Yang if (ret) 2013a7e13edfSXiaoliang Yang goto err; 2014a7e13edfSXiaoliang Yang 2015a7e13edfSXiaoliang Yang stream_entry->sfid = old_sfi.index; 2016a7e13edfSXiaoliang Yang } else { 20177d4b564dSXiaoliang Yang ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 20187d4b564dSXiaoliang Yang if (ret) 201923ae3a78SXiaoliang Yang goto err; 2020a7e13edfSXiaoliang Yang } 20217d4b564dSXiaoliang Yang 20227d4b564dSXiaoliang Yang stream.sfid = sfi.index; 20237d4b564dSXiaoliang Yang stream.sfid_valid = 1; 20247d4b564dSXiaoliang Yang ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 20257d4b564dSXiaoliang Yang &stream, extack); 202623ae3a78SXiaoliang Yang if (ret) { 20277d4b564dSXiaoliang Yang vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 202823ae3a78SXiaoliang Yang goto err; 202923ae3a78SXiaoliang Yang } 203023ae3a78SXiaoliang Yang 203123ae3a78SXiaoliang Yang return 0; 203223ae3a78SXiaoliang Yang 203323ae3a78SXiaoliang Yang err: 203423ae3a78SXiaoliang Yang if (sfi.sg_valid) 203523ae3a78SXiaoliang Yang vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 20367d4b564dSXiaoliang Yang 203776c13edeSXiaoliang Yang if (sfi.fm_valid) 203876c13edeSXiaoliang Yang ocelot_vcap_policer_del(ocelot, sfi.fmid); 203976c13edeSXiaoliang Yang 20407d4b564dSXiaoliang Yang return ret; 20417d4b564dSXiaoliang Yang } 20427d4b564dSXiaoliang Yang 20437d4b564dSXiaoliang Yang static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 20447d4b564dSXiaoliang Yang struct flow_cls_offload *f) 20457d4b564dSXiaoliang Yang { 2046a7e13edfSXiaoliang Yang struct felix_stream *stream, tmp, *stream_entry; 204723ae3a78SXiaoliang Yang static struct felix_stream_filter *sfi; 20487d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 20497d4b564dSXiaoliang Yang 20507d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 20517d4b564dSXiaoliang Yang 20527d4b564dSXiaoliang Yang stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 20537d4b564dSXiaoliang Yang if (!stream) 20547d4b564dSXiaoliang Yang return -ENOMEM; 20557d4b564dSXiaoliang Yang 205623ae3a78SXiaoliang Yang sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 205723ae3a78SXiaoliang Yang if (!sfi) 205823ae3a78SXiaoliang Yang return -ENOMEM; 205923ae3a78SXiaoliang Yang 206023ae3a78SXiaoliang Yang if (sfi->sg_valid) 206123ae3a78SXiaoliang Yang vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 206223ae3a78SXiaoliang Yang 206376c13edeSXiaoliang Yang if (sfi->fm_valid) 206476c13edeSXiaoliang Yang ocelot_vcap_policer_del(ocelot, sfi->fmid); 206576c13edeSXiaoliang Yang 20667d4b564dSXiaoliang Yang vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 20677d4b564dSXiaoliang Yang 2068a7e13edfSXiaoliang Yang memcpy(&tmp, stream, sizeof(tmp)); 2069a7e13edfSXiaoliang Yang 20707d4b564dSXiaoliang Yang stream->sfid_valid = 0; 20717d4b564dSXiaoliang Yang vsc9959_stream_table_del(ocelot, stream); 20727d4b564dSXiaoliang Yang 2073a7e13edfSXiaoliang Yang stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp); 2074a7e13edfSXiaoliang Yang if (stream_entry) { 2075a7e13edfSXiaoliang Yang stream_entry->ports = BIT(stream_entry->port); 2076a7e13edfSXiaoliang Yang if (stream_entry->dummy) { 2077a7e13edfSXiaoliang Yang stream_entry->dummy = false; 2078a7e13edfSXiaoliang Yang vsc9959_mact_stream_set(ocelot, stream_entry, NULL); 2079a7e13edfSXiaoliang Yang } 2080a7e13edfSXiaoliang Yang vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid, 2081a7e13edfSXiaoliang Yang stream_entry->ports); 2082a7e13edfSXiaoliang Yang } 2083a7e13edfSXiaoliang Yang 20847d4b564dSXiaoliang Yang return 0; 20857d4b564dSXiaoliang Yang } 20867d4b564dSXiaoliang Yang 20877d4b564dSXiaoliang Yang static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 20887d4b564dSXiaoliang Yang struct flow_cls_offload *f, 20897d4b564dSXiaoliang Yang struct flow_stats *stats) 20907d4b564dSXiaoliang Yang { 20917d4b564dSXiaoliang Yang struct felix_stream_filter_counters counters; 20927d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 20937d4b564dSXiaoliang Yang struct felix_stream *stream; 20947d4b564dSXiaoliang Yang 20957d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 20967d4b564dSXiaoliang Yang stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 20977d4b564dSXiaoliang Yang if (!stream) 20987d4b564dSXiaoliang Yang return -ENOMEM; 20997d4b564dSXiaoliang Yang 21007d4b564dSXiaoliang Yang vsc9959_psfp_counters_get(ocelot, stream->sfid, &counters); 21017d4b564dSXiaoliang Yang 21027d4b564dSXiaoliang Yang stats->pkts = counters.match; 21037d4b564dSXiaoliang Yang stats->drops = counters.not_pass_gate + counters.not_pass_sdu + 21047d4b564dSXiaoliang Yang counters.red; 21057d4b564dSXiaoliang Yang 21067d4b564dSXiaoliang Yang return 0; 21077d4b564dSXiaoliang Yang } 21087d4b564dSXiaoliang Yang 21097d4b564dSXiaoliang Yang static void vsc9959_psfp_init(struct ocelot *ocelot) 21107d4b564dSXiaoliang Yang { 21117d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp = &ocelot->psfp; 21127d4b564dSXiaoliang Yang 21137d4b564dSXiaoliang Yang INIT_LIST_HEAD(&psfp->stream_list); 21147d4b564dSXiaoliang Yang INIT_LIST_HEAD(&psfp->sfi_list); 21157d4b564dSXiaoliang Yang INIT_LIST_HEAD(&psfp->sgi_list); 21167d4b564dSXiaoliang Yang } 21177d4b564dSXiaoliang Yang 21188abe1970SVladimir Oltean /* When using cut-through forwarding and the egress port runs at a higher data 21198abe1970SVladimir Oltean * rate than the ingress port, the packet currently under transmission would 21208abe1970SVladimir Oltean * suffer an underrun since it would be transmitted faster than it is received. 21218abe1970SVladimir Oltean * The Felix switch implementation of cut-through forwarding does not check in 21228abe1970SVladimir Oltean * hardware whether this condition is satisfied or not, so we must restrict the 21238abe1970SVladimir Oltean * list of ports that have cut-through forwarding enabled on egress to only be 21248abe1970SVladimir Oltean * the ports operating at the lowest link speed within their respective 21258abe1970SVladimir Oltean * forwarding domain. 21268abe1970SVladimir Oltean */ 21278abe1970SVladimir Oltean static void vsc9959_cut_through_fwd(struct ocelot *ocelot) 21288abe1970SVladimir Oltean { 21298abe1970SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 21308abe1970SVladimir Oltean struct dsa_switch *ds = felix->ds; 21318abe1970SVladimir Oltean int port, other_port; 21328abe1970SVladimir Oltean 21338abe1970SVladimir Oltean lockdep_assert_held(&ocelot->fwd_domain_lock); 21348abe1970SVladimir Oltean 21358abe1970SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) { 21368abe1970SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 21378abe1970SVladimir Oltean int min_speed = ocelot_port->speed; 21388abe1970SVladimir Oltean unsigned long mask = 0; 21398abe1970SVladimir Oltean u32 tmp, val = 0; 21408abe1970SVladimir Oltean 21418abe1970SVladimir Oltean /* Disable cut-through on ports that are down */ 21428abe1970SVladimir Oltean if (ocelot_port->speed <= 0) 21438abe1970SVladimir Oltean goto set; 21448abe1970SVladimir Oltean 21458abe1970SVladimir Oltean if (dsa_is_cpu_port(ds, port)) { 21468abe1970SVladimir Oltean /* Ocelot switches forward from the NPI port towards 21478abe1970SVladimir Oltean * any port, regardless of it being in the NPI port's 21488abe1970SVladimir Oltean * forwarding domain or not. 21498abe1970SVladimir Oltean */ 21508abe1970SVladimir Oltean mask = dsa_user_ports(ds); 21518abe1970SVladimir Oltean } else { 21528abe1970SVladimir Oltean mask = ocelot_get_bridge_fwd_mask(ocelot, port); 21538abe1970SVladimir Oltean mask &= ~BIT(port); 21548abe1970SVladimir Oltean if (ocelot->npi >= 0) 21558abe1970SVladimir Oltean mask |= BIT(ocelot->npi); 21568abe1970SVladimir Oltean else 21578abe1970SVladimir Oltean mask |= ocelot_get_dsa_8021q_cpu_mask(ocelot); 21588abe1970SVladimir Oltean } 21598abe1970SVladimir Oltean 21608abe1970SVladimir Oltean /* Calculate the minimum link speed, among the ports that are 21618abe1970SVladimir Oltean * up, of this source port's forwarding domain. 21628abe1970SVladimir Oltean */ 21638abe1970SVladimir Oltean for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { 21648abe1970SVladimir Oltean struct ocelot_port *other_ocelot_port; 21658abe1970SVladimir Oltean 21668abe1970SVladimir Oltean other_ocelot_port = ocelot->ports[other_port]; 21678abe1970SVladimir Oltean if (other_ocelot_port->speed <= 0) 21688abe1970SVladimir Oltean continue; 21698abe1970SVladimir Oltean 21708abe1970SVladimir Oltean if (min_speed > other_ocelot_port->speed) 21718abe1970SVladimir Oltean min_speed = other_ocelot_port->speed; 21728abe1970SVladimir Oltean } 21738abe1970SVladimir Oltean 21748abe1970SVladimir Oltean /* Enable cut-through forwarding for all traffic classes. */ 21758abe1970SVladimir Oltean if (ocelot_port->speed == min_speed) 21768abe1970SVladimir Oltean val = GENMASK(7, 0); 21778abe1970SVladimir Oltean 21788abe1970SVladimir Oltean set: 21798abe1970SVladimir Oltean tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); 21808abe1970SVladimir Oltean if (tmp == val) 21818abe1970SVladimir Oltean continue; 21828abe1970SVladimir Oltean 21838abe1970SVladimir Oltean dev_dbg(ocelot->dev, 21848abe1970SVladimir Oltean "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding\n", 21858abe1970SVladimir Oltean port, mask, ocelot_port->speed, min_speed, 21868abe1970SVladimir Oltean val ? "enabling" : "disabling"); 21878abe1970SVladimir Oltean 21888abe1970SVladimir Oltean ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); 21898abe1970SVladimir Oltean } 21908abe1970SVladimir Oltean } 21918abe1970SVladimir Oltean 21927d4b564dSXiaoliang Yang static const struct ocelot_ops vsc9959_ops = { 21937d4b564dSXiaoliang Yang .reset = vsc9959_reset, 21947d4b564dSXiaoliang Yang .wm_enc = vsc9959_wm_enc, 21957d4b564dSXiaoliang Yang .wm_dec = vsc9959_wm_dec, 21967d4b564dSXiaoliang Yang .wm_stat = vsc9959_wm_stat, 21977d4b564dSXiaoliang Yang .port_to_netdev = felix_port_to_netdev, 21987d4b564dSXiaoliang Yang .netdev_to_port = felix_netdev_to_port, 21997d4b564dSXiaoliang Yang .psfp_init = vsc9959_psfp_init, 22007d4b564dSXiaoliang Yang .psfp_filter_add = vsc9959_psfp_filter_add, 22017d4b564dSXiaoliang Yang .psfp_filter_del = vsc9959_psfp_filter_del, 22027d4b564dSXiaoliang Yang .psfp_stats_get = vsc9959_psfp_stats_get, 22038abe1970SVladimir Oltean .cut_through_fwd = vsc9959_cut_through_fwd, 22047d4b564dSXiaoliang Yang }; 22057d4b564dSXiaoliang Yang 2206375e1314SVladimir Oltean static const struct felix_info felix_info_vsc9959 = { 220756051948SVladimir Oltean .target_io_res = vsc9959_target_io_res, 220856051948SVladimir Oltean .port_io_res = vsc9959_port_io_res, 2209bdeced75SVladimir Oltean .imdio_res = &vsc9959_imdio_res, 221056051948SVladimir Oltean .regfields = vsc9959_regfields, 221156051948SVladimir Oltean .map = vsc9959_regmap, 221256051948SVladimir Oltean .ops = &vsc9959_ops, 221356051948SVladimir Oltean .stats_layout = vsc9959_stats_layout, 221456051948SVladimir Oltean .num_stats = ARRAY_SIZE(vsc9959_stats_layout), 221507d985eeSVladimir Oltean .vcap = vsc9959_vcap_props, 221677043c37SXiaoliang Yang .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 221777043c37SXiaoliang Yang .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 221877043c37SXiaoliang Yang .vcap_pol_base2 = 0, 221977043c37SXiaoliang Yang .vcap_pol_max2 = 0, 222021ce7f3eSVladimir Oltean .num_mact_rows = 2048, 2221*acf242fcSColin Foster .num_ports = VSC9959_NUM_PORTS, 222270d39a6eSVladimir Oltean .num_tx_queues = OCELOT_NUM_TC, 2223c8c0ba4fSVladimir Oltean .quirk_no_xtr_irq = true, 22242ac7c6c5SVladimir Oltean .ptp_caps = &vsc9959_ptp_caps, 2225bdeced75SVladimir Oltean .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2226bdeced75SVladimir Oltean .mdio_bus_free = vsc9959_mdio_bus_free, 2227375e1314SVladimir Oltean .phylink_validate = vsc9959_phylink_validate, 2228*acf242fcSColin Foster .port_modes = vsc9959_port_modes, 2229de143c0eSXiaoliang Yang .port_setup_tc = vsc9959_port_setup_tc, 2230de143c0eSXiaoliang Yang .port_sched_speed_set = vsc9959_sched_speed_set, 2231242bd0c1SColin Foster .init_regmap = ocelot_regmap_init, 223256051948SVladimir Oltean }; 2233375e1314SVladimir Oltean 2234375e1314SVladimir Oltean static irqreturn_t felix_irq_handler(int irq, void *data) 2235375e1314SVladimir Oltean { 2236375e1314SVladimir Oltean struct ocelot *ocelot = (struct ocelot *)data; 2237375e1314SVladimir Oltean 2238375e1314SVladimir Oltean /* The INTB interrupt is used for both PTP TX timestamp interrupt 2239375e1314SVladimir Oltean * and preemption status change interrupt on each port. 2240375e1314SVladimir Oltean * 2241375e1314SVladimir Oltean * - Get txtstamp if have 2242375e1314SVladimir Oltean * - TODO: handle preemption. Without handling it, driver may get 2243375e1314SVladimir Oltean * interrupt storm. 2244375e1314SVladimir Oltean */ 2245375e1314SVladimir Oltean 2246375e1314SVladimir Oltean ocelot_get_txtstamp(ocelot); 2247375e1314SVladimir Oltean 2248375e1314SVladimir Oltean return IRQ_HANDLED; 2249375e1314SVladimir Oltean } 2250375e1314SVladimir Oltean 2251375e1314SVladimir Oltean static int felix_pci_probe(struct pci_dev *pdev, 2252375e1314SVladimir Oltean const struct pci_device_id *id) 2253375e1314SVladimir Oltean { 2254375e1314SVladimir Oltean struct dsa_switch *ds; 2255375e1314SVladimir Oltean struct ocelot *ocelot; 2256375e1314SVladimir Oltean struct felix *felix; 2257375e1314SVladimir Oltean int err; 2258375e1314SVladimir Oltean 2259375e1314SVladimir Oltean if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 2260375e1314SVladimir Oltean dev_info(&pdev->dev, "device is disabled, skipping\n"); 2261375e1314SVladimir Oltean return -ENODEV; 2262375e1314SVladimir Oltean } 2263375e1314SVladimir Oltean 2264375e1314SVladimir Oltean err = pci_enable_device(pdev); 2265375e1314SVladimir Oltean if (err) { 2266375e1314SVladimir Oltean dev_err(&pdev->dev, "device enable failed\n"); 2267375e1314SVladimir Oltean goto err_pci_enable; 2268375e1314SVladimir Oltean } 2269375e1314SVladimir Oltean 2270375e1314SVladimir Oltean felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 2271375e1314SVladimir Oltean if (!felix) { 2272375e1314SVladimir Oltean err = -ENOMEM; 2273375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 2274375e1314SVladimir Oltean goto err_alloc_felix; 2275375e1314SVladimir Oltean } 2276375e1314SVladimir Oltean 2277375e1314SVladimir Oltean pci_set_drvdata(pdev, felix); 2278375e1314SVladimir Oltean ocelot = &felix->ocelot; 2279375e1314SVladimir Oltean ocelot->dev = &pdev->dev; 228070d39a6eSVladimir Oltean ocelot->num_flooding_pgids = OCELOT_NUM_TC; 2281375e1314SVladimir Oltean felix->info = &felix_info_vsc9959; 2282c9910484SColin Foster felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); 2283c9910484SColin Foster felix->imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); 2284375e1314SVladimir Oltean 2285375e1314SVladimir Oltean pci_set_master(pdev); 2286375e1314SVladimir Oltean 2287375e1314SVladimir Oltean err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 2288375e1314SVladimir Oltean &felix_irq_handler, IRQF_ONESHOT, 2289375e1314SVladimir Oltean "felix-intb", ocelot); 2290375e1314SVladimir Oltean if (err) { 2291375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to request irq\n"); 2292375e1314SVladimir Oltean goto err_alloc_irq; 2293375e1314SVladimir Oltean } 2294375e1314SVladimir Oltean 2295375e1314SVladimir Oltean ocelot->ptp = 1; 2296375e1314SVladimir Oltean 2297375e1314SVladimir Oltean ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 2298375e1314SVladimir Oltean if (!ds) { 2299375e1314SVladimir Oltean err = -ENOMEM; 2300375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 2301375e1314SVladimir Oltean goto err_alloc_ds; 2302375e1314SVladimir Oltean } 2303375e1314SVladimir Oltean 2304375e1314SVladimir Oltean ds->dev = &pdev->dev; 2305375e1314SVladimir Oltean ds->num_ports = felix->info->num_ports; 2306375e1314SVladimir Oltean ds->num_tx_queues = felix->info->num_tx_queues; 2307375e1314SVladimir Oltean ds->ops = &felix_switch_ops; 2308375e1314SVladimir Oltean ds->priv = ocelot; 2309375e1314SVladimir Oltean felix->ds = ds; 2310adb3dccfSVladimir Oltean felix->tag_proto = DSA_TAG_PROTO_OCELOT; 2311375e1314SVladimir Oltean 2312375e1314SVladimir Oltean err = dsa_register_switch(ds); 2313375e1314SVladimir Oltean if (err) { 2314375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err); 2315375e1314SVladimir Oltean goto err_register_ds; 2316375e1314SVladimir Oltean } 2317375e1314SVladimir Oltean 2318375e1314SVladimir Oltean return 0; 2319375e1314SVladimir Oltean 2320375e1314SVladimir Oltean err_register_ds: 2321375e1314SVladimir Oltean kfree(ds); 2322375e1314SVladimir Oltean err_alloc_ds: 2323375e1314SVladimir Oltean err_alloc_irq: 2324375e1314SVladimir Oltean kfree(felix); 2325537e2b88SVladimir Oltean err_alloc_felix: 2326375e1314SVladimir Oltean pci_disable_device(pdev); 2327375e1314SVladimir Oltean err_pci_enable: 2328375e1314SVladimir Oltean return err; 2329375e1314SVladimir Oltean } 2330375e1314SVladimir Oltean 2331375e1314SVladimir Oltean static void felix_pci_remove(struct pci_dev *pdev) 2332375e1314SVladimir Oltean { 23330650bf52SVladimir Oltean struct felix *felix = pci_get_drvdata(pdev); 2334375e1314SVladimir Oltean 23350650bf52SVladimir Oltean if (!felix) 23360650bf52SVladimir Oltean return; 2337375e1314SVladimir Oltean 2338375e1314SVladimir Oltean dsa_unregister_switch(felix->ds); 2339375e1314SVladimir Oltean 2340375e1314SVladimir Oltean kfree(felix->ds); 2341375e1314SVladimir Oltean kfree(felix); 2342375e1314SVladimir Oltean 2343375e1314SVladimir Oltean pci_disable_device(pdev); 23440650bf52SVladimir Oltean 23450650bf52SVladimir Oltean pci_set_drvdata(pdev, NULL); 23460650bf52SVladimir Oltean } 23470650bf52SVladimir Oltean 23480650bf52SVladimir Oltean static void felix_pci_shutdown(struct pci_dev *pdev) 23490650bf52SVladimir Oltean { 23500650bf52SVladimir Oltean struct felix *felix = pci_get_drvdata(pdev); 23510650bf52SVladimir Oltean 23520650bf52SVladimir Oltean if (!felix) 23530650bf52SVladimir Oltean return; 23540650bf52SVladimir Oltean 23550650bf52SVladimir Oltean dsa_switch_shutdown(felix->ds); 23560650bf52SVladimir Oltean 23570650bf52SVladimir Oltean pci_set_drvdata(pdev, NULL); 2358375e1314SVladimir Oltean } 2359375e1314SVladimir Oltean 2360375e1314SVladimir Oltean static struct pci_device_id felix_ids[] = { 2361375e1314SVladimir Oltean { 2362375e1314SVladimir Oltean /* NXP LS1028A */ 2363375e1314SVladimir Oltean PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 2364375e1314SVladimir Oltean }, 2365375e1314SVladimir Oltean { 0, } 2366375e1314SVladimir Oltean }; 2367375e1314SVladimir Oltean MODULE_DEVICE_TABLE(pci, felix_ids); 2368375e1314SVladimir Oltean 2369d60bc62dSVladimir Oltean static struct pci_driver felix_vsc9959_pci_driver = { 2370375e1314SVladimir Oltean .name = "mscc_felix", 2371375e1314SVladimir Oltean .id_table = felix_ids, 2372375e1314SVladimir Oltean .probe = felix_pci_probe, 2373375e1314SVladimir Oltean .remove = felix_pci_remove, 23740650bf52SVladimir Oltean .shutdown = felix_pci_shutdown, 2375375e1314SVladimir Oltean }; 2376d60bc62dSVladimir Oltean module_pci_driver(felix_vsc9959_pci_driver); 2377d60bc62dSVladimir Oltean 2378d60bc62dSVladimir Oltean MODULE_DESCRIPTION("Felix Switch driver"); 2379d60bc62dSVladimir Oltean MODULE_LICENSE("GPL v2"); 2380