156051948SVladimir Oltean // SPDX-License-Identifier: (GPL-2.0 OR MIT) 256051948SVladimir Oltean /* Copyright 2017 Microsemi Corporation 356051948SVladimir Oltean * Copyright 2018-2019 NXP Semiconductors 456051948SVladimir Oltean */ 5bdeced75SVladimir Oltean #include <linux/fsl/enetc_mdio.h> 656051948SVladimir Oltean #include <soc/mscc/ocelot_sys.h> 756051948SVladimir Oltean #include <soc/mscc/ocelot.h> 856051948SVladimir Oltean #include <linux/iopoll.h> 956051948SVladimir Oltean #include <linux/pci.h> 1056051948SVladimir Oltean #include "felix.h" 1156051948SVladimir Oltean 12bdeced75SVladimir Oltean /* TODO: should find a better place for these */ 13bdeced75SVladimir Oltean #define USXGMII_BMCR_RESET BIT(15) 14bdeced75SVladimir Oltean #define USXGMII_BMCR_AN_EN BIT(12) 15bdeced75SVladimir Oltean #define USXGMII_BMCR_RST_AN BIT(9) 16bdeced75SVladimir Oltean #define USXGMII_BMSR_LNKS(status) (((status) & GENMASK(2, 2)) >> 2) 17bdeced75SVladimir Oltean #define USXGMII_BMSR_AN_CMPL(status) (((status) & GENMASK(5, 5)) >> 5) 18bdeced75SVladimir Oltean #define USXGMII_ADVERTISE_LNKS(x) (((x) << 15) & BIT(15)) 19bdeced75SVladimir Oltean #define USXGMII_ADVERTISE_FDX BIT(12) 20bdeced75SVladimir Oltean #define USXGMII_ADVERTISE_SPEED(x) (((x) << 9) & GENMASK(11, 9)) 21bdeced75SVladimir Oltean #define USXGMII_LPA_LNKS(lpa) ((lpa) >> 15) 22bdeced75SVladimir Oltean #define USXGMII_LPA_DUPLEX(lpa) (((lpa) & GENMASK(12, 12)) >> 12) 23bdeced75SVladimir Oltean #define USXGMII_LPA_SPEED(lpa) (((lpa) & GENMASK(11, 9)) >> 9) 24bdeced75SVladimir Oltean 25bdeced75SVladimir Oltean enum usxgmii_speed { 26bdeced75SVladimir Oltean USXGMII_SPEED_10 = 0, 27bdeced75SVladimir Oltean USXGMII_SPEED_100 = 1, 28bdeced75SVladimir Oltean USXGMII_SPEED_1000 = 2, 29bdeced75SVladimir Oltean USXGMII_SPEED_2500 = 4, 30bdeced75SVladimir Oltean }; 31bdeced75SVladimir Oltean 3256051948SVladimir Oltean static const u32 vsc9959_ana_regmap[] = { 3356051948SVladimir Oltean REG(ANA_ADVLEARN, 0x0089a0), 3456051948SVladimir Oltean REG(ANA_VLANMASK, 0x0089a4), 3556051948SVladimir Oltean REG_RESERVED(ANA_PORT_B_DOMAIN), 3656051948SVladimir Oltean REG(ANA_ANAGEFIL, 0x0089ac), 3756051948SVladimir Oltean REG(ANA_ANEVENTS, 0x0089b0), 3856051948SVladimir Oltean REG(ANA_STORMLIMIT_BURST, 0x0089b4), 3956051948SVladimir Oltean REG(ANA_STORMLIMIT_CFG, 0x0089b8), 4056051948SVladimir Oltean REG(ANA_ISOLATED_PORTS, 0x0089c8), 4156051948SVladimir Oltean REG(ANA_COMMUNITY_PORTS, 0x0089cc), 4256051948SVladimir Oltean REG(ANA_AUTOAGE, 0x0089d0), 4356051948SVladimir Oltean REG(ANA_MACTOPTIONS, 0x0089d4), 4456051948SVladimir Oltean REG(ANA_LEARNDISC, 0x0089d8), 4556051948SVladimir Oltean REG(ANA_AGENCTRL, 0x0089dc), 4656051948SVladimir Oltean REG(ANA_MIRRORPORTS, 0x0089e0), 4756051948SVladimir Oltean REG(ANA_EMIRRORPORTS, 0x0089e4), 4856051948SVladimir Oltean REG(ANA_FLOODING, 0x0089e8), 4956051948SVladimir Oltean REG(ANA_FLOODING_IPMC, 0x008a08), 5056051948SVladimir Oltean REG(ANA_SFLOW_CFG, 0x008a0c), 5156051948SVladimir Oltean REG(ANA_PORT_MODE, 0x008a28), 5256051948SVladimir Oltean REG(ANA_CUT_THRU_CFG, 0x008a48), 5356051948SVladimir Oltean REG(ANA_PGID_PGID, 0x008400), 5456051948SVladimir Oltean REG(ANA_TABLES_ANMOVED, 0x007f1c), 5556051948SVladimir Oltean REG(ANA_TABLES_MACHDATA, 0x007f20), 5656051948SVladimir Oltean REG(ANA_TABLES_MACLDATA, 0x007f24), 5756051948SVladimir Oltean REG(ANA_TABLES_STREAMDATA, 0x007f28), 5856051948SVladimir Oltean REG(ANA_TABLES_MACACCESS, 0x007f2c), 5956051948SVladimir Oltean REG(ANA_TABLES_MACTINDX, 0x007f30), 6056051948SVladimir Oltean REG(ANA_TABLES_VLANACCESS, 0x007f34), 6156051948SVladimir Oltean REG(ANA_TABLES_VLANTIDX, 0x007f38), 6256051948SVladimir Oltean REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 6356051948SVladimir Oltean REG(ANA_TABLES_ISDXTIDX, 0x007f40), 6456051948SVladimir Oltean REG(ANA_TABLES_ENTRYLIM, 0x007f00), 6556051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 6656051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 6756051948SVladimir Oltean REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 6856051948SVladimir Oltean REG(ANA_TABLES_STREAMTIDX, 0x007f50), 6956051948SVladimir Oltean REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 7056051948SVladimir Oltean REG(ANA_TABLES_SEQ_MASK, 0x007f58), 7156051948SVladimir Oltean REG(ANA_TABLES_SFID_MASK, 0x007f5c), 7256051948SVladimir Oltean REG(ANA_TABLES_SFIDACCESS, 0x007f60), 7356051948SVladimir Oltean REG(ANA_TABLES_SFIDTIDX, 0x007f64), 7456051948SVladimir Oltean REG(ANA_MSTI_STATE, 0x008600), 7556051948SVladimir Oltean REG(ANA_OAM_UPM_LM_CNT, 0x008000), 7656051948SVladimir Oltean REG(ANA_SG_ACCESS_CTRL, 0x008a64), 7756051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 7856051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 7956051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 8056051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 8156051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 8256051948SVladimir Oltean REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 8356051948SVladimir Oltean REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 8456051948SVladimir Oltean REG(ANA_SG_STATUS_REG_1, 0x008980), 8556051948SVladimir Oltean REG(ANA_SG_STATUS_REG_2, 0x008984), 8656051948SVladimir Oltean REG(ANA_SG_STATUS_REG_3, 0x008988), 8756051948SVladimir Oltean REG(ANA_PORT_VLAN_CFG, 0x007800), 8856051948SVladimir Oltean REG(ANA_PORT_DROP_CFG, 0x007804), 8956051948SVladimir Oltean REG(ANA_PORT_QOS_CFG, 0x007808), 9056051948SVladimir Oltean REG(ANA_PORT_VCAP_CFG, 0x00780c), 9156051948SVladimir Oltean REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 9256051948SVladimir Oltean REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 9356051948SVladimir Oltean REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 9456051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 9556051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 9656051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 9756051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 9856051948SVladimir Oltean REG(ANA_PORT_PORT_CFG, 0x007870), 9956051948SVladimir Oltean REG(ANA_PORT_POL_CFG, 0x007874), 10056051948SVladimir Oltean REG(ANA_PORT_PTP_CFG, 0x007878), 10156051948SVladimir Oltean REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 10256051948SVladimir Oltean REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 10356051948SVladimir Oltean REG(ANA_PORT_SFID_CFG, 0x007884), 10456051948SVladimir Oltean REG(ANA_PFC_PFC_CFG, 0x008800), 10556051948SVladimir Oltean REG_RESERVED(ANA_PFC_PFC_TIMER), 10656051948SVladimir Oltean REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 10756051948SVladimir Oltean REG_RESERVED(ANA_IPT_IPT), 10856051948SVladimir Oltean REG_RESERVED(ANA_PPT_PPT), 10956051948SVladimir Oltean REG_RESERVED(ANA_FID_MAP_FID_MAP), 11056051948SVladimir Oltean REG(ANA_AGGR_CFG, 0x008a68), 11156051948SVladimir Oltean REG(ANA_CPUQ_CFG, 0x008a6c), 11256051948SVladimir Oltean REG_RESERVED(ANA_CPUQ_CFG2), 11356051948SVladimir Oltean REG(ANA_CPUQ_8021_CFG, 0x008a74), 11456051948SVladimir Oltean REG(ANA_DSCP_CFG, 0x008ab4), 11556051948SVladimir Oltean REG(ANA_DSCP_REWR_CFG, 0x008bb4), 11656051948SVladimir Oltean REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 11756051948SVladimir Oltean REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 11856051948SVladimir Oltean REG_RESERVED(ANA_VRAP_CFG), 11956051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_DATA), 12056051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_MASK), 12156051948SVladimir Oltean REG(ANA_DISCARD_CFG, 0x008c40), 12256051948SVladimir Oltean REG(ANA_FID_CFG, 0x008c44), 12356051948SVladimir Oltean REG(ANA_POL_PIR_CFG, 0x004000), 12456051948SVladimir Oltean REG(ANA_POL_CIR_CFG, 0x004004), 12556051948SVladimir Oltean REG(ANA_POL_MODE_CFG, 0x004008), 12656051948SVladimir Oltean REG(ANA_POL_PIR_STATE, 0x00400c), 12756051948SVladimir Oltean REG(ANA_POL_CIR_STATE, 0x004010), 12856051948SVladimir Oltean REG_RESERVED(ANA_POL_STATE), 12956051948SVladimir Oltean REG(ANA_POL_FLOWC, 0x008c48), 13056051948SVladimir Oltean REG(ANA_POL_HYST, 0x008cb4), 13156051948SVladimir Oltean REG_RESERVED(ANA_POL_MISC_CFG), 13256051948SVladimir Oltean }; 13356051948SVladimir Oltean 13456051948SVladimir Oltean static const u32 vsc9959_qs_regmap[] = { 13556051948SVladimir Oltean REG(QS_XTR_GRP_CFG, 0x000000), 13656051948SVladimir Oltean REG(QS_XTR_RD, 0x000008), 13756051948SVladimir Oltean REG(QS_XTR_FRM_PRUNING, 0x000010), 13856051948SVladimir Oltean REG(QS_XTR_FLUSH, 0x000018), 13956051948SVladimir Oltean REG(QS_XTR_DATA_PRESENT, 0x00001c), 14056051948SVladimir Oltean REG(QS_XTR_CFG, 0x000020), 14156051948SVladimir Oltean REG(QS_INJ_GRP_CFG, 0x000024), 14256051948SVladimir Oltean REG(QS_INJ_WR, 0x00002c), 14356051948SVladimir Oltean REG(QS_INJ_CTRL, 0x000034), 14456051948SVladimir Oltean REG(QS_INJ_STATUS, 0x00003c), 14556051948SVladimir Oltean REG(QS_INJ_ERR, 0x000040), 14656051948SVladimir Oltean REG_RESERVED(QS_INH_DBG), 14756051948SVladimir Oltean }; 14856051948SVladimir Oltean 14956051948SVladimir Oltean static const u32 vsc9959_s2_regmap[] = { 15056051948SVladimir Oltean REG(S2_CORE_UPDATE_CTRL, 0x000000), 15156051948SVladimir Oltean REG(S2_CORE_MV_CFG, 0x000004), 15256051948SVladimir Oltean REG(S2_CACHE_ENTRY_DAT, 0x000008), 15356051948SVladimir Oltean REG(S2_CACHE_MASK_DAT, 0x000108), 15456051948SVladimir Oltean REG(S2_CACHE_ACTION_DAT, 0x000208), 15556051948SVladimir Oltean REG(S2_CACHE_CNT_DAT, 0x000308), 15656051948SVladimir Oltean REG(S2_CACHE_TG_DAT, 0x000388), 15756051948SVladimir Oltean }; 15856051948SVladimir Oltean 15956051948SVladimir Oltean static const u32 vsc9959_qsys_regmap[] = { 16056051948SVladimir Oltean REG(QSYS_PORT_MODE, 0x00f460), 16156051948SVladimir Oltean REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 16256051948SVladimir Oltean REG(QSYS_STAT_CNT_CFG, 0x00f49c), 16356051948SVladimir Oltean REG(QSYS_EEE_CFG, 0x00f4a0), 16456051948SVladimir Oltean REG(QSYS_EEE_THRES, 0x00f4b8), 16556051948SVladimir Oltean REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 16656051948SVladimir Oltean REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 16756051948SVladimir Oltean REG(QSYS_SW_STATUS, 0x00f4c4), 16856051948SVladimir Oltean REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 16956051948SVladimir Oltean REG_RESERVED(QSYS_PAD_CFG), 17056051948SVladimir Oltean REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 17156051948SVladimir Oltean REG_RESERVED(QSYS_QMAP), 17256051948SVladimir Oltean REG_RESERVED(QSYS_ISDX_SGRP), 17356051948SVladimir Oltean REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 17456051948SVladimir Oltean REG(QSYS_TFRM_MISC, 0x00f50c), 17556051948SVladimir Oltean REG(QSYS_TFRM_PORT_DLY, 0x00f510), 17656051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 17756051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 17856051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 17956051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 18056051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 18156051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 18256051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 18356051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 18456051948SVladimir Oltean REG(QSYS_RED_PROFILE, 0x00f534), 18556051948SVladimir Oltean REG(QSYS_RES_QOS_MODE, 0x00f574), 18656051948SVladimir Oltean REG(QSYS_RES_CFG, 0x00c000), 18756051948SVladimir Oltean REG(QSYS_RES_STAT, 0x00c004), 18856051948SVladimir Oltean REG(QSYS_EGR_DROP_MODE, 0x00f578), 18956051948SVladimir Oltean REG(QSYS_EQ_CTRL, 0x00f57c), 19056051948SVladimir Oltean REG_RESERVED(QSYS_EVENTS_CORE), 19156051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 19256051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 19356051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 19456051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 19556051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 19656051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 19756051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 19856051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 19956051948SVladimir Oltean REG(QSYS_PREEMPTION_CFG, 0x00f664), 20056051948SVladimir Oltean REG_RESERVED(QSYS_CIR_CFG), 20156051948SVladimir Oltean REG(QSYS_EIR_CFG, 0x000004), 20256051948SVladimir Oltean REG(QSYS_SE_CFG, 0x000008), 20356051948SVladimir Oltean REG(QSYS_SE_DWRR_CFG, 0x00000c), 20456051948SVladimir Oltean REG_RESERVED(QSYS_SE_CONNECT), 20556051948SVladimir Oltean REG(QSYS_SE_DLB_SENSE, 0x000040), 20656051948SVladimir Oltean REG(QSYS_CIR_STATE, 0x000044), 20756051948SVladimir Oltean REG(QSYS_EIR_STATE, 0x000048), 20856051948SVladimir Oltean REG_RESERVED(QSYS_SE_STATE), 20956051948SVladimir Oltean REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 21056051948SVladimir Oltean REG(QSYS_TAG_CONFIG, 0x00f680), 21156051948SVladimir Oltean REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 21256051948SVladimir Oltean REG(QSYS_PORT_MAX_SDU, 0x00f69c), 21356051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 21456051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 21556051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 21656051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 21756051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 21856051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_1, 0x00f454), 21956051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_2, 0x00f458), 22056051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 22156051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 22256051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 22356051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 22456051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 22556051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 22656051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 22756051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 22856051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 22956051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 23056051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 23156051948SVladimir Oltean }; 23256051948SVladimir Oltean 23356051948SVladimir Oltean static const u32 vsc9959_rew_regmap[] = { 23456051948SVladimir Oltean REG(REW_PORT_VLAN_CFG, 0x000000), 23556051948SVladimir Oltean REG(REW_TAG_CFG, 0x000004), 23656051948SVladimir Oltean REG(REW_PORT_CFG, 0x000008), 23756051948SVladimir Oltean REG(REW_DSCP_CFG, 0x00000c), 23856051948SVladimir Oltean REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 23956051948SVladimir Oltean REG(REW_PTP_CFG, 0x000050), 24056051948SVladimir Oltean REG(REW_PTP_DLY1_CFG, 0x000054), 24156051948SVladimir Oltean REG(REW_RED_TAG_CFG, 0x000058), 24256051948SVladimir Oltean REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 24356051948SVladimir Oltean REG(REW_DSCP_REMAP_CFG, 0x000510), 24456051948SVladimir Oltean REG_RESERVED(REW_STAT_CFG), 24556051948SVladimir Oltean REG_RESERVED(REW_REW_STICKY), 24656051948SVladimir Oltean REG_RESERVED(REW_PPT), 24756051948SVladimir Oltean }; 24856051948SVladimir Oltean 24956051948SVladimir Oltean static const u32 vsc9959_sys_regmap[] = { 25056051948SVladimir Oltean REG(SYS_COUNT_RX_OCTETS, 0x000000), 25156051948SVladimir Oltean REG(SYS_COUNT_RX_MULTICAST, 0x000008), 25256051948SVladimir Oltean REG(SYS_COUNT_RX_SHORTS, 0x000010), 25356051948SVladimir Oltean REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 25456051948SVladimir Oltean REG(SYS_COUNT_RX_JABBERS, 0x000018), 25556051948SVladimir Oltean REG(SYS_COUNT_RX_64, 0x000024), 25656051948SVladimir Oltean REG(SYS_COUNT_RX_65_127, 0x000028), 25756051948SVladimir Oltean REG(SYS_COUNT_RX_128_255, 0x00002c), 25856051948SVladimir Oltean REG(SYS_COUNT_RX_256_1023, 0x000030), 25956051948SVladimir Oltean REG(SYS_COUNT_RX_1024_1526, 0x000034), 26056051948SVladimir Oltean REG(SYS_COUNT_RX_1527_MAX, 0x000038), 26156051948SVladimir Oltean REG(SYS_COUNT_RX_LONGS, 0x000044), 26256051948SVladimir Oltean REG(SYS_COUNT_TX_OCTETS, 0x000200), 26356051948SVladimir Oltean REG(SYS_COUNT_TX_COLLISION, 0x000210), 26456051948SVladimir Oltean REG(SYS_COUNT_TX_DROPS, 0x000214), 26556051948SVladimir Oltean REG(SYS_COUNT_TX_64, 0x00021c), 26656051948SVladimir Oltean REG(SYS_COUNT_TX_65_127, 0x000220), 26756051948SVladimir Oltean REG(SYS_COUNT_TX_128_511, 0x000224), 26856051948SVladimir Oltean REG(SYS_COUNT_TX_512_1023, 0x000228), 26956051948SVladimir Oltean REG(SYS_COUNT_TX_1024_1526, 0x00022c), 27056051948SVladimir Oltean REG(SYS_COUNT_TX_1527_MAX, 0x000230), 27156051948SVladimir Oltean REG(SYS_COUNT_TX_AGING, 0x000278), 27256051948SVladimir Oltean REG(SYS_RESET_CFG, 0x000e00), 27356051948SVladimir Oltean REG(SYS_SR_ETYPE_CFG, 0x000e04), 27456051948SVladimir Oltean REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 27556051948SVladimir Oltean REG(SYS_PORT_MODE, 0x000e0c), 27656051948SVladimir Oltean REG(SYS_FRONT_PORT_MODE, 0x000e2c), 27756051948SVladimir Oltean REG(SYS_FRM_AGING, 0x000e44), 27856051948SVladimir Oltean REG(SYS_STAT_CFG, 0x000e48), 27956051948SVladimir Oltean REG(SYS_SW_STATUS, 0x000e4c), 28056051948SVladimir Oltean REG_RESERVED(SYS_MISC_CFG), 28156051948SVladimir Oltean REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 28256051948SVladimir Oltean REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 28356051948SVladimir Oltean REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 28456051948SVladimir Oltean REG(SYS_PAUSE_CFG, 0x000ea0), 28556051948SVladimir Oltean REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 28656051948SVladimir Oltean REG(SYS_ATOP, 0x000ec0), 28756051948SVladimir Oltean REG(SYS_ATOP_TOT_CFG, 0x000edc), 28856051948SVladimir Oltean REG(SYS_MAC_FC_CFG, 0x000ee0), 28956051948SVladimir Oltean REG(SYS_MMGT, 0x000ef8), 29056051948SVladimir Oltean REG_RESERVED(SYS_MMGT_FAST), 29156051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_DIF), 29256051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_CORE), 29356051948SVladimir Oltean REG_RESERVED(SYS_CNT), 29456051948SVladimir Oltean REG(SYS_PTP_STATUS, 0x000f14), 29556051948SVladimir Oltean REG(SYS_PTP_TXSTAMP, 0x000f18), 29656051948SVladimir Oltean REG(SYS_PTP_NXT, 0x000f1c), 29756051948SVladimir Oltean REG(SYS_PTP_CFG, 0x000f20), 29856051948SVladimir Oltean REG(SYS_RAM_INIT, 0x000f24), 29956051948SVladimir Oltean REG_RESERVED(SYS_CM_ADDR), 30056051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_WR), 30156051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_RD), 30256051948SVladimir Oltean REG_RESERVED(SYS_CM_OP), 30356051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA), 30456051948SVladimir Oltean }; 30556051948SVladimir Oltean 3065df66c48SYangbo Lu static const u32 vsc9959_ptp_regmap[] = { 3075df66c48SYangbo Lu REG(PTP_PIN_CFG, 0x000000), 3085df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 3095df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 3105df66c48SYangbo Lu REG(PTP_PIN_TOD_NSEC, 0x00000c), 3115df66c48SYangbo Lu REG(PTP_CFG_MISC, 0x0000a0), 3125df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 3135df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 3145df66c48SYangbo Lu }; 3155df66c48SYangbo Lu 31656051948SVladimir Oltean static const u32 vsc9959_gcb_regmap[] = { 31756051948SVladimir Oltean REG(GCB_SOFT_RST, 0x000004), 31856051948SVladimir Oltean }; 31956051948SVladimir Oltean 32056051948SVladimir Oltean static const u32 *vsc9959_regmap[] = { 32156051948SVladimir Oltean [ANA] = vsc9959_ana_regmap, 32256051948SVladimir Oltean [QS] = vsc9959_qs_regmap, 32356051948SVladimir Oltean [QSYS] = vsc9959_qsys_regmap, 32456051948SVladimir Oltean [REW] = vsc9959_rew_regmap, 32556051948SVladimir Oltean [SYS] = vsc9959_sys_regmap, 32656051948SVladimir Oltean [S2] = vsc9959_s2_regmap, 3275df66c48SYangbo Lu [PTP] = vsc9959_ptp_regmap, 32856051948SVladimir Oltean [GCB] = vsc9959_gcb_regmap, 32956051948SVladimir Oltean }; 33056051948SVladimir Oltean 33156051948SVladimir Oltean /* Addresses are relative to the PCI device's base address and 33256051948SVladimir Oltean * will be fixed up at ioremap time. 33356051948SVladimir Oltean */ 33456051948SVladimir Oltean static struct resource vsc9959_target_io_res[] = { 33556051948SVladimir Oltean [ANA] = { 33656051948SVladimir Oltean .start = 0x0280000, 33756051948SVladimir Oltean .end = 0x028ffff, 33856051948SVladimir Oltean .name = "ana", 33956051948SVladimir Oltean }, 34056051948SVladimir Oltean [QS] = { 34156051948SVladimir Oltean .start = 0x0080000, 34256051948SVladimir Oltean .end = 0x00800ff, 34356051948SVladimir Oltean .name = "qs", 34456051948SVladimir Oltean }, 34556051948SVladimir Oltean [QSYS] = { 34656051948SVladimir Oltean .start = 0x0200000, 34756051948SVladimir Oltean .end = 0x021ffff, 34856051948SVladimir Oltean .name = "qsys", 34956051948SVladimir Oltean }, 35056051948SVladimir Oltean [REW] = { 35156051948SVladimir Oltean .start = 0x0030000, 35256051948SVladimir Oltean .end = 0x003ffff, 35356051948SVladimir Oltean .name = "rew", 35456051948SVladimir Oltean }, 35556051948SVladimir Oltean [SYS] = { 35656051948SVladimir Oltean .start = 0x0010000, 35756051948SVladimir Oltean .end = 0x001ffff, 35856051948SVladimir Oltean .name = "sys", 35956051948SVladimir Oltean }, 36056051948SVladimir Oltean [S2] = { 36156051948SVladimir Oltean .start = 0x0060000, 36256051948SVladimir Oltean .end = 0x00603ff, 36356051948SVladimir Oltean .name = "s2", 36456051948SVladimir Oltean }, 3655df66c48SYangbo Lu [PTP] = { 3665df66c48SYangbo Lu .start = 0x0090000, 3675df66c48SYangbo Lu .end = 0x00900cb, 3685df66c48SYangbo Lu .name = "ptp", 3695df66c48SYangbo Lu }, 37056051948SVladimir Oltean [GCB] = { 37156051948SVladimir Oltean .start = 0x0070000, 37256051948SVladimir Oltean .end = 0x00701ff, 37356051948SVladimir Oltean .name = "devcpu_gcb", 37456051948SVladimir Oltean }, 37556051948SVladimir Oltean }; 37656051948SVladimir Oltean 37756051948SVladimir Oltean static struct resource vsc9959_port_io_res[] = { 37856051948SVladimir Oltean { 37956051948SVladimir Oltean .start = 0x0100000, 38056051948SVladimir Oltean .end = 0x010ffff, 38156051948SVladimir Oltean .name = "port0", 38256051948SVladimir Oltean }, 38356051948SVladimir Oltean { 38456051948SVladimir Oltean .start = 0x0110000, 38556051948SVladimir Oltean .end = 0x011ffff, 38656051948SVladimir Oltean .name = "port1", 38756051948SVladimir Oltean }, 38856051948SVladimir Oltean { 38956051948SVladimir Oltean .start = 0x0120000, 39056051948SVladimir Oltean .end = 0x012ffff, 39156051948SVladimir Oltean .name = "port2", 39256051948SVladimir Oltean }, 39356051948SVladimir Oltean { 39456051948SVladimir Oltean .start = 0x0130000, 39556051948SVladimir Oltean .end = 0x013ffff, 39656051948SVladimir Oltean .name = "port3", 39756051948SVladimir Oltean }, 39856051948SVladimir Oltean { 39956051948SVladimir Oltean .start = 0x0140000, 40056051948SVladimir Oltean .end = 0x014ffff, 40156051948SVladimir Oltean .name = "port4", 40256051948SVladimir Oltean }, 40356051948SVladimir Oltean { 40456051948SVladimir Oltean .start = 0x0150000, 40556051948SVladimir Oltean .end = 0x015ffff, 40656051948SVladimir Oltean .name = "port5", 40756051948SVladimir Oltean }, 40856051948SVladimir Oltean }; 40956051948SVladimir Oltean 410bdeced75SVladimir Oltean /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 411bdeced75SVladimir Oltean * SGMII/QSGMII MAC PCS can be found. 412bdeced75SVladimir Oltean */ 413bdeced75SVladimir Oltean static struct resource vsc9959_imdio_res = { 414bdeced75SVladimir Oltean .start = 0x8030, 415bdeced75SVladimir Oltean .end = 0x8040, 416bdeced75SVladimir Oltean .name = "imdio", 417bdeced75SVladimir Oltean }; 418bdeced75SVladimir Oltean 41956051948SVladimir Oltean static const struct reg_field vsc9959_regfields[] = { 42056051948SVladimir Oltean [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 42156051948SVladimir Oltean [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 42256051948SVladimir Oltean [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 42356051948SVladimir Oltean [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 42456051948SVladimir Oltean [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 42556051948SVladimir Oltean [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 42656051948SVladimir Oltean [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 42756051948SVladimir Oltean [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 42856051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 42956051948SVladimir Oltean [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 43056051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 43156051948SVladimir Oltean [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 43256051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 43356051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 43456051948SVladimir Oltean [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 43556051948SVladimir Oltean [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 43656051948SVladimir Oltean [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 43756051948SVladimir Oltean [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 43856051948SVladimir Oltean [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 43956051948SVladimir Oltean [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 44056051948SVladimir Oltean [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 44156051948SVladimir Oltean [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 44256051948SVladimir Oltean [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 44356051948SVladimir Oltean [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 44456051948SVladimir Oltean [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 44556051948SVladimir Oltean [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 44656051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 44756051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 44856051948SVladimir Oltean [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 44956051948SVladimir Oltean [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 45056051948SVladimir Oltean [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 45156051948SVladimir Oltean [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 45256051948SVladimir Oltean [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 45356051948SVladimir Oltean }; 45456051948SVladimir Oltean 45556051948SVladimir Oltean static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 45656051948SVladimir Oltean { .offset = 0x00, .name = "rx_octets", }, 45756051948SVladimir Oltean { .offset = 0x01, .name = "rx_unicast", }, 45856051948SVladimir Oltean { .offset = 0x02, .name = "rx_multicast", }, 45956051948SVladimir Oltean { .offset = 0x03, .name = "rx_broadcast", }, 46056051948SVladimir Oltean { .offset = 0x04, .name = "rx_shorts", }, 46156051948SVladimir Oltean { .offset = 0x05, .name = "rx_fragments", }, 46256051948SVladimir Oltean { .offset = 0x06, .name = "rx_jabbers", }, 46356051948SVladimir Oltean { .offset = 0x07, .name = "rx_crc_align_errs", }, 46456051948SVladimir Oltean { .offset = 0x08, .name = "rx_sym_errs", }, 46556051948SVladimir Oltean { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 46656051948SVladimir Oltean { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 46756051948SVladimir Oltean { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 46856051948SVladimir Oltean { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 46956051948SVladimir Oltean { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 47056051948SVladimir Oltean { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 47156051948SVladimir Oltean { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 47256051948SVladimir Oltean { .offset = 0x10, .name = "rx_pause", }, 47356051948SVladimir Oltean { .offset = 0x11, .name = "rx_control", }, 47456051948SVladimir Oltean { .offset = 0x12, .name = "rx_longs", }, 47556051948SVladimir Oltean { .offset = 0x13, .name = "rx_classified_drops", }, 47656051948SVladimir Oltean { .offset = 0x14, .name = "rx_red_prio_0", }, 47756051948SVladimir Oltean { .offset = 0x15, .name = "rx_red_prio_1", }, 47856051948SVladimir Oltean { .offset = 0x16, .name = "rx_red_prio_2", }, 47956051948SVladimir Oltean { .offset = 0x17, .name = "rx_red_prio_3", }, 48056051948SVladimir Oltean { .offset = 0x18, .name = "rx_red_prio_4", }, 48156051948SVladimir Oltean { .offset = 0x19, .name = "rx_red_prio_5", }, 48256051948SVladimir Oltean { .offset = 0x1A, .name = "rx_red_prio_6", }, 48356051948SVladimir Oltean { .offset = 0x1B, .name = "rx_red_prio_7", }, 48456051948SVladimir Oltean { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 48556051948SVladimir Oltean { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 48656051948SVladimir Oltean { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 48756051948SVladimir Oltean { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 48856051948SVladimir Oltean { .offset = 0x20, .name = "rx_yellow_prio_4", }, 48956051948SVladimir Oltean { .offset = 0x21, .name = "rx_yellow_prio_5", }, 49056051948SVladimir Oltean { .offset = 0x22, .name = "rx_yellow_prio_6", }, 49156051948SVladimir Oltean { .offset = 0x23, .name = "rx_yellow_prio_7", }, 49256051948SVladimir Oltean { .offset = 0x24, .name = "rx_green_prio_0", }, 49356051948SVladimir Oltean { .offset = 0x25, .name = "rx_green_prio_1", }, 49456051948SVladimir Oltean { .offset = 0x26, .name = "rx_green_prio_2", }, 49556051948SVladimir Oltean { .offset = 0x27, .name = "rx_green_prio_3", }, 49656051948SVladimir Oltean { .offset = 0x28, .name = "rx_green_prio_4", }, 49756051948SVladimir Oltean { .offset = 0x29, .name = "rx_green_prio_5", }, 49856051948SVladimir Oltean { .offset = 0x2A, .name = "rx_green_prio_6", }, 49956051948SVladimir Oltean { .offset = 0x2B, .name = "rx_green_prio_7", }, 50056051948SVladimir Oltean { .offset = 0x80, .name = "tx_octets", }, 50156051948SVladimir Oltean { .offset = 0x81, .name = "tx_unicast", }, 50256051948SVladimir Oltean { .offset = 0x82, .name = "tx_multicast", }, 50356051948SVladimir Oltean { .offset = 0x83, .name = "tx_broadcast", }, 50456051948SVladimir Oltean { .offset = 0x84, .name = "tx_collision", }, 50556051948SVladimir Oltean { .offset = 0x85, .name = "tx_drops", }, 50656051948SVladimir Oltean { .offset = 0x86, .name = "tx_pause", }, 50756051948SVladimir Oltean { .offset = 0x87, .name = "tx_frames_below_65_octets", }, 50856051948SVladimir Oltean { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, 50956051948SVladimir Oltean { .offset = 0x89, .name = "tx_frames_128_255_octets", }, 51056051948SVladimir Oltean { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, 51156051948SVladimir Oltean { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, 51256051948SVladimir Oltean { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, 51356051948SVladimir Oltean { .offset = 0x8E, .name = "tx_yellow_prio_0", }, 51456051948SVladimir Oltean { .offset = 0x8F, .name = "tx_yellow_prio_1", }, 51556051948SVladimir Oltean { .offset = 0x90, .name = "tx_yellow_prio_2", }, 51656051948SVladimir Oltean { .offset = 0x91, .name = "tx_yellow_prio_3", }, 51756051948SVladimir Oltean { .offset = 0x92, .name = "tx_yellow_prio_4", }, 51856051948SVladimir Oltean { .offset = 0x93, .name = "tx_yellow_prio_5", }, 51956051948SVladimir Oltean { .offset = 0x94, .name = "tx_yellow_prio_6", }, 52056051948SVladimir Oltean { .offset = 0x95, .name = "tx_yellow_prio_7", }, 52156051948SVladimir Oltean { .offset = 0x96, .name = "tx_green_prio_0", }, 52256051948SVladimir Oltean { .offset = 0x97, .name = "tx_green_prio_1", }, 52356051948SVladimir Oltean { .offset = 0x98, .name = "tx_green_prio_2", }, 52456051948SVladimir Oltean { .offset = 0x99, .name = "tx_green_prio_3", }, 52556051948SVladimir Oltean { .offset = 0x9A, .name = "tx_green_prio_4", }, 52656051948SVladimir Oltean { .offset = 0x9B, .name = "tx_green_prio_5", }, 52756051948SVladimir Oltean { .offset = 0x9C, .name = "tx_green_prio_6", }, 52856051948SVladimir Oltean { .offset = 0x9D, .name = "tx_green_prio_7", }, 52956051948SVladimir Oltean { .offset = 0x9E, .name = "tx_aged", }, 53056051948SVladimir Oltean { .offset = 0x100, .name = "drop_local", }, 53156051948SVladimir Oltean { .offset = 0x101, .name = "drop_tail", }, 53256051948SVladimir Oltean { .offset = 0x102, .name = "drop_yellow_prio_0", }, 53356051948SVladimir Oltean { .offset = 0x103, .name = "drop_yellow_prio_1", }, 53456051948SVladimir Oltean { .offset = 0x104, .name = "drop_yellow_prio_2", }, 53556051948SVladimir Oltean { .offset = 0x105, .name = "drop_yellow_prio_3", }, 53656051948SVladimir Oltean { .offset = 0x106, .name = "drop_yellow_prio_4", }, 53756051948SVladimir Oltean { .offset = 0x107, .name = "drop_yellow_prio_5", }, 53856051948SVladimir Oltean { .offset = 0x108, .name = "drop_yellow_prio_6", }, 53956051948SVladimir Oltean { .offset = 0x109, .name = "drop_yellow_prio_7", }, 54056051948SVladimir Oltean { .offset = 0x10A, .name = "drop_green_prio_0", }, 54156051948SVladimir Oltean { .offset = 0x10B, .name = "drop_green_prio_1", }, 54256051948SVladimir Oltean { .offset = 0x10C, .name = "drop_green_prio_2", }, 54356051948SVladimir Oltean { .offset = 0x10D, .name = "drop_green_prio_3", }, 54456051948SVladimir Oltean { .offset = 0x10E, .name = "drop_green_prio_4", }, 54556051948SVladimir Oltean { .offset = 0x10F, .name = "drop_green_prio_5", }, 54656051948SVladimir Oltean { .offset = 0x110, .name = "drop_green_prio_6", }, 54756051948SVladimir Oltean { .offset = 0x111, .name = "drop_green_prio_7", }, 54856051948SVladimir Oltean }; 54956051948SVladimir Oltean 55056051948SVladimir Oltean #define VSC9959_INIT_TIMEOUT 50000 55156051948SVladimir Oltean #define VSC9959_GCB_RST_SLEEP 100 55256051948SVladimir Oltean #define VSC9959_SYS_RAMINIT_SLEEP 80 55356051948SVladimir Oltean 55456051948SVladimir Oltean static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 55556051948SVladimir Oltean { 55656051948SVladimir Oltean int val; 55756051948SVladimir Oltean 55856051948SVladimir Oltean regmap_field_read(ocelot->regfields[GCB_SOFT_RST_SWC_RST], &val); 55956051948SVladimir Oltean 56056051948SVladimir Oltean return val; 56156051948SVladimir Oltean } 56256051948SVladimir Oltean 56356051948SVladimir Oltean static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 56456051948SVladimir Oltean { 56556051948SVladimir Oltean return ocelot_read(ocelot, SYS_RAM_INIT); 56656051948SVladimir Oltean } 56756051948SVladimir Oltean 56856051948SVladimir Oltean static int vsc9959_reset(struct ocelot *ocelot) 56956051948SVladimir Oltean { 57056051948SVladimir Oltean int val, err; 57156051948SVladimir Oltean 57256051948SVladimir Oltean /* soft-reset the switch core */ 57356051948SVladimir Oltean regmap_field_write(ocelot->regfields[GCB_SOFT_RST_SWC_RST], 1); 57456051948SVladimir Oltean 57556051948SVladimir Oltean err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 57656051948SVladimir Oltean VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 57756051948SVladimir Oltean if (err) { 57856051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch core reset\n"); 57956051948SVladimir Oltean return err; 58056051948SVladimir Oltean } 58156051948SVladimir Oltean 58256051948SVladimir Oltean /* initialize switch mem ~40us */ 58356051948SVladimir Oltean ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 58456051948SVladimir Oltean err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 58556051948SVladimir Oltean VSC9959_SYS_RAMINIT_SLEEP, 58656051948SVladimir Oltean VSC9959_INIT_TIMEOUT); 58756051948SVladimir Oltean if (err) { 58856051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch sram init\n"); 58956051948SVladimir Oltean return err; 59056051948SVladimir Oltean } 59156051948SVladimir Oltean 59256051948SVladimir Oltean /* enable switch core */ 59356051948SVladimir Oltean regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 59456051948SVladimir Oltean 59556051948SVladimir Oltean return 0; 59656051948SVladimir Oltean } 59756051948SVladimir Oltean 598bdeced75SVladimir Oltean static void vsc9959_pcs_an_restart_sgmii(struct phy_device *pcs) 599bdeced75SVladimir Oltean { 600bdeced75SVladimir Oltean phy_set_bits(pcs, MII_BMCR, BMCR_ANRESTART); 601bdeced75SVladimir Oltean } 602bdeced75SVladimir Oltean 603bdeced75SVladimir Oltean static void vsc9959_pcs_an_restart_usxgmii(struct phy_device *pcs) 604bdeced75SVladimir Oltean { 605bdeced75SVladimir Oltean phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_BMCR, 606bdeced75SVladimir Oltean USXGMII_BMCR_RESET | 607bdeced75SVladimir Oltean USXGMII_BMCR_AN_EN | 608bdeced75SVladimir Oltean USXGMII_BMCR_RST_AN); 609bdeced75SVladimir Oltean } 610bdeced75SVladimir Oltean 611bdeced75SVladimir Oltean static void vsc9959_pcs_an_restart(struct ocelot *ocelot, int port) 612bdeced75SVladimir Oltean { 613bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 614bdeced75SVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 615bdeced75SVladimir Oltean 616bdeced75SVladimir Oltean if (!pcs) 617bdeced75SVladimir Oltean return; 618bdeced75SVladimir Oltean 619bdeced75SVladimir Oltean switch (pcs->interface) { 620bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 621bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 622bdeced75SVladimir Oltean vsc9959_pcs_an_restart_sgmii(pcs); 623bdeced75SVladimir Oltean break; 624bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 625bdeced75SVladimir Oltean vsc9959_pcs_an_restart_usxgmii(pcs); 626bdeced75SVladimir Oltean break; 627bdeced75SVladimir Oltean default: 628bdeced75SVladimir Oltean dev_err(ocelot->dev, "Invalid PCS interface type %s\n", 629bdeced75SVladimir Oltean phy_modes(pcs->interface)); 630bdeced75SVladimir Oltean break; 631bdeced75SVladimir Oltean } 632bdeced75SVladimir Oltean } 633bdeced75SVladimir Oltean 634bdeced75SVladimir Oltean /* We enable SGMII AN only when the PHY has managed = "in-band-status" in the 635bdeced75SVladimir Oltean * device tree. If we are in MLO_AN_PHY mode, we program directly state->speed 636bdeced75SVladimir Oltean * into the PCS, which is retrieved out-of-band over MDIO. This also has the 637bdeced75SVladimir Oltean * benefit of working with SGMII fixed-links, like downstream switches, where 638bdeced75SVladimir Oltean * both link partners attempt to operate as AN slaves and therefore AN never 639bdeced75SVladimir Oltean * completes. But it also has the disadvantage that some PHY chips don't pass 640bdeced75SVladimir Oltean * traffic if SGMII AN is enabled but not completed (acknowledged by us), so 641bdeced75SVladimir Oltean * setting MLO_AN_INBAND is actually required for those. 642bdeced75SVladimir Oltean */ 643bdeced75SVladimir Oltean static void vsc9959_pcs_init_sgmii(struct phy_device *pcs, 644bdeced75SVladimir Oltean unsigned int link_an_mode, 645bdeced75SVladimir Oltean const struct phylink_link_state *state) 646bdeced75SVladimir Oltean { 647bdeced75SVladimir Oltean if (link_an_mode == MLO_AN_INBAND) { 648*8c6123e1SAlex Marginean int bmsr, bmcr; 649*8c6123e1SAlex Marginean 650*8c6123e1SAlex Marginean /* Some PHYs like VSC8234 don't like it when AN restarts on 651*8c6123e1SAlex Marginean * their system side and they restart line side AN too, going 652*8c6123e1SAlex Marginean * into an endless link up/down loop. Don't restart PCS AN if 653*8c6123e1SAlex Marginean * link is up already. 654*8c6123e1SAlex Marginean * We do check that AN is enabled just in case this is the 1st 655*8c6123e1SAlex Marginean * call, PCS detects a carrier but AN is disabled from power on 656*8c6123e1SAlex Marginean * or by boot loader. 657*8c6123e1SAlex Marginean */ 658*8c6123e1SAlex Marginean bmcr = phy_read(pcs, MII_BMCR); 659*8c6123e1SAlex Marginean if (bmcr < 0) 660*8c6123e1SAlex Marginean return; 661*8c6123e1SAlex Marginean 662*8c6123e1SAlex Marginean bmsr = phy_read(pcs, MII_BMSR); 663*8c6123e1SAlex Marginean if (bmsr < 0) 664*8c6123e1SAlex Marginean return; 665*8c6123e1SAlex Marginean 666*8c6123e1SAlex Marginean if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_LSTATUS)) 667*8c6123e1SAlex Marginean return; 668*8c6123e1SAlex Marginean 669bdeced75SVladimir Oltean /* SGMII spec requires tx_config_Reg[15:0] to be exactly 0x4001 670bdeced75SVladimir Oltean * for the MAC PCS in order to acknowledge the AN. 671bdeced75SVladimir Oltean */ 672bdeced75SVladimir Oltean phy_write(pcs, MII_ADVERTISE, ADVERTISE_SGMII | 673bdeced75SVladimir Oltean ADVERTISE_LPACK); 674bdeced75SVladimir Oltean 675bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_IF_MODE, 676bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_SGMII_EN | 677bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_USE_SGMII_AN); 678bdeced75SVladimir Oltean 679bdeced75SVladimir Oltean /* Adjust link timer for SGMII */ 680bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_LINK_TIMER1, 681bdeced75SVladimir Oltean ENETC_PCS_LINK_TIMER1_VAL); 682bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_LINK_TIMER2, 683bdeced75SVladimir Oltean ENETC_PCS_LINK_TIMER2_VAL); 684bdeced75SVladimir Oltean 685bdeced75SVladimir Oltean phy_write(pcs, MII_BMCR, BMCR_ANRESTART | BMCR_ANENABLE); 686bdeced75SVladimir Oltean } else { 687bdeced75SVladimir Oltean int speed; 688bdeced75SVladimir Oltean 689bdeced75SVladimir Oltean if (state->duplex == DUPLEX_HALF) { 690bdeced75SVladimir Oltean phydev_err(pcs, "Half duplex not supported\n"); 691bdeced75SVladimir Oltean return; 692bdeced75SVladimir Oltean } 693bdeced75SVladimir Oltean switch (state->speed) { 694bdeced75SVladimir Oltean case SPEED_1000: 695bdeced75SVladimir Oltean speed = ENETC_PCS_SPEED_1000; 696bdeced75SVladimir Oltean break; 697bdeced75SVladimir Oltean case SPEED_100: 698bdeced75SVladimir Oltean speed = ENETC_PCS_SPEED_100; 699bdeced75SVladimir Oltean break; 700bdeced75SVladimir Oltean case SPEED_10: 701bdeced75SVladimir Oltean speed = ENETC_PCS_SPEED_10; 702bdeced75SVladimir Oltean break; 703bdeced75SVladimir Oltean case SPEED_UNKNOWN: 704bdeced75SVladimir Oltean /* Silently don't do anything */ 705bdeced75SVladimir Oltean return; 706bdeced75SVladimir Oltean default: 707bdeced75SVladimir Oltean phydev_err(pcs, "Invalid PCS speed %d\n", state->speed); 708bdeced75SVladimir Oltean return; 709bdeced75SVladimir Oltean } 710bdeced75SVladimir Oltean 711bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_IF_MODE, 712bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_SGMII_EN | 713bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_SGMII_SPEED(speed)); 714bdeced75SVladimir Oltean 715bdeced75SVladimir Oltean /* Yes, not a mistake: speed is given by IF_MODE. */ 716bdeced75SVladimir Oltean phy_write(pcs, MII_BMCR, BMCR_RESET | 717bdeced75SVladimir Oltean BMCR_SPEED1000 | 718bdeced75SVladimir Oltean BMCR_FULLDPLX); 719bdeced75SVladimir Oltean } 720bdeced75SVladimir Oltean } 721bdeced75SVladimir Oltean 722bdeced75SVladimir Oltean /* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane 723bdeced75SVladimir Oltean * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have 724bdeced75SVladimir Oltean * auto-negotiation of any link parameters. Electrically it is compatible with 725bdeced75SVladimir Oltean * a single lane of XAUI. 726bdeced75SVladimir Oltean * The hardware reference manual wants to call this mode SGMII, but it isn't 727bdeced75SVladimir Oltean * really, since the fundamental features of SGMII: 728bdeced75SVladimir Oltean * - Downgrading the link speed by duplicating symbols 729bdeced75SVladimir Oltean * - Auto-negotiation 730bdeced75SVladimir Oltean * are not there. 731bdeced75SVladimir Oltean * The speed is configured at 1000 in the IF_MODE and BMCR MDIO registers 732bdeced75SVladimir Oltean * because the clock frequency is actually given by a PLL configured in the 733bdeced75SVladimir Oltean * Reset Configuration Word (RCW). 734bdeced75SVladimir Oltean * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o 735bdeced75SVladimir Oltean * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a 736bdeced75SVladimir Oltean * lower link speed on line side, the system-side interface remains fixed at 737bdeced75SVladimir Oltean * 2500 Mbps and we do rate adaptation through pause frames. 738bdeced75SVladimir Oltean */ 739bdeced75SVladimir Oltean static void vsc9959_pcs_init_2500basex(struct phy_device *pcs, 740bdeced75SVladimir Oltean unsigned int link_an_mode, 741bdeced75SVladimir Oltean const struct phylink_link_state *state) 742bdeced75SVladimir Oltean { 743bdeced75SVladimir Oltean if (link_an_mode == MLO_AN_INBAND) { 744bdeced75SVladimir Oltean phydev_err(pcs, "AN not supported on 3.125GHz SerDes lane\n"); 745bdeced75SVladimir Oltean return; 746bdeced75SVladimir Oltean } 747bdeced75SVladimir Oltean 748bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_IF_MODE, 749bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_SGMII_EN | 750bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500)); 751bdeced75SVladimir Oltean 752bdeced75SVladimir Oltean phy_write(pcs, MII_BMCR, BMCR_SPEED1000 | 753bdeced75SVladimir Oltean BMCR_FULLDPLX | 754bdeced75SVladimir Oltean BMCR_RESET); 755bdeced75SVladimir Oltean } 756bdeced75SVladimir Oltean 757bdeced75SVladimir Oltean static void vsc9959_pcs_init_usxgmii(struct phy_device *pcs, 758bdeced75SVladimir Oltean unsigned int link_an_mode, 759bdeced75SVladimir Oltean const struct phylink_link_state *state) 760bdeced75SVladimir Oltean { 761bdeced75SVladimir Oltean if (link_an_mode != MLO_AN_INBAND) { 762bdeced75SVladimir Oltean phydev_err(pcs, "USXGMII only supports in-band AN for now\n"); 763bdeced75SVladimir Oltean return; 764bdeced75SVladimir Oltean } 765bdeced75SVladimir Oltean 766bdeced75SVladimir Oltean /* Configure device ability for the USXGMII Replicator */ 767bdeced75SVladimir Oltean phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_ADVERTISE, 768bdeced75SVladimir Oltean USXGMII_ADVERTISE_SPEED(USXGMII_SPEED_2500) | 769bdeced75SVladimir Oltean USXGMII_ADVERTISE_LNKS(1) | 770bdeced75SVladimir Oltean ADVERTISE_SGMII | 771bdeced75SVladimir Oltean ADVERTISE_LPACK | 772bdeced75SVladimir Oltean USXGMII_ADVERTISE_FDX); 773bdeced75SVladimir Oltean } 774bdeced75SVladimir Oltean 775bdeced75SVladimir Oltean static void vsc9959_pcs_init(struct ocelot *ocelot, int port, 776bdeced75SVladimir Oltean unsigned int link_an_mode, 777bdeced75SVladimir Oltean const struct phylink_link_state *state) 778bdeced75SVladimir Oltean { 779bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 780bdeced75SVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 781bdeced75SVladimir Oltean 782bdeced75SVladimir Oltean if (!pcs) 783bdeced75SVladimir Oltean return; 784bdeced75SVladimir Oltean 785bdeced75SVladimir Oltean /* The PCS does not implement the BMSR register fully, so capability 786bdeced75SVladimir Oltean * detection via genphy_read_abilities does not work. Since we can get 787bdeced75SVladimir Oltean * the PHY config word from the LPA register though, there is still 788bdeced75SVladimir Oltean * value in using the generic phy_resolve_aneg_linkmode function. So 789bdeced75SVladimir Oltean * populate the supported and advertising link modes manually here. 790bdeced75SVladimir Oltean */ 791bdeced75SVladimir Oltean linkmode_set_bit_array(phy_basic_ports_array, 792bdeced75SVladimir Oltean ARRAY_SIZE(phy_basic_ports_array), 793bdeced75SVladimir Oltean pcs->supported); 794bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, pcs->supported); 795bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pcs->supported); 796bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, pcs->supported); 797bdeced75SVladimir Oltean if (pcs->interface == PHY_INTERFACE_MODE_2500BASEX || 798bdeced75SVladimir Oltean pcs->interface == PHY_INTERFACE_MODE_USXGMII) 799bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 800bdeced75SVladimir Oltean pcs->supported); 801bdeced75SVladimir Oltean if (pcs->interface != PHY_INTERFACE_MODE_2500BASEX) 802bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 803bdeced75SVladimir Oltean pcs->supported); 804bdeced75SVladimir Oltean phy_advertise_supported(pcs); 805bdeced75SVladimir Oltean 806bdeced75SVladimir Oltean switch (pcs->interface) { 807bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 808bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 809bdeced75SVladimir Oltean vsc9959_pcs_init_sgmii(pcs, link_an_mode, state); 810bdeced75SVladimir Oltean break; 811bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 812bdeced75SVladimir Oltean vsc9959_pcs_init_2500basex(pcs, link_an_mode, state); 813bdeced75SVladimir Oltean break; 814bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 815bdeced75SVladimir Oltean vsc9959_pcs_init_usxgmii(pcs, link_an_mode, state); 816bdeced75SVladimir Oltean break; 817bdeced75SVladimir Oltean default: 818bdeced75SVladimir Oltean dev_err(ocelot->dev, "Unsupported link mode %s\n", 819bdeced75SVladimir Oltean phy_modes(pcs->interface)); 820bdeced75SVladimir Oltean } 821bdeced75SVladimir Oltean } 822bdeced75SVladimir Oltean 823bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_resolve(struct phy_device *pcs, 824bdeced75SVladimir Oltean struct phylink_link_state *state) 825bdeced75SVladimir Oltean { 826bdeced75SVladimir Oltean state->an_complete = pcs->autoneg_complete; 827bdeced75SVladimir Oltean state->an_enabled = pcs->autoneg; 828bdeced75SVladimir Oltean state->link = pcs->link; 829bdeced75SVladimir Oltean state->duplex = pcs->duplex; 830bdeced75SVladimir Oltean state->speed = pcs->speed; 831bdeced75SVladimir Oltean /* SGMII AN does not negotiate flow control, but that's ok, 832bdeced75SVladimir Oltean * since phylink already knows that, and does: 833bdeced75SVladimir Oltean * link_state.pause |= pl->phy_state.pause; 834bdeced75SVladimir Oltean */ 835bdeced75SVladimir Oltean state->pause = MLO_PAUSE_NONE; 836bdeced75SVladimir Oltean 837bdeced75SVladimir Oltean phydev_dbg(pcs, 838bdeced75SVladimir Oltean "mode=%s/%s/%s adv=%*pb lpa=%*pb link=%u an_enabled=%u an_complete=%u\n", 839bdeced75SVladimir Oltean phy_modes(pcs->interface), 840bdeced75SVladimir Oltean phy_speed_to_str(pcs->speed), 841bdeced75SVladimir Oltean phy_duplex_to_str(pcs->duplex), 842bdeced75SVladimir Oltean __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->advertising, 843bdeced75SVladimir Oltean __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->lp_advertising, 844bdeced75SVladimir Oltean pcs->link, pcs->autoneg, pcs->autoneg_complete); 845bdeced75SVladimir Oltean } 846bdeced75SVladimir Oltean 847bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_sgmii(struct phy_device *pcs, 848bdeced75SVladimir Oltean struct phylink_link_state *state) 849bdeced75SVladimir Oltean { 850bdeced75SVladimir Oltean int err; 851bdeced75SVladimir Oltean 852bdeced75SVladimir Oltean err = genphy_update_link(pcs); 853bdeced75SVladimir Oltean if (err < 0) 854bdeced75SVladimir Oltean return; 855bdeced75SVladimir Oltean 856bdeced75SVladimir Oltean if (pcs->autoneg_complete) { 857bdeced75SVladimir Oltean u16 lpa = phy_read(pcs, MII_LPA); 858bdeced75SVladimir Oltean 859bdeced75SVladimir Oltean mii_lpa_to_linkmode_lpa_sgmii(pcs->lp_advertising, lpa); 860bdeced75SVladimir Oltean 861bdeced75SVladimir Oltean phy_resolve_aneg_linkmode(pcs); 862bdeced75SVladimir Oltean } 863bdeced75SVladimir Oltean } 864bdeced75SVladimir Oltean 865bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_2500basex(struct phy_device *pcs, 866bdeced75SVladimir Oltean struct phylink_link_state *state) 867bdeced75SVladimir Oltean { 868bdeced75SVladimir Oltean int err; 869bdeced75SVladimir Oltean 870bdeced75SVladimir Oltean err = genphy_update_link(pcs); 871bdeced75SVladimir Oltean if (err < 0) 872bdeced75SVladimir Oltean return; 873bdeced75SVladimir Oltean 874bdeced75SVladimir Oltean pcs->speed = SPEED_2500; 875bdeced75SVladimir Oltean pcs->asym_pause = true; 876bdeced75SVladimir Oltean pcs->pause = true; 877bdeced75SVladimir Oltean } 878bdeced75SVladimir Oltean 879bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_usxgmii(struct phy_device *pcs, 880bdeced75SVladimir Oltean struct phylink_link_state *state) 881bdeced75SVladimir Oltean { 882bdeced75SVladimir Oltean int status, lpa; 883bdeced75SVladimir Oltean 884bdeced75SVladimir Oltean status = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_BMSR); 885bdeced75SVladimir Oltean if (status < 0) 886bdeced75SVladimir Oltean return; 887bdeced75SVladimir Oltean 888bdeced75SVladimir Oltean pcs->autoneg = true; 889bdeced75SVladimir Oltean pcs->autoneg_complete = USXGMII_BMSR_AN_CMPL(status); 890bdeced75SVladimir Oltean pcs->link = USXGMII_BMSR_LNKS(status); 891bdeced75SVladimir Oltean 892bdeced75SVladimir Oltean if (!pcs->link || !pcs->autoneg_complete) 893bdeced75SVladimir Oltean return; 894bdeced75SVladimir Oltean 895bdeced75SVladimir Oltean lpa = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_LPA); 896bdeced75SVladimir Oltean if (lpa < 0) 897bdeced75SVladimir Oltean return; 898bdeced75SVladimir Oltean 899bdeced75SVladimir Oltean switch (USXGMII_LPA_SPEED(lpa)) { 900bdeced75SVladimir Oltean case USXGMII_SPEED_10: 901bdeced75SVladimir Oltean pcs->speed = SPEED_10; 902bdeced75SVladimir Oltean break; 903bdeced75SVladimir Oltean case USXGMII_SPEED_100: 904bdeced75SVladimir Oltean pcs->speed = SPEED_100; 905bdeced75SVladimir Oltean break; 906bdeced75SVladimir Oltean case USXGMII_SPEED_1000: 907bdeced75SVladimir Oltean pcs->speed = SPEED_1000; 908bdeced75SVladimir Oltean break; 909bdeced75SVladimir Oltean case USXGMII_SPEED_2500: 910bdeced75SVladimir Oltean pcs->speed = SPEED_2500; 911bdeced75SVladimir Oltean break; 912bdeced75SVladimir Oltean default: 913bdeced75SVladimir Oltean break; 914bdeced75SVladimir Oltean } 915bdeced75SVladimir Oltean 916bdeced75SVladimir Oltean if (USXGMII_LPA_DUPLEX(lpa)) 917bdeced75SVladimir Oltean pcs->duplex = DUPLEX_FULL; 918bdeced75SVladimir Oltean else 919bdeced75SVladimir Oltean pcs->duplex = DUPLEX_HALF; 920bdeced75SVladimir Oltean } 921bdeced75SVladimir Oltean 922bdeced75SVladimir Oltean static void vsc9959_pcs_link_state(struct ocelot *ocelot, int port, 923bdeced75SVladimir Oltean struct phylink_link_state *state) 924bdeced75SVladimir Oltean { 925bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 926bdeced75SVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 927bdeced75SVladimir Oltean 928bdeced75SVladimir Oltean if (!pcs) 929bdeced75SVladimir Oltean return; 930bdeced75SVladimir Oltean 931bdeced75SVladimir Oltean pcs->speed = SPEED_UNKNOWN; 932bdeced75SVladimir Oltean pcs->duplex = DUPLEX_UNKNOWN; 933bdeced75SVladimir Oltean pcs->pause = 0; 934bdeced75SVladimir Oltean pcs->asym_pause = 0; 935bdeced75SVladimir Oltean 936bdeced75SVladimir Oltean switch (pcs->interface) { 937bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 938bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 939bdeced75SVladimir Oltean vsc9959_pcs_link_state_sgmii(pcs, state); 940bdeced75SVladimir Oltean break; 941bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 942bdeced75SVladimir Oltean vsc9959_pcs_link_state_2500basex(pcs, state); 943bdeced75SVladimir Oltean break; 944bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 945bdeced75SVladimir Oltean vsc9959_pcs_link_state_usxgmii(pcs, state); 946bdeced75SVladimir Oltean break; 947bdeced75SVladimir Oltean default: 948bdeced75SVladimir Oltean return; 949bdeced75SVladimir Oltean } 950bdeced75SVladimir Oltean 951bdeced75SVladimir Oltean vsc9959_pcs_link_state_resolve(pcs, state); 952bdeced75SVladimir Oltean } 953bdeced75SVladimir Oltean 954bdeced75SVladimir Oltean static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port, 955bdeced75SVladimir Oltean phy_interface_t phy_mode) 956bdeced75SVladimir Oltean { 957bdeced75SVladimir Oltean switch (phy_mode) { 958bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_GMII: 959bdeced75SVladimir Oltean /* Only supported on internal to-CPU ports */ 960bdeced75SVladimir Oltean if (port != 4 && port != 5) 961bdeced75SVladimir Oltean return -ENOTSUPP; 962bdeced75SVladimir Oltean return 0; 963bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 964bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 965bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 966bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 967bdeced75SVladimir Oltean /* Not supported on internal to-CPU ports */ 968bdeced75SVladimir Oltean if (port == 4 || port == 5) 969bdeced75SVladimir Oltean return -ENOTSUPP; 970bdeced75SVladimir Oltean return 0; 971bdeced75SVladimir Oltean default: 972bdeced75SVladimir Oltean return -ENOTSUPP; 973bdeced75SVladimir Oltean } 974bdeced75SVladimir Oltean } 975bdeced75SVladimir Oltean 97656051948SVladimir Oltean static const struct ocelot_ops vsc9959_ops = { 97756051948SVladimir Oltean .reset = vsc9959_reset, 97856051948SVladimir Oltean }; 97956051948SVladimir Oltean 980bdeced75SVladimir Oltean static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 981bdeced75SVladimir Oltean { 982bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 983bdeced75SVladimir Oltean struct enetc_mdio_priv *mdio_priv; 984bdeced75SVladimir Oltean struct device *dev = ocelot->dev; 985bdeced75SVladimir Oltean resource_size_t imdio_base; 986bdeced75SVladimir Oltean void __iomem *imdio_regs; 987bdeced75SVladimir Oltean struct resource *res; 988bdeced75SVladimir Oltean struct enetc_hw *hw; 989bdeced75SVladimir Oltean struct mii_bus *bus; 990bdeced75SVladimir Oltean int port; 991bdeced75SVladimir Oltean int rc; 992bdeced75SVladimir Oltean 993bdeced75SVladimir Oltean felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 994bdeced75SVladimir Oltean sizeof(struct phy_device *), 995bdeced75SVladimir Oltean GFP_KERNEL); 996bdeced75SVladimir Oltean if (!felix->pcs) { 997bdeced75SVladimir Oltean dev_err(dev, "failed to allocate array for PCS PHYs\n"); 998bdeced75SVladimir Oltean return -ENOMEM; 999bdeced75SVladimir Oltean } 1000bdeced75SVladimir Oltean 1001bdeced75SVladimir Oltean imdio_base = pci_resource_start(felix->pdev, 1002bdeced75SVladimir Oltean felix->info->imdio_pci_bar); 1003bdeced75SVladimir Oltean 1004bdeced75SVladimir Oltean res = felix->info->imdio_res; 1005bdeced75SVladimir Oltean res->flags = IORESOURCE_MEM; 1006bdeced75SVladimir Oltean res->start += imdio_base; 1007bdeced75SVladimir Oltean res->end += imdio_base; 1008bdeced75SVladimir Oltean 1009bdeced75SVladimir Oltean imdio_regs = devm_ioremap_resource(dev, res); 1010bdeced75SVladimir Oltean if (IS_ERR(imdio_regs)) { 1011bdeced75SVladimir Oltean dev_err(dev, "failed to map internal MDIO registers\n"); 1012bdeced75SVladimir Oltean return PTR_ERR(imdio_regs); 1013bdeced75SVladimir Oltean } 1014bdeced75SVladimir Oltean 1015bdeced75SVladimir Oltean hw = enetc_hw_alloc(dev, imdio_regs); 1016bdeced75SVladimir Oltean if (IS_ERR(hw)) { 1017bdeced75SVladimir Oltean dev_err(dev, "failed to allocate ENETC HW structure\n"); 1018bdeced75SVladimir Oltean return PTR_ERR(hw); 1019bdeced75SVladimir Oltean } 1020bdeced75SVladimir Oltean 1021bdeced75SVladimir Oltean bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv)); 1022bdeced75SVladimir Oltean if (!bus) 1023bdeced75SVladimir Oltean return -ENOMEM; 1024bdeced75SVladimir Oltean 1025bdeced75SVladimir Oltean bus->name = "VSC9959 internal MDIO bus"; 1026bdeced75SVladimir Oltean bus->read = enetc_mdio_read; 1027bdeced75SVladimir Oltean bus->write = enetc_mdio_write; 1028bdeced75SVladimir Oltean bus->parent = dev; 1029bdeced75SVladimir Oltean mdio_priv = bus->priv; 1030bdeced75SVladimir Oltean mdio_priv->hw = hw; 1031bdeced75SVladimir Oltean /* This gets added to imdio_regs, which already maps addresses 1032bdeced75SVladimir Oltean * starting with the proper offset. 1033bdeced75SVladimir Oltean */ 1034bdeced75SVladimir Oltean mdio_priv->mdio_base = 0; 1035bdeced75SVladimir Oltean snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1036bdeced75SVladimir Oltean 1037bdeced75SVladimir Oltean /* Needed in order to initialize the bus mutex lock */ 1038bdeced75SVladimir Oltean rc = mdiobus_register(bus); 1039bdeced75SVladimir Oltean if (rc < 0) { 1040bdeced75SVladimir Oltean dev_err(dev, "failed to register MDIO bus\n"); 1041bdeced75SVladimir Oltean return rc; 1042bdeced75SVladimir Oltean } 1043bdeced75SVladimir Oltean 1044bdeced75SVladimir Oltean felix->imdio = bus; 1045bdeced75SVladimir Oltean 1046bdeced75SVladimir Oltean for (port = 0; port < felix->info->num_ports; port++) { 1047bdeced75SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 1048bdeced75SVladimir Oltean struct phy_device *pcs; 1049bdeced75SVladimir Oltean bool is_c45 = false; 1050bdeced75SVladimir Oltean 1051bdeced75SVladimir Oltean if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_USXGMII) 1052bdeced75SVladimir Oltean is_c45 = true; 1053bdeced75SVladimir Oltean 1054bdeced75SVladimir Oltean pcs = get_phy_device(felix->imdio, port, is_c45); 1055bdeced75SVladimir Oltean if (IS_ERR(pcs)) 1056bdeced75SVladimir Oltean continue; 1057bdeced75SVladimir Oltean 1058bdeced75SVladimir Oltean pcs->interface = ocelot_port->phy_mode; 1059bdeced75SVladimir Oltean felix->pcs[port] = pcs; 1060bdeced75SVladimir Oltean 1061bdeced75SVladimir Oltean dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1062bdeced75SVladimir Oltean } 1063bdeced75SVladimir Oltean 1064bdeced75SVladimir Oltean return 0; 1065bdeced75SVladimir Oltean } 1066bdeced75SVladimir Oltean 1067bdeced75SVladimir Oltean static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1068bdeced75SVladimir Oltean { 1069bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1070bdeced75SVladimir Oltean int port; 1071bdeced75SVladimir Oltean 1072bdeced75SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) { 1073bdeced75SVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 1074bdeced75SVladimir Oltean 1075bdeced75SVladimir Oltean if (!pcs) 1076bdeced75SVladimir Oltean continue; 1077bdeced75SVladimir Oltean 1078bdeced75SVladimir Oltean put_device(&pcs->mdio.dev); 1079bdeced75SVladimir Oltean } 1080bdeced75SVladimir Oltean mdiobus_unregister(felix->imdio); 1081bdeced75SVladimir Oltean } 1082bdeced75SVladimir Oltean 108356051948SVladimir Oltean struct felix_info felix_info_vsc9959 = { 108456051948SVladimir Oltean .target_io_res = vsc9959_target_io_res, 108556051948SVladimir Oltean .port_io_res = vsc9959_port_io_res, 1086bdeced75SVladimir Oltean .imdio_res = &vsc9959_imdio_res, 108756051948SVladimir Oltean .regfields = vsc9959_regfields, 108856051948SVladimir Oltean .map = vsc9959_regmap, 108956051948SVladimir Oltean .ops = &vsc9959_ops, 109056051948SVladimir Oltean .stats_layout = vsc9959_stats_layout, 109156051948SVladimir Oltean .num_stats = ARRAY_SIZE(vsc9959_stats_layout), 109256051948SVladimir Oltean .shared_queue_sz = 128 * 1024, 109356051948SVladimir Oltean .num_ports = 6, 1094bdeced75SVladimir Oltean .switch_pci_bar = 4, 1095bdeced75SVladimir Oltean .imdio_pci_bar = 0, 1096bdeced75SVladimir Oltean .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 1097bdeced75SVladimir Oltean .mdio_bus_free = vsc9959_mdio_bus_free, 1098bdeced75SVladimir Oltean .pcs_init = vsc9959_pcs_init, 1099bdeced75SVladimir Oltean .pcs_an_restart = vsc9959_pcs_an_restart, 1100bdeced75SVladimir Oltean .pcs_link_state = vsc9959_pcs_link_state, 1101bdeced75SVladimir Oltean .prevalidate_phy_mode = vsc9959_prevalidate_phy_mode, 110256051948SVladimir Oltean }; 1103