156051948SVladimir Oltean // SPDX-License-Identifier: (GPL-2.0 OR MIT) 256051948SVladimir Oltean /* Copyright 2017 Microsemi Corporation 33c9cfb52SVladimir Oltean * Copyright 2018-2019 NXP 456051948SVladimir Oltean */ 5bdeced75SVladimir Oltean #include <linux/fsl/enetc_mdio.h> 6de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_qsys.h> 707d985eeSVladimir Oltean #include <soc/mscc/ocelot_vcap.h> 87d4b564dSXiaoliang Yang #include <soc/mscc/ocelot_ana.h> 9de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_ptp.h> 1056051948SVladimir Oltean #include <soc/mscc/ocelot_sys.h> 1123ae3a78SXiaoliang Yang #include <net/tc_act/tc_gate.h> 1256051948SVladimir Oltean #include <soc/mscc/ocelot.h> 1340d3f295SVladimir Oltean #include <linux/dsa/ocelot.h> 14588d0550SIoana Ciornei #include <linux/pcs-lynx.h> 15de143c0eSXiaoliang Yang #include <net/pkt_sched.h> 1656051948SVladimir Oltean #include <linux/iopoll.h> 1716659b81SMichael Walle #include <linux/mdio.h> 1856051948SVladimir Oltean #include <linux/pci.h> 19837ced3aSVladimir Oltean #include <linux/time.h> 2056051948SVladimir Oltean #include "felix.h" 2156051948SVladimir Oltean 22acf242fcSColin Foster #define VSC9959_NUM_PORTS 6 23acf242fcSColin Foster 24de143c0eSXiaoliang Yang #define VSC9959_TAS_GCL_ENTRY_MAX 63 2577043c37SXiaoliang Yang #define VSC9959_VCAP_POLICER_BASE 63 2677043c37SXiaoliang Yang #define VSC9959_VCAP_POLICER_MAX 383 27c9910484SColin Foster #define VSC9959_SWITCH_PCI_BAR 4 28c9910484SColin Foster #define VSC9959_IMDIO_PCI_BAR 0 29de143c0eSXiaoliang Yang 30acf242fcSColin Foster #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ 31acf242fcSColin Foster OCELOT_PORT_MODE_QSGMII | \ 3211ecf341SVladimir Oltean OCELOT_PORT_MODE_1000BASEX | \ 33acf242fcSColin Foster OCELOT_PORT_MODE_2500BASEX | \ 34acf242fcSColin Foster OCELOT_PORT_MODE_USXGMII) 35acf242fcSColin Foster 36acf242fcSColin Foster static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { 37acf242fcSColin Foster VSC9959_PORT_MODE_SERDES, 38acf242fcSColin Foster VSC9959_PORT_MODE_SERDES, 39acf242fcSColin Foster VSC9959_PORT_MODE_SERDES, 40acf242fcSColin Foster VSC9959_PORT_MODE_SERDES, 41acf242fcSColin Foster OCELOT_PORT_MODE_INTERNAL, 42a53cbe5dSVladimir Oltean OCELOT_PORT_MODE_INTERNAL, 43acf242fcSColin Foster }; 44acf242fcSColin Foster 4556051948SVladimir Oltean static const u32 vsc9959_ana_regmap[] = { 4656051948SVladimir Oltean REG(ANA_ADVLEARN, 0x0089a0), 4756051948SVladimir Oltean REG(ANA_VLANMASK, 0x0089a4), 4856051948SVladimir Oltean REG_RESERVED(ANA_PORT_B_DOMAIN), 4956051948SVladimir Oltean REG(ANA_ANAGEFIL, 0x0089ac), 5056051948SVladimir Oltean REG(ANA_ANEVENTS, 0x0089b0), 5156051948SVladimir Oltean REG(ANA_STORMLIMIT_BURST, 0x0089b4), 5256051948SVladimir Oltean REG(ANA_STORMLIMIT_CFG, 0x0089b8), 5356051948SVladimir Oltean REG(ANA_ISOLATED_PORTS, 0x0089c8), 5456051948SVladimir Oltean REG(ANA_COMMUNITY_PORTS, 0x0089cc), 5556051948SVladimir Oltean REG(ANA_AUTOAGE, 0x0089d0), 5656051948SVladimir Oltean REG(ANA_MACTOPTIONS, 0x0089d4), 5756051948SVladimir Oltean REG(ANA_LEARNDISC, 0x0089d8), 5856051948SVladimir Oltean REG(ANA_AGENCTRL, 0x0089dc), 5956051948SVladimir Oltean REG(ANA_MIRRORPORTS, 0x0089e0), 6056051948SVladimir Oltean REG(ANA_EMIRRORPORTS, 0x0089e4), 6156051948SVladimir Oltean REG(ANA_FLOODING, 0x0089e8), 6256051948SVladimir Oltean REG(ANA_FLOODING_IPMC, 0x008a08), 6356051948SVladimir Oltean REG(ANA_SFLOW_CFG, 0x008a0c), 6456051948SVladimir Oltean REG(ANA_PORT_MODE, 0x008a28), 6556051948SVladimir Oltean REG(ANA_CUT_THRU_CFG, 0x008a48), 6656051948SVladimir Oltean REG(ANA_PGID_PGID, 0x008400), 6756051948SVladimir Oltean REG(ANA_TABLES_ANMOVED, 0x007f1c), 6856051948SVladimir Oltean REG(ANA_TABLES_MACHDATA, 0x007f20), 6956051948SVladimir Oltean REG(ANA_TABLES_MACLDATA, 0x007f24), 7056051948SVladimir Oltean REG(ANA_TABLES_STREAMDATA, 0x007f28), 7156051948SVladimir Oltean REG(ANA_TABLES_MACACCESS, 0x007f2c), 7256051948SVladimir Oltean REG(ANA_TABLES_MACTINDX, 0x007f30), 7356051948SVladimir Oltean REG(ANA_TABLES_VLANACCESS, 0x007f34), 7456051948SVladimir Oltean REG(ANA_TABLES_VLANTIDX, 0x007f38), 7556051948SVladimir Oltean REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 7656051948SVladimir Oltean REG(ANA_TABLES_ISDXTIDX, 0x007f40), 7756051948SVladimir Oltean REG(ANA_TABLES_ENTRYLIM, 0x007f00), 7856051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 7956051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 8056051948SVladimir Oltean REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 8156051948SVladimir Oltean REG(ANA_TABLES_STREAMTIDX, 0x007f50), 8256051948SVladimir Oltean REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 8356051948SVladimir Oltean REG(ANA_TABLES_SEQ_MASK, 0x007f58), 8456051948SVladimir Oltean REG(ANA_TABLES_SFID_MASK, 0x007f5c), 8556051948SVladimir Oltean REG(ANA_TABLES_SFIDACCESS, 0x007f60), 8656051948SVladimir Oltean REG(ANA_TABLES_SFIDTIDX, 0x007f64), 8756051948SVladimir Oltean REG(ANA_MSTI_STATE, 0x008600), 8856051948SVladimir Oltean REG(ANA_OAM_UPM_LM_CNT, 0x008000), 8956051948SVladimir Oltean REG(ANA_SG_ACCESS_CTRL, 0x008a64), 9056051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 9156051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 9256051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 9356051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 9456051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 9556051948SVladimir Oltean REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 9656051948SVladimir Oltean REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 9756051948SVladimir Oltean REG(ANA_SG_STATUS_REG_1, 0x008980), 9856051948SVladimir Oltean REG(ANA_SG_STATUS_REG_2, 0x008984), 9956051948SVladimir Oltean REG(ANA_SG_STATUS_REG_3, 0x008988), 10056051948SVladimir Oltean REG(ANA_PORT_VLAN_CFG, 0x007800), 10156051948SVladimir Oltean REG(ANA_PORT_DROP_CFG, 0x007804), 10256051948SVladimir Oltean REG(ANA_PORT_QOS_CFG, 0x007808), 10356051948SVladimir Oltean REG(ANA_PORT_VCAP_CFG, 0x00780c), 10456051948SVladimir Oltean REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 10556051948SVladimir Oltean REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 10656051948SVladimir Oltean REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 10756051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 10856051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 10956051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 11056051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 11156051948SVladimir Oltean REG(ANA_PORT_PORT_CFG, 0x007870), 11256051948SVladimir Oltean REG(ANA_PORT_POL_CFG, 0x007874), 11356051948SVladimir Oltean REG(ANA_PORT_PTP_CFG, 0x007878), 11456051948SVladimir Oltean REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 11556051948SVladimir Oltean REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 11656051948SVladimir Oltean REG(ANA_PORT_SFID_CFG, 0x007884), 11756051948SVladimir Oltean REG(ANA_PFC_PFC_CFG, 0x008800), 11856051948SVladimir Oltean REG_RESERVED(ANA_PFC_PFC_TIMER), 11956051948SVladimir Oltean REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 12056051948SVladimir Oltean REG_RESERVED(ANA_IPT_IPT), 12156051948SVladimir Oltean REG_RESERVED(ANA_PPT_PPT), 12256051948SVladimir Oltean REG_RESERVED(ANA_FID_MAP_FID_MAP), 12356051948SVladimir Oltean REG(ANA_AGGR_CFG, 0x008a68), 12456051948SVladimir Oltean REG(ANA_CPUQ_CFG, 0x008a6c), 12556051948SVladimir Oltean REG_RESERVED(ANA_CPUQ_CFG2), 12656051948SVladimir Oltean REG(ANA_CPUQ_8021_CFG, 0x008a74), 12756051948SVladimir Oltean REG(ANA_DSCP_CFG, 0x008ab4), 12856051948SVladimir Oltean REG(ANA_DSCP_REWR_CFG, 0x008bb4), 12956051948SVladimir Oltean REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 13056051948SVladimir Oltean REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 13156051948SVladimir Oltean REG_RESERVED(ANA_VRAP_CFG), 13256051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_DATA), 13356051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_MASK), 13456051948SVladimir Oltean REG(ANA_DISCARD_CFG, 0x008c40), 13556051948SVladimir Oltean REG(ANA_FID_CFG, 0x008c44), 13656051948SVladimir Oltean REG(ANA_POL_PIR_CFG, 0x004000), 13756051948SVladimir Oltean REG(ANA_POL_CIR_CFG, 0x004004), 13856051948SVladimir Oltean REG(ANA_POL_MODE_CFG, 0x004008), 13956051948SVladimir Oltean REG(ANA_POL_PIR_STATE, 0x00400c), 14056051948SVladimir Oltean REG(ANA_POL_CIR_STATE, 0x004010), 14156051948SVladimir Oltean REG_RESERVED(ANA_POL_STATE), 14256051948SVladimir Oltean REG(ANA_POL_FLOWC, 0x008c48), 14356051948SVladimir Oltean REG(ANA_POL_HYST, 0x008cb4), 14456051948SVladimir Oltean REG_RESERVED(ANA_POL_MISC_CFG), 14556051948SVladimir Oltean }; 14656051948SVladimir Oltean 14756051948SVladimir Oltean static const u32 vsc9959_qs_regmap[] = { 14856051948SVladimir Oltean REG(QS_XTR_GRP_CFG, 0x000000), 14956051948SVladimir Oltean REG(QS_XTR_RD, 0x000008), 15056051948SVladimir Oltean REG(QS_XTR_FRM_PRUNING, 0x000010), 15156051948SVladimir Oltean REG(QS_XTR_FLUSH, 0x000018), 15256051948SVladimir Oltean REG(QS_XTR_DATA_PRESENT, 0x00001c), 15356051948SVladimir Oltean REG(QS_XTR_CFG, 0x000020), 15456051948SVladimir Oltean REG(QS_INJ_GRP_CFG, 0x000024), 15556051948SVladimir Oltean REG(QS_INJ_WR, 0x00002c), 15656051948SVladimir Oltean REG(QS_INJ_CTRL, 0x000034), 15756051948SVladimir Oltean REG(QS_INJ_STATUS, 0x00003c), 15856051948SVladimir Oltean REG(QS_INJ_ERR, 0x000040), 15956051948SVladimir Oltean REG_RESERVED(QS_INH_DBG), 16056051948SVladimir Oltean }; 16156051948SVladimir Oltean 162c1c3993eSVladimir Oltean static const u32 vsc9959_vcap_regmap[] = { 163c1c3993eSVladimir Oltean /* VCAP_CORE_CFG */ 164c1c3993eSVladimir Oltean REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 165c1c3993eSVladimir Oltean REG(VCAP_CORE_MV_CFG, 0x000004), 166c1c3993eSVladimir Oltean /* VCAP_CORE_CACHE */ 167c1c3993eSVladimir Oltean REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 168c1c3993eSVladimir Oltean REG(VCAP_CACHE_MASK_DAT, 0x000108), 169c1c3993eSVladimir Oltean REG(VCAP_CACHE_ACTION_DAT, 0x000208), 170c1c3993eSVladimir Oltean REG(VCAP_CACHE_CNT_DAT, 0x000308), 171c1c3993eSVladimir Oltean REG(VCAP_CACHE_TG_DAT, 0x000388), 17220968054SVladimir Oltean /* VCAP_CONST */ 17320968054SVladimir Oltean REG(VCAP_CONST_VCAP_VER, 0x000398), 17420968054SVladimir Oltean REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 17520968054SVladimir Oltean REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 17620968054SVladimir Oltean REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 17720968054SVladimir Oltean REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 17820968054SVladimir Oltean REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 17920968054SVladimir Oltean REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 18020968054SVladimir Oltean REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 18120968054SVladimir Oltean REG(VCAP_CONST_CORE_CNT, 0x0003b8), 18220968054SVladimir Oltean REG(VCAP_CONST_IF_CNT, 0x0003bc), 18356051948SVladimir Oltean }; 18456051948SVladimir Oltean 18556051948SVladimir Oltean static const u32 vsc9959_qsys_regmap[] = { 18656051948SVladimir Oltean REG(QSYS_PORT_MODE, 0x00f460), 18756051948SVladimir Oltean REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 18856051948SVladimir Oltean REG(QSYS_STAT_CNT_CFG, 0x00f49c), 18956051948SVladimir Oltean REG(QSYS_EEE_CFG, 0x00f4a0), 19056051948SVladimir Oltean REG(QSYS_EEE_THRES, 0x00f4b8), 19156051948SVladimir Oltean REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 19256051948SVladimir Oltean REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 19356051948SVladimir Oltean REG(QSYS_SW_STATUS, 0x00f4c4), 19456051948SVladimir Oltean REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 19556051948SVladimir Oltean REG_RESERVED(QSYS_PAD_CFG), 19656051948SVladimir Oltean REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 19756051948SVladimir Oltean REG_RESERVED(QSYS_QMAP), 19856051948SVladimir Oltean REG_RESERVED(QSYS_ISDX_SGRP), 19956051948SVladimir Oltean REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 20056051948SVladimir Oltean REG(QSYS_TFRM_MISC, 0x00f50c), 20156051948SVladimir Oltean REG(QSYS_TFRM_PORT_DLY, 0x00f510), 20256051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 20356051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 20456051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 20556051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 20656051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 20756051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 20856051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 20956051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 21056051948SVladimir Oltean REG(QSYS_RED_PROFILE, 0x00f534), 21156051948SVladimir Oltean REG(QSYS_RES_QOS_MODE, 0x00f574), 21256051948SVladimir Oltean REG(QSYS_RES_CFG, 0x00c000), 21356051948SVladimir Oltean REG(QSYS_RES_STAT, 0x00c004), 21456051948SVladimir Oltean REG(QSYS_EGR_DROP_MODE, 0x00f578), 21556051948SVladimir Oltean REG(QSYS_EQ_CTRL, 0x00f57c), 21656051948SVladimir Oltean REG_RESERVED(QSYS_EVENTS_CORE), 21756051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 21856051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 21956051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 22056051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 22156051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 22256051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 22356051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 22456051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 22556051948SVladimir Oltean REG(QSYS_PREEMPTION_CFG, 0x00f664), 2260fbabf87SXiaoliang Yang REG(QSYS_CIR_CFG, 0x000000), 22756051948SVladimir Oltean REG(QSYS_EIR_CFG, 0x000004), 22856051948SVladimir Oltean REG(QSYS_SE_CFG, 0x000008), 22956051948SVladimir Oltean REG(QSYS_SE_DWRR_CFG, 0x00000c), 23056051948SVladimir Oltean REG_RESERVED(QSYS_SE_CONNECT), 23156051948SVladimir Oltean REG(QSYS_SE_DLB_SENSE, 0x000040), 23256051948SVladimir Oltean REG(QSYS_CIR_STATE, 0x000044), 23356051948SVladimir Oltean REG(QSYS_EIR_STATE, 0x000048), 23456051948SVladimir Oltean REG_RESERVED(QSYS_SE_STATE), 23556051948SVladimir Oltean REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 23656051948SVladimir Oltean REG(QSYS_TAG_CONFIG, 0x00f680), 23756051948SVladimir Oltean REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 23856051948SVladimir Oltean REG(QSYS_PORT_MAX_SDU, 0x00f69c), 23956051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 24056051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 24156051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 24256051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 24356051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 24456051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_1, 0x00f454), 24556051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_2, 0x00f458), 24656051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 24756051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 24856051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 24956051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 25056051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 25156051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 25256051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 25356051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 25456051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 25556051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 25656051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 25756051948SVladimir Oltean }; 25856051948SVladimir Oltean 25956051948SVladimir Oltean static const u32 vsc9959_rew_regmap[] = { 26056051948SVladimir Oltean REG(REW_PORT_VLAN_CFG, 0x000000), 26156051948SVladimir Oltean REG(REW_TAG_CFG, 0x000004), 26256051948SVladimir Oltean REG(REW_PORT_CFG, 0x000008), 26356051948SVladimir Oltean REG(REW_DSCP_CFG, 0x00000c), 26456051948SVladimir Oltean REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 26556051948SVladimir Oltean REG(REW_PTP_CFG, 0x000050), 26656051948SVladimir Oltean REG(REW_PTP_DLY1_CFG, 0x000054), 26756051948SVladimir Oltean REG(REW_RED_TAG_CFG, 0x000058), 26856051948SVladimir Oltean REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 26956051948SVladimir Oltean REG(REW_DSCP_REMAP_CFG, 0x000510), 27056051948SVladimir Oltean REG_RESERVED(REW_STAT_CFG), 27156051948SVladimir Oltean REG_RESERVED(REW_REW_STICKY), 27256051948SVladimir Oltean REG_RESERVED(REW_PPT), 27356051948SVladimir Oltean }; 27456051948SVladimir Oltean 27556051948SVladimir Oltean static const u32 vsc9959_sys_regmap[] = { 27656051948SVladimir Oltean REG(SYS_COUNT_RX_OCTETS, 0x000000), 27756051948SVladimir Oltean REG(SYS_COUNT_RX_MULTICAST, 0x000008), 27856051948SVladimir Oltean REG(SYS_COUNT_RX_SHORTS, 0x000010), 27956051948SVladimir Oltean REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 28056051948SVladimir Oltean REG(SYS_COUNT_RX_JABBERS, 0x000018), 28156051948SVladimir Oltean REG(SYS_COUNT_RX_64, 0x000024), 28256051948SVladimir Oltean REG(SYS_COUNT_RX_65_127, 0x000028), 28356051948SVladimir Oltean REG(SYS_COUNT_RX_128_255, 0x00002c), 28456051948SVladimir Oltean REG(SYS_COUNT_RX_256_1023, 0x000030), 28556051948SVladimir Oltean REG(SYS_COUNT_RX_1024_1526, 0x000034), 28656051948SVladimir Oltean REG(SYS_COUNT_RX_1527_MAX, 0x000038), 28756051948SVladimir Oltean REG(SYS_COUNT_RX_LONGS, 0x000044), 28856051948SVladimir Oltean REG(SYS_COUNT_TX_OCTETS, 0x000200), 28956051948SVladimir Oltean REG(SYS_COUNT_TX_COLLISION, 0x000210), 29056051948SVladimir Oltean REG(SYS_COUNT_TX_DROPS, 0x000214), 29156051948SVladimir Oltean REG(SYS_COUNT_TX_64, 0x00021c), 29256051948SVladimir Oltean REG(SYS_COUNT_TX_65_127, 0x000220), 29356051948SVladimir Oltean REG(SYS_COUNT_TX_128_511, 0x000224), 29456051948SVladimir Oltean REG(SYS_COUNT_TX_512_1023, 0x000228), 29556051948SVladimir Oltean REG(SYS_COUNT_TX_1024_1526, 0x00022c), 29656051948SVladimir Oltean REG(SYS_COUNT_TX_1527_MAX, 0x000230), 29756051948SVladimir Oltean REG(SYS_COUNT_TX_AGING, 0x000278), 29856051948SVladimir Oltean REG(SYS_RESET_CFG, 0x000e00), 29956051948SVladimir Oltean REG(SYS_SR_ETYPE_CFG, 0x000e04), 30056051948SVladimir Oltean REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 30156051948SVladimir Oltean REG(SYS_PORT_MODE, 0x000e0c), 30256051948SVladimir Oltean REG(SYS_FRONT_PORT_MODE, 0x000e2c), 30356051948SVladimir Oltean REG(SYS_FRM_AGING, 0x000e44), 30456051948SVladimir Oltean REG(SYS_STAT_CFG, 0x000e48), 30556051948SVladimir Oltean REG(SYS_SW_STATUS, 0x000e4c), 30656051948SVladimir Oltean REG_RESERVED(SYS_MISC_CFG), 30756051948SVladimir Oltean REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 30856051948SVladimir Oltean REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 30956051948SVladimir Oltean REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 31056051948SVladimir Oltean REG(SYS_PAUSE_CFG, 0x000ea0), 31156051948SVladimir Oltean REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 31256051948SVladimir Oltean REG(SYS_ATOP, 0x000ec0), 31356051948SVladimir Oltean REG(SYS_ATOP_TOT_CFG, 0x000edc), 31456051948SVladimir Oltean REG(SYS_MAC_FC_CFG, 0x000ee0), 31556051948SVladimir Oltean REG(SYS_MMGT, 0x000ef8), 31656051948SVladimir Oltean REG_RESERVED(SYS_MMGT_FAST), 31756051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_DIF), 31856051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_CORE), 3197d4b564dSXiaoliang Yang REG(SYS_CNT, 0x000000), 32056051948SVladimir Oltean REG(SYS_PTP_STATUS, 0x000f14), 32156051948SVladimir Oltean REG(SYS_PTP_TXSTAMP, 0x000f18), 32256051948SVladimir Oltean REG(SYS_PTP_NXT, 0x000f1c), 32356051948SVladimir Oltean REG(SYS_PTP_CFG, 0x000f20), 32456051948SVladimir Oltean REG(SYS_RAM_INIT, 0x000f24), 32556051948SVladimir Oltean REG_RESERVED(SYS_CM_ADDR), 32656051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_WR), 32756051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_RD), 32856051948SVladimir Oltean REG_RESERVED(SYS_CM_OP), 32956051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA), 33056051948SVladimir Oltean }; 33156051948SVladimir Oltean 3325df66c48SYangbo Lu static const u32 vsc9959_ptp_regmap[] = { 3335df66c48SYangbo Lu REG(PTP_PIN_CFG, 0x000000), 3345df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 3355df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 3365df66c48SYangbo Lu REG(PTP_PIN_TOD_NSEC, 0x00000c), 33794aca082SYangbo Lu REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 33894aca082SYangbo Lu REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 3395df66c48SYangbo Lu REG(PTP_CFG_MISC, 0x0000a0), 3405df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 3415df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 3425df66c48SYangbo Lu }; 3435df66c48SYangbo Lu 34456051948SVladimir Oltean static const u32 vsc9959_gcb_regmap[] = { 34556051948SVladimir Oltean REG(GCB_SOFT_RST, 0x000004), 34656051948SVladimir Oltean }; 34756051948SVladimir Oltean 34891c724cfSVladimir Oltean static const u32 vsc9959_dev_gmii_regmap[] = { 34991c724cfSVladimir Oltean REG(DEV_CLOCK_CFG, 0x0), 35091c724cfSVladimir Oltean REG(DEV_PORT_MISC, 0x4), 35191c724cfSVladimir Oltean REG(DEV_EVENTS, 0x8), 35291c724cfSVladimir Oltean REG(DEV_EEE_CFG, 0xc), 35391c724cfSVladimir Oltean REG(DEV_RX_PATH_DELAY, 0x10), 35491c724cfSVladimir Oltean REG(DEV_TX_PATH_DELAY, 0x14), 35591c724cfSVladimir Oltean REG(DEV_PTP_PREDICT_CFG, 0x18), 35691c724cfSVladimir Oltean REG(DEV_MAC_ENA_CFG, 0x1c), 35791c724cfSVladimir Oltean REG(DEV_MAC_MODE_CFG, 0x20), 35891c724cfSVladimir Oltean REG(DEV_MAC_MAXLEN_CFG, 0x24), 35991c724cfSVladimir Oltean REG(DEV_MAC_TAGS_CFG, 0x28), 36091c724cfSVladimir Oltean REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 36191c724cfSVladimir Oltean REG(DEV_MAC_IFG_CFG, 0x30), 36291c724cfSVladimir Oltean REG(DEV_MAC_HDX_CFG, 0x34), 36391c724cfSVladimir Oltean REG(DEV_MAC_DBG_CFG, 0x38), 36491c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 36591c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 36691c724cfSVladimir Oltean REG(DEV_MAC_STICKY, 0x44), 36791c724cfSVladimir Oltean REG_RESERVED(PCS1G_CFG), 36891c724cfSVladimir Oltean REG_RESERVED(PCS1G_MODE_CFG), 36991c724cfSVladimir Oltean REG_RESERVED(PCS1G_SD_CFG), 37091c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_CFG), 37191c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_CFG), 37291c724cfSVladimir Oltean REG_RESERVED(PCS1G_LB_CFG), 37391c724cfSVladimir Oltean REG_RESERVED(PCS1G_DBG_CFG), 37491c724cfSVladimir Oltean REG_RESERVED(PCS1G_CDET_CFG), 37591c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_STATUS), 37691c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_STATUS), 37791c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_STATUS), 37891c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_DOWN_CNT), 37991c724cfSVladimir Oltean REG_RESERVED(PCS1G_STICKY), 38091c724cfSVladimir Oltean REG_RESERVED(PCS1G_DEBUG_STATUS), 38191c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_CFG), 38291c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 38391c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_STATUS), 38491c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 38591c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_STATUS), 38691c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_CFG), 38791c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_STATUS), 38891c724cfSVladimir Oltean }; 38991c724cfSVladimir Oltean 39091c724cfSVladimir Oltean static const u32 *vsc9959_regmap[TARGET_MAX] = { 39156051948SVladimir Oltean [ANA] = vsc9959_ana_regmap, 39256051948SVladimir Oltean [QS] = vsc9959_qs_regmap, 39356051948SVladimir Oltean [QSYS] = vsc9959_qsys_regmap, 39456051948SVladimir Oltean [REW] = vsc9959_rew_regmap, 39556051948SVladimir Oltean [SYS] = vsc9959_sys_regmap, 396e3aea296SVladimir Oltean [S0] = vsc9959_vcap_regmap, 397a61e365dSVladimir Oltean [S1] = vsc9959_vcap_regmap, 398c1c3993eSVladimir Oltean [S2] = vsc9959_vcap_regmap, 3995df66c48SYangbo Lu [PTP] = vsc9959_ptp_regmap, 40056051948SVladimir Oltean [GCB] = vsc9959_gcb_regmap, 40191c724cfSVladimir Oltean [DEV_GMII] = vsc9959_dev_gmii_regmap, 40256051948SVladimir Oltean }; 40356051948SVladimir Oltean 404b4024c9eSClaudiu Manoil /* Addresses are relative to the PCI device's base address */ 40591c724cfSVladimir Oltean static const struct resource vsc9959_target_io_res[TARGET_MAX] = { 40656051948SVladimir Oltean [ANA] = { 40756051948SVladimir Oltean .start = 0x0280000, 40856051948SVladimir Oltean .end = 0x028ffff, 40956051948SVladimir Oltean .name = "ana", 41056051948SVladimir Oltean }, 41156051948SVladimir Oltean [QS] = { 41256051948SVladimir Oltean .start = 0x0080000, 41356051948SVladimir Oltean .end = 0x00800ff, 41456051948SVladimir Oltean .name = "qs", 41556051948SVladimir Oltean }, 41656051948SVladimir Oltean [QSYS] = { 41756051948SVladimir Oltean .start = 0x0200000, 41856051948SVladimir Oltean .end = 0x021ffff, 41956051948SVladimir Oltean .name = "qsys", 42056051948SVladimir Oltean }, 42156051948SVladimir Oltean [REW] = { 42256051948SVladimir Oltean .start = 0x0030000, 42356051948SVladimir Oltean .end = 0x003ffff, 42456051948SVladimir Oltean .name = "rew", 42556051948SVladimir Oltean }, 42656051948SVladimir Oltean [SYS] = { 42756051948SVladimir Oltean .start = 0x0010000, 42856051948SVladimir Oltean .end = 0x001ffff, 42956051948SVladimir Oltean .name = "sys", 43056051948SVladimir Oltean }, 431e3aea296SVladimir Oltean [S0] = { 432e3aea296SVladimir Oltean .start = 0x0040000, 433e3aea296SVladimir Oltean .end = 0x00403ff, 434e3aea296SVladimir Oltean .name = "s0", 435e3aea296SVladimir Oltean }, 436a61e365dSVladimir Oltean [S1] = { 437a61e365dSVladimir Oltean .start = 0x0050000, 438a61e365dSVladimir Oltean .end = 0x00503ff, 439a61e365dSVladimir Oltean .name = "s1", 440a61e365dSVladimir Oltean }, 44156051948SVladimir Oltean [S2] = { 44256051948SVladimir Oltean .start = 0x0060000, 44356051948SVladimir Oltean .end = 0x00603ff, 44456051948SVladimir Oltean .name = "s2", 44556051948SVladimir Oltean }, 4465df66c48SYangbo Lu [PTP] = { 4475df66c48SYangbo Lu .start = 0x0090000, 4485df66c48SYangbo Lu .end = 0x00900cb, 4495df66c48SYangbo Lu .name = "ptp", 4505df66c48SYangbo Lu }, 45156051948SVladimir Oltean [GCB] = { 45256051948SVladimir Oltean .start = 0x0070000, 45356051948SVladimir Oltean .end = 0x00701ff, 45456051948SVladimir Oltean .name = "devcpu_gcb", 45556051948SVladimir Oltean }, 45656051948SVladimir Oltean }; 45756051948SVladimir Oltean 458b4024c9eSClaudiu Manoil static const struct resource vsc9959_port_io_res[] = { 45956051948SVladimir Oltean { 46056051948SVladimir Oltean .start = 0x0100000, 46156051948SVladimir Oltean .end = 0x010ffff, 46256051948SVladimir Oltean .name = "port0", 46356051948SVladimir Oltean }, 46456051948SVladimir Oltean { 46556051948SVladimir Oltean .start = 0x0110000, 46656051948SVladimir Oltean .end = 0x011ffff, 46756051948SVladimir Oltean .name = "port1", 46856051948SVladimir Oltean }, 46956051948SVladimir Oltean { 47056051948SVladimir Oltean .start = 0x0120000, 47156051948SVladimir Oltean .end = 0x012ffff, 47256051948SVladimir Oltean .name = "port2", 47356051948SVladimir Oltean }, 47456051948SVladimir Oltean { 47556051948SVladimir Oltean .start = 0x0130000, 47656051948SVladimir Oltean .end = 0x013ffff, 47756051948SVladimir Oltean .name = "port3", 47856051948SVladimir Oltean }, 47956051948SVladimir Oltean { 48056051948SVladimir Oltean .start = 0x0140000, 48156051948SVladimir Oltean .end = 0x014ffff, 48256051948SVladimir Oltean .name = "port4", 48356051948SVladimir Oltean }, 48456051948SVladimir Oltean { 48556051948SVladimir Oltean .start = 0x0150000, 48656051948SVladimir Oltean .end = 0x015ffff, 48756051948SVladimir Oltean .name = "port5", 48856051948SVladimir Oltean }, 48956051948SVladimir Oltean }; 49056051948SVladimir Oltean 491bdeced75SVladimir Oltean /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 492bdeced75SVladimir Oltean * SGMII/QSGMII MAC PCS can be found. 493bdeced75SVladimir Oltean */ 494b4024c9eSClaudiu Manoil static const struct resource vsc9959_imdio_res = { 495bdeced75SVladimir Oltean .start = 0x8030, 496bdeced75SVladimir Oltean .end = 0x8040, 497bdeced75SVladimir Oltean .name = "imdio", 498bdeced75SVladimir Oltean }; 499bdeced75SVladimir Oltean 5002789658fSMaxim Kochetkov static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 50156051948SVladimir Oltean [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 50256051948SVladimir Oltean [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 50356051948SVladimir Oltean [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 50456051948SVladimir Oltean [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 50556051948SVladimir Oltean [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 50656051948SVladimir Oltean [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 50756051948SVladimir Oltean [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 50856051948SVladimir Oltean [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 50956051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 51056051948SVladimir Oltean [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 51156051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 51256051948SVladimir Oltean [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 51356051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 51456051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 51556051948SVladimir Oltean [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 51656051948SVladimir Oltean [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 51756051948SVladimir Oltean [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 51856051948SVladimir Oltean [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 51956051948SVladimir Oltean [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 52056051948SVladimir Oltean [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 52156051948SVladimir Oltean [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 52256051948SVladimir Oltean [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 52356051948SVladimir Oltean [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 52456051948SVladimir Oltean [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 52556051948SVladimir Oltean [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 52656051948SVladimir Oltean [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 52756051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 52856051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 52956051948SVladimir Oltean [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 53056051948SVladimir Oltean [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 53156051948SVladimir Oltean [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 53256051948SVladimir Oltean [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 53356051948SVladimir Oltean [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 534886e1387SVladimir Oltean /* Replicated per number of ports (7), register size 4 per port */ 535886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 536886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 537886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 538886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 539886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 540886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 541886e1387SVladimir Oltean [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 542886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 543886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 544886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 545541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 546541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 547541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 54856051948SVladimir Oltean }; 54956051948SVladimir Oltean 55056051948SVladimir Oltean static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 55156051948SVladimir Oltean { .offset = 0x00, .name = "rx_octets", }, 55256051948SVladimir Oltean { .offset = 0x01, .name = "rx_unicast", }, 55356051948SVladimir Oltean { .offset = 0x02, .name = "rx_multicast", }, 55456051948SVladimir Oltean { .offset = 0x03, .name = "rx_broadcast", }, 55556051948SVladimir Oltean { .offset = 0x04, .name = "rx_shorts", }, 55656051948SVladimir Oltean { .offset = 0x05, .name = "rx_fragments", }, 55756051948SVladimir Oltean { .offset = 0x06, .name = "rx_jabbers", }, 55856051948SVladimir Oltean { .offset = 0x07, .name = "rx_crc_align_errs", }, 55956051948SVladimir Oltean { .offset = 0x08, .name = "rx_sym_errs", }, 56056051948SVladimir Oltean { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 56156051948SVladimir Oltean { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 56256051948SVladimir Oltean { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 56356051948SVladimir Oltean { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 56456051948SVladimir Oltean { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 56556051948SVladimir Oltean { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 56656051948SVladimir Oltean { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 56756051948SVladimir Oltean { .offset = 0x10, .name = "rx_pause", }, 56856051948SVladimir Oltean { .offset = 0x11, .name = "rx_control", }, 56956051948SVladimir Oltean { .offset = 0x12, .name = "rx_longs", }, 57056051948SVladimir Oltean { .offset = 0x13, .name = "rx_classified_drops", }, 57156051948SVladimir Oltean { .offset = 0x14, .name = "rx_red_prio_0", }, 57256051948SVladimir Oltean { .offset = 0x15, .name = "rx_red_prio_1", }, 57356051948SVladimir Oltean { .offset = 0x16, .name = "rx_red_prio_2", }, 57456051948SVladimir Oltean { .offset = 0x17, .name = "rx_red_prio_3", }, 57556051948SVladimir Oltean { .offset = 0x18, .name = "rx_red_prio_4", }, 57656051948SVladimir Oltean { .offset = 0x19, .name = "rx_red_prio_5", }, 57756051948SVladimir Oltean { .offset = 0x1A, .name = "rx_red_prio_6", }, 57856051948SVladimir Oltean { .offset = 0x1B, .name = "rx_red_prio_7", }, 57956051948SVladimir Oltean { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 58056051948SVladimir Oltean { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 58156051948SVladimir Oltean { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 58256051948SVladimir Oltean { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 58356051948SVladimir Oltean { .offset = 0x20, .name = "rx_yellow_prio_4", }, 58456051948SVladimir Oltean { .offset = 0x21, .name = "rx_yellow_prio_5", }, 58556051948SVladimir Oltean { .offset = 0x22, .name = "rx_yellow_prio_6", }, 58656051948SVladimir Oltean { .offset = 0x23, .name = "rx_yellow_prio_7", }, 58756051948SVladimir Oltean { .offset = 0x24, .name = "rx_green_prio_0", }, 58856051948SVladimir Oltean { .offset = 0x25, .name = "rx_green_prio_1", }, 58956051948SVladimir Oltean { .offset = 0x26, .name = "rx_green_prio_2", }, 59056051948SVladimir Oltean { .offset = 0x27, .name = "rx_green_prio_3", }, 59156051948SVladimir Oltean { .offset = 0x28, .name = "rx_green_prio_4", }, 59256051948SVladimir Oltean { .offset = 0x29, .name = "rx_green_prio_5", }, 59356051948SVladimir Oltean { .offset = 0x2A, .name = "rx_green_prio_6", }, 59456051948SVladimir Oltean { .offset = 0x2B, .name = "rx_green_prio_7", }, 59556051948SVladimir Oltean { .offset = 0x80, .name = "tx_octets", }, 59656051948SVladimir Oltean { .offset = 0x81, .name = "tx_unicast", }, 59756051948SVladimir Oltean { .offset = 0x82, .name = "tx_multicast", }, 59856051948SVladimir Oltean { .offset = 0x83, .name = "tx_broadcast", }, 59956051948SVladimir Oltean { .offset = 0x84, .name = "tx_collision", }, 60056051948SVladimir Oltean { .offset = 0x85, .name = "tx_drops", }, 60156051948SVladimir Oltean { .offset = 0x86, .name = "tx_pause", }, 60256051948SVladimir Oltean { .offset = 0x87, .name = "tx_frames_below_65_octets", }, 60356051948SVladimir Oltean { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, 60456051948SVladimir Oltean { .offset = 0x89, .name = "tx_frames_128_255_octets", }, 60556051948SVladimir Oltean { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, 60656051948SVladimir Oltean { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, 60756051948SVladimir Oltean { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, 60856051948SVladimir Oltean { .offset = 0x8E, .name = "tx_yellow_prio_0", }, 60956051948SVladimir Oltean { .offset = 0x8F, .name = "tx_yellow_prio_1", }, 61056051948SVladimir Oltean { .offset = 0x90, .name = "tx_yellow_prio_2", }, 61156051948SVladimir Oltean { .offset = 0x91, .name = "tx_yellow_prio_3", }, 61256051948SVladimir Oltean { .offset = 0x92, .name = "tx_yellow_prio_4", }, 61356051948SVladimir Oltean { .offset = 0x93, .name = "tx_yellow_prio_5", }, 61456051948SVladimir Oltean { .offset = 0x94, .name = "tx_yellow_prio_6", }, 61556051948SVladimir Oltean { .offset = 0x95, .name = "tx_yellow_prio_7", }, 61656051948SVladimir Oltean { .offset = 0x96, .name = "tx_green_prio_0", }, 61756051948SVladimir Oltean { .offset = 0x97, .name = "tx_green_prio_1", }, 61856051948SVladimir Oltean { .offset = 0x98, .name = "tx_green_prio_2", }, 61956051948SVladimir Oltean { .offset = 0x99, .name = "tx_green_prio_3", }, 62056051948SVladimir Oltean { .offset = 0x9A, .name = "tx_green_prio_4", }, 62156051948SVladimir Oltean { .offset = 0x9B, .name = "tx_green_prio_5", }, 62256051948SVladimir Oltean { .offset = 0x9C, .name = "tx_green_prio_6", }, 62356051948SVladimir Oltean { .offset = 0x9D, .name = "tx_green_prio_7", }, 62456051948SVladimir Oltean { .offset = 0x9E, .name = "tx_aged", }, 62556051948SVladimir Oltean { .offset = 0x100, .name = "drop_local", }, 62656051948SVladimir Oltean { .offset = 0x101, .name = "drop_tail", }, 62756051948SVladimir Oltean { .offset = 0x102, .name = "drop_yellow_prio_0", }, 62856051948SVladimir Oltean { .offset = 0x103, .name = "drop_yellow_prio_1", }, 62956051948SVladimir Oltean { .offset = 0x104, .name = "drop_yellow_prio_2", }, 63056051948SVladimir Oltean { .offset = 0x105, .name = "drop_yellow_prio_3", }, 63156051948SVladimir Oltean { .offset = 0x106, .name = "drop_yellow_prio_4", }, 63256051948SVladimir Oltean { .offset = 0x107, .name = "drop_yellow_prio_5", }, 63356051948SVladimir Oltean { .offset = 0x108, .name = "drop_yellow_prio_6", }, 63456051948SVladimir Oltean { .offset = 0x109, .name = "drop_yellow_prio_7", }, 63556051948SVladimir Oltean { .offset = 0x10A, .name = "drop_green_prio_0", }, 63656051948SVladimir Oltean { .offset = 0x10B, .name = "drop_green_prio_1", }, 63756051948SVladimir Oltean { .offset = 0x10C, .name = "drop_green_prio_2", }, 63856051948SVladimir Oltean { .offset = 0x10D, .name = "drop_green_prio_3", }, 63956051948SVladimir Oltean { .offset = 0x10E, .name = "drop_green_prio_4", }, 64056051948SVladimir Oltean { .offset = 0x10F, .name = "drop_green_prio_5", }, 64156051948SVladimir Oltean { .offset = 0x110, .name = "drop_green_prio_6", }, 64256051948SVladimir Oltean { .offset = 0x111, .name = "drop_green_prio_7", }, 6432f187bfaSColin Foster OCELOT_STAT_END 64456051948SVladimir Oltean }; 64556051948SVladimir Oltean 646e3aea296SVladimir Oltean static const struct vcap_field vsc9959_vcap_es0_keys[] = { 647e3aea296SVladimir Oltean [VCAP_ES0_EGR_PORT] = { 0, 3}, 648e3aea296SVladimir Oltean [VCAP_ES0_IGR_PORT] = { 3, 3}, 649e3aea296SVladimir Oltean [VCAP_ES0_RSV] = { 6, 2}, 650e3aea296SVladimir Oltean [VCAP_ES0_L2_MC] = { 8, 1}, 651e3aea296SVladimir Oltean [VCAP_ES0_L2_BC] = { 9, 1}, 652e3aea296SVladimir Oltean [VCAP_ES0_VID] = { 10, 12}, 653e3aea296SVladimir Oltean [VCAP_ES0_DP] = { 22, 1}, 654e3aea296SVladimir Oltean [VCAP_ES0_PCP] = { 23, 3}, 655e3aea296SVladimir Oltean }; 656e3aea296SVladimir Oltean 657e3aea296SVladimir Oltean static const struct vcap_field vsc9959_vcap_es0_actions[] = { 658e3aea296SVladimir Oltean [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 659e3aea296SVladimir Oltean [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 660e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 661e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 662e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 663e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 664e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 665e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 666e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 667e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 668e3aea296SVladimir Oltean [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 669e3aea296SVladimir Oltean [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 670e3aea296SVladimir Oltean [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 671e3aea296SVladimir Oltean [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 672e3aea296SVladimir Oltean [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 673e3aea296SVladimir Oltean [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 674e3aea296SVladimir Oltean [VCAP_ES0_ACT_RSV] = { 49, 23}, 675e3aea296SVladimir Oltean [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 676e3aea296SVladimir Oltean }; 677e3aea296SVladimir Oltean 678a61e365dSVladimir Oltean static const struct vcap_field vsc9959_vcap_is1_keys[] = { 679a61e365dSVladimir Oltean [VCAP_IS1_HK_TYPE] = { 0, 1}, 680a61e365dSVladimir Oltean [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 681a61e365dSVladimir Oltean [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 682a61e365dSVladimir Oltean [VCAP_IS1_HK_RSV] = { 10, 9}, 683a61e365dSVladimir Oltean [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 684a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_MC] = { 20, 1}, 685a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_BC] = { 21, 1}, 686a61e365dSVladimir Oltean [VCAP_IS1_HK_IP_MC] = { 22, 1}, 687a61e365dSVladimir Oltean [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 688a61e365dSVladimir Oltean [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 689a61e365dSVladimir Oltean [VCAP_IS1_HK_TPID] = { 25, 1}, 690a61e365dSVladimir Oltean [VCAP_IS1_HK_VID] = { 26, 12}, 691a61e365dSVladimir Oltean [VCAP_IS1_HK_DEI] = { 38, 1}, 692a61e365dSVladimir Oltean [VCAP_IS1_HK_PCP] = { 39, 3}, 693a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_NORMAL */ 694a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 695a61e365dSVladimir Oltean [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 696a61e365dSVladimir Oltean [VCAP_IS1_HK_ETYPE] = { 91, 16}, 697a61e365dSVladimir Oltean [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 698a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4] = {108, 1}, 699a61e365dSVladimir Oltean /* Layer-3 Information */ 700a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 701a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 702a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 703a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 704a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 705a61e365dSVladimir Oltean /* Layer-4 Information */ 706a61e365dSVladimir Oltean [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 707a61e365dSVladimir Oltean [VCAP_IS1_HK_TCP] = {151, 1}, 708a61e365dSVladimir Oltean [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 709a61e365dSVladimir Oltean [VCAP_IS1_HK_L4_RNG] = {168, 8}, 710a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 711a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 712a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 713a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 714a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 715a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 716a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 717a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 718a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 719a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 720a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 721a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 722a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 723a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 724a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 725a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 726a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 727a61e365dSVladimir Oltean }; 728a61e365dSVladimir Oltean 729a61e365dSVladimir Oltean static const struct vcap_field vsc9959_vcap_is1_actions[] = { 730a61e365dSVladimir Oltean [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 731a61e365dSVladimir Oltean [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 732a61e365dSVladimir Oltean [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 733a61e365dSVladimir Oltean [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 734a61e365dSVladimir Oltean [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 735a61e365dSVladimir Oltean [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 736a61e365dSVladimir Oltean [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 737a61e365dSVladimir Oltean [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 738a61e365dSVladimir Oltean [VCAP_IS1_ACT_RSV] = { 29, 9}, 73975944fdaSXiaoliang Yang /* The fields below are incorrectly shifted by 2 in the manual */ 740a61e365dSVladimir Oltean [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 741a61e365dSVladimir Oltean [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 742a61e365dSVladimir Oltean [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 743a61e365dSVladimir Oltean [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 744a61e365dSVladimir Oltean [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 745a61e365dSVladimir Oltean [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 746a61e365dSVladimir Oltean [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 747a61e365dSVladimir Oltean [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 748a61e365dSVladimir Oltean [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 749a61e365dSVladimir Oltean [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 750a61e365dSVladimir Oltean [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 751a61e365dSVladimir Oltean }; 752a61e365dSVladimir Oltean 7533ab4ceb6SVladimir Oltean static struct vcap_field vsc9959_vcap_is2_keys[] = { 75407d985eeSVladimir Oltean /* Common: 41 bits */ 75507d985eeSVladimir Oltean [VCAP_IS2_TYPE] = { 0, 4}, 75607d985eeSVladimir Oltean [VCAP_IS2_HK_FIRST] = { 4, 1}, 75707d985eeSVladimir Oltean [VCAP_IS2_HK_PAG] = { 5, 8}, 75807d985eeSVladimir Oltean [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 75907d985eeSVladimir Oltean [VCAP_IS2_HK_RSV2] = { 20, 1}, 76007d985eeSVladimir Oltean [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 76107d985eeSVladimir Oltean [VCAP_IS2_HK_L2_MC] = { 22, 1}, 76207d985eeSVladimir Oltean [VCAP_IS2_HK_L2_BC] = { 23, 1}, 76307d985eeSVladimir Oltean [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 76407d985eeSVladimir Oltean [VCAP_IS2_HK_VID] = { 25, 12}, 76507d985eeSVladimir Oltean [VCAP_IS2_HK_DEI] = { 37, 1}, 76607d985eeSVladimir Oltean [VCAP_IS2_HK_PCP] = { 38, 3}, 76707d985eeSVladimir Oltean /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 76807d985eeSVladimir Oltean [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 76907d985eeSVladimir Oltean [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 77007d985eeSVladimir Oltean /* MAC_ETYPE (TYPE=000) */ 77107d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 77207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 77307d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 77407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 77507d985eeSVladimir Oltean /* MAC_LLC (TYPE=001) */ 77607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 77707d985eeSVladimir Oltean /* MAC_SNAP (TYPE=010) */ 77807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 77907d985eeSVladimir Oltean /* MAC_ARP (TYPE=011) */ 78007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 78107d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 78207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 78307d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 78407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 78507d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 78607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 78707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 78807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 78907d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 79007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 79107d985eeSVladimir Oltean /* IP4_TCP_UDP / IP4_OTHER common */ 79207d985eeSVladimir Oltean [VCAP_IS2_HK_IP4] = { 41, 1}, 79307d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 79407d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 79507d985eeSVladimir Oltean [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 79607d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 79707d985eeSVladimir Oltean [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 79807d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 79907d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 80007d985eeSVladimir Oltean [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 80107d985eeSVladimir Oltean /* IP4_TCP_UDP (TYPE=100) */ 80207d985eeSVladimir Oltean [VCAP_IS2_HK_TCP] = {119, 1}, 8038b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 8048b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 80507d985eeSVladimir Oltean [VCAP_IS2_HK_L4_RNG] = {152, 8}, 80607d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 80707d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 8088b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_FIN] = {162, 1}, 8098b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_SYN] = {163, 1}, 8108b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_RST] = {164, 1}, 8118b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_PSH] = {165, 1}, 8128b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_ACK] = {166, 1}, 8138b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_URG] = {167, 1}, 81407d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 81507d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 81607d985eeSVladimir Oltean /* IP4_OTHER (TYPE=101) */ 81707d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 81807d985eeSVladimir Oltean [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 81907d985eeSVladimir Oltean /* IP6_STD (TYPE=110) */ 82007d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 82107d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 82207d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 82307d985eeSVladimir Oltean /* OAM (TYPE=111) */ 82407d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 82507d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_VER] = {144, 5}, 82607d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 82707d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 82807d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 82907d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 83007d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 83107d985eeSVladimir Oltean }; 83207d985eeSVladimir Oltean 8333ab4ceb6SVladimir Oltean static struct vcap_field vsc9959_vcap_is2_actions[] = { 83407d985eeSVladimir Oltean [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 83507d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 83607d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 83707d985eeSVladimir Oltean [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 83807d985eeSVladimir Oltean [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 83907d985eeSVladimir Oltean [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 84007d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 84107d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 84207d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 843460e985eSVladimir Oltean [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 844460e985eSVladimir Oltean [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 845460e985eSVladimir Oltean [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 846460e985eSVladimir Oltean [VCAP_IS2_ACT_RSV] = { 36, 2}, 847460e985eSVladimir Oltean [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 848460e985eSVladimir Oltean [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 84907d985eeSVladimir Oltean }; 85007d985eeSVladimir Oltean 85120968054SVladimir Oltean static struct vcap_props vsc9959_vcap_props[] = { 852e3aea296SVladimir Oltean [VCAP_ES0] = { 853e3aea296SVladimir Oltean .action_type_width = 0, 854e3aea296SVladimir Oltean .action_table = { 855e3aea296SVladimir Oltean [ES0_ACTION_TYPE_NORMAL] = { 856e3aea296SVladimir Oltean .width = 72, /* HIT_STICKY not included */ 857e3aea296SVladimir Oltean .count = 1, 858e3aea296SVladimir Oltean }, 859e3aea296SVladimir Oltean }, 860e3aea296SVladimir Oltean .target = S0, 861e3aea296SVladimir Oltean .keys = vsc9959_vcap_es0_keys, 862e3aea296SVladimir Oltean .actions = vsc9959_vcap_es0_actions, 863e3aea296SVladimir Oltean }, 864a61e365dSVladimir Oltean [VCAP_IS1] = { 865a61e365dSVladimir Oltean .action_type_width = 0, 866a61e365dSVladimir Oltean .action_table = { 867a61e365dSVladimir Oltean [IS1_ACTION_TYPE_NORMAL] = { 868a61e365dSVladimir Oltean .width = 78, /* HIT_STICKY not included */ 869a61e365dSVladimir Oltean .count = 4, 870a61e365dSVladimir Oltean }, 871a61e365dSVladimir Oltean }, 872a61e365dSVladimir Oltean .target = S1, 873a61e365dSVladimir Oltean .keys = vsc9959_vcap_is1_keys, 874a61e365dSVladimir Oltean .actions = vsc9959_vcap_is1_actions, 875a61e365dSVladimir Oltean }, 87607d985eeSVladimir Oltean [VCAP_IS2] = { 87707d985eeSVladimir Oltean .action_type_width = 1, 87807d985eeSVladimir Oltean .action_table = { 87907d985eeSVladimir Oltean [IS2_ACTION_TYPE_NORMAL] = { 88007d985eeSVladimir Oltean .width = 44, 88107d985eeSVladimir Oltean .count = 2 88207d985eeSVladimir Oltean }, 88307d985eeSVladimir Oltean [IS2_ACTION_TYPE_SMAC_SIP] = { 88407d985eeSVladimir Oltean .width = 6, 88507d985eeSVladimir Oltean .count = 4 88607d985eeSVladimir Oltean }, 88707d985eeSVladimir Oltean }, 888c1c3993eSVladimir Oltean .target = S2, 889c1c3993eSVladimir Oltean .keys = vsc9959_vcap_is2_keys, 890c1c3993eSVladimir Oltean .actions = vsc9959_vcap_is2_actions, 89107d985eeSVladimir Oltean }, 89207d985eeSVladimir Oltean }; 89307d985eeSVladimir Oltean 8942ac7c6c5SVladimir Oltean static const struct ptp_clock_info vsc9959_ptp_caps = { 8952ac7c6c5SVladimir Oltean .owner = THIS_MODULE, 8962ac7c6c5SVladimir Oltean .name = "felix ptp", 8972ac7c6c5SVladimir Oltean .max_adj = 0x7fffffff, 8982ac7c6c5SVladimir Oltean .n_alarm = 0, 8992ac7c6c5SVladimir Oltean .n_ext_ts = 0, 9002ac7c6c5SVladimir Oltean .n_per_out = OCELOT_PTP_PINS_NUM, 9012ac7c6c5SVladimir Oltean .n_pins = OCELOT_PTP_PINS_NUM, 9022ac7c6c5SVladimir Oltean .pps = 0, 9032ac7c6c5SVladimir Oltean .gettime64 = ocelot_ptp_gettime64, 9042ac7c6c5SVladimir Oltean .settime64 = ocelot_ptp_settime64, 9052ac7c6c5SVladimir Oltean .adjtime = ocelot_ptp_adjtime, 9062ac7c6c5SVladimir Oltean .adjfine = ocelot_ptp_adjfine, 9072ac7c6c5SVladimir Oltean .verify = ocelot_ptp_verify, 9082ac7c6c5SVladimir Oltean .enable = ocelot_ptp_enable, 9092ac7c6c5SVladimir Oltean }; 9102ac7c6c5SVladimir Oltean 91156051948SVladimir Oltean #define VSC9959_INIT_TIMEOUT 50000 91256051948SVladimir Oltean #define VSC9959_GCB_RST_SLEEP 100 91356051948SVladimir Oltean #define VSC9959_SYS_RAMINIT_SLEEP 80 91456051948SVladimir Oltean 91556051948SVladimir Oltean static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 91656051948SVladimir Oltean { 91756051948SVladimir Oltean int val; 91856051948SVladimir Oltean 91975cea9cbSVladimir Oltean ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 92056051948SVladimir Oltean 92156051948SVladimir Oltean return val; 92256051948SVladimir Oltean } 92356051948SVladimir Oltean 92456051948SVladimir Oltean static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 92556051948SVladimir Oltean { 92656051948SVladimir Oltean return ocelot_read(ocelot, SYS_RAM_INIT); 92756051948SVladimir Oltean } 92856051948SVladimir Oltean 929c129fc55SVladimir Oltean /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 930c129fc55SVladimir Oltean * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 931c129fc55SVladimir Oltean */ 93256051948SVladimir Oltean static int vsc9959_reset(struct ocelot *ocelot) 93356051948SVladimir Oltean { 93456051948SVladimir Oltean int val, err; 93556051948SVladimir Oltean 93656051948SVladimir Oltean /* soft-reset the switch core */ 93775cea9cbSVladimir Oltean ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 93856051948SVladimir Oltean 93956051948SVladimir Oltean err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 94056051948SVladimir Oltean VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 94156051948SVladimir Oltean if (err) { 94256051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch core reset\n"); 94356051948SVladimir Oltean return err; 94456051948SVladimir Oltean } 94556051948SVladimir Oltean 94656051948SVladimir Oltean /* initialize switch mem ~40us */ 94756051948SVladimir Oltean ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 94856051948SVladimir Oltean err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 94956051948SVladimir Oltean VSC9959_SYS_RAMINIT_SLEEP, 95056051948SVladimir Oltean VSC9959_INIT_TIMEOUT); 95156051948SVladimir Oltean if (err) { 95256051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch sram init\n"); 95356051948SVladimir Oltean return err; 95456051948SVladimir Oltean } 95556051948SVladimir Oltean 95656051948SVladimir Oltean /* enable switch core */ 95775cea9cbSVladimir Oltean ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 95856051948SVladimir Oltean 95956051948SVladimir Oltean return 0; 96056051948SVladimir Oltean } 96156051948SVladimir Oltean 962375e1314SVladimir Oltean static void vsc9959_phylink_validate(struct ocelot *ocelot, int port, 963375e1314SVladimir Oltean unsigned long *supported, 964375e1314SVladimir Oltean struct phylink_link_state *state) 965375e1314SVladimir Oltean { 966375e1314SVladimir Oltean __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 967375e1314SVladimir Oltean 968375e1314SVladimir Oltean phylink_set_port_modes(mask); 969375e1314SVladimir Oltean phylink_set(mask, Autoneg); 970375e1314SVladimir Oltean phylink_set(mask, Pause); 971375e1314SVladimir Oltean phylink_set(mask, Asym_Pause); 972375e1314SVladimir Oltean phylink_set(mask, 10baseT_Half); 973375e1314SVladimir Oltean phylink_set(mask, 10baseT_Full); 974375e1314SVladimir Oltean phylink_set(mask, 100baseT_Half); 975375e1314SVladimir Oltean phylink_set(mask, 100baseT_Full); 976375e1314SVladimir Oltean phylink_set(mask, 1000baseT_Half); 977375e1314SVladimir Oltean phylink_set(mask, 1000baseT_Full); 97811ecf341SVladimir Oltean phylink_set(mask, 1000baseX_Full); 979375e1314SVladimir Oltean 980375e1314SVladimir Oltean if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 981375e1314SVladimir Oltean state->interface == PHY_INTERFACE_MODE_2500BASEX || 982375e1314SVladimir Oltean state->interface == PHY_INTERFACE_MODE_USXGMII) { 983375e1314SVladimir Oltean phylink_set(mask, 2500baseT_Full); 984375e1314SVladimir Oltean phylink_set(mask, 2500baseX_Full); 985375e1314SVladimir Oltean } 986375e1314SVladimir Oltean 9874973056cSSean Anderson linkmode_and(supported, supported, mask); 9884973056cSSean Anderson linkmode_and(state->advertising, state->advertising, mask); 989375e1314SVladimir Oltean } 990375e1314SVladimir Oltean 991aa92d836SMaxim Kochetkov /* Watermark encode 992aa92d836SMaxim Kochetkov * Bit 8: Unit; 0:1, 1:16 993aa92d836SMaxim Kochetkov * Bit 7-0: Value to be multiplied with unit 994aa92d836SMaxim Kochetkov */ 995aa92d836SMaxim Kochetkov static u16 vsc9959_wm_enc(u16 value) 996aa92d836SMaxim Kochetkov { 99701326493SVladimir Oltean WARN_ON(value >= 16 * BIT(8)); 99801326493SVladimir Oltean 999aa92d836SMaxim Kochetkov if (value >= BIT(8)) 1000aa92d836SMaxim Kochetkov return BIT(8) | (value / 16); 1001aa92d836SMaxim Kochetkov 1002aa92d836SMaxim Kochetkov return value; 1003aa92d836SMaxim Kochetkov } 1004aa92d836SMaxim Kochetkov 1005703b7621SVladimir Oltean static u16 vsc9959_wm_dec(u16 wm) 1006703b7621SVladimir Oltean { 1007703b7621SVladimir Oltean WARN_ON(wm & ~GENMASK(8, 0)); 1008703b7621SVladimir Oltean 1009703b7621SVladimir Oltean if (wm & BIT(8)) 1010703b7621SVladimir Oltean return (wm & GENMASK(7, 0)) * 16; 1011703b7621SVladimir Oltean 1012703b7621SVladimir Oltean return wm; 1013703b7621SVladimir Oltean } 1014703b7621SVladimir Oltean 1015703b7621SVladimir Oltean static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 1016703b7621SVladimir Oltean { 1017703b7621SVladimir Oltean *inuse = (val & GENMASK(23, 12)) >> 12; 1018703b7621SVladimir Oltean *maxuse = val & GENMASK(11, 0); 1019703b7621SVladimir Oltean } 1020703b7621SVladimir Oltean 1021bdeced75SVladimir Oltean static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 1022bdeced75SVladimir Oltean { 1023bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1024bdeced75SVladimir Oltean struct enetc_mdio_priv *mdio_priv; 1025bdeced75SVladimir Oltean struct device *dev = ocelot->dev; 1026bdeced75SVladimir Oltean void __iomem *imdio_regs; 1027b4024c9eSClaudiu Manoil struct resource res; 1028bdeced75SVladimir Oltean struct enetc_hw *hw; 1029bdeced75SVladimir Oltean struct mii_bus *bus; 1030bdeced75SVladimir Oltean int port; 1031bdeced75SVladimir Oltean int rc; 1032bdeced75SVladimir Oltean 1033bdeced75SVladimir Oltean felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 1034e7026f15SColin Foster sizeof(struct phylink_pcs *), 1035bdeced75SVladimir Oltean GFP_KERNEL); 1036bdeced75SVladimir Oltean if (!felix->pcs) { 1037bdeced75SVladimir Oltean dev_err(dev, "failed to allocate array for PCS PHYs\n"); 1038bdeced75SVladimir Oltean return -ENOMEM; 1039bdeced75SVladimir Oltean } 1040bdeced75SVladimir Oltean 1041b4024c9eSClaudiu Manoil memcpy(&res, felix->info->imdio_res, sizeof(res)); 1042b4024c9eSClaudiu Manoil res.flags = IORESOURCE_MEM; 1043375e1314SVladimir Oltean res.start += felix->imdio_base; 1044375e1314SVladimir Oltean res.end += felix->imdio_base; 1045bdeced75SVladimir Oltean 1046b4024c9eSClaudiu Manoil imdio_regs = devm_ioremap_resource(dev, &res); 1047a180be79SGuobin Huang if (IS_ERR(imdio_regs)) 1048bdeced75SVladimir Oltean return PTR_ERR(imdio_regs); 1049bdeced75SVladimir Oltean 1050bdeced75SVladimir Oltean hw = enetc_hw_alloc(dev, imdio_regs); 1051bdeced75SVladimir Oltean if (IS_ERR(hw)) { 1052bdeced75SVladimir Oltean dev_err(dev, "failed to allocate ENETC HW structure\n"); 1053bdeced75SVladimir Oltean return PTR_ERR(hw); 1054bdeced75SVladimir Oltean } 1055bdeced75SVladimir Oltean 1056209bdb7eSVladimir Oltean bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 1057bdeced75SVladimir Oltean if (!bus) 1058bdeced75SVladimir Oltean return -ENOMEM; 1059bdeced75SVladimir Oltean 1060bdeced75SVladimir Oltean bus->name = "VSC9959 internal MDIO bus"; 1061bdeced75SVladimir Oltean bus->read = enetc_mdio_read; 1062bdeced75SVladimir Oltean bus->write = enetc_mdio_write; 1063bdeced75SVladimir Oltean bus->parent = dev; 1064bdeced75SVladimir Oltean mdio_priv = bus->priv; 1065bdeced75SVladimir Oltean mdio_priv->hw = hw; 1066bdeced75SVladimir Oltean /* This gets added to imdio_regs, which already maps addresses 1067bdeced75SVladimir Oltean * starting with the proper offset. 1068bdeced75SVladimir Oltean */ 1069bdeced75SVladimir Oltean mdio_priv->mdio_base = 0; 1070bdeced75SVladimir Oltean snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1071bdeced75SVladimir Oltean 1072bdeced75SVladimir Oltean /* Needed in order to initialize the bus mutex lock */ 1073bdeced75SVladimir Oltean rc = mdiobus_register(bus); 1074bdeced75SVladimir Oltean if (rc < 0) { 1075bdeced75SVladimir Oltean dev_err(dev, "failed to register MDIO bus\n"); 1076209bdb7eSVladimir Oltean mdiobus_free(bus); 1077bdeced75SVladimir Oltean return rc; 1078bdeced75SVladimir Oltean } 1079bdeced75SVladimir Oltean 1080bdeced75SVladimir Oltean felix->imdio = bus; 1081bdeced75SVladimir Oltean 1082bdeced75SVladimir Oltean for (port = 0; port < felix->info->num_ports; port++) { 1083bdeced75SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 1084e7026f15SColin Foster struct phylink_pcs *phylink_pcs; 108561f0d0c3SColin Foster struct mdio_device *mdio_device; 1086bdeced75SVladimir Oltean 1087588d0550SIoana Ciornei if (dsa_is_unused_port(felix->ds, port)) 1088588d0550SIoana Ciornei continue; 1089bdeced75SVladimir Oltean 1090588d0550SIoana Ciornei if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1091588d0550SIoana Ciornei continue; 1092588d0550SIoana Ciornei 109361f0d0c3SColin Foster mdio_device = mdio_device_create(felix->imdio, port); 109461f0d0c3SColin Foster if (IS_ERR(mdio_device)) 1095bdeced75SVladimir Oltean continue; 1096bdeced75SVladimir Oltean 109761f0d0c3SColin Foster phylink_pcs = lynx_pcs_create(mdio_device); 1098e7026f15SColin Foster if (!phylink_pcs) { 109961f0d0c3SColin Foster mdio_device_free(mdio_device); 1100588d0550SIoana Ciornei continue; 1101588d0550SIoana Ciornei } 1102588d0550SIoana Ciornei 1103e7026f15SColin Foster felix->pcs[port] = phylink_pcs; 1104bdeced75SVladimir Oltean 1105bdeced75SVladimir Oltean dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1106bdeced75SVladimir Oltean } 1107bdeced75SVladimir Oltean 1108bdeced75SVladimir Oltean return 0; 1109bdeced75SVladimir Oltean } 1110bdeced75SVladimir Oltean 1111ccfdbab5SVladimir Oltean static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1112bdeced75SVladimir Oltean { 1113bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1114bdeced75SVladimir Oltean int port; 1115bdeced75SVladimir Oltean 1116bdeced75SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) { 1117e7026f15SColin Foster struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1118e7026f15SColin Foster struct mdio_device *mdio_device; 1119bdeced75SVladimir Oltean 1120e7026f15SColin Foster if (!phylink_pcs) 1121bdeced75SVladimir Oltean continue; 1122bdeced75SVladimir Oltean 1123e7026f15SColin Foster mdio_device = lynx_get_mdio_device(phylink_pcs); 1124e7026f15SColin Foster mdio_device_free(mdio_device); 1125e7026f15SColin Foster lynx_pcs_destroy(phylink_pcs); 1126bdeced75SVladimir Oltean } 1127bdeced75SVladimir Oltean mdiobus_unregister(felix->imdio); 1128209bdb7eSVladimir Oltean mdiobus_free(felix->imdio); 1129bdeced75SVladimir Oltean } 1130bdeced75SVladimir Oltean 113155a515b1SVladimir Oltean /* Extract shortest continuous gate open intervals in ns for each traffic class 113255a515b1SVladimir Oltean * of a cyclic tc-taprio schedule. If a gate is always open, the duration is 113355a515b1SVladimir Oltean * considered U64_MAX. If the gate is always closed, it is considered 0. 113455a515b1SVladimir Oltean */ 113555a515b1SVladimir Oltean static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio, 113655a515b1SVladimir Oltean u64 min_gate_len[OCELOT_NUM_TC]) 113755a515b1SVladimir Oltean { 113855a515b1SVladimir Oltean struct tc_taprio_sched_entry *entry; 113955a515b1SVladimir Oltean u64 gate_len[OCELOT_NUM_TC]; 1140*7e4babffSVladimir Oltean u8 gates_ever_opened = 0; 114155a515b1SVladimir Oltean int tc, i, n; 114255a515b1SVladimir Oltean 114355a515b1SVladimir Oltean /* Initialize arrays */ 114455a515b1SVladimir Oltean for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 114555a515b1SVladimir Oltean min_gate_len[tc] = U64_MAX; 114655a515b1SVladimir Oltean gate_len[tc] = 0; 114755a515b1SVladimir Oltean } 114855a515b1SVladimir Oltean 114955a515b1SVladimir Oltean /* If we don't have taprio, consider all gates as permanently open */ 115055a515b1SVladimir Oltean if (!taprio) 115155a515b1SVladimir Oltean return; 115255a515b1SVladimir Oltean 115355a515b1SVladimir Oltean n = taprio->num_entries; 115455a515b1SVladimir Oltean 115555a515b1SVladimir Oltean /* Walk through the gate list twice to determine the length 115655a515b1SVladimir Oltean * of consecutively open gates for a traffic class, including 115755a515b1SVladimir Oltean * open gates that wrap around. We are just interested in the 115855a515b1SVladimir Oltean * minimum window size, and this doesn't change what the 115955a515b1SVladimir Oltean * minimum is (if the gate never closes, min_gate_len will 116055a515b1SVladimir Oltean * remain U64_MAX). 116155a515b1SVladimir Oltean */ 116255a515b1SVladimir Oltean for (i = 0; i < 2 * n; i++) { 116355a515b1SVladimir Oltean entry = &taprio->entries[i % n]; 116455a515b1SVladimir Oltean 116555a515b1SVladimir Oltean for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 116655a515b1SVladimir Oltean if (entry->gate_mask & BIT(tc)) { 116755a515b1SVladimir Oltean gate_len[tc] += entry->interval; 1168*7e4babffSVladimir Oltean gates_ever_opened |= BIT(tc); 116955a515b1SVladimir Oltean } else { 117055a515b1SVladimir Oltean /* Gate closes now, record a potential new 117155a515b1SVladimir Oltean * minimum and reinitialize length 117255a515b1SVladimir Oltean */ 1173*7e4babffSVladimir Oltean if (min_gate_len[tc] > gate_len[tc] && 1174*7e4babffSVladimir Oltean gate_len[tc]) 117555a515b1SVladimir Oltean min_gate_len[tc] = gate_len[tc]; 117655a515b1SVladimir Oltean gate_len[tc] = 0; 117755a515b1SVladimir Oltean } 117855a515b1SVladimir Oltean } 117955a515b1SVladimir Oltean } 1180*7e4babffSVladimir Oltean 1181*7e4babffSVladimir Oltean /* min_gate_len[tc] actually tracks minimum *open* gate time, so for 1182*7e4babffSVladimir Oltean * permanently closed gates, min_gate_len[tc] will still be U64_MAX. 1183*7e4babffSVladimir Oltean * Therefore they are currently indistinguishable from permanently 1184*7e4babffSVladimir Oltean * open gates. Overwrite the gate len with 0 when we know they're 1185*7e4babffSVladimir Oltean * actually permanently closed, i.e. after the loop above. 1186*7e4babffSVladimir Oltean */ 1187*7e4babffSVladimir Oltean for (tc = 0; tc < OCELOT_NUM_TC; tc++) 1188*7e4babffSVladimir Oltean if (!(gates_ever_opened & BIT(tc))) 1189*7e4babffSVladimir Oltean min_gate_len[tc] = 0; 119055a515b1SVladimir Oltean } 119155a515b1SVladimir Oltean 119255a515b1SVladimir Oltean /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the 119355a515b1SVladimir Oltean * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU 119455a515b1SVladimir Oltean * values (the default value is 1518). Also, for traffic class windows smaller 119555a515b1SVladimir Oltean * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame 119655a515b1SVladimir Oltean * dropping, such that these won't hang the port, as they will never be sent. 119755a515b1SVladimir Oltean */ 119855a515b1SVladimir Oltean static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port) 119955a515b1SVladimir Oltean { 120055a515b1SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 120155a515b1SVladimir Oltean u64 min_gate_len[OCELOT_NUM_TC]; 120255a515b1SVladimir Oltean int speed, picos_per_byte; 120355a515b1SVladimir Oltean u64 needed_bit_time_ps; 120455a515b1SVladimir Oltean u32 val, maxlen; 120555a515b1SVladimir Oltean u8 tas_speed; 120655a515b1SVladimir Oltean int tc; 120755a515b1SVladimir Oltean 120855a515b1SVladimir Oltean lockdep_assert_held(&ocelot->tas_lock); 120955a515b1SVladimir Oltean 121055a515b1SVladimir Oltean val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port); 121155a515b1SVladimir Oltean tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val); 121255a515b1SVladimir Oltean 121355a515b1SVladimir Oltean switch (tas_speed) { 121455a515b1SVladimir Oltean case OCELOT_SPEED_10: 121555a515b1SVladimir Oltean speed = SPEED_10; 121655a515b1SVladimir Oltean break; 121755a515b1SVladimir Oltean case OCELOT_SPEED_100: 121855a515b1SVladimir Oltean speed = SPEED_100; 121955a515b1SVladimir Oltean break; 122055a515b1SVladimir Oltean case OCELOT_SPEED_1000: 122155a515b1SVladimir Oltean speed = SPEED_1000; 122255a515b1SVladimir Oltean break; 122355a515b1SVladimir Oltean case OCELOT_SPEED_2500: 122455a515b1SVladimir Oltean speed = SPEED_2500; 122555a515b1SVladimir Oltean break; 122655a515b1SVladimir Oltean default: 122755a515b1SVladimir Oltean return; 122855a515b1SVladimir Oltean } 122955a515b1SVladimir Oltean 123055a515b1SVladimir Oltean picos_per_byte = (USEC_PER_SEC * 8) / speed; 123155a515b1SVladimir Oltean 123255a515b1SVladimir Oltean val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG); 123355a515b1SVladimir Oltean /* MAXLEN_CFG accounts automatically for VLAN. We need to include it 123455a515b1SVladimir Oltean * manually in the bit time calculation, plus the preamble and SFD. 123555a515b1SVladimir Oltean */ 123655a515b1SVladimir Oltean maxlen = val + 2 * VLAN_HLEN; 123755a515b1SVladimir Oltean /* Consider the standard Ethernet overhead of 8 octets preamble+SFD, 123855a515b1SVladimir Oltean * 4 octets FCS, 12 octets IFG. 123955a515b1SVladimir Oltean */ 124055a515b1SVladimir Oltean needed_bit_time_ps = (maxlen + 24) * picos_per_byte; 124155a515b1SVladimir Oltean 124255a515b1SVladimir Oltean dev_dbg(ocelot->dev, 124355a515b1SVladimir Oltean "port %d: max frame size %d needs %llu ps at speed %d\n", 124455a515b1SVladimir Oltean port, maxlen, needed_bit_time_ps, speed); 124555a515b1SVladimir Oltean 124655a515b1SVladimir Oltean vsc9959_tas_min_gate_lengths(ocelot_port->taprio, min_gate_len); 124755a515b1SVladimir Oltean 124855a515b1SVladimir Oltean for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 124955a515b1SVladimir Oltean u32 max_sdu; 125055a515b1SVladimir Oltean 125155a515b1SVladimir Oltean if (min_gate_len[tc] == U64_MAX /* Gate always open */ || 1252837ced3aSVladimir Oltean min_gate_len[tc] * PSEC_PER_NSEC > needed_bit_time_ps) { 125355a515b1SVladimir Oltean /* Setting QMAXSDU_CFG to 0 disables oversized frame 125455a515b1SVladimir Oltean * dropping. 125555a515b1SVladimir Oltean */ 125655a515b1SVladimir Oltean max_sdu = 0; 125755a515b1SVladimir Oltean dev_dbg(ocelot->dev, 125855a515b1SVladimir Oltean "port %d tc %d min gate len %llu" 125955a515b1SVladimir Oltean ", sending all frames\n", 126055a515b1SVladimir Oltean port, tc, min_gate_len[tc]); 126155a515b1SVladimir Oltean } else { 126255a515b1SVladimir Oltean /* If traffic class doesn't support a full MTU sized 126355a515b1SVladimir Oltean * frame, make sure to enable oversize frame dropping 126455a515b1SVladimir Oltean * for frames larger than the smallest that would fit. 126555a515b1SVladimir Oltean */ 1266837ced3aSVladimir Oltean max_sdu = div_u64(min_gate_len[tc] * PSEC_PER_NSEC, 126755a515b1SVladimir Oltean picos_per_byte); 126855a515b1SVladimir Oltean /* A TC gate may be completely closed, which is a 126955a515b1SVladimir Oltean * special case where all packets are oversized. 127055a515b1SVladimir Oltean * Any limit smaller than 64 octets accomplishes this 127155a515b1SVladimir Oltean */ 127255a515b1SVladimir Oltean if (!max_sdu) 127355a515b1SVladimir Oltean max_sdu = 1; 127455a515b1SVladimir Oltean /* Take L1 overhead into account, but just don't allow 127555a515b1SVladimir Oltean * max_sdu to go negative or to 0. Here we use 20 127655a515b1SVladimir Oltean * because QSYS_MAXSDU_CFG_* already counts the 4 FCS 127755a515b1SVladimir Oltean * octets as part of packet size. 127855a515b1SVladimir Oltean */ 127955a515b1SVladimir Oltean if (max_sdu > 20) 128055a515b1SVladimir Oltean max_sdu -= 20; 128155a515b1SVladimir Oltean dev_info(ocelot->dev, 128255a515b1SVladimir Oltean "port %d tc %d min gate length %llu" 128355a515b1SVladimir Oltean " ns not enough for max frame size %d at %d" 128455a515b1SVladimir Oltean " Mbps, dropping frames over %d" 128555a515b1SVladimir Oltean " octets including FCS\n", 128655a515b1SVladimir Oltean port, tc, min_gate_len[tc], maxlen, speed, 128755a515b1SVladimir Oltean max_sdu); 128855a515b1SVladimir Oltean } 128955a515b1SVladimir Oltean 129055a515b1SVladimir Oltean /* ocelot_write_rix is a macro that concatenates 129155a515b1SVladimir Oltean * QSYS_MAXSDU_CFG_* with _RSZ, so we need to spell out 129255a515b1SVladimir Oltean * the writes to each traffic class 129355a515b1SVladimir Oltean */ 129455a515b1SVladimir Oltean switch (tc) { 129555a515b1SVladimir Oltean case 0: 129655a515b1SVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0, 129755a515b1SVladimir Oltean port); 129855a515b1SVladimir Oltean break; 129955a515b1SVladimir Oltean case 1: 130055a515b1SVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1, 130155a515b1SVladimir Oltean port); 130255a515b1SVladimir Oltean break; 130355a515b1SVladimir Oltean case 2: 130455a515b1SVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2, 130555a515b1SVladimir Oltean port); 130655a515b1SVladimir Oltean break; 130755a515b1SVladimir Oltean case 3: 130855a515b1SVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3, 130955a515b1SVladimir Oltean port); 131055a515b1SVladimir Oltean break; 131155a515b1SVladimir Oltean case 4: 131255a515b1SVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4, 131355a515b1SVladimir Oltean port); 131455a515b1SVladimir Oltean break; 131555a515b1SVladimir Oltean case 5: 131655a515b1SVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5, 131755a515b1SVladimir Oltean port); 131855a515b1SVladimir Oltean break; 131955a515b1SVladimir Oltean case 6: 132055a515b1SVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6, 132155a515b1SVladimir Oltean port); 132255a515b1SVladimir Oltean break; 132355a515b1SVladimir Oltean case 7: 132455a515b1SVladimir Oltean ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7, 132555a515b1SVladimir Oltean port); 132655a515b1SVladimir Oltean break; 132755a515b1SVladimir Oltean } 132855a515b1SVladimir Oltean } 132955a515b1SVladimir Oltean 133055a515b1SVladimir Oltean ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port); 133155a515b1SVladimir Oltean } 133255a515b1SVladimir Oltean 1333de143c0eSXiaoliang Yang static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1334de143c0eSXiaoliang Yang u32 speed) 1335de143c0eSXiaoliang Yang { 133655a515b1SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 1337dba1e466SXiaoliang Yang u8 tas_speed; 1338dba1e466SXiaoliang Yang 1339dba1e466SXiaoliang Yang switch (speed) { 1340dba1e466SXiaoliang Yang case SPEED_10: 1341dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_10; 1342dba1e466SXiaoliang Yang break; 1343dba1e466SXiaoliang Yang case SPEED_100: 1344dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_100; 1345dba1e466SXiaoliang Yang break; 1346dba1e466SXiaoliang Yang case SPEED_1000: 1347dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_1000; 1348dba1e466SXiaoliang Yang break; 1349dba1e466SXiaoliang Yang case SPEED_2500: 1350dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_2500; 1351dba1e466SXiaoliang Yang break; 1352dba1e466SXiaoliang Yang default: 1353dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_1000; 1354dba1e466SXiaoliang Yang break; 1355dba1e466SXiaoliang Yang } 1356dba1e466SXiaoliang Yang 1357de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1358dba1e466SXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1359de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED_M, 1360de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 136155a515b1SVladimir Oltean 136255a515b1SVladimir Oltean mutex_lock(&ocelot->tas_lock); 136355a515b1SVladimir Oltean 136455a515b1SVladimir Oltean if (ocelot_port->taprio) 136555a515b1SVladimir Oltean vsc9959_tas_guard_bands_update(ocelot, port); 136655a515b1SVladimir Oltean 136755a515b1SVladimir Oltean mutex_unlock(&ocelot->tas_lock); 1368de143c0eSXiaoliang Yang } 1369de143c0eSXiaoliang Yang 1370de143c0eSXiaoliang Yang static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1371de143c0eSXiaoliang Yang u64 cycle_time, 1372de143c0eSXiaoliang Yang struct timespec64 *new_base_ts) 1373de143c0eSXiaoliang Yang { 1374de143c0eSXiaoliang Yang struct timespec64 ts; 1375de143c0eSXiaoliang Yang ktime_t new_base_time; 1376de143c0eSXiaoliang Yang ktime_t current_time; 1377de143c0eSXiaoliang Yang 1378de143c0eSXiaoliang Yang ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1379de143c0eSXiaoliang Yang current_time = timespec64_to_ktime(ts); 1380de143c0eSXiaoliang Yang new_base_time = base_time; 1381de143c0eSXiaoliang Yang 1382de143c0eSXiaoliang Yang if (base_time < current_time) { 1383de143c0eSXiaoliang Yang u64 nr_of_cycles = current_time - base_time; 1384de143c0eSXiaoliang Yang 1385de143c0eSXiaoliang Yang do_div(nr_of_cycles, cycle_time); 1386de143c0eSXiaoliang Yang new_base_time += cycle_time * (nr_of_cycles + 1); 1387de143c0eSXiaoliang Yang } 1388de143c0eSXiaoliang Yang 1389de143c0eSXiaoliang Yang *new_base_ts = ktime_to_timespec64(new_base_time); 1390de143c0eSXiaoliang Yang } 1391de143c0eSXiaoliang Yang 1392de143c0eSXiaoliang Yang static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1393de143c0eSXiaoliang Yang { 1394de143c0eSXiaoliang Yang return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1395de143c0eSXiaoliang Yang } 1396de143c0eSXiaoliang Yang 1397de143c0eSXiaoliang Yang static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1398de143c0eSXiaoliang Yang struct tc_taprio_sched_entry *entry) 1399de143c0eSXiaoliang Yang { 1400de143c0eSXiaoliang Yang ocelot_write(ocelot, 1401de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1402de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1403de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1); 1404de143c0eSXiaoliang Yang ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1405de143c0eSXiaoliang Yang } 1406de143c0eSXiaoliang Yang 1407de143c0eSXiaoliang Yang static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1408de143c0eSXiaoliang Yang struct tc_taprio_qopt_offload *taprio) 1409de143c0eSXiaoliang Yang { 14108670dc33SXiaoliang Yang struct ocelot_port *ocelot_port = ocelot->ports[port]; 1411de143c0eSXiaoliang Yang struct timespec64 base_ts; 1412de143c0eSXiaoliang Yang int ret, i; 1413de143c0eSXiaoliang Yang u32 val; 1414de143c0eSXiaoliang Yang 14158670dc33SXiaoliang Yang mutex_lock(&ocelot->tas_lock); 14168670dc33SXiaoliang Yang 1417de143c0eSXiaoliang Yang if (!taprio->enable) { 1418d68a373bSVladimir Oltean ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1419de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1420de143c0eSXiaoliang Yang 14211c9017e4SVladimir Oltean taprio_offload_free(ocelot_port->taprio); 14221c9017e4SVladimir Oltean ocelot_port->taprio = NULL; 14231c9017e4SVladimir Oltean 142455a515b1SVladimir Oltean vsc9959_tas_guard_bands_update(ocelot, port); 142555a515b1SVladimir Oltean 14268670dc33SXiaoliang Yang mutex_unlock(&ocelot->tas_lock); 1427de143c0eSXiaoliang Yang return 0; 1428de143c0eSXiaoliang Yang } 1429de143c0eSXiaoliang Yang 1430de143c0eSXiaoliang Yang if (taprio->cycle_time > NSEC_PER_SEC || 14318670dc33SXiaoliang Yang taprio->cycle_time_extension >= NSEC_PER_SEC) { 14328670dc33SXiaoliang Yang ret = -EINVAL; 14338670dc33SXiaoliang Yang goto err; 14348670dc33SXiaoliang Yang } 1435de143c0eSXiaoliang Yang 14368670dc33SXiaoliang Yang if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) { 14378670dc33SXiaoliang Yang ret = -ERANGE; 14388670dc33SXiaoliang Yang goto err; 14398670dc33SXiaoliang Yang } 1440de143c0eSXiaoliang Yang 1441297c4de6SMichael Walle /* Enable guard band. The switch will schedule frames without taking 1442297c4de6SMichael Walle * their length into account. Thus we'll always need to enable the 1443297c4de6SMichael Walle * guard band which reserves the time of a maximum sized frame at the 1444297c4de6SMichael Walle * end of the time window. 1445297c4de6SMichael Walle * 1446297c4de6SMichael Walle * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1447297c4de6SMichael Walle * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1448297c4de6SMichael Walle * operate on the port number. 1449316bcffeSXiaoliang Yang */ 1450297c4de6SMichael Walle ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1451297c4de6SMichael Walle QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1452de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1453de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1454de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 1455de143c0eSXiaoliang Yang 1456de143c0eSXiaoliang Yang /* Hardware errata - Admin config could not be overwritten if 1457de143c0eSXiaoliang Yang * config is pending, need reset the TAS module 1458de143c0eSXiaoliang Yang */ 1459de143c0eSXiaoliang Yang val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 14608670dc33SXiaoliang Yang if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) { 14618670dc33SXiaoliang Yang ret = -EBUSY; 14628670dc33SXiaoliang Yang goto err; 14638670dc33SXiaoliang Yang } 1464de143c0eSXiaoliang Yang 1465de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1466de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1467de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1468de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1469de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1470de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1471de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1472de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1473de143c0eSXiaoliang Yang 1474de143c0eSXiaoliang Yang vsc9959_new_base_time(ocelot, taprio->base_time, 1475de143c0eSXiaoliang Yang taprio->cycle_time, &base_ts); 1476de143c0eSXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1477de143c0eSXiaoliang Yang ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1478de143c0eSXiaoliang Yang val = upper_32_bits(base_ts.tv_sec); 1479de143c0eSXiaoliang Yang ocelot_write(ocelot, 1480de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1481de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1482de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3); 1483de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1484de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1485de143c0eSXiaoliang Yang 1486de143c0eSXiaoliang Yang for (i = 0; i < taprio->num_entries; i++) 1487de143c0eSXiaoliang Yang vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1488de143c0eSXiaoliang Yang 1489de143c0eSXiaoliang Yang ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1490de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1491de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 1492de143c0eSXiaoliang Yang 1493de143c0eSXiaoliang Yang ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1494de143c0eSXiaoliang Yang !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1495de143c0eSXiaoliang Yang 10, 100000); 14961c9017e4SVladimir Oltean if (ret) 14971c9017e4SVladimir Oltean goto err; 14981c9017e4SVladimir Oltean 14991c9017e4SVladimir Oltean ocelot_port->taprio = taprio_offload_get(taprio); 150055a515b1SVladimir Oltean vsc9959_tas_guard_bands_update(ocelot, port); 1501de143c0eSXiaoliang Yang 15028670dc33SXiaoliang Yang err: 15038670dc33SXiaoliang Yang mutex_unlock(&ocelot->tas_lock); 15048670dc33SXiaoliang Yang 1505de143c0eSXiaoliang Yang return ret; 1506de143c0eSXiaoliang Yang } 1507de143c0eSXiaoliang Yang 15088670dc33SXiaoliang Yang static void vsc9959_tas_clock_adjust(struct ocelot *ocelot) 15098670dc33SXiaoliang Yang { 15101c9017e4SVladimir Oltean struct tc_taprio_qopt_offload *taprio; 15118670dc33SXiaoliang Yang struct ocelot_port *ocelot_port; 15128670dc33SXiaoliang Yang struct timespec64 base_ts; 15138670dc33SXiaoliang Yang int port; 15148670dc33SXiaoliang Yang u32 val; 15158670dc33SXiaoliang Yang 15168670dc33SXiaoliang Yang mutex_lock(&ocelot->tas_lock); 15178670dc33SXiaoliang Yang 15188670dc33SXiaoliang Yang for (port = 0; port < ocelot->num_phys_ports; port++) { 15191c9017e4SVladimir Oltean ocelot_port = ocelot->ports[port]; 15201c9017e4SVladimir Oltean taprio = ocelot_port->taprio; 15211c9017e4SVladimir Oltean if (!taprio) 15228670dc33SXiaoliang Yang continue; 15238670dc33SXiaoliang Yang 15248670dc33SXiaoliang Yang ocelot_rmw(ocelot, 15258670dc33SXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port), 15268670dc33SXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M, 15278670dc33SXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 15288670dc33SXiaoliang Yang 1529d68a373bSVladimir Oltean /* Disable time-aware shaper */ 1530d68a373bSVladimir Oltean ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 15318670dc33SXiaoliang Yang QSYS_TAG_CONFIG, port); 15328670dc33SXiaoliang Yang 15331c9017e4SVladimir Oltean vsc9959_new_base_time(ocelot, taprio->base_time, 15341c9017e4SVladimir Oltean taprio->cycle_time, &base_ts); 15358670dc33SXiaoliang Yang 15368670dc33SXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 15378670dc33SXiaoliang Yang ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), 15388670dc33SXiaoliang Yang QSYS_PARAM_CFG_REG_2); 15398670dc33SXiaoliang Yang val = upper_32_bits(base_ts.tv_sec); 15408670dc33SXiaoliang Yang ocelot_rmw(ocelot, 15418670dc33SXiaoliang Yang QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val), 15428670dc33SXiaoliang Yang QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M, 15438670dc33SXiaoliang Yang QSYS_PARAM_CFG_REG_3); 15448670dc33SXiaoliang Yang 15458670dc33SXiaoliang Yang ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 15468670dc33SXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 15478670dc33SXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 15488670dc33SXiaoliang Yang 1549d68a373bSVladimir Oltean /* Re-enable time-aware shaper */ 1550d68a373bSVladimir Oltean ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE, 15518670dc33SXiaoliang Yang QSYS_TAG_CONFIG_ENABLE, 15528670dc33SXiaoliang Yang QSYS_TAG_CONFIG, port); 15538670dc33SXiaoliang Yang } 15548670dc33SXiaoliang Yang mutex_unlock(&ocelot->tas_lock); 15558670dc33SXiaoliang Yang } 15568670dc33SXiaoliang Yang 15570fbabf87SXiaoliang Yang static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 15580fbabf87SXiaoliang Yang struct tc_cbs_qopt_offload *cbs_qopt) 15590fbabf87SXiaoliang Yang { 15600fbabf87SXiaoliang Yang struct ocelot *ocelot = ds->priv; 15610fbabf87SXiaoliang Yang int port_ix = port * 8 + cbs_qopt->queue; 15620fbabf87SXiaoliang Yang u32 rate, burst; 15630fbabf87SXiaoliang Yang 15640fbabf87SXiaoliang Yang if (cbs_qopt->queue >= ds->num_tx_queues) 15650fbabf87SXiaoliang Yang return -EINVAL; 15660fbabf87SXiaoliang Yang 15670fbabf87SXiaoliang Yang if (!cbs_qopt->enable) { 15680fbabf87SXiaoliang Yang ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 15690fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(0), 15700fbabf87SXiaoliang Yang QSYS_CIR_CFG, port_ix); 15710fbabf87SXiaoliang Yang 15720fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 15730fbabf87SXiaoliang Yang QSYS_SE_CFG, port_ix); 15740fbabf87SXiaoliang Yang 15750fbabf87SXiaoliang Yang return 0; 15760fbabf87SXiaoliang Yang } 15770fbabf87SXiaoliang Yang 15780fbabf87SXiaoliang Yang /* Rate unit is 100 kbps */ 15790fbabf87SXiaoliang Yang rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 15800fbabf87SXiaoliang Yang /* Avoid using zero rate */ 15810fbabf87SXiaoliang Yang rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 15820fbabf87SXiaoliang Yang /* Burst unit is 4kB */ 15830fbabf87SXiaoliang Yang burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 15840fbabf87SXiaoliang Yang /* Avoid using zero burst size */ 1585b014d043SColin Ian King burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 15860fbabf87SXiaoliang Yang ocelot_write_gix(ocelot, 15870fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_RATE(rate) | 15880fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(burst), 15890fbabf87SXiaoliang Yang QSYS_CIR_CFG, 15900fbabf87SXiaoliang Yang port_ix); 15910fbabf87SXiaoliang Yang 15920fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot, 15930fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE(0) | 15940fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA, 15950fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA | 15960fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE_M, 15970fbabf87SXiaoliang Yang QSYS_SE_CFG, 15980fbabf87SXiaoliang Yang port_ix); 15990fbabf87SXiaoliang Yang 16000fbabf87SXiaoliang Yang return 0; 16010fbabf87SXiaoliang Yang } 16020fbabf87SXiaoliang Yang 1603de143c0eSXiaoliang Yang static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1604de143c0eSXiaoliang Yang enum tc_setup_type type, 1605de143c0eSXiaoliang Yang void *type_data) 1606de143c0eSXiaoliang Yang { 1607de143c0eSXiaoliang Yang struct ocelot *ocelot = ds->priv; 1608de143c0eSXiaoliang Yang 1609de143c0eSXiaoliang Yang switch (type) { 1610de143c0eSXiaoliang Yang case TC_SETUP_QDISC_TAPRIO: 1611de143c0eSXiaoliang Yang return vsc9959_qos_port_tas_set(ocelot, port, type_data); 16120fbabf87SXiaoliang Yang case TC_SETUP_QDISC_CBS: 16130fbabf87SXiaoliang Yang return vsc9959_qos_port_cbs_set(ds, port, type_data); 1614de143c0eSXiaoliang Yang default: 1615de143c0eSXiaoliang Yang return -EOPNOTSUPP; 1616de143c0eSXiaoliang Yang } 1617de143c0eSXiaoliang Yang } 1618de143c0eSXiaoliang Yang 16197d4b564dSXiaoliang Yang #define VSC9959_PSFP_SFID_MAX 175 16207d4b564dSXiaoliang Yang #define VSC9959_PSFP_GATE_ID_MAX 183 162176c13edeSXiaoliang Yang #define VSC9959_PSFP_POLICER_BASE 63 16227d4b564dSXiaoliang Yang #define VSC9959_PSFP_POLICER_MAX 383 162323ae3a78SXiaoliang Yang #define VSC9959_PSFP_GATE_LIST_NUM 4 162423ae3a78SXiaoliang Yang #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 16257d4b564dSXiaoliang Yang 16267d4b564dSXiaoliang Yang struct felix_stream { 16277d4b564dSXiaoliang Yang struct list_head list; 16287d4b564dSXiaoliang Yang unsigned long id; 1629a7e13edfSXiaoliang Yang bool dummy; 1630a7e13edfSXiaoliang Yang int ports; 1631a7e13edfSXiaoliang Yang int port; 16327d4b564dSXiaoliang Yang u8 dmac[ETH_ALEN]; 16337d4b564dSXiaoliang Yang u16 vid; 16347d4b564dSXiaoliang Yang s8 prio; 16357d4b564dSXiaoliang Yang u8 sfid_valid; 16367d4b564dSXiaoliang Yang u8 ssid_valid; 16377d4b564dSXiaoliang Yang u32 sfid; 16387d4b564dSXiaoliang Yang u32 ssid; 16397d4b564dSXiaoliang Yang }; 16407d4b564dSXiaoliang Yang 16417d4b564dSXiaoliang Yang struct felix_stream_filter { 16427d4b564dSXiaoliang Yang struct list_head list; 16437d4b564dSXiaoliang Yang refcount_t refcount; 16447d4b564dSXiaoliang Yang u32 index; 16457d4b564dSXiaoliang Yang u8 enable; 1646a7e13edfSXiaoliang Yang int portmask; 16477d4b564dSXiaoliang Yang u8 sg_valid; 16487d4b564dSXiaoliang Yang u32 sgid; 16497d4b564dSXiaoliang Yang u8 fm_valid; 16507d4b564dSXiaoliang Yang u32 fmid; 16517d4b564dSXiaoliang Yang u8 prio_valid; 16527d4b564dSXiaoliang Yang u8 prio; 16537d4b564dSXiaoliang Yang u32 maxsdu; 16547d4b564dSXiaoliang Yang }; 16557d4b564dSXiaoliang Yang 16567d4b564dSXiaoliang Yang struct felix_stream_filter_counters { 16577d4b564dSXiaoliang Yang u32 match; 16587d4b564dSXiaoliang Yang u32 not_pass_gate; 16597d4b564dSXiaoliang Yang u32 not_pass_sdu; 16607d4b564dSXiaoliang Yang u32 red; 16617d4b564dSXiaoliang Yang }; 16627d4b564dSXiaoliang Yang 166323ae3a78SXiaoliang Yang struct felix_stream_gate { 166423ae3a78SXiaoliang Yang u32 index; 166523ae3a78SXiaoliang Yang u8 enable; 166623ae3a78SXiaoliang Yang u8 ipv_valid; 166723ae3a78SXiaoliang Yang u8 init_ipv; 166823ae3a78SXiaoliang Yang u64 basetime; 166923ae3a78SXiaoliang Yang u64 cycletime; 167023ae3a78SXiaoliang Yang u64 cycletime_ext; 167123ae3a78SXiaoliang Yang u32 num_entries; 1672dcad856fSkernel test robot struct action_gate_entry entries[]; 167323ae3a78SXiaoliang Yang }; 167423ae3a78SXiaoliang Yang 167523ae3a78SXiaoliang Yang struct felix_stream_gate_entry { 167623ae3a78SXiaoliang Yang struct list_head list; 167723ae3a78SXiaoliang Yang refcount_t refcount; 167823ae3a78SXiaoliang Yang u32 index; 167923ae3a78SXiaoliang Yang }; 168023ae3a78SXiaoliang Yang 16817d4b564dSXiaoliang Yang static int vsc9959_stream_identify(struct flow_cls_offload *f, 16827d4b564dSXiaoliang Yang struct felix_stream *stream) 16837d4b564dSXiaoliang Yang { 16847d4b564dSXiaoliang Yang struct flow_rule *rule = flow_cls_offload_flow_rule(f); 16857d4b564dSXiaoliang Yang struct flow_dissector *dissector = rule->match.dissector; 16867d4b564dSXiaoliang Yang 16877d4b564dSXiaoliang Yang if (dissector->used_keys & 16887d4b564dSXiaoliang Yang ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 16897d4b564dSXiaoliang Yang BIT(FLOW_DISSECTOR_KEY_BASIC) | 16907d4b564dSXiaoliang Yang BIT(FLOW_DISSECTOR_KEY_VLAN) | 16917d4b564dSXiaoliang Yang BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 16927d4b564dSXiaoliang Yang return -EOPNOTSUPP; 16937d4b564dSXiaoliang Yang 16947d4b564dSXiaoliang Yang if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 16957d4b564dSXiaoliang Yang struct flow_match_eth_addrs match; 16967d4b564dSXiaoliang Yang 16977d4b564dSXiaoliang Yang flow_rule_match_eth_addrs(rule, &match); 16987d4b564dSXiaoliang Yang ether_addr_copy(stream->dmac, match.key->dst); 16997d4b564dSXiaoliang Yang if (!is_zero_ether_addr(match.mask->src)) 17007d4b564dSXiaoliang Yang return -EOPNOTSUPP; 17017d4b564dSXiaoliang Yang } else { 17027d4b564dSXiaoliang Yang return -EOPNOTSUPP; 17037d4b564dSXiaoliang Yang } 17047d4b564dSXiaoliang Yang 17057d4b564dSXiaoliang Yang if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 17067d4b564dSXiaoliang Yang struct flow_match_vlan match; 17077d4b564dSXiaoliang Yang 17087d4b564dSXiaoliang Yang flow_rule_match_vlan(rule, &match); 17097d4b564dSXiaoliang Yang if (match.mask->vlan_priority) 17107d4b564dSXiaoliang Yang stream->prio = match.key->vlan_priority; 17117d4b564dSXiaoliang Yang else 17127d4b564dSXiaoliang Yang stream->prio = -1; 17137d4b564dSXiaoliang Yang 17147d4b564dSXiaoliang Yang if (!match.mask->vlan_id) 17157d4b564dSXiaoliang Yang return -EOPNOTSUPP; 17167d4b564dSXiaoliang Yang stream->vid = match.key->vlan_id; 17177d4b564dSXiaoliang Yang } else { 17187d4b564dSXiaoliang Yang return -EOPNOTSUPP; 17197d4b564dSXiaoliang Yang } 17207d4b564dSXiaoliang Yang 17217d4b564dSXiaoliang Yang stream->id = f->cookie; 17227d4b564dSXiaoliang Yang 17237d4b564dSXiaoliang Yang return 0; 17247d4b564dSXiaoliang Yang } 17257d4b564dSXiaoliang Yang 17267d4b564dSXiaoliang Yang static int vsc9959_mact_stream_set(struct ocelot *ocelot, 17277d4b564dSXiaoliang Yang struct felix_stream *stream, 17287d4b564dSXiaoliang Yang struct netlink_ext_ack *extack) 17297d4b564dSXiaoliang Yang { 17307d4b564dSXiaoliang Yang enum macaccess_entry_type type; 17317d4b564dSXiaoliang Yang int ret, sfid, ssid; 17327d4b564dSXiaoliang Yang u32 vid, dst_idx; 17337d4b564dSXiaoliang Yang u8 mac[ETH_ALEN]; 17347d4b564dSXiaoliang Yang 17357d4b564dSXiaoliang Yang ether_addr_copy(mac, stream->dmac); 17367d4b564dSXiaoliang Yang vid = stream->vid; 17377d4b564dSXiaoliang Yang 17387d4b564dSXiaoliang Yang /* Stream identification desn't support to add a stream with non 17397d4b564dSXiaoliang Yang * existent MAC (The MAC entry has not been learned in MAC table). 17407d4b564dSXiaoliang Yang */ 17417d4b564dSXiaoliang Yang ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 17427d4b564dSXiaoliang Yang if (ret) { 17437d4b564dSXiaoliang Yang if (extack) 17447d4b564dSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 17457d4b564dSXiaoliang Yang return -EOPNOTSUPP; 17467d4b564dSXiaoliang Yang } 17477d4b564dSXiaoliang Yang 17487d4b564dSXiaoliang Yang if ((stream->sfid_valid || stream->ssid_valid) && 17497d4b564dSXiaoliang Yang type == ENTRYTYPE_NORMAL) 17507d4b564dSXiaoliang Yang type = ENTRYTYPE_LOCKED; 17517d4b564dSXiaoliang Yang 17527d4b564dSXiaoliang Yang sfid = stream->sfid_valid ? stream->sfid : -1; 17537d4b564dSXiaoliang Yang ssid = stream->ssid_valid ? stream->ssid : -1; 17547d4b564dSXiaoliang Yang 17557d4b564dSXiaoliang Yang ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 17567d4b564dSXiaoliang Yang sfid, ssid); 17577d4b564dSXiaoliang Yang 17587d4b564dSXiaoliang Yang return ret; 17597d4b564dSXiaoliang Yang } 17607d4b564dSXiaoliang Yang 17617d4b564dSXiaoliang Yang static struct felix_stream * 17627d4b564dSXiaoliang Yang vsc9959_stream_table_lookup(struct list_head *stream_list, 17637d4b564dSXiaoliang Yang struct felix_stream *stream) 17647d4b564dSXiaoliang Yang { 17657d4b564dSXiaoliang Yang struct felix_stream *tmp; 17667d4b564dSXiaoliang Yang 17677d4b564dSXiaoliang Yang list_for_each_entry(tmp, stream_list, list) 17687d4b564dSXiaoliang Yang if (ether_addr_equal(tmp->dmac, stream->dmac) && 17697d4b564dSXiaoliang Yang tmp->vid == stream->vid) 17707d4b564dSXiaoliang Yang return tmp; 17717d4b564dSXiaoliang Yang 17727d4b564dSXiaoliang Yang return NULL; 17737d4b564dSXiaoliang Yang } 17747d4b564dSXiaoliang Yang 17757d4b564dSXiaoliang Yang static int vsc9959_stream_table_add(struct ocelot *ocelot, 17767d4b564dSXiaoliang Yang struct list_head *stream_list, 17777d4b564dSXiaoliang Yang struct felix_stream *stream, 17787d4b564dSXiaoliang Yang struct netlink_ext_ack *extack) 17797d4b564dSXiaoliang Yang { 17807d4b564dSXiaoliang Yang struct felix_stream *stream_entry; 17817d4b564dSXiaoliang Yang int ret; 17827d4b564dSXiaoliang Yang 1783e44aecc7SYihao Han stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL); 17847d4b564dSXiaoliang Yang if (!stream_entry) 17857d4b564dSXiaoliang Yang return -ENOMEM; 17867d4b564dSXiaoliang Yang 1787a7e13edfSXiaoliang Yang if (!stream->dummy) { 17887d4b564dSXiaoliang Yang ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 17897d4b564dSXiaoliang Yang if (ret) { 17907d4b564dSXiaoliang Yang kfree(stream_entry); 17917d4b564dSXiaoliang Yang return ret; 17927d4b564dSXiaoliang Yang } 1793a7e13edfSXiaoliang Yang } 17947d4b564dSXiaoliang Yang 17957d4b564dSXiaoliang Yang list_add_tail(&stream_entry->list, stream_list); 17967d4b564dSXiaoliang Yang 17977d4b564dSXiaoliang Yang return 0; 17987d4b564dSXiaoliang Yang } 17997d4b564dSXiaoliang Yang 18007d4b564dSXiaoliang Yang static struct felix_stream * 18017d4b564dSXiaoliang Yang vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 18027d4b564dSXiaoliang Yang { 18037d4b564dSXiaoliang Yang struct felix_stream *tmp; 18047d4b564dSXiaoliang Yang 18057d4b564dSXiaoliang Yang list_for_each_entry(tmp, stream_list, list) 18067d4b564dSXiaoliang Yang if (tmp->id == id) 18077d4b564dSXiaoliang Yang return tmp; 18087d4b564dSXiaoliang Yang 18097d4b564dSXiaoliang Yang return NULL; 18107d4b564dSXiaoliang Yang } 18117d4b564dSXiaoliang Yang 18127d4b564dSXiaoliang Yang static void vsc9959_stream_table_del(struct ocelot *ocelot, 18137d4b564dSXiaoliang Yang struct felix_stream *stream) 18147d4b564dSXiaoliang Yang { 1815a7e13edfSXiaoliang Yang if (!stream->dummy) 18167d4b564dSXiaoliang Yang vsc9959_mact_stream_set(ocelot, stream, NULL); 18177d4b564dSXiaoliang Yang 18187d4b564dSXiaoliang Yang list_del(&stream->list); 18197d4b564dSXiaoliang Yang kfree(stream); 18207d4b564dSXiaoliang Yang } 18217d4b564dSXiaoliang Yang 18227d4b564dSXiaoliang Yang static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 18237d4b564dSXiaoliang Yang { 18247d4b564dSXiaoliang Yang return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 18257d4b564dSXiaoliang Yang } 18267d4b564dSXiaoliang Yang 18277d4b564dSXiaoliang Yang static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 18287d4b564dSXiaoliang Yang struct felix_stream_filter *sfi) 18297d4b564dSXiaoliang Yang { 18307d4b564dSXiaoliang Yang u32 val; 18317d4b564dSXiaoliang Yang 18327d4b564dSXiaoliang Yang if (sfi->index > VSC9959_PSFP_SFID_MAX) 18337d4b564dSXiaoliang Yang return -EINVAL; 18347d4b564dSXiaoliang Yang 18357d4b564dSXiaoliang Yang if (!sfi->enable) { 18367d4b564dSXiaoliang Yang ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 18377d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX); 18387d4b564dSXiaoliang Yang 18397d4b564dSXiaoliang Yang val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 18407d4b564dSXiaoliang Yang ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 18417d4b564dSXiaoliang Yang 18427d4b564dSXiaoliang Yang return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 18437d4b564dSXiaoliang Yang (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 18447d4b564dSXiaoliang Yang 10, 100000); 18457d4b564dSXiaoliang Yang } 18467d4b564dSXiaoliang Yang 18477d4b564dSXiaoliang Yang if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 18487d4b564dSXiaoliang Yang sfi->fmid > VSC9959_PSFP_POLICER_MAX) 18497d4b564dSXiaoliang Yang return -EINVAL; 18507d4b564dSXiaoliang Yang 18517d4b564dSXiaoliang Yang ocelot_write(ocelot, 18527d4b564dSXiaoliang Yang (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 18537d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 18547d4b564dSXiaoliang Yang (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 18557d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 18567d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 18577d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX); 18587d4b564dSXiaoliang Yang 18597d4b564dSXiaoliang Yang ocelot_write(ocelot, 18607d4b564dSXiaoliang Yang (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 18617d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 18627d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 18637d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 18647d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS); 18657d4b564dSXiaoliang Yang 18667d4b564dSXiaoliang Yang return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 18677d4b564dSXiaoliang Yang (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 18687d4b564dSXiaoliang Yang 10, 100000); 18697d4b564dSXiaoliang Yang } 18707d4b564dSXiaoliang Yang 1871a7e13edfSXiaoliang Yang static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) 18727d4b564dSXiaoliang Yang { 1873a7e13edfSXiaoliang Yang u32 val; 1874a7e13edfSXiaoliang Yang 1875a7e13edfSXiaoliang Yang ocelot_rmw(ocelot, 1876a7e13edfSXiaoliang Yang ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), 1877a7e13edfSXiaoliang Yang ANA_TABLES_SFIDTIDX_SFID_INDEX_M, 1878a7e13edfSXiaoliang Yang ANA_TABLES_SFIDTIDX); 1879a7e13edfSXiaoliang Yang 1880a7e13edfSXiaoliang Yang ocelot_write(ocelot, 1881a7e13edfSXiaoliang Yang ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | 1882a7e13edfSXiaoliang Yang ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, 1883a7e13edfSXiaoliang Yang ANA_TABLES_SFID_MASK); 1884a7e13edfSXiaoliang Yang 1885a7e13edfSXiaoliang Yang ocelot_rmw(ocelot, 1886a7e13edfSXiaoliang Yang ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1887a7e13edfSXiaoliang Yang ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, 1888a7e13edfSXiaoliang Yang ANA_TABLES_SFIDACCESS); 1889a7e13edfSXiaoliang Yang 1890a7e13edfSXiaoliang Yang return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1891a7e13edfSXiaoliang Yang (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1892a7e13edfSXiaoliang Yang 10, 100000); 1893a7e13edfSXiaoliang Yang } 1894a7e13edfSXiaoliang Yang 1895a7e13edfSXiaoliang Yang static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, 1896a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi, 1897a7e13edfSXiaoliang Yang struct list_head *pos) 1898a7e13edfSXiaoliang Yang { 1899a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi_entry; 19007d4b564dSXiaoliang Yang int ret; 19017d4b564dSXiaoliang Yang 1902e44aecc7SYihao Han sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL); 19037d4b564dSXiaoliang Yang if (!sfi_entry) 19047d4b564dSXiaoliang Yang return -ENOMEM; 19057d4b564dSXiaoliang Yang 19067d4b564dSXiaoliang Yang refcount_set(&sfi_entry->refcount, 1); 19077d4b564dSXiaoliang Yang 19087d4b564dSXiaoliang Yang ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 19097d4b564dSXiaoliang Yang if (ret) { 19107d4b564dSXiaoliang Yang kfree(sfi_entry); 19117d4b564dSXiaoliang Yang return ret; 19127d4b564dSXiaoliang Yang } 19137d4b564dSXiaoliang Yang 1914a7e13edfSXiaoliang Yang vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask); 1915a7e13edfSXiaoliang Yang 1916a7e13edfSXiaoliang Yang list_add(&sfi_entry->list, pos); 19177d4b564dSXiaoliang Yang 19187d4b564dSXiaoliang Yang return 0; 19197d4b564dSXiaoliang Yang } 19207d4b564dSXiaoliang Yang 1921a7e13edfSXiaoliang Yang static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 1922a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi) 1923a7e13edfSXiaoliang Yang { 1924a7e13edfSXiaoliang Yang struct list_head *pos, *q, *last; 1925a7e13edfSXiaoliang Yang struct felix_stream_filter *tmp; 1926a7e13edfSXiaoliang Yang struct ocelot_psfp_list *psfp; 1927a7e13edfSXiaoliang Yang u32 insert = 0; 1928a7e13edfSXiaoliang Yang 1929a7e13edfSXiaoliang Yang psfp = &ocelot->psfp; 1930a7e13edfSXiaoliang Yang last = &psfp->sfi_list; 1931a7e13edfSXiaoliang Yang 1932a7e13edfSXiaoliang Yang list_for_each_safe(pos, q, &psfp->sfi_list) { 1933a7e13edfSXiaoliang Yang tmp = list_entry(pos, struct felix_stream_filter, list); 1934a7e13edfSXiaoliang Yang if (sfi->sg_valid == tmp->sg_valid && 1935a7e13edfSXiaoliang Yang sfi->fm_valid == tmp->fm_valid && 1936a7e13edfSXiaoliang Yang sfi->portmask == tmp->portmask && 1937a7e13edfSXiaoliang Yang tmp->sgid == sfi->sgid && 1938a7e13edfSXiaoliang Yang tmp->fmid == sfi->fmid) { 1939a7e13edfSXiaoliang Yang sfi->index = tmp->index; 1940a7e13edfSXiaoliang Yang refcount_inc(&tmp->refcount); 1941a7e13edfSXiaoliang Yang return 0; 1942a7e13edfSXiaoliang Yang } 1943a7e13edfSXiaoliang Yang /* Make sure that the index is increasing in order. */ 1944a7e13edfSXiaoliang Yang if (tmp->index == insert) { 1945a7e13edfSXiaoliang Yang last = pos; 1946a7e13edfSXiaoliang Yang insert++; 1947a7e13edfSXiaoliang Yang } 1948a7e13edfSXiaoliang Yang } 1949a7e13edfSXiaoliang Yang sfi->index = insert; 1950a7e13edfSXiaoliang Yang 1951a7e13edfSXiaoliang Yang return vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1952a7e13edfSXiaoliang Yang } 1953a7e13edfSXiaoliang Yang 1954a7e13edfSXiaoliang Yang static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, 1955a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi, 1956a7e13edfSXiaoliang Yang struct felix_stream_filter *sfi2) 1957a7e13edfSXiaoliang Yang { 1958a7e13edfSXiaoliang Yang struct felix_stream_filter *tmp; 1959a7e13edfSXiaoliang Yang struct list_head *pos, *q, *last; 1960a7e13edfSXiaoliang Yang struct ocelot_psfp_list *psfp; 1961a7e13edfSXiaoliang Yang u32 insert = 0; 1962a7e13edfSXiaoliang Yang int ret; 1963a7e13edfSXiaoliang Yang 1964a7e13edfSXiaoliang Yang psfp = &ocelot->psfp; 1965a7e13edfSXiaoliang Yang last = &psfp->sfi_list; 1966a7e13edfSXiaoliang Yang 1967a7e13edfSXiaoliang Yang list_for_each_safe(pos, q, &psfp->sfi_list) { 1968a7e13edfSXiaoliang Yang tmp = list_entry(pos, struct felix_stream_filter, list); 1969a7e13edfSXiaoliang Yang /* Make sure that the index is increasing in order. */ 1970a7e13edfSXiaoliang Yang if (tmp->index >= insert + 2) 1971a7e13edfSXiaoliang Yang break; 1972a7e13edfSXiaoliang Yang 1973a7e13edfSXiaoliang Yang insert = tmp->index + 1; 1974a7e13edfSXiaoliang Yang last = pos; 1975a7e13edfSXiaoliang Yang } 1976a7e13edfSXiaoliang Yang sfi->index = insert; 1977a7e13edfSXiaoliang Yang 1978a7e13edfSXiaoliang Yang ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1979a7e13edfSXiaoliang Yang if (ret) 1980a7e13edfSXiaoliang Yang return ret; 1981a7e13edfSXiaoliang Yang 1982a7e13edfSXiaoliang Yang sfi2->index = insert + 1; 1983a7e13edfSXiaoliang Yang 1984a7e13edfSXiaoliang Yang return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next); 1985a7e13edfSXiaoliang Yang } 1986a7e13edfSXiaoliang Yang 198723ae3a78SXiaoliang Yang static struct felix_stream_filter * 198823ae3a78SXiaoliang Yang vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 198923ae3a78SXiaoliang Yang { 199023ae3a78SXiaoliang Yang struct felix_stream_filter *tmp; 199123ae3a78SXiaoliang Yang 199223ae3a78SXiaoliang Yang list_for_each_entry(tmp, sfi_list, list) 199323ae3a78SXiaoliang Yang if (tmp->index == index) 199423ae3a78SXiaoliang Yang return tmp; 199523ae3a78SXiaoliang Yang 199623ae3a78SXiaoliang Yang return NULL; 199723ae3a78SXiaoliang Yang } 199823ae3a78SXiaoliang Yang 19997d4b564dSXiaoliang Yang static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 20007d4b564dSXiaoliang Yang { 20017d4b564dSXiaoliang Yang struct felix_stream_filter *tmp, *n; 20027d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 20037d4b564dSXiaoliang Yang u8 z; 20047d4b564dSXiaoliang Yang 20057d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 20067d4b564dSXiaoliang Yang 20077d4b564dSXiaoliang Yang list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 20087d4b564dSXiaoliang Yang if (tmp->index == index) { 20097d4b564dSXiaoliang Yang z = refcount_dec_and_test(&tmp->refcount); 20107d4b564dSXiaoliang Yang if (z) { 20117d4b564dSXiaoliang Yang tmp->enable = 0; 20127d4b564dSXiaoliang Yang vsc9959_psfp_sfi_set(ocelot, tmp); 20137d4b564dSXiaoliang Yang list_del(&tmp->list); 20147d4b564dSXiaoliang Yang kfree(tmp); 20157d4b564dSXiaoliang Yang } 20167d4b564dSXiaoliang Yang break; 20177d4b564dSXiaoliang Yang } 20187d4b564dSXiaoliang Yang } 20197d4b564dSXiaoliang Yang 202023ae3a78SXiaoliang Yang static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 202123ae3a78SXiaoliang Yang struct felix_stream_gate *sgi) 202223ae3a78SXiaoliang Yang { 20235a995900SBaowen Zheng sgi->index = entry->hw_index; 202423ae3a78SXiaoliang Yang sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 202523ae3a78SXiaoliang Yang sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 202623ae3a78SXiaoliang Yang sgi->basetime = entry->gate.basetime; 202723ae3a78SXiaoliang Yang sgi->cycletime = entry->gate.cycletime; 202823ae3a78SXiaoliang Yang sgi->num_entries = entry->gate.num_entries; 202923ae3a78SXiaoliang Yang sgi->enable = 1; 203023ae3a78SXiaoliang Yang 203123ae3a78SXiaoliang Yang memcpy(sgi->entries, entry->gate.entries, 203223ae3a78SXiaoliang Yang entry->gate.num_entries * sizeof(struct action_gate_entry)); 203323ae3a78SXiaoliang Yang } 203423ae3a78SXiaoliang Yang 203523ae3a78SXiaoliang Yang static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 203623ae3a78SXiaoliang Yang { 203723ae3a78SXiaoliang Yang return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 203823ae3a78SXiaoliang Yang } 203923ae3a78SXiaoliang Yang 204023ae3a78SXiaoliang Yang static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 204123ae3a78SXiaoliang Yang struct felix_stream_gate *sgi) 204223ae3a78SXiaoliang Yang { 204323ae3a78SXiaoliang Yang struct action_gate_entry *e; 204423ae3a78SXiaoliang Yang struct timespec64 base_ts; 204523ae3a78SXiaoliang Yang u32 interval_sum = 0; 204623ae3a78SXiaoliang Yang u32 val; 204723ae3a78SXiaoliang Yang int i; 204823ae3a78SXiaoliang Yang 204923ae3a78SXiaoliang Yang if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 205023ae3a78SXiaoliang Yang return -EINVAL; 205123ae3a78SXiaoliang Yang 205223ae3a78SXiaoliang Yang ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 205323ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL); 205423ae3a78SXiaoliang Yang 205523ae3a78SXiaoliang Yang if (!sgi->enable) { 205623ae3a78SXiaoliang Yang ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 205723ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 205823ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_GATE_ENABLE, 205923ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3); 206023ae3a78SXiaoliang Yang 206123ae3a78SXiaoliang Yang return 0; 206223ae3a78SXiaoliang Yang } 206323ae3a78SXiaoliang Yang 206423ae3a78SXiaoliang Yang if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 206523ae3a78SXiaoliang Yang sgi->cycletime > NSEC_PER_SEC) 206623ae3a78SXiaoliang Yang return -EINVAL; 206723ae3a78SXiaoliang Yang 206823ae3a78SXiaoliang Yang if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 206923ae3a78SXiaoliang Yang return -EINVAL; 207023ae3a78SXiaoliang Yang 207123ae3a78SXiaoliang Yang vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 207223ae3a78SXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 207323ae3a78SXiaoliang Yang val = lower_32_bits(base_ts.tv_sec); 207423ae3a78SXiaoliang Yang ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 207523ae3a78SXiaoliang Yang 207623ae3a78SXiaoliang Yang val = upper_32_bits(base_ts.tv_sec); 207723ae3a78SXiaoliang Yang ocelot_write(ocelot, 207823ae3a78SXiaoliang Yang (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 207923ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 208023ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_GATE_ENABLE | 208123ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 208223ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 208323ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 208423ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3); 208523ae3a78SXiaoliang Yang 208623ae3a78SXiaoliang Yang ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 208723ae3a78SXiaoliang Yang 208823ae3a78SXiaoliang Yang e = sgi->entries; 208923ae3a78SXiaoliang Yang for (i = 0; i < sgi->num_entries; i++) { 209023ae3a78SXiaoliang Yang u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 209123ae3a78SXiaoliang Yang 209223ae3a78SXiaoliang Yang ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 209323ae3a78SXiaoliang Yang (e[i].gate_state ? 209423ae3a78SXiaoliang Yang ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 209523ae3a78SXiaoliang Yang ANA_SG_GCL_GS_CONFIG, i); 209623ae3a78SXiaoliang Yang 209723ae3a78SXiaoliang Yang interval_sum += e[i].interval; 209823ae3a78SXiaoliang Yang ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 209923ae3a78SXiaoliang Yang } 210023ae3a78SXiaoliang Yang 210123ae3a78SXiaoliang Yang ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 210223ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 210323ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL); 210423ae3a78SXiaoliang Yang 210523ae3a78SXiaoliang Yang return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 210623ae3a78SXiaoliang Yang (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 210723ae3a78SXiaoliang Yang 10, 100000); 210823ae3a78SXiaoliang Yang } 210923ae3a78SXiaoliang Yang 211023ae3a78SXiaoliang Yang static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 211123ae3a78SXiaoliang Yang struct felix_stream_gate *sgi) 211223ae3a78SXiaoliang Yang { 211323ae3a78SXiaoliang Yang struct felix_stream_gate_entry *tmp; 211423ae3a78SXiaoliang Yang struct ocelot_psfp_list *psfp; 211523ae3a78SXiaoliang Yang int ret; 211623ae3a78SXiaoliang Yang 211723ae3a78SXiaoliang Yang psfp = &ocelot->psfp; 211823ae3a78SXiaoliang Yang 211923ae3a78SXiaoliang Yang list_for_each_entry(tmp, &psfp->sgi_list, list) 212023ae3a78SXiaoliang Yang if (tmp->index == sgi->index) { 212123ae3a78SXiaoliang Yang refcount_inc(&tmp->refcount); 212223ae3a78SXiaoliang Yang return 0; 212323ae3a78SXiaoliang Yang } 212423ae3a78SXiaoliang Yang 212523ae3a78SXiaoliang Yang tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 212623ae3a78SXiaoliang Yang if (!tmp) 212723ae3a78SXiaoliang Yang return -ENOMEM; 212823ae3a78SXiaoliang Yang 212923ae3a78SXiaoliang Yang ret = vsc9959_psfp_sgi_set(ocelot, sgi); 213023ae3a78SXiaoliang Yang if (ret) { 213123ae3a78SXiaoliang Yang kfree(tmp); 213223ae3a78SXiaoliang Yang return ret; 213323ae3a78SXiaoliang Yang } 213423ae3a78SXiaoliang Yang 213523ae3a78SXiaoliang Yang tmp->index = sgi->index; 213623ae3a78SXiaoliang Yang refcount_set(&tmp->refcount, 1); 213723ae3a78SXiaoliang Yang list_add_tail(&tmp->list, &psfp->sgi_list); 213823ae3a78SXiaoliang Yang 213923ae3a78SXiaoliang Yang return 0; 214023ae3a78SXiaoliang Yang } 214123ae3a78SXiaoliang Yang 214223ae3a78SXiaoliang Yang static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 214323ae3a78SXiaoliang Yang u32 index) 214423ae3a78SXiaoliang Yang { 214523ae3a78SXiaoliang Yang struct felix_stream_gate_entry *tmp, *n; 214623ae3a78SXiaoliang Yang struct felix_stream_gate sgi = {0}; 214723ae3a78SXiaoliang Yang struct ocelot_psfp_list *psfp; 214823ae3a78SXiaoliang Yang u8 z; 214923ae3a78SXiaoliang Yang 215023ae3a78SXiaoliang Yang psfp = &ocelot->psfp; 215123ae3a78SXiaoliang Yang 215223ae3a78SXiaoliang Yang list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 215323ae3a78SXiaoliang Yang if (tmp->index == index) { 215423ae3a78SXiaoliang Yang z = refcount_dec_and_test(&tmp->refcount); 215523ae3a78SXiaoliang Yang if (z) { 215623ae3a78SXiaoliang Yang sgi.index = index; 215723ae3a78SXiaoliang Yang sgi.enable = 0; 215823ae3a78SXiaoliang Yang vsc9959_psfp_sgi_set(ocelot, &sgi); 215923ae3a78SXiaoliang Yang list_del(&tmp->list); 216023ae3a78SXiaoliang Yang kfree(tmp); 216123ae3a78SXiaoliang Yang } 216223ae3a78SXiaoliang Yang break; 216323ae3a78SXiaoliang Yang } 216423ae3a78SXiaoliang Yang } 216523ae3a78SXiaoliang Yang 21667d4b564dSXiaoliang Yang static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index, 21677d4b564dSXiaoliang Yang struct felix_stream_filter_counters *counters) 21687d4b564dSXiaoliang Yang { 216958bf4db6SVladimir Oltean mutex_lock(&ocelot->stats_lock); 217058bf4db6SVladimir Oltean 21717d4b564dSXiaoliang Yang ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index), 21727d4b564dSXiaoliang Yang SYS_STAT_CFG_STAT_VIEW_M, 21737d4b564dSXiaoliang Yang SYS_STAT_CFG); 21747d4b564dSXiaoliang Yang 21757d4b564dSXiaoliang Yang counters->match = ocelot_read_gix(ocelot, SYS_CNT, 0x200); 21767d4b564dSXiaoliang Yang counters->not_pass_gate = ocelot_read_gix(ocelot, SYS_CNT, 0x201); 21777d4b564dSXiaoliang Yang counters->not_pass_sdu = ocelot_read_gix(ocelot, SYS_CNT, 0x202); 21787d4b564dSXiaoliang Yang counters->red = ocelot_read_gix(ocelot, SYS_CNT, 0x203); 21797d4b564dSXiaoliang Yang 21807d4b564dSXiaoliang Yang /* Clear the PSFP counter. */ 21817d4b564dSXiaoliang Yang ocelot_write(ocelot, 21827d4b564dSXiaoliang Yang SYS_STAT_CFG_STAT_VIEW(index) | 21837d4b564dSXiaoliang Yang SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 21847d4b564dSXiaoliang Yang SYS_STAT_CFG); 218558bf4db6SVladimir Oltean 218658bf4db6SVladimir Oltean mutex_unlock(&ocelot->stats_lock); 21877d4b564dSXiaoliang Yang } 21887d4b564dSXiaoliang Yang 2189a7e13edfSXiaoliang Yang static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, 21907d4b564dSXiaoliang Yang struct flow_cls_offload *f) 21917d4b564dSXiaoliang Yang { 21927d4b564dSXiaoliang Yang struct netlink_ext_ack *extack = f->common.extack; 2193a7e13edfSXiaoliang Yang struct felix_stream_filter old_sfi, *sfi_entry; 21947d4b564dSXiaoliang Yang struct felix_stream_filter sfi = {0}; 21957d4b564dSXiaoliang Yang const struct flow_action_entry *a; 21967d4b564dSXiaoliang Yang struct felix_stream *stream_entry; 21977d4b564dSXiaoliang Yang struct felix_stream stream = {0}; 219823ae3a78SXiaoliang Yang struct felix_stream_gate *sgi; 21997d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 220076c13edeSXiaoliang Yang struct ocelot_policer pol; 220123ae3a78SXiaoliang Yang int ret, i, size; 220276c13edeSXiaoliang Yang u64 rate, burst; 220376c13edeSXiaoliang Yang u32 index; 22047d4b564dSXiaoliang Yang 22057d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 22067d4b564dSXiaoliang Yang 22077d4b564dSXiaoliang Yang ret = vsc9959_stream_identify(f, &stream); 22087d4b564dSXiaoliang Yang if (ret) { 22097d4b564dSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 22107d4b564dSXiaoliang Yang return ret; 22117d4b564dSXiaoliang Yang } 22127d4b564dSXiaoliang Yang 22137d4b564dSXiaoliang Yang flow_action_for_each(i, a, &f->rule->action) { 22147d4b564dSXiaoliang Yang switch (a->id) { 22157d4b564dSXiaoliang Yang case FLOW_ACTION_GATE: 221623ae3a78SXiaoliang Yang size = struct_size(sgi, entries, a->gate.num_entries); 221723ae3a78SXiaoliang Yang sgi = kzalloc(size, GFP_KERNEL); 2218866b7a27SZheng Yongjun if (!sgi) { 2219866b7a27SZheng Yongjun ret = -ENOMEM; 2220866b7a27SZheng Yongjun goto err; 2221866b7a27SZheng Yongjun } 222223ae3a78SXiaoliang Yang vsc9959_psfp_parse_gate(a, sgi); 222323ae3a78SXiaoliang Yang ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 222423ae3a78SXiaoliang Yang if (ret) { 222523ae3a78SXiaoliang Yang kfree(sgi); 222676c13edeSXiaoliang Yang goto err; 222723ae3a78SXiaoliang Yang } 222823ae3a78SXiaoliang Yang sfi.sg_valid = 1; 222923ae3a78SXiaoliang Yang sfi.sgid = sgi->index; 223023ae3a78SXiaoliang Yang kfree(sgi); 223123ae3a78SXiaoliang Yang break; 22327d4b564dSXiaoliang Yang case FLOW_ACTION_POLICE: 22335a995900SBaowen Zheng index = a->hw_index + VSC9959_PSFP_POLICER_BASE; 223476c13edeSXiaoliang Yang if (index > VSC9959_PSFP_POLICER_MAX) { 223576c13edeSXiaoliang Yang ret = -EINVAL; 223676c13edeSXiaoliang Yang goto err; 223776c13edeSXiaoliang Yang } 223876c13edeSXiaoliang Yang 223976c13edeSXiaoliang Yang rate = a->police.rate_bytes_ps; 224076c13edeSXiaoliang Yang burst = rate * PSCHED_NS2TICKS(a->police.burst); 224176c13edeSXiaoliang Yang pol = (struct ocelot_policer) { 224276c13edeSXiaoliang Yang .burst = div_u64(burst, PSCHED_TICKS_PER_SEC), 224376c13edeSXiaoliang Yang .rate = div_u64(rate, 1000) * 8, 224476c13edeSXiaoliang Yang }; 224576c13edeSXiaoliang Yang ret = ocelot_vcap_policer_add(ocelot, index, &pol); 224676c13edeSXiaoliang Yang if (ret) 224776c13edeSXiaoliang Yang goto err; 224876c13edeSXiaoliang Yang 224976c13edeSXiaoliang Yang sfi.fm_valid = 1; 225076c13edeSXiaoliang Yang sfi.fmid = index; 225176c13edeSXiaoliang Yang sfi.maxsdu = a->police.mtu; 225276c13edeSXiaoliang Yang break; 22537d4b564dSXiaoliang Yang default: 22547d4b564dSXiaoliang Yang return -EOPNOTSUPP; 22557d4b564dSXiaoliang Yang } 22567d4b564dSXiaoliang Yang } 22577d4b564dSXiaoliang Yang 2258a7e13edfSXiaoliang Yang stream.ports = BIT(port); 2259a7e13edfSXiaoliang Yang stream.port = port; 22607d4b564dSXiaoliang Yang 2261a7e13edfSXiaoliang Yang sfi.portmask = stream.ports; 22627d4b564dSXiaoliang Yang sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 22637d4b564dSXiaoliang Yang sfi.prio = (sfi.prio_valid ? stream.prio : 0); 22647d4b564dSXiaoliang Yang sfi.enable = 1; 22657d4b564dSXiaoliang Yang 2266a7e13edfSXiaoliang Yang /* Check if stream is set. */ 2267a7e13edfSXiaoliang Yang stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 2268a7e13edfSXiaoliang Yang if (stream_entry) { 2269a7e13edfSXiaoliang Yang if (stream_entry->ports & BIT(port)) { 2270a7e13edfSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, 2271a7e13edfSXiaoliang Yang "The stream is added on this port"); 2272a7e13edfSXiaoliang Yang ret = -EEXIST; 2273a7e13edfSXiaoliang Yang goto err; 2274a7e13edfSXiaoliang Yang } 2275a7e13edfSXiaoliang Yang 2276a7e13edfSXiaoliang Yang if (stream_entry->ports != BIT(stream_entry->port)) { 2277a7e13edfSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, 2278a7e13edfSXiaoliang Yang "The stream is added on two ports"); 2279a7e13edfSXiaoliang Yang ret = -EEXIST; 2280a7e13edfSXiaoliang Yang goto err; 2281a7e13edfSXiaoliang Yang } 2282a7e13edfSXiaoliang Yang 2283a7e13edfSXiaoliang Yang stream_entry->ports |= BIT(port); 2284a7e13edfSXiaoliang Yang stream.ports = stream_entry->ports; 2285a7e13edfSXiaoliang Yang 2286a7e13edfSXiaoliang Yang sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, 2287a7e13edfSXiaoliang Yang stream_entry->sfid); 2288a7e13edfSXiaoliang Yang memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); 2289a7e13edfSXiaoliang Yang 2290a7e13edfSXiaoliang Yang vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid); 2291a7e13edfSXiaoliang Yang 2292a7e13edfSXiaoliang Yang old_sfi.portmask = stream_entry->ports; 2293a7e13edfSXiaoliang Yang sfi.portmask = stream.ports; 2294a7e13edfSXiaoliang Yang 2295a7e13edfSXiaoliang Yang if (stream_entry->port > port) { 2296a7e13edfSXiaoliang Yang ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi, 2297a7e13edfSXiaoliang Yang &old_sfi); 2298a7e13edfSXiaoliang Yang stream_entry->dummy = true; 2299a7e13edfSXiaoliang Yang } else { 2300a7e13edfSXiaoliang Yang ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi, 2301a7e13edfSXiaoliang Yang &sfi); 2302a7e13edfSXiaoliang Yang stream.dummy = true; 2303a7e13edfSXiaoliang Yang } 2304a7e13edfSXiaoliang Yang if (ret) 2305a7e13edfSXiaoliang Yang goto err; 2306a7e13edfSXiaoliang Yang 2307a7e13edfSXiaoliang Yang stream_entry->sfid = old_sfi.index; 2308a7e13edfSXiaoliang Yang } else { 23097d4b564dSXiaoliang Yang ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 23107d4b564dSXiaoliang Yang if (ret) 231123ae3a78SXiaoliang Yang goto err; 2312a7e13edfSXiaoliang Yang } 23137d4b564dSXiaoliang Yang 23147d4b564dSXiaoliang Yang stream.sfid = sfi.index; 23157d4b564dSXiaoliang Yang stream.sfid_valid = 1; 23167d4b564dSXiaoliang Yang ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 23177d4b564dSXiaoliang Yang &stream, extack); 231823ae3a78SXiaoliang Yang if (ret) { 23197d4b564dSXiaoliang Yang vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 232023ae3a78SXiaoliang Yang goto err; 232123ae3a78SXiaoliang Yang } 232223ae3a78SXiaoliang Yang 232323ae3a78SXiaoliang Yang return 0; 232423ae3a78SXiaoliang Yang 232523ae3a78SXiaoliang Yang err: 232623ae3a78SXiaoliang Yang if (sfi.sg_valid) 232723ae3a78SXiaoliang Yang vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 23287d4b564dSXiaoliang Yang 232976c13edeSXiaoliang Yang if (sfi.fm_valid) 233076c13edeSXiaoliang Yang ocelot_vcap_policer_del(ocelot, sfi.fmid); 233176c13edeSXiaoliang Yang 23327d4b564dSXiaoliang Yang return ret; 23337d4b564dSXiaoliang Yang } 23347d4b564dSXiaoliang Yang 23357d4b564dSXiaoliang Yang static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 23367d4b564dSXiaoliang Yang struct flow_cls_offload *f) 23377d4b564dSXiaoliang Yang { 2338a7e13edfSXiaoliang Yang struct felix_stream *stream, tmp, *stream_entry; 233923ae3a78SXiaoliang Yang static struct felix_stream_filter *sfi; 23407d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 23417d4b564dSXiaoliang Yang 23427d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 23437d4b564dSXiaoliang Yang 23447d4b564dSXiaoliang Yang stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 23457d4b564dSXiaoliang Yang if (!stream) 23467d4b564dSXiaoliang Yang return -ENOMEM; 23477d4b564dSXiaoliang Yang 234823ae3a78SXiaoliang Yang sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 234923ae3a78SXiaoliang Yang if (!sfi) 235023ae3a78SXiaoliang Yang return -ENOMEM; 235123ae3a78SXiaoliang Yang 235223ae3a78SXiaoliang Yang if (sfi->sg_valid) 235323ae3a78SXiaoliang Yang vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 235423ae3a78SXiaoliang Yang 235576c13edeSXiaoliang Yang if (sfi->fm_valid) 235676c13edeSXiaoliang Yang ocelot_vcap_policer_del(ocelot, sfi->fmid); 235776c13edeSXiaoliang Yang 23587d4b564dSXiaoliang Yang vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 23597d4b564dSXiaoliang Yang 2360a7e13edfSXiaoliang Yang memcpy(&tmp, stream, sizeof(tmp)); 2361a7e13edfSXiaoliang Yang 23627d4b564dSXiaoliang Yang stream->sfid_valid = 0; 23637d4b564dSXiaoliang Yang vsc9959_stream_table_del(ocelot, stream); 23647d4b564dSXiaoliang Yang 2365a7e13edfSXiaoliang Yang stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp); 2366a7e13edfSXiaoliang Yang if (stream_entry) { 2367a7e13edfSXiaoliang Yang stream_entry->ports = BIT(stream_entry->port); 2368a7e13edfSXiaoliang Yang if (stream_entry->dummy) { 2369a7e13edfSXiaoliang Yang stream_entry->dummy = false; 2370a7e13edfSXiaoliang Yang vsc9959_mact_stream_set(ocelot, stream_entry, NULL); 2371a7e13edfSXiaoliang Yang } 2372a7e13edfSXiaoliang Yang vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid, 2373a7e13edfSXiaoliang Yang stream_entry->ports); 2374a7e13edfSXiaoliang Yang } 2375a7e13edfSXiaoliang Yang 23767d4b564dSXiaoliang Yang return 0; 23777d4b564dSXiaoliang Yang } 23787d4b564dSXiaoliang Yang 23797d4b564dSXiaoliang Yang static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 23807d4b564dSXiaoliang Yang struct flow_cls_offload *f, 23817d4b564dSXiaoliang Yang struct flow_stats *stats) 23827d4b564dSXiaoliang Yang { 23837d4b564dSXiaoliang Yang struct felix_stream_filter_counters counters; 23847d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 23857d4b564dSXiaoliang Yang struct felix_stream *stream; 23867d4b564dSXiaoliang Yang 23877d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 23887d4b564dSXiaoliang Yang stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 23897d4b564dSXiaoliang Yang if (!stream) 23907d4b564dSXiaoliang Yang return -ENOMEM; 23917d4b564dSXiaoliang Yang 23927d4b564dSXiaoliang Yang vsc9959_psfp_counters_get(ocelot, stream->sfid, &counters); 23937d4b564dSXiaoliang Yang 23947d4b564dSXiaoliang Yang stats->pkts = counters.match; 23957d4b564dSXiaoliang Yang stats->drops = counters.not_pass_gate + counters.not_pass_sdu + 23967d4b564dSXiaoliang Yang counters.red; 23977d4b564dSXiaoliang Yang 23987d4b564dSXiaoliang Yang return 0; 23997d4b564dSXiaoliang Yang } 24007d4b564dSXiaoliang Yang 24017d4b564dSXiaoliang Yang static void vsc9959_psfp_init(struct ocelot *ocelot) 24027d4b564dSXiaoliang Yang { 24037d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp = &ocelot->psfp; 24047d4b564dSXiaoliang Yang 24057d4b564dSXiaoliang Yang INIT_LIST_HEAD(&psfp->stream_list); 24067d4b564dSXiaoliang Yang INIT_LIST_HEAD(&psfp->sfi_list); 24077d4b564dSXiaoliang Yang INIT_LIST_HEAD(&psfp->sgi_list); 24087d4b564dSXiaoliang Yang } 24097d4b564dSXiaoliang Yang 24108abe1970SVladimir Oltean /* When using cut-through forwarding and the egress port runs at a higher data 24118abe1970SVladimir Oltean * rate than the ingress port, the packet currently under transmission would 24128abe1970SVladimir Oltean * suffer an underrun since it would be transmitted faster than it is received. 24138abe1970SVladimir Oltean * The Felix switch implementation of cut-through forwarding does not check in 24148abe1970SVladimir Oltean * hardware whether this condition is satisfied or not, so we must restrict the 24158abe1970SVladimir Oltean * list of ports that have cut-through forwarding enabled on egress to only be 24168abe1970SVladimir Oltean * the ports operating at the lowest link speed within their respective 24178abe1970SVladimir Oltean * forwarding domain. 24188abe1970SVladimir Oltean */ 24198abe1970SVladimir Oltean static void vsc9959_cut_through_fwd(struct ocelot *ocelot) 24208abe1970SVladimir Oltean { 24218abe1970SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 24228abe1970SVladimir Oltean struct dsa_switch *ds = felix->ds; 24238abe1970SVladimir Oltean int port, other_port; 24248abe1970SVladimir Oltean 24258abe1970SVladimir Oltean lockdep_assert_held(&ocelot->fwd_domain_lock); 24268abe1970SVladimir Oltean 24278abe1970SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) { 24288abe1970SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 24298abe1970SVladimir Oltean int min_speed = ocelot_port->speed; 24308abe1970SVladimir Oltean unsigned long mask = 0; 24318abe1970SVladimir Oltean u32 tmp, val = 0; 24328abe1970SVladimir Oltean 24338abe1970SVladimir Oltean /* Disable cut-through on ports that are down */ 24348abe1970SVladimir Oltean if (ocelot_port->speed <= 0) 24358abe1970SVladimir Oltean goto set; 24368abe1970SVladimir Oltean 24378abe1970SVladimir Oltean if (dsa_is_cpu_port(ds, port)) { 24388abe1970SVladimir Oltean /* Ocelot switches forward from the NPI port towards 24398abe1970SVladimir Oltean * any port, regardless of it being in the NPI port's 24408abe1970SVladimir Oltean * forwarding domain or not. 24418abe1970SVladimir Oltean */ 24428abe1970SVladimir Oltean mask = dsa_user_ports(ds); 24438abe1970SVladimir Oltean } else { 24448abe1970SVladimir Oltean mask = ocelot_get_bridge_fwd_mask(ocelot, port); 24458abe1970SVladimir Oltean mask &= ~BIT(port); 24468abe1970SVladimir Oltean if (ocelot->npi >= 0) 24478abe1970SVladimir Oltean mask |= BIT(ocelot->npi); 24488abe1970SVladimir Oltean else 2449c295f983SVladimir Oltean mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 2450c295f983SVladimir Oltean port); 24518abe1970SVladimir Oltean } 24528abe1970SVladimir Oltean 24538abe1970SVladimir Oltean /* Calculate the minimum link speed, among the ports that are 24548abe1970SVladimir Oltean * up, of this source port's forwarding domain. 24558abe1970SVladimir Oltean */ 24568abe1970SVladimir Oltean for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { 24578abe1970SVladimir Oltean struct ocelot_port *other_ocelot_port; 24588abe1970SVladimir Oltean 24598abe1970SVladimir Oltean other_ocelot_port = ocelot->ports[other_port]; 24608abe1970SVladimir Oltean if (other_ocelot_port->speed <= 0) 24618abe1970SVladimir Oltean continue; 24628abe1970SVladimir Oltean 24638abe1970SVladimir Oltean if (min_speed > other_ocelot_port->speed) 24648abe1970SVladimir Oltean min_speed = other_ocelot_port->speed; 24658abe1970SVladimir Oltean } 24668abe1970SVladimir Oltean 24678abe1970SVladimir Oltean /* Enable cut-through forwarding for all traffic classes. */ 24688abe1970SVladimir Oltean if (ocelot_port->speed == min_speed) 24698abe1970SVladimir Oltean val = GENMASK(7, 0); 24708abe1970SVladimir Oltean 24718abe1970SVladimir Oltean set: 24728abe1970SVladimir Oltean tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); 24738abe1970SVladimir Oltean if (tmp == val) 24748abe1970SVladimir Oltean continue; 24758abe1970SVladimir Oltean 24768abe1970SVladimir Oltean dev_dbg(ocelot->dev, 24778abe1970SVladimir Oltean "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding\n", 24788abe1970SVladimir Oltean port, mask, ocelot_port->speed, min_speed, 24798abe1970SVladimir Oltean val ? "enabling" : "disabling"); 24808abe1970SVladimir Oltean 24818abe1970SVladimir Oltean ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); 24828abe1970SVladimir Oltean } 24838abe1970SVladimir Oltean } 24848abe1970SVladimir Oltean 24857d4b564dSXiaoliang Yang static const struct ocelot_ops vsc9959_ops = { 24867d4b564dSXiaoliang Yang .reset = vsc9959_reset, 24877d4b564dSXiaoliang Yang .wm_enc = vsc9959_wm_enc, 24887d4b564dSXiaoliang Yang .wm_dec = vsc9959_wm_dec, 24897d4b564dSXiaoliang Yang .wm_stat = vsc9959_wm_stat, 24907d4b564dSXiaoliang Yang .port_to_netdev = felix_port_to_netdev, 24917d4b564dSXiaoliang Yang .netdev_to_port = felix_netdev_to_port, 24927d4b564dSXiaoliang Yang .psfp_init = vsc9959_psfp_init, 24937d4b564dSXiaoliang Yang .psfp_filter_add = vsc9959_psfp_filter_add, 24947d4b564dSXiaoliang Yang .psfp_filter_del = vsc9959_psfp_filter_del, 24957d4b564dSXiaoliang Yang .psfp_stats_get = vsc9959_psfp_stats_get, 24968abe1970SVladimir Oltean .cut_through_fwd = vsc9959_cut_through_fwd, 24978670dc33SXiaoliang Yang .tas_clock_adjust = vsc9959_tas_clock_adjust, 24987d4b564dSXiaoliang Yang }; 24997d4b564dSXiaoliang Yang 2500375e1314SVladimir Oltean static const struct felix_info felix_info_vsc9959 = { 250156051948SVladimir Oltean .target_io_res = vsc9959_target_io_res, 250256051948SVladimir Oltean .port_io_res = vsc9959_port_io_res, 2503bdeced75SVladimir Oltean .imdio_res = &vsc9959_imdio_res, 250456051948SVladimir Oltean .regfields = vsc9959_regfields, 250556051948SVladimir Oltean .map = vsc9959_regmap, 250656051948SVladimir Oltean .ops = &vsc9959_ops, 250756051948SVladimir Oltean .stats_layout = vsc9959_stats_layout, 250807d985eeSVladimir Oltean .vcap = vsc9959_vcap_props, 250977043c37SXiaoliang Yang .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 251077043c37SXiaoliang Yang .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 251177043c37SXiaoliang Yang .vcap_pol_base2 = 0, 251277043c37SXiaoliang Yang .vcap_pol_max2 = 0, 251321ce7f3eSVladimir Oltean .num_mact_rows = 2048, 2514acf242fcSColin Foster .num_ports = VSC9959_NUM_PORTS, 251570d39a6eSVladimir Oltean .num_tx_queues = OCELOT_NUM_TC, 2516c8c0ba4fSVladimir Oltean .quirk_no_xtr_irq = true, 25172ac7c6c5SVladimir Oltean .ptp_caps = &vsc9959_ptp_caps, 2518bdeced75SVladimir Oltean .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2519bdeced75SVladimir Oltean .mdio_bus_free = vsc9959_mdio_bus_free, 2520375e1314SVladimir Oltean .phylink_validate = vsc9959_phylink_validate, 2521acf242fcSColin Foster .port_modes = vsc9959_port_modes, 2522de143c0eSXiaoliang Yang .port_setup_tc = vsc9959_port_setup_tc, 2523de143c0eSXiaoliang Yang .port_sched_speed_set = vsc9959_sched_speed_set, 252455a515b1SVladimir Oltean .tas_guard_bands_update = vsc9959_tas_guard_bands_update, 2525242bd0c1SColin Foster .init_regmap = ocelot_regmap_init, 252656051948SVladimir Oltean }; 2527375e1314SVladimir Oltean 2528375e1314SVladimir Oltean static irqreturn_t felix_irq_handler(int irq, void *data) 2529375e1314SVladimir Oltean { 2530375e1314SVladimir Oltean struct ocelot *ocelot = (struct ocelot *)data; 2531375e1314SVladimir Oltean 2532375e1314SVladimir Oltean /* The INTB interrupt is used for both PTP TX timestamp interrupt 2533375e1314SVladimir Oltean * and preemption status change interrupt on each port. 2534375e1314SVladimir Oltean * 2535375e1314SVladimir Oltean * - Get txtstamp if have 2536375e1314SVladimir Oltean * - TODO: handle preemption. Without handling it, driver may get 2537375e1314SVladimir Oltean * interrupt storm. 2538375e1314SVladimir Oltean */ 2539375e1314SVladimir Oltean 2540375e1314SVladimir Oltean ocelot_get_txtstamp(ocelot); 2541375e1314SVladimir Oltean 2542375e1314SVladimir Oltean return IRQ_HANDLED; 2543375e1314SVladimir Oltean } 2544375e1314SVladimir Oltean 2545375e1314SVladimir Oltean static int felix_pci_probe(struct pci_dev *pdev, 2546375e1314SVladimir Oltean const struct pci_device_id *id) 2547375e1314SVladimir Oltean { 2548375e1314SVladimir Oltean struct dsa_switch *ds; 2549375e1314SVladimir Oltean struct ocelot *ocelot; 2550375e1314SVladimir Oltean struct felix *felix; 2551375e1314SVladimir Oltean int err; 2552375e1314SVladimir Oltean 2553375e1314SVladimir Oltean if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 2554375e1314SVladimir Oltean dev_info(&pdev->dev, "device is disabled, skipping\n"); 2555375e1314SVladimir Oltean return -ENODEV; 2556375e1314SVladimir Oltean } 2557375e1314SVladimir Oltean 2558375e1314SVladimir Oltean err = pci_enable_device(pdev); 2559375e1314SVladimir Oltean if (err) { 2560375e1314SVladimir Oltean dev_err(&pdev->dev, "device enable failed\n"); 2561375e1314SVladimir Oltean goto err_pci_enable; 2562375e1314SVladimir Oltean } 2563375e1314SVladimir Oltean 2564375e1314SVladimir Oltean felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 2565375e1314SVladimir Oltean if (!felix) { 2566375e1314SVladimir Oltean err = -ENOMEM; 2567375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 2568375e1314SVladimir Oltean goto err_alloc_felix; 2569375e1314SVladimir Oltean } 2570375e1314SVladimir Oltean 2571375e1314SVladimir Oltean pci_set_drvdata(pdev, felix); 2572375e1314SVladimir Oltean ocelot = &felix->ocelot; 2573375e1314SVladimir Oltean ocelot->dev = &pdev->dev; 257470d39a6eSVladimir Oltean ocelot->num_flooding_pgids = OCELOT_NUM_TC; 2575375e1314SVladimir Oltean felix->info = &felix_info_vsc9959; 2576c9910484SColin Foster felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); 2577c9910484SColin Foster felix->imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); 2578375e1314SVladimir Oltean 2579375e1314SVladimir Oltean pci_set_master(pdev); 2580375e1314SVladimir Oltean 2581375e1314SVladimir Oltean err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 2582375e1314SVladimir Oltean &felix_irq_handler, IRQF_ONESHOT, 2583375e1314SVladimir Oltean "felix-intb", ocelot); 2584375e1314SVladimir Oltean if (err) { 2585375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to request irq\n"); 2586375e1314SVladimir Oltean goto err_alloc_irq; 2587375e1314SVladimir Oltean } 2588375e1314SVladimir Oltean 2589375e1314SVladimir Oltean ocelot->ptp = 1; 2590375e1314SVladimir Oltean 2591375e1314SVladimir Oltean ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 2592375e1314SVladimir Oltean if (!ds) { 2593375e1314SVladimir Oltean err = -ENOMEM; 2594375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 2595375e1314SVladimir Oltean goto err_alloc_ds; 2596375e1314SVladimir Oltean } 2597375e1314SVladimir Oltean 2598375e1314SVladimir Oltean ds->dev = &pdev->dev; 2599375e1314SVladimir Oltean ds->num_ports = felix->info->num_ports; 2600375e1314SVladimir Oltean ds->num_tx_queues = felix->info->num_tx_queues; 2601375e1314SVladimir Oltean ds->ops = &felix_switch_ops; 2602375e1314SVladimir Oltean ds->priv = ocelot; 2603375e1314SVladimir Oltean felix->ds = ds; 2604adb3dccfSVladimir Oltean felix->tag_proto = DSA_TAG_PROTO_OCELOT; 2605375e1314SVladimir Oltean 2606375e1314SVladimir Oltean err = dsa_register_switch(ds); 2607375e1314SVladimir Oltean if (err) { 2608e6934e40SMichael Walle dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n"); 2609375e1314SVladimir Oltean goto err_register_ds; 2610375e1314SVladimir Oltean } 2611375e1314SVladimir Oltean 2612375e1314SVladimir Oltean return 0; 2613375e1314SVladimir Oltean 2614375e1314SVladimir Oltean err_register_ds: 2615375e1314SVladimir Oltean kfree(ds); 2616375e1314SVladimir Oltean err_alloc_ds: 2617375e1314SVladimir Oltean err_alloc_irq: 2618375e1314SVladimir Oltean kfree(felix); 2619537e2b88SVladimir Oltean err_alloc_felix: 2620375e1314SVladimir Oltean pci_disable_device(pdev); 2621375e1314SVladimir Oltean err_pci_enable: 2622375e1314SVladimir Oltean return err; 2623375e1314SVladimir Oltean } 2624375e1314SVladimir Oltean 2625375e1314SVladimir Oltean static void felix_pci_remove(struct pci_dev *pdev) 2626375e1314SVladimir Oltean { 26270650bf52SVladimir Oltean struct felix *felix = pci_get_drvdata(pdev); 2628375e1314SVladimir Oltean 26290650bf52SVladimir Oltean if (!felix) 26300650bf52SVladimir Oltean return; 2631375e1314SVladimir Oltean 2632375e1314SVladimir Oltean dsa_unregister_switch(felix->ds); 2633375e1314SVladimir Oltean 2634375e1314SVladimir Oltean kfree(felix->ds); 2635375e1314SVladimir Oltean kfree(felix); 2636375e1314SVladimir Oltean 2637375e1314SVladimir Oltean pci_disable_device(pdev); 26380650bf52SVladimir Oltean 26390650bf52SVladimir Oltean pci_set_drvdata(pdev, NULL); 26400650bf52SVladimir Oltean } 26410650bf52SVladimir Oltean 26420650bf52SVladimir Oltean static void felix_pci_shutdown(struct pci_dev *pdev) 26430650bf52SVladimir Oltean { 26440650bf52SVladimir Oltean struct felix *felix = pci_get_drvdata(pdev); 26450650bf52SVladimir Oltean 26460650bf52SVladimir Oltean if (!felix) 26470650bf52SVladimir Oltean return; 26480650bf52SVladimir Oltean 26490650bf52SVladimir Oltean dsa_switch_shutdown(felix->ds); 26500650bf52SVladimir Oltean 26510650bf52SVladimir Oltean pci_set_drvdata(pdev, NULL); 2652375e1314SVladimir Oltean } 2653375e1314SVladimir Oltean 2654375e1314SVladimir Oltean static struct pci_device_id felix_ids[] = { 2655375e1314SVladimir Oltean { 2656375e1314SVladimir Oltean /* NXP LS1028A */ 2657375e1314SVladimir Oltean PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 2658375e1314SVladimir Oltean }, 2659375e1314SVladimir Oltean { 0, } 2660375e1314SVladimir Oltean }; 2661375e1314SVladimir Oltean MODULE_DEVICE_TABLE(pci, felix_ids); 2662375e1314SVladimir Oltean 2663d60bc62dSVladimir Oltean static struct pci_driver felix_vsc9959_pci_driver = { 2664375e1314SVladimir Oltean .name = "mscc_felix", 2665375e1314SVladimir Oltean .id_table = felix_ids, 2666375e1314SVladimir Oltean .probe = felix_pci_probe, 2667375e1314SVladimir Oltean .remove = felix_pci_remove, 26680650bf52SVladimir Oltean .shutdown = felix_pci_shutdown, 2669375e1314SVladimir Oltean }; 2670d60bc62dSVladimir Oltean module_pci_driver(felix_vsc9959_pci_driver); 2671d60bc62dSVladimir Oltean 2672d60bc62dSVladimir Oltean MODULE_DESCRIPTION("Felix Switch driver"); 2673d60bc62dSVladimir Oltean MODULE_LICENSE("GPL v2"); 2674