156051948SVladimir Oltean // SPDX-License-Identifier: (GPL-2.0 OR MIT) 256051948SVladimir Oltean /* Copyright 2017 Microsemi Corporation 33c9cfb52SVladimir Oltean * Copyright 2018-2019 NXP 456051948SVladimir Oltean */ 5bdeced75SVladimir Oltean #include <linux/fsl/enetc_mdio.h> 6de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_qsys.h> 707d985eeSVladimir Oltean #include <soc/mscc/ocelot_vcap.h> 87d4b564dSXiaoliang Yang #include <soc/mscc/ocelot_ana.h> 9de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_ptp.h> 1056051948SVladimir Oltean #include <soc/mscc/ocelot_sys.h> 1123ae3a78SXiaoliang Yang #include <net/tc_act/tc_gate.h> 1256051948SVladimir Oltean #include <soc/mscc/ocelot.h> 1340d3f295SVladimir Oltean #include <linux/dsa/ocelot.h> 14588d0550SIoana Ciornei #include <linux/pcs-lynx.h> 15de143c0eSXiaoliang Yang #include <net/pkt_sched.h> 1656051948SVladimir Oltean #include <linux/iopoll.h> 1716659b81SMichael Walle #include <linux/mdio.h> 1856051948SVladimir Oltean #include <linux/pci.h> 1956051948SVladimir Oltean #include "felix.h" 2056051948SVladimir Oltean 21de143c0eSXiaoliang Yang #define VSC9959_TAS_GCL_ENTRY_MAX 63 22*77043c37SXiaoliang Yang #define VSC9959_VCAP_POLICER_BASE 63 23*77043c37SXiaoliang Yang #define VSC9959_VCAP_POLICER_MAX 383 24de143c0eSXiaoliang Yang 2556051948SVladimir Oltean static const u32 vsc9959_ana_regmap[] = { 2656051948SVladimir Oltean REG(ANA_ADVLEARN, 0x0089a0), 2756051948SVladimir Oltean REG(ANA_VLANMASK, 0x0089a4), 2856051948SVladimir Oltean REG_RESERVED(ANA_PORT_B_DOMAIN), 2956051948SVladimir Oltean REG(ANA_ANAGEFIL, 0x0089ac), 3056051948SVladimir Oltean REG(ANA_ANEVENTS, 0x0089b0), 3156051948SVladimir Oltean REG(ANA_STORMLIMIT_BURST, 0x0089b4), 3256051948SVladimir Oltean REG(ANA_STORMLIMIT_CFG, 0x0089b8), 3356051948SVladimir Oltean REG(ANA_ISOLATED_PORTS, 0x0089c8), 3456051948SVladimir Oltean REG(ANA_COMMUNITY_PORTS, 0x0089cc), 3556051948SVladimir Oltean REG(ANA_AUTOAGE, 0x0089d0), 3656051948SVladimir Oltean REG(ANA_MACTOPTIONS, 0x0089d4), 3756051948SVladimir Oltean REG(ANA_LEARNDISC, 0x0089d8), 3856051948SVladimir Oltean REG(ANA_AGENCTRL, 0x0089dc), 3956051948SVladimir Oltean REG(ANA_MIRRORPORTS, 0x0089e0), 4056051948SVladimir Oltean REG(ANA_EMIRRORPORTS, 0x0089e4), 4156051948SVladimir Oltean REG(ANA_FLOODING, 0x0089e8), 4256051948SVladimir Oltean REG(ANA_FLOODING_IPMC, 0x008a08), 4356051948SVladimir Oltean REG(ANA_SFLOW_CFG, 0x008a0c), 4456051948SVladimir Oltean REG(ANA_PORT_MODE, 0x008a28), 4556051948SVladimir Oltean REG(ANA_CUT_THRU_CFG, 0x008a48), 4656051948SVladimir Oltean REG(ANA_PGID_PGID, 0x008400), 4756051948SVladimir Oltean REG(ANA_TABLES_ANMOVED, 0x007f1c), 4856051948SVladimir Oltean REG(ANA_TABLES_MACHDATA, 0x007f20), 4956051948SVladimir Oltean REG(ANA_TABLES_MACLDATA, 0x007f24), 5056051948SVladimir Oltean REG(ANA_TABLES_STREAMDATA, 0x007f28), 5156051948SVladimir Oltean REG(ANA_TABLES_MACACCESS, 0x007f2c), 5256051948SVladimir Oltean REG(ANA_TABLES_MACTINDX, 0x007f30), 5356051948SVladimir Oltean REG(ANA_TABLES_VLANACCESS, 0x007f34), 5456051948SVladimir Oltean REG(ANA_TABLES_VLANTIDX, 0x007f38), 5556051948SVladimir Oltean REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 5656051948SVladimir Oltean REG(ANA_TABLES_ISDXTIDX, 0x007f40), 5756051948SVladimir Oltean REG(ANA_TABLES_ENTRYLIM, 0x007f00), 5856051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 5956051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 6056051948SVladimir Oltean REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 6156051948SVladimir Oltean REG(ANA_TABLES_STREAMTIDX, 0x007f50), 6256051948SVladimir Oltean REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 6356051948SVladimir Oltean REG(ANA_TABLES_SEQ_MASK, 0x007f58), 6456051948SVladimir Oltean REG(ANA_TABLES_SFID_MASK, 0x007f5c), 6556051948SVladimir Oltean REG(ANA_TABLES_SFIDACCESS, 0x007f60), 6656051948SVladimir Oltean REG(ANA_TABLES_SFIDTIDX, 0x007f64), 6756051948SVladimir Oltean REG(ANA_MSTI_STATE, 0x008600), 6856051948SVladimir Oltean REG(ANA_OAM_UPM_LM_CNT, 0x008000), 6956051948SVladimir Oltean REG(ANA_SG_ACCESS_CTRL, 0x008a64), 7056051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 7156051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 7256051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 7356051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 7456051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 7556051948SVladimir Oltean REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 7656051948SVladimir Oltean REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 7756051948SVladimir Oltean REG(ANA_SG_STATUS_REG_1, 0x008980), 7856051948SVladimir Oltean REG(ANA_SG_STATUS_REG_2, 0x008984), 7956051948SVladimir Oltean REG(ANA_SG_STATUS_REG_3, 0x008988), 8056051948SVladimir Oltean REG(ANA_PORT_VLAN_CFG, 0x007800), 8156051948SVladimir Oltean REG(ANA_PORT_DROP_CFG, 0x007804), 8256051948SVladimir Oltean REG(ANA_PORT_QOS_CFG, 0x007808), 8356051948SVladimir Oltean REG(ANA_PORT_VCAP_CFG, 0x00780c), 8456051948SVladimir Oltean REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 8556051948SVladimir Oltean REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 8656051948SVladimir Oltean REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 8756051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 8856051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 8956051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 9056051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 9156051948SVladimir Oltean REG(ANA_PORT_PORT_CFG, 0x007870), 9256051948SVladimir Oltean REG(ANA_PORT_POL_CFG, 0x007874), 9356051948SVladimir Oltean REG(ANA_PORT_PTP_CFG, 0x007878), 9456051948SVladimir Oltean REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 9556051948SVladimir Oltean REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 9656051948SVladimir Oltean REG(ANA_PORT_SFID_CFG, 0x007884), 9756051948SVladimir Oltean REG(ANA_PFC_PFC_CFG, 0x008800), 9856051948SVladimir Oltean REG_RESERVED(ANA_PFC_PFC_TIMER), 9956051948SVladimir Oltean REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 10056051948SVladimir Oltean REG_RESERVED(ANA_IPT_IPT), 10156051948SVladimir Oltean REG_RESERVED(ANA_PPT_PPT), 10256051948SVladimir Oltean REG_RESERVED(ANA_FID_MAP_FID_MAP), 10356051948SVladimir Oltean REG(ANA_AGGR_CFG, 0x008a68), 10456051948SVladimir Oltean REG(ANA_CPUQ_CFG, 0x008a6c), 10556051948SVladimir Oltean REG_RESERVED(ANA_CPUQ_CFG2), 10656051948SVladimir Oltean REG(ANA_CPUQ_8021_CFG, 0x008a74), 10756051948SVladimir Oltean REG(ANA_DSCP_CFG, 0x008ab4), 10856051948SVladimir Oltean REG(ANA_DSCP_REWR_CFG, 0x008bb4), 10956051948SVladimir Oltean REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 11056051948SVladimir Oltean REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 11156051948SVladimir Oltean REG_RESERVED(ANA_VRAP_CFG), 11256051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_DATA), 11356051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_MASK), 11456051948SVladimir Oltean REG(ANA_DISCARD_CFG, 0x008c40), 11556051948SVladimir Oltean REG(ANA_FID_CFG, 0x008c44), 11656051948SVladimir Oltean REG(ANA_POL_PIR_CFG, 0x004000), 11756051948SVladimir Oltean REG(ANA_POL_CIR_CFG, 0x004004), 11856051948SVladimir Oltean REG(ANA_POL_MODE_CFG, 0x004008), 11956051948SVladimir Oltean REG(ANA_POL_PIR_STATE, 0x00400c), 12056051948SVladimir Oltean REG(ANA_POL_CIR_STATE, 0x004010), 12156051948SVladimir Oltean REG_RESERVED(ANA_POL_STATE), 12256051948SVladimir Oltean REG(ANA_POL_FLOWC, 0x008c48), 12356051948SVladimir Oltean REG(ANA_POL_HYST, 0x008cb4), 12456051948SVladimir Oltean REG_RESERVED(ANA_POL_MISC_CFG), 12556051948SVladimir Oltean }; 12656051948SVladimir Oltean 12756051948SVladimir Oltean static const u32 vsc9959_qs_regmap[] = { 12856051948SVladimir Oltean REG(QS_XTR_GRP_CFG, 0x000000), 12956051948SVladimir Oltean REG(QS_XTR_RD, 0x000008), 13056051948SVladimir Oltean REG(QS_XTR_FRM_PRUNING, 0x000010), 13156051948SVladimir Oltean REG(QS_XTR_FLUSH, 0x000018), 13256051948SVladimir Oltean REG(QS_XTR_DATA_PRESENT, 0x00001c), 13356051948SVladimir Oltean REG(QS_XTR_CFG, 0x000020), 13456051948SVladimir Oltean REG(QS_INJ_GRP_CFG, 0x000024), 13556051948SVladimir Oltean REG(QS_INJ_WR, 0x00002c), 13656051948SVladimir Oltean REG(QS_INJ_CTRL, 0x000034), 13756051948SVladimir Oltean REG(QS_INJ_STATUS, 0x00003c), 13856051948SVladimir Oltean REG(QS_INJ_ERR, 0x000040), 13956051948SVladimir Oltean REG_RESERVED(QS_INH_DBG), 14056051948SVladimir Oltean }; 14156051948SVladimir Oltean 142c1c3993eSVladimir Oltean static const u32 vsc9959_vcap_regmap[] = { 143c1c3993eSVladimir Oltean /* VCAP_CORE_CFG */ 144c1c3993eSVladimir Oltean REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 145c1c3993eSVladimir Oltean REG(VCAP_CORE_MV_CFG, 0x000004), 146c1c3993eSVladimir Oltean /* VCAP_CORE_CACHE */ 147c1c3993eSVladimir Oltean REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 148c1c3993eSVladimir Oltean REG(VCAP_CACHE_MASK_DAT, 0x000108), 149c1c3993eSVladimir Oltean REG(VCAP_CACHE_ACTION_DAT, 0x000208), 150c1c3993eSVladimir Oltean REG(VCAP_CACHE_CNT_DAT, 0x000308), 151c1c3993eSVladimir Oltean REG(VCAP_CACHE_TG_DAT, 0x000388), 15220968054SVladimir Oltean /* VCAP_CONST */ 15320968054SVladimir Oltean REG(VCAP_CONST_VCAP_VER, 0x000398), 15420968054SVladimir Oltean REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 15520968054SVladimir Oltean REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 15620968054SVladimir Oltean REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 15720968054SVladimir Oltean REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 15820968054SVladimir Oltean REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 15920968054SVladimir Oltean REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 16020968054SVladimir Oltean REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 16120968054SVladimir Oltean REG(VCAP_CONST_CORE_CNT, 0x0003b8), 16220968054SVladimir Oltean REG(VCAP_CONST_IF_CNT, 0x0003bc), 16356051948SVladimir Oltean }; 16456051948SVladimir Oltean 16556051948SVladimir Oltean static const u32 vsc9959_qsys_regmap[] = { 16656051948SVladimir Oltean REG(QSYS_PORT_MODE, 0x00f460), 16756051948SVladimir Oltean REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 16856051948SVladimir Oltean REG(QSYS_STAT_CNT_CFG, 0x00f49c), 16956051948SVladimir Oltean REG(QSYS_EEE_CFG, 0x00f4a0), 17056051948SVladimir Oltean REG(QSYS_EEE_THRES, 0x00f4b8), 17156051948SVladimir Oltean REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 17256051948SVladimir Oltean REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 17356051948SVladimir Oltean REG(QSYS_SW_STATUS, 0x00f4c4), 17456051948SVladimir Oltean REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 17556051948SVladimir Oltean REG_RESERVED(QSYS_PAD_CFG), 17656051948SVladimir Oltean REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 17756051948SVladimir Oltean REG_RESERVED(QSYS_QMAP), 17856051948SVladimir Oltean REG_RESERVED(QSYS_ISDX_SGRP), 17956051948SVladimir Oltean REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 18056051948SVladimir Oltean REG(QSYS_TFRM_MISC, 0x00f50c), 18156051948SVladimir Oltean REG(QSYS_TFRM_PORT_DLY, 0x00f510), 18256051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 18356051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 18456051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 18556051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 18656051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 18756051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 18856051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 18956051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 19056051948SVladimir Oltean REG(QSYS_RED_PROFILE, 0x00f534), 19156051948SVladimir Oltean REG(QSYS_RES_QOS_MODE, 0x00f574), 19256051948SVladimir Oltean REG(QSYS_RES_CFG, 0x00c000), 19356051948SVladimir Oltean REG(QSYS_RES_STAT, 0x00c004), 19456051948SVladimir Oltean REG(QSYS_EGR_DROP_MODE, 0x00f578), 19556051948SVladimir Oltean REG(QSYS_EQ_CTRL, 0x00f57c), 19656051948SVladimir Oltean REG_RESERVED(QSYS_EVENTS_CORE), 19756051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 19856051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 19956051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 20056051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 20156051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 20256051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 20356051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 20456051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 20556051948SVladimir Oltean REG(QSYS_PREEMPTION_CFG, 0x00f664), 2060fbabf87SXiaoliang Yang REG(QSYS_CIR_CFG, 0x000000), 20756051948SVladimir Oltean REG(QSYS_EIR_CFG, 0x000004), 20856051948SVladimir Oltean REG(QSYS_SE_CFG, 0x000008), 20956051948SVladimir Oltean REG(QSYS_SE_DWRR_CFG, 0x00000c), 21056051948SVladimir Oltean REG_RESERVED(QSYS_SE_CONNECT), 21156051948SVladimir Oltean REG(QSYS_SE_DLB_SENSE, 0x000040), 21256051948SVladimir Oltean REG(QSYS_CIR_STATE, 0x000044), 21356051948SVladimir Oltean REG(QSYS_EIR_STATE, 0x000048), 21456051948SVladimir Oltean REG_RESERVED(QSYS_SE_STATE), 21556051948SVladimir Oltean REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 21656051948SVladimir Oltean REG(QSYS_TAG_CONFIG, 0x00f680), 21756051948SVladimir Oltean REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 21856051948SVladimir Oltean REG(QSYS_PORT_MAX_SDU, 0x00f69c), 21956051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 22056051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 22156051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 22256051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 22356051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 22456051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_1, 0x00f454), 22556051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_2, 0x00f458), 22656051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 22756051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 22856051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 22956051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 23056051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 23156051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 23256051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 23356051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 23456051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 23556051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 23656051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 23756051948SVladimir Oltean }; 23856051948SVladimir Oltean 23956051948SVladimir Oltean static const u32 vsc9959_rew_regmap[] = { 24056051948SVladimir Oltean REG(REW_PORT_VLAN_CFG, 0x000000), 24156051948SVladimir Oltean REG(REW_TAG_CFG, 0x000004), 24256051948SVladimir Oltean REG(REW_PORT_CFG, 0x000008), 24356051948SVladimir Oltean REG(REW_DSCP_CFG, 0x00000c), 24456051948SVladimir Oltean REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 24556051948SVladimir Oltean REG(REW_PTP_CFG, 0x000050), 24656051948SVladimir Oltean REG(REW_PTP_DLY1_CFG, 0x000054), 24756051948SVladimir Oltean REG(REW_RED_TAG_CFG, 0x000058), 24856051948SVladimir Oltean REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 24956051948SVladimir Oltean REG(REW_DSCP_REMAP_CFG, 0x000510), 25056051948SVladimir Oltean REG_RESERVED(REW_STAT_CFG), 25156051948SVladimir Oltean REG_RESERVED(REW_REW_STICKY), 25256051948SVladimir Oltean REG_RESERVED(REW_PPT), 25356051948SVladimir Oltean }; 25456051948SVladimir Oltean 25556051948SVladimir Oltean static const u32 vsc9959_sys_regmap[] = { 25656051948SVladimir Oltean REG(SYS_COUNT_RX_OCTETS, 0x000000), 25756051948SVladimir Oltean REG(SYS_COUNT_RX_MULTICAST, 0x000008), 25856051948SVladimir Oltean REG(SYS_COUNT_RX_SHORTS, 0x000010), 25956051948SVladimir Oltean REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 26056051948SVladimir Oltean REG(SYS_COUNT_RX_JABBERS, 0x000018), 26156051948SVladimir Oltean REG(SYS_COUNT_RX_64, 0x000024), 26256051948SVladimir Oltean REG(SYS_COUNT_RX_65_127, 0x000028), 26356051948SVladimir Oltean REG(SYS_COUNT_RX_128_255, 0x00002c), 26456051948SVladimir Oltean REG(SYS_COUNT_RX_256_1023, 0x000030), 26556051948SVladimir Oltean REG(SYS_COUNT_RX_1024_1526, 0x000034), 26656051948SVladimir Oltean REG(SYS_COUNT_RX_1527_MAX, 0x000038), 26756051948SVladimir Oltean REG(SYS_COUNT_RX_LONGS, 0x000044), 26856051948SVladimir Oltean REG(SYS_COUNT_TX_OCTETS, 0x000200), 26956051948SVladimir Oltean REG(SYS_COUNT_TX_COLLISION, 0x000210), 27056051948SVladimir Oltean REG(SYS_COUNT_TX_DROPS, 0x000214), 27156051948SVladimir Oltean REG(SYS_COUNT_TX_64, 0x00021c), 27256051948SVladimir Oltean REG(SYS_COUNT_TX_65_127, 0x000220), 27356051948SVladimir Oltean REG(SYS_COUNT_TX_128_511, 0x000224), 27456051948SVladimir Oltean REG(SYS_COUNT_TX_512_1023, 0x000228), 27556051948SVladimir Oltean REG(SYS_COUNT_TX_1024_1526, 0x00022c), 27656051948SVladimir Oltean REG(SYS_COUNT_TX_1527_MAX, 0x000230), 27756051948SVladimir Oltean REG(SYS_COUNT_TX_AGING, 0x000278), 27856051948SVladimir Oltean REG(SYS_RESET_CFG, 0x000e00), 27956051948SVladimir Oltean REG(SYS_SR_ETYPE_CFG, 0x000e04), 28056051948SVladimir Oltean REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 28156051948SVladimir Oltean REG(SYS_PORT_MODE, 0x000e0c), 28256051948SVladimir Oltean REG(SYS_FRONT_PORT_MODE, 0x000e2c), 28356051948SVladimir Oltean REG(SYS_FRM_AGING, 0x000e44), 28456051948SVladimir Oltean REG(SYS_STAT_CFG, 0x000e48), 28556051948SVladimir Oltean REG(SYS_SW_STATUS, 0x000e4c), 28656051948SVladimir Oltean REG_RESERVED(SYS_MISC_CFG), 28756051948SVladimir Oltean REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 28856051948SVladimir Oltean REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 28956051948SVladimir Oltean REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 29056051948SVladimir Oltean REG(SYS_PAUSE_CFG, 0x000ea0), 29156051948SVladimir Oltean REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 29256051948SVladimir Oltean REG(SYS_ATOP, 0x000ec0), 29356051948SVladimir Oltean REG(SYS_ATOP_TOT_CFG, 0x000edc), 29456051948SVladimir Oltean REG(SYS_MAC_FC_CFG, 0x000ee0), 29556051948SVladimir Oltean REG(SYS_MMGT, 0x000ef8), 29656051948SVladimir Oltean REG_RESERVED(SYS_MMGT_FAST), 29756051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_DIF), 29856051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_CORE), 2997d4b564dSXiaoliang Yang REG(SYS_CNT, 0x000000), 30056051948SVladimir Oltean REG(SYS_PTP_STATUS, 0x000f14), 30156051948SVladimir Oltean REG(SYS_PTP_TXSTAMP, 0x000f18), 30256051948SVladimir Oltean REG(SYS_PTP_NXT, 0x000f1c), 30356051948SVladimir Oltean REG(SYS_PTP_CFG, 0x000f20), 30456051948SVladimir Oltean REG(SYS_RAM_INIT, 0x000f24), 30556051948SVladimir Oltean REG_RESERVED(SYS_CM_ADDR), 30656051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_WR), 30756051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_RD), 30856051948SVladimir Oltean REG_RESERVED(SYS_CM_OP), 30956051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA), 31056051948SVladimir Oltean }; 31156051948SVladimir Oltean 3125df66c48SYangbo Lu static const u32 vsc9959_ptp_regmap[] = { 3135df66c48SYangbo Lu REG(PTP_PIN_CFG, 0x000000), 3145df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 3155df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 3165df66c48SYangbo Lu REG(PTP_PIN_TOD_NSEC, 0x00000c), 31794aca082SYangbo Lu REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 31894aca082SYangbo Lu REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 3195df66c48SYangbo Lu REG(PTP_CFG_MISC, 0x0000a0), 3205df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 3215df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 3225df66c48SYangbo Lu }; 3235df66c48SYangbo Lu 32456051948SVladimir Oltean static const u32 vsc9959_gcb_regmap[] = { 32556051948SVladimir Oltean REG(GCB_SOFT_RST, 0x000004), 32656051948SVladimir Oltean }; 32756051948SVladimir Oltean 32891c724cfSVladimir Oltean static const u32 vsc9959_dev_gmii_regmap[] = { 32991c724cfSVladimir Oltean REG(DEV_CLOCK_CFG, 0x0), 33091c724cfSVladimir Oltean REG(DEV_PORT_MISC, 0x4), 33191c724cfSVladimir Oltean REG(DEV_EVENTS, 0x8), 33291c724cfSVladimir Oltean REG(DEV_EEE_CFG, 0xc), 33391c724cfSVladimir Oltean REG(DEV_RX_PATH_DELAY, 0x10), 33491c724cfSVladimir Oltean REG(DEV_TX_PATH_DELAY, 0x14), 33591c724cfSVladimir Oltean REG(DEV_PTP_PREDICT_CFG, 0x18), 33691c724cfSVladimir Oltean REG(DEV_MAC_ENA_CFG, 0x1c), 33791c724cfSVladimir Oltean REG(DEV_MAC_MODE_CFG, 0x20), 33891c724cfSVladimir Oltean REG(DEV_MAC_MAXLEN_CFG, 0x24), 33991c724cfSVladimir Oltean REG(DEV_MAC_TAGS_CFG, 0x28), 34091c724cfSVladimir Oltean REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 34191c724cfSVladimir Oltean REG(DEV_MAC_IFG_CFG, 0x30), 34291c724cfSVladimir Oltean REG(DEV_MAC_HDX_CFG, 0x34), 34391c724cfSVladimir Oltean REG(DEV_MAC_DBG_CFG, 0x38), 34491c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 34591c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 34691c724cfSVladimir Oltean REG(DEV_MAC_STICKY, 0x44), 34791c724cfSVladimir Oltean REG_RESERVED(PCS1G_CFG), 34891c724cfSVladimir Oltean REG_RESERVED(PCS1G_MODE_CFG), 34991c724cfSVladimir Oltean REG_RESERVED(PCS1G_SD_CFG), 35091c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_CFG), 35191c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_CFG), 35291c724cfSVladimir Oltean REG_RESERVED(PCS1G_LB_CFG), 35391c724cfSVladimir Oltean REG_RESERVED(PCS1G_DBG_CFG), 35491c724cfSVladimir Oltean REG_RESERVED(PCS1G_CDET_CFG), 35591c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_STATUS), 35691c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_STATUS), 35791c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_STATUS), 35891c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_DOWN_CNT), 35991c724cfSVladimir Oltean REG_RESERVED(PCS1G_STICKY), 36091c724cfSVladimir Oltean REG_RESERVED(PCS1G_DEBUG_STATUS), 36191c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_CFG), 36291c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 36391c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_STATUS), 36491c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 36591c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_STATUS), 36691c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_CFG), 36791c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_STATUS), 36891c724cfSVladimir Oltean }; 36991c724cfSVladimir Oltean 37091c724cfSVladimir Oltean static const u32 *vsc9959_regmap[TARGET_MAX] = { 37156051948SVladimir Oltean [ANA] = vsc9959_ana_regmap, 37256051948SVladimir Oltean [QS] = vsc9959_qs_regmap, 37356051948SVladimir Oltean [QSYS] = vsc9959_qsys_regmap, 37456051948SVladimir Oltean [REW] = vsc9959_rew_regmap, 37556051948SVladimir Oltean [SYS] = vsc9959_sys_regmap, 376e3aea296SVladimir Oltean [S0] = vsc9959_vcap_regmap, 377a61e365dSVladimir Oltean [S1] = vsc9959_vcap_regmap, 378c1c3993eSVladimir Oltean [S2] = vsc9959_vcap_regmap, 3795df66c48SYangbo Lu [PTP] = vsc9959_ptp_regmap, 38056051948SVladimir Oltean [GCB] = vsc9959_gcb_regmap, 38191c724cfSVladimir Oltean [DEV_GMII] = vsc9959_dev_gmii_regmap, 38256051948SVladimir Oltean }; 38356051948SVladimir Oltean 384b4024c9eSClaudiu Manoil /* Addresses are relative to the PCI device's base address */ 38591c724cfSVladimir Oltean static const struct resource vsc9959_target_io_res[TARGET_MAX] = { 38656051948SVladimir Oltean [ANA] = { 38756051948SVladimir Oltean .start = 0x0280000, 38856051948SVladimir Oltean .end = 0x028ffff, 38956051948SVladimir Oltean .name = "ana", 39056051948SVladimir Oltean }, 39156051948SVladimir Oltean [QS] = { 39256051948SVladimir Oltean .start = 0x0080000, 39356051948SVladimir Oltean .end = 0x00800ff, 39456051948SVladimir Oltean .name = "qs", 39556051948SVladimir Oltean }, 39656051948SVladimir Oltean [QSYS] = { 39756051948SVladimir Oltean .start = 0x0200000, 39856051948SVladimir Oltean .end = 0x021ffff, 39956051948SVladimir Oltean .name = "qsys", 40056051948SVladimir Oltean }, 40156051948SVladimir Oltean [REW] = { 40256051948SVladimir Oltean .start = 0x0030000, 40356051948SVladimir Oltean .end = 0x003ffff, 40456051948SVladimir Oltean .name = "rew", 40556051948SVladimir Oltean }, 40656051948SVladimir Oltean [SYS] = { 40756051948SVladimir Oltean .start = 0x0010000, 40856051948SVladimir Oltean .end = 0x001ffff, 40956051948SVladimir Oltean .name = "sys", 41056051948SVladimir Oltean }, 411e3aea296SVladimir Oltean [S0] = { 412e3aea296SVladimir Oltean .start = 0x0040000, 413e3aea296SVladimir Oltean .end = 0x00403ff, 414e3aea296SVladimir Oltean .name = "s0", 415e3aea296SVladimir Oltean }, 416a61e365dSVladimir Oltean [S1] = { 417a61e365dSVladimir Oltean .start = 0x0050000, 418a61e365dSVladimir Oltean .end = 0x00503ff, 419a61e365dSVladimir Oltean .name = "s1", 420a61e365dSVladimir Oltean }, 42156051948SVladimir Oltean [S2] = { 42256051948SVladimir Oltean .start = 0x0060000, 42356051948SVladimir Oltean .end = 0x00603ff, 42456051948SVladimir Oltean .name = "s2", 42556051948SVladimir Oltean }, 4265df66c48SYangbo Lu [PTP] = { 4275df66c48SYangbo Lu .start = 0x0090000, 4285df66c48SYangbo Lu .end = 0x00900cb, 4295df66c48SYangbo Lu .name = "ptp", 4305df66c48SYangbo Lu }, 43156051948SVladimir Oltean [GCB] = { 43256051948SVladimir Oltean .start = 0x0070000, 43356051948SVladimir Oltean .end = 0x00701ff, 43456051948SVladimir Oltean .name = "devcpu_gcb", 43556051948SVladimir Oltean }, 43656051948SVladimir Oltean }; 43756051948SVladimir Oltean 438b4024c9eSClaudiu Manoil static const struct resource vsc9959_port_io_res[] = { 43956051948SVladimir Oltean { 44056051948SVladimir Oltean .start = 0x0100000, 44156051948SVladimir Oltean .end = 0x010ffff, 44256051948SVladimir Oltean .name = "port0", 44356051948SVladimir Oltean }, 44456051948SVladimir Oltean { 44556051948SVladimir Oltean .start = 0x0110000, 44656051948SVladimir Oltean .end = 0x011ffff, 44756051948SVladimir Oltean .name = "port1", 44856051948SVladimir Oltean }, 44956051948SVladimir Oltean { 45056051948SVladimir Oltean .start = 0x0120000, 45156051948SVladimir Oltean .end = 0x012ffff, 45256051948SVladimir Oltean .name = "port2", 45356051948SVladimir Oltean }, 45456051948SVladimir Oltean { 45556051948SVladimir Oltean .start = 0x0130000, 45656051948SVladimir Oltean .end = 0x013ffff, 45756051948SVladimir Oltean .name = "port3", 45856051948SVladimir Oltean }, 45956051948SVladimir Oltean { 46056051948SVladimir Oltean .start = 0x0140000, 46156051948SVladimir Oltean .end = 0x014ffff, 46256051948SVladimir Oltean .name = "port4", 46356051948SVladimir Oltean }, 46456051948SVladimir Oltean { 46556051948SVladimir Oltean .start = 0x0150000, 46656051948SVladimir Oltean .end = 0x015ffff, 46756051948SVladimir Oltean .name = "port5", 46856051948SVladimir Oltean }, 46956051948SVladimir Oltean }; 47056051948SVladimir Oltean 471bdeced75SVladimir Oltean /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 472bdeced75SVladimir Oltean * SGMII/QSGMII MAC PCS can be found. 473bdeced75SVladimir Oltean */ 474b4024c9eSClaudiu Manoil static const struct resource vsc9959_imdio_res = { 475bdeced75SVladimir Oltean .start = 0x8030, 476bdeced75SVladimir Oltean .end = 0x8040, 477bdeced75SVladimir Oltean .name = "imdio", 478bdeced75SVladimir Oltean }; 479bdeced75SVladimir Oltean 4802789658fSMaxim Kochetkov static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 48156051948SVladimir Oltean [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 48256051948SVladimir Oltean [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 48356051948SVladimir Oltean [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 48456051948SVladimir Oltean [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 48556051948SVladimir Oltean [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 48656051948SVladimir Oltean [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 48756051948SVladimir Oltean [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 48856051948SVladimir Oltean [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 48956051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 49056051948SVladimir Oltean [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 49156051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 49256051948SVladimir Oltean [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 49356051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 49456051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 49556051948SVladimir Oltean [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 49656051948SVladimir Oltean [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 49756051948SVladimir Oltean [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 49856051948SVladimir Oltean [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 49956051948SVladimir Oltean [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 50056051948SVladimir Oltean [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 50156051948SVladimir Oltean [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 50256051948SVladimir Oltean [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 50356051948SVladimir Oltean [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 50456051948SVladimir Oltean [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 50556051948SVladimir Oltean [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 50656051948SVladimir Oltean [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 50756051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 50856051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 50956051948SVladimir Oltean [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 51056051948SVladimir Oltean [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 51156051948SVladimir Oltean [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 51256051948SVladimir Oltean [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 51356051948SVladimir Oltean [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 514886e1387SVladimir Oltean /* Replicated per number of ports (7), register size 4 per port */ 515886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 516886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 517886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 518886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 519886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 520886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 521886e1387SVladimir Oltean [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 522886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 523886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 524886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 525541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 526541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 527541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 52856051948SVladimir Oltean }; 52956051948SVladimir Oltean 53056051948SVladimir Oltean static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 53156051948SVladimir Oltean { .offset = 0x00, .name = "rx_octets", }, 53256051948SVladimir Oltean { .offset = 0x01, .name = "rx_unicast", }, 53356051948SVladimir Oltean { .offset = 0x02, .name = "rx_multicast", }, 53456051948SVladimir Oltean { .offset = 0x03, .name = "rx_broadcast", }, 53556051948SVladimir Oltean { .offset = 0x04, .name = "rx_shorts", }, 53656051948SVladimir Oltean { .offset = 0x05, .name = "rx_fragments", }, 53756051948SVladimir Oltean { .offset = 0x06, .name = "rx_jabbers", }, 53856051948SVladimir Oltean { .offset = 0x07, .name = "rx_crc_align_errs", }, 53956051948SVladimir Oltean { .offset = 0x08, .name = "rx_sym_errs", }, 54056051948SVladimir Oltean { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 54156051948SVladimir Oltean { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 54256051948SVladimir Oltean { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 54356051948SVladimir Oltean { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 54456051948SVladimir Oltean { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 54556051948SVladimir Oltean { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 54656051948SVladimir Oltean { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 54756051948SVladimir Oltean { .offset = 0x10, .name = "rx_pause", }, 54856051948SVladimir Oltean { .offset = 0x11, .name = "rx_control", }, 54956051948SVladimir Oltean { .offset = 0x12, .name = "rx_longs", }, 55056051948SVladimir Oltean { .offset = 0x13, .name = "rx_classified_drops", }, 55156051948SVladimir Oltean { .offset = 0x14, .name = "rx_red_prio_0", }, 55256051948SVladimir Oltean { .offset = 0x15, .name = "rx_red_prio_1", }, 55356051948SVladimir Oltean { .offset = 0x16, .name = "rx_red_prio_2", }, 55456051948SVladimir Oltean { .offset = 0x17, .name = "rx_red_prio_3", }, 55556051948SVladimir Oltean { .offset = 0x18, .name = "rx_red_prio_4", }, 55656051948SVladimir Oltean { .offset = 0x19, .name = "rx_red_prio_5", }, 55756051948SVladimir Oltean { .offset = 0x1A, .name = "rx_red_prio_6", }, 55856051948SVladimir Oltean { .offset = 0x1B, .name = "rx_red_prio_7", }, 55956051948SVladimir Oltean { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 56056051948SVladimir Oltean { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 56156051948SVladimir Oltean { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 56256051948SVladimir Oltean { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 56356051948SVladimir Oltean { .offset = 0x20, .name = "rx_yellow_prio_4", }, 56456051948SVladimir Oltean { .offset = 0x21, .name = "rx_yellow_prio_5", }, 56556051948SVladimir Oltean { .offset = 0x22, .name = "rx_yellow_prio_6", }, 56656051948SVladimir Oltean { .offset = 0x23, .name = "rx_yellow_prio_7", }, 56756051948SVladimir Oltean { .offset = 0x24, .name = "rx_green_prio_0", }, 56856051948SVladimir Oltean { .offset = 0x25, .name = "rx_green_prio_1", }, 56956051948SVladimir Oltean { .offset = 0x26, .name = "rx_green_prio_2", }, 57056051948SVladimir Oltean { .offset = 0x27, .name = "rx_green_prio_3", }, 57156051948SVladimir Oltean { .offset = 0x28, .name = "rx_green_prio_4", }, 57256051948SVladimir Oltean { .offset = 0x29, .name = "rx_green_prio_5", }, 57356051948SVladimir Oltean { .offset = 0x2A, .name = "rx_green_prio_6", }, 57456051948SVladimir Oltean { .offset = 0x2B, .name = "rx_green_prio_7", }, 57556051948SVladimir Oltean { .offset = 0x80, .name = "tx_octets", }, 57656051948SVladimir Oltean { .offset = 0x81, .name = "tx_unicast", }, 57756051948SVladimir Oltean { .offset = 0x82, .name = "tx_multicast", }, 57856051948SVladimir Oltean { .offset = 0x83, .name = "tx_broadcast", }, 57956051948SVladimir Oltean { .offset = 0x84, .name = "tx_collision", }, 58056051948SVladimir Oltean { .offset = 0x85, .name = "tx_drops", }, 58156051948SVladimir Oltean { .offset = 0x86, .name = "tx_pause", }, 58256051948SVladimir Oltean { .offset = 0x87, .name = "tx_frames_below_65_octets", }, 58356051948SVladimir Oltean { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, 58456051948SVladimir Oltean { .offset = 0x89, .name = "tx_frames_128_255_octets", }, 58556051948SVladimir Oltean { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, 58656051948SVladimir Oltean { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, 58756051948SVladimir Oltean { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, 58856051948SVladimir Oltean { .offset = 0x8E, .name = "tx_yellow_prio_0", }, 58956051948SVladimir Oltean { .offset = 0x8F, .name = "tx_yellow_prio_1", }, 59056051948SVladimir Oltean { .offset = 0x90, .name = "tx_yellow_prio_2", }, 59156051948SVladimir Oltean { .offset = 0x91, .name = "tx_yellow_prio_3", }, 59256051948SVladimir Oltean { .offset = 0x92, .name = "tx_yellow_prio_4", }, 59356051948SVladimir Oltean { .offset = 0x93, .name = "tx_yellow_prio_5", }, 59456051948SVladimir Oltean { .offset = 0x94, .name = "tx_yellow_prio_6", }, 59556051948SVladimir Oltean { .offset = 0x95, .name = "tx_yellow_prio_7", }, 59656051948SVladimir Oltean { .offset = 0x96, .name = "tx_green_prio_0", }, 59756051948SVladimir Oltean { .offset = 0x97, .name = "tx_green_prio_1", }, 59856051948SVladimir Oltean { .offset = 0x98, .name = "tx_green_prio_2", }, 59956051948SVladimir Oltean { .offset = 0x99, .name = "tx_green_prio_3", }, 60056051948SVladimir Oltean { .offset = 0x9A, .name = "tx_green_prio_4", }, 60156051948SVladimir Oltean { .offset = 0x9B, .name = "tx_green_prio_5", }, 60256051948SVladimir Oltean { .offset = 0x9C, .name = "tx_green_prio_6", }, 60356051948SVladimir Oltean { .offset = 0x9D, .name = "tx_green_prio_7", }, 60456051948SVladimir Oltean { .offset = 0x9E, .name = "tx_aged", }, 60556051948SVladimir Oltean { .offset = 0x100, .name = "drop_local", }, 60656051948SVladimir Oltean { .offset = 0x101, .name = "drop_tail", }, 60756051948SVladimir Oltean { .offset = 0x102, .name = "drop_yellow_prio_0", }, 60856051948SVladimir Oltean { .offset = 0x103, .name = "drop_yellow_prio_1", }, 60956051948SVladimir Oltean { .offset = 0x104, .name = "drop_yellow_prio_2", }, 61056051948SVladimir Oltean { .offset = 0x105, .name = "drop_yellow_prio_3", }, 61156051948SVladimir Oltean { .offset = 0x106, .name = "drop_yellow_prio_4", }, 61256051948SVladimir Oltean { .offset = 0x107, .name = "drop_yellow_prio_5", }, 61356051948SVladimir Oltean { .offset = 0x108, .name = "drop_yellow_prio_6", }, 61456051948SVladimir Oltean { .offset = 0x109, .name = "drop_yellow_prio_7", }, 61556051948SVladimir Oltean { .offset = 0x10A, .name = "drop_green_prio_0", }, 61656051948SVladimir Oltean { .offset = 0x10B, .name = "drop_green_prio_1", }, 61756051948SVladimir Oltean { .offset = 0x10C, .name = "drop_green_prio_2", }, 61856051948SVladimir Oltean { .offset = 0x10D, .name = "drop_green_prio_3", }, 61956051948SVladimir Oltean { .offset = 0x10E, .name = "drop_green_prio_4", }, 62056051948SVladimir Oltean { .offset = 0x10F, .name = "drop_green_prio_5", }, 62156051948SVladimir Oltean { .offset = 0x110, .name = "drop_green_prio_6", }, 62256051948SVladimir Oltean { .offset = 0x111, .name = "drop_green_prio_7", }, 62356051948SVladimir Oltean }; 62456051948SVladimir Oltean 625e3aea296SVladimir Oltean static const struct vcap_field vsc9959_vcap_es0_keys[] = { 626e3aea296SVladimir Oltean [VCAP_ES0_EGR_PORT] = { 0, 3}, 627e3aea296SVladimir Oltean [VCAP_ES0_IGR_PORT] = { 3, 3}, 628e3aea296SVladimir Oltean [VCAP_ES0_RSV] = { 6, 2}, 629e3aea296SVladimir Oltean [VCAP_ES0_L2_MC] = { 8, 1}, 630e3aea296SVladimir Oltean [VCAP_ES0_L2_BC] = { 9, 1}, 631e3aea296SVladimir Oltean [VCAP_ES0_VID] = { 10, 12}, 632e3aea296SVladimir Oltean [VCAP_ES0_DP] = { 22, 1}, 633e3aea296SVladimir Oltean [VCAP_ES0_PCP] = { 23, 3}, 634e3aea296SVladimir Oltean }; 635e3aea296SVladimir Oltean 636e3aea296SVladimir Oltean static const struct vcap_field vsc9959_vcap_es0_actions[] = { 637e3aea296SVladimir Oltean [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 638e3aea296SVladimir Oltean [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 639e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 640e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 641e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 642e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 643e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 644e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 645e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 646e3aea296SVladimir Oltean [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 647e3aea296SVladimir Oltean [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 648e3aea296SVladimir Oltean [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 649e3aea296SVladimir Oltean [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 650e3aea296SVladimir Oltean [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 651e3aea296SVladimir Oltean [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 652e3aea296SVladimir Oltean [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 653e3aea296SVladimir Oltean [VCAP_ES0_ACT_RSV] = { 49, 23}, 654e3aea296SVladimir Oltean [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 655e3aea296SVladimir Oltean }; 656e3aea296SVladimir Oltean 657a61e365dSVladimir Oltean static const struct vcap_field vsc9959_vcap_is1_keys[] = { 658a61e365dSVladimir Oltean [VCAP_IS1_HK_TYPE] = { 0, 1}, 659a61e365dSVladimir Oltean [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 660a61e365dSVladimir Oltean [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 661a61e365dSVladimir Oltean [VCAP_IS1_HK_RSV] = { 10, 9}, 662a61e365dSVladimir Oltean [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 663a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_MC] = { 20, 1}, 664a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_BC] = { 21, 1}, 665a61e365dSVladimir Oltean [VCAP_IS1_HK_IP_MC] = { 22, 1}, 666a61e365dSVladimir Oltean [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 667a61e365dSVladimir Oltean [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 668a61e365dSVladimir Oltean [VCAP_IS1_HK_TPID] = { 25, 1}, 669a61e365dSVladimir Oltean [VCAP_IS1_HK_VID] = { 26, 12}, 670a61e365dSVladimir Oltean [VCAP_IS1_HK_DEI] = { 38, 1}, 671a61e365dSVladimir Oltean [VCAP_IS1_HK_PCP] = { 39, 3}, 672a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_NORMAL */ 673a61e365dSVladimir Oltean [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 674a61e365dSVladimir Oltean [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 675a61e365dSVladimir Oltean [VCAP_IS1_HK_ETYPE] = { 91, 16}, 676a61e365dSVladimir Oltean [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 677a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4] = {108, 1}, 678a61e365dSVladimir Oltean /* Layer-3 Information */ 679a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 680a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 681a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 682a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 683a61e365dSVladimir Oltean [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 684a61e365dSVladimir Oltean /* Layer-4 Information */ 685a61e365dSVladimir Oltean [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 686a61e365dSVladimir Oltean [VCAP_IS1_HK_TCP] = {151, 1}, 687a61e365dSVladimir Oltean [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 688a61e365dSVladimir Oltean [VCAP_IS1_HK_L4_RNG] = {168, 8}, 689a61e365dSVladimir Oltean /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 690a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 691a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 692a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 693a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 694a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 695a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 696a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 697a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 698a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 699a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 700a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 701a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 702a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 703a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 704a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 705a61e365dSVladimir Oltean [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 706a61e365dSVladimir Oltean }; 707a61e365dSVladimir Oltean 708a61e365dSVladimir Oltean static const struct vcap_field vsc9959_vcap_is1_actions[] = { 709a61e365dSVladimir Oltean [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 710a61e365dSVladimir Oltean [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 711a61e365dSVladimir Oltean [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 712a61e365dSVladimir Oltean [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 713a61e365dSVladimir Oltean [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 714a61e365dSVladimir Oltean [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 715a61e365dSVladimir Oltean [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 716a61e365dSVladimir Oltean [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 717a61e365dSVladimir Oltean [VCAP_IS1_ACT_RSV] = { 29, 9}, 71875944fdaSXiaoliang Yang /* The fields below are incorrectly shifted by 2 in the manual */ 719a61e365dSVladimir Oltean [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 720a61e365dSVladimir Oltean [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 721a61e365dSVladimir Oltean [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 722a61e365dSVladimir Oltean [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 723a61e365dSVladimir Oltean [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 724a61e365dSVladimir Oltean [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 725a61e365dSVladimir Oltean [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 726a61e365dSVladimir Oltean [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 727a61e365dSVladimir Oltean [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 728a61e365dSVladimir Oltean [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 729a61e365dSVladimir Oltean [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 730a61e365dSVladimir Oltean }; 731a61e365dSVladimir Oltean 7323ab4ceb6SVladimir Oltean static struct vcap_field vsc9959_vcap_is2_keys[] = { 73307d985eeSVladimir Oltean /* Common: 41 bits */ 73407d985eeSVladimir Oltean [VCAP_IS2_TYPE] = { 0, 4}, 73507d985eeSVladimir Oltean [VCAP_IS2_HK_FIRST] = { 4, 1}, 73607d985eeSVladimir Oltean [VCAP_IS2_HK_PAG] = { 5, 8}, 73707d985eeSVladimir Oltean [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 73807d985eeSVladimir Oltean [VCAP_IS2_HK_RSV2] = { 20, 1}, 73907d985eeSVladimir Oltean [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 74007d985eeSVladimir Oltean [VCAP_IS2_HK_L2_MC] = { 22, 1}, 74107d985eeSVladimir Oltean [VCAP_IS2_HK_L2_BC] = { 23, 1}, 74207d985eeSVladimir Oltean [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 74307d985eeSVladimir Oltean [VCAP_IS2_HK_VID] = { 25, 12}, 74407d985eeSVladimir Oltean [VCAP_IS2_HK_DEI] = { 37, 1}, 74507d985eeSVladimir Oltean [VCAP_IS2_HK_PCP] = { 38, 3}, 74607d985eeSVladimir Oltean /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 74707d985eeSVladimir Oltean [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 74807d985eeSVladimir Oltean [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 74907d985eeSVladimir Oltean /* MAC_ETYPE (TYPE=000) */ 75007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 75107d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 75207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 75307d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 75407d985eeSVladimir Oltean /* MAC_LLC (TYPE=001) */ 75507d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 75607d985eeSVladimir Oltean /* MAC_SNAP (TYPE=010) */ 75707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 75807d985eeSVladimir Oltean /* MAC_ARP (TYPE=011) */ 75907d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 76007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 76107d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 76207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 76307d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 76407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 76507d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 76607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 76707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 76807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 76907d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 77007d985eeSVladimir Oltean /* IP4_TCP_UDP / IP4_OTHER common */ 77107d985eeSVladimir Oltean [VCAP_IS2_HK_IP4] = { 41, 1}, 77207d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 77307d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 77407d985eeSVladimir Oltean [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 77507d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 77607d985eeSVladimir Oltean [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 77707d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 77807d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 77907d985eeSVladimir Oltean [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 78007d985eeSVladimir Oltean /* IP4_TCP_UDP (TYPE=100) */ 78107d985eeSVladimir Oltean [VCAP_IS2_HK_TCP] = {119, 1}, 7828b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 7838b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 78407d985eeSVladimir Oltean [VCAP_IS2_HK_L4_RNG] = {152, 8}, 78507d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 78607d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 7878b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_FIN] = {162, 1}, 7888b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_SYN] = {163, 1}, 7898b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_RST] = {164, 1}, 7908b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_PSH] = {165, 1}, 7918b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_ACK] = {166, 1}, 7928b9e03cdSXiaoliang Yang [VCAP_IS2_HK_L4_URG] = {167, 1}, 79307d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 79407d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 79507d985eeSVladimir Oltean /* IP4_OTHER (TYPE=101) */ 79607d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 79707d985eeSVladimir Oltean [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 79807d985eeSVladimir Oltean /* IP6_STD (TYPE=110) */ 79907d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 80007d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 80107d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 80207d985eeSVladimir Oltean /* OAM (TYPE=111) */ 80307d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 80407d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_VER] = {144, 5}, 80507d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 80607d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 80707d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 80807d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 80907d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 81007d985eeSVladimir Oltean }; 81107d985eeSVladimir Oltean 8123ab4ceb6SVladimir Oltean static struct vcap_field vsc9959_vcap_is2_actions[] = { 81307d985eeSVladimir Oltean [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 81407d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 81507d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 81607d985eeSVladimir Oltean [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 81707d985eeSVladimir Oltean [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 81807d985eeSVladimir Oltean [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 81907d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 82007d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 82107d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 822460e985eSVladimir Oltean [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 823460e985eSVladimir Oltean [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 824460e985eSVladimir Oltean [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 825460e985eSVladimir Oltean [VCAP_IS2_ACT_RSV] = { 36, 2}, 826460e985eSVladimir Oltean [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 827460e985eSVladimir Oltean [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 82807d985eeSVladimir Oltean }; 82907d985eeSVladimir Oltean 83020968054SVladimir Oltean static struct vcap_props vsc9959_vcap_props[] = { 831e3aea296SVladimir Oltean [VCAP_ES0] = { 832e3aea296SVladimir Oltean .action_type_width = 0, 833e3aea296SVladimir Oltean .action_table = { 834e3aea296SVladimir Oltean [ES0_ACTION_TYPE_NORMAL] = { 835e3aea296SVladimir Oltean .width = 72, /* HIT_STICKY not included */ 836e3aea296SVladimir Oltean .count = 1, 837e3aea296SVladimir Oltean }, 838e3aea296SVladimir Oltean }, 839e3aea296SVladimir Oltean .target = S0, 840e3aea296SVladimir Oltean .keys = vsc9959_vcap_es0_keys, 841e3aea296SVladimir Oltean .actions = vsc9959_vcap_es0_actions, 842e3aea296SVladimir Oltean }, 843a61e365dSVladimir Oltean [VCAP_IS1] = { 844a61e365dSVladimir Oltean .action_type_width = 0, 845a61e365dSVladimir Oltean .action_table = { 846a61e365dSVladimir Oltean [IS1_ACTION_TYPE_NORMAL] = { 847a61e365dSVladimir Oltean .width = 78, /* HIT_STICKY not included */ 848a61e365dSVladimir Oltean .count = 4, 849a61e365dSVladimir Oltean }, 850a61e365dSVladimir Oltean }, 851a61e365dSVladimir Oltean .target = S1, 852a61e365dSVladimir Oltean .keys = vsc9959_vcap_is1_keys, 853a61e365dSVladimir Oltean .actions = vsc9959_vcap_is1_actions, 854a61e365dSVladimir Oltean }, 85507d985eeSVladimir Oltean [VCAP_IS2] = { 85607d985eeSVladimir Oltean .action_type_width = 1, 85707d985eeSVladimir Oltean .action_table = { 85807d985eeSVladimir Oltean [IS2_ACTION_TYPE_NORMAL] = { 85907d985eeSVladimir Oltean .width = 44, 86007d985eeSVladimir Oltean .count = 2 86107d985eeSVladimir Oltean }, 86207d985eeSVladimir Oltean [IS2_ACTION_TYPE_SMAC_SIP] = { 86307d985eeSVladimir Oltean .width = 6, 86407d985eeSVladimir Oltean .count = 4 86507d985eeSVladimir Oltean }, 86607d985eeSVladimir Oltean }, 867c1c3993eSVladimir Oltean .target = S2, 868c1c3993eSVladimir Oltean .keys = vsc9959_vcap_is2_keys, 869c1c3993eSVladimir Oltean .actions = vsc9959_vcap_is2_actions, 87007d985eeSVladimir Oltean }, 87107d985eeSVladimir Oltean }; 87207d985eeSVladimir Oltean 8732ac7c6c5SVladimir Oltean static const struct ptp_clock_info vsc9959_ptp_caps = { 8742ac7c6c5SVladimir Oltean .owner = THIS_MODULE, 8752ac7c6c5SVladimir Oltean .name = "felix ptp", 8762ac7c6c5SVladimir Oltean .max_adj = 0x7fffffff, 8772ac7c6c5SVladimir Oltean .n_alarm = 0, 8782ac7c6c5SVladimir Oltean .n_ext_ts = 0, 8792ac7c6c5SVladimir Oltean .n_per_out = OCELOT_PTP_PINS_NUM, 8802ac7c6c5SVladimir Oltean .n_pins = OCELOT_PTP_PINS_NUM, 8812ac7c6c5SVladimir Oltean .pps = 0, 8822ac7c6c5SVladimir Oltean .gettime64 = ocelot_ptp_gettime64, 8832ac7c6c5SVladimir Oltean .settime64 = ocelot_ptp_settime64, 8842ac7c6c5SVladimir Oltean .adjtime = ocelot_ptp_adjtime, 8852ac7c6c5SVladimir Oltean .adjfine = ocelot_ptp_adjfine, 8862ac7c6c5SVladimir Oltean .verify = ocelot_ptp_verify, 8872ac7c6c5SVladimir Oltean .enable = ocelot_ptp_enable, 8882ac7c6c5SVladimir Oltean }; 8892ac7c6c5SVladimir Oltean 89056051948SVladimir Oltean #define VSC9959_INIT_TIMEOUT 50000 89156051948SVladimir Oltean #define VSC9959_GCB_RST_SLEEP 100 89256051948SVladimir Oltean #define VSC9959_SYS_RAMINIT_SLEEP 80 89356051948SVladimir Oltean 89456051948SVladimir Oltean static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 89556051948SVladimir Oltean { 89656051948SVladimir Oltean int val; 89756051948SVladimir Oltean 89875cea9cbSVladimir Oltean ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 89956051948SVladimir Oltean 90056051948SVladimir Oltean return val; 90156051948SVladimir Oltean } 90256051948SVladimir Oltean 90356051948SVladimir Oltean static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 90456051948SVladimir Oltean { 90556051948SVladimir Oltean return ocelot_read(ocelot, SYS_RAM_INIT); 90656051948SVladimir Oltean } 90756051948SVladimir Oltean 908c129fc55SVladimir Oltean /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 909c129fc55SVladimir Oltean * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 910c129fc55SVladimir Oltean */ 91156051948SVladimir Oltean static int vsc9959_reset(struct ocelot *ocelot) 91256051948SVladimir Oltean { 91356051948SVladimir Oltean int val, err; 91456051948SVladimir Oltean 91556051948SVladimir Oltean /* soft-reset the switch core */ 91675cea9cbSVladimir Oltean ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 91756051948SVladimir Oltean 91856051948SVladimir Oltean err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 91956051948SVladimir Oltean VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 92056051948SVladimir Oltean if (err) { 92156051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch core reset\n"); 92256051948SVladimir Oltean return err; 92356051948SVladimir Oltean } 92456051948SVladimir Oltean 92556051948SVladimir Oltean /* initialize switch mem ~40us */ 92656051948SVladimir Oltean ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 92756051948SVladimir Oltean err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 92856051948SVladimir Oltean VSC9959_SYS_RAMINIT_SLEEP, 92956051948SVladimir Oltean VSC9959_INIT_TIMEOUT); 93056051948SVladimir Oltean if (err) { 93156051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch sram init\n"); 93256051948SVladimir Oltean return err; 93356051948SVladimir Oltean } 93456051948SVladimir Oltean 93556051948SVladimir Oltean /* enable switch core */ 93675cea9cbSVladimir Oltean ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 93756051948SVladimir Oltean 93856051948SVladimir Oltean return 0; 93956051948SVladimir Oltean } 94056051948SVladimir Oltean 941375e1314SVladimir Oltean static void vsc9959_phylink_validate(struct ocelot *ocelot, int port, 942375e1314SVladimir Oltean unsigned long *supported, 943375e1314SVladimir Oltean struct phylink_link_state *state) 944375e1314SVladimir Oltean { 945375e1314SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 946375e1314SVladimir Oltean __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 947375e1314SVladimir Oltean 948375e1314SVladimir Oltean if (state->interface != PHY_INTERFACE_MODE_NA && 949375e1314SVladimir Oltean state->interface != ocelot_port->phy_mode) { 9504973056cSSean Anderson linkmode_zero(supported); 951375e1314SVladimir Oltean return; 952375e1314SVladimir Oltean } 953375e1314SVladimir Oltean 954375e1314SVladimir Oltean phylink_set_port_modes(mask); 955375e1314SVladimir Oltean phylink_set(mask, Autoneg); 956375e1314SVladimir Oltean phylink_set(mask, Pause); 957375e1314SVladimir Oltean phylink_set(mask, Asym_Pause); 958375e1314SVladimir Oltean phylink_set(mask, 10baseT_Half); 959375e1314SVladimir Oltean phylink_set(mask, 10baseT_Full); 960375e1314SVladimir Oltean phylink_set(mask, 100baseT_Half); 961375e1314SVladimir Oltean phylink_set(mask, 100baseT_Full); 962375e1314SVladimir Oltean phylink_set(mask, 1000baseT_Half); 963375e1314SVladimir Oltean phylink_set(mask, 1000baseT_Full); 964375e1314SVladimir Oltean 965375e1314SVladimir Oltean if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 966375e1314SVladimir Oltean state->interface == PHY_INTERFACE_MODE_2500BASEX || 967375e1314SVladimir Oltean state->interface == PHY_INTERFACE_MODE_USXGMII) { 968375e1314SVladimir Oltean phylink_set(mask, 2500baseT_Full); 969375e1314SVladimir Oltean phylink_set(mask, 2500baseX_Full); 970375e1314SVladimir Oltean } 971375e1314SVladimir Oltean 9724973056cSSean Anderson linkmode_and(supported, supported, mask); 9734973056cSSean Anderson linkmode_and(state->advertising, state->advertising, mask); 974375e1314SVladimir Oltean } 975375e1314SVladimir Oltean 976bdeced75SVladimir Oltean static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port, 977bdeced75SVladimir Oltean phy_interface_t phy_mode) 978bdeced75SVladimir Oltean { 979bdeced75SVladimir Oltean switch (phy_mode) { 98028a134f5SVladimir Oltean case PHY_INTERFACE_MODE_INTERNAL: 981bdeced75SVladimir Oltean if (port != 4 && port != 5) 982bdeced75SVladimir Oltean return -ENOTSUPP; 983bdeced75SVladimir Oltean return 0; 984bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 985bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 986bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 987bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 988bdeced75SVladimir Oltean /* Not supported on internal to-CPU ports */ 989bdeced75SVladimir Oltean if (port == 4 || port == 5) 990bdeced75SVladimir Oltean return -ENOTSUPP; 991bdeced75SVladimir Oltean return 0; 992bdeced75SVladimir Oltean default: 993bdeced75SVladimir Oltean return -ENOTSUPP; 994bdeced75SVladimir Oltean } 995bdeced75SVladimir Oltean } 996bdeced75SVladimir Oltean 997aa92d836SMaxim Kochetkov /* Watermark encode 998aa92d836SMaxim Kochetkov * Bit 8: Unit; 0:1, 1:16 999aa92d836SMaxim Kochetkov * Bit 7-0: Value to be multiplied with unit 1000aa92d836SMaxim Kochetkov */ 1001aa92d836SMaxim Kochetkov static u16 vsc9959_wm_enc(u16 value) 1002aa92d836SMaxim Kochetkov { 100301326493SVladimir Oltean WARN_ON(value >= 16 * BIT(8)); 100401326493SVladimir Oltean 1005aa92d836SMaxim Kochetkov if (value >= BIT(8)) 1006aa92d836SMaxim Kochetkov return BIT(8) | (value / 16); 1007aa92d836SMaxim Kochetkov 1008aa92d836SMaxim Kochetkov return value; 1009aa92d836SMaxim Kochetkov } 1010aa92d836SMaxim Kochetkov 1011703b7621SVladimir Oltean static u16 vsc9959_wm_dec(u16 wm) 1012703b7621SVladimir Oltean { 1013703b7621SVladimir Oltean WARN_ON(wm & ~GENMASK(8, 0)); 1014703b7621SVladimir Oltean 1015703b7621SVladimir Oltean if (wm & BIT(8)) 1016703b7621SVladimir Oltean return (wm & GENMASK(7, 0)) * 16; 1017703b7621SVladimir Oltean 1018703b7621SVladimir Oltean return wm; 1019703b7621SVladimir Oltean } 1020703b7621SVladimir Oltean 1021703b7621SVladimir Oltean static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 1022703b7621SVladimir Oltean { 1023703b7621SVladimir Oltean *inuse = (val & GENMASK(23, 12)) >> 12; 1024703b7621SVladimir Oltean *maxuse = val & GENMASK(11, 0); 1025703b7621SVladimir Oltean } 1026703b7621SVladimir Oltean 1027bdeced75SVladimir Oltean static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 1028bdeced75SVladimir Oltean { 1029bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1030bdeced75SVladimir Oltean struct enetc_mdio_priv *mdio_priv; 1031bdeced75SVladimir Oltean struct device *dev = ocelot->dev; 1032bdeced75SVladimir Oltean void __iomem *imdio_regs; 1033b4024c9eSClaudiu Manoil struct resource res; 1034bdeced75SVladimir Oltean struct enetc_hw *hw; 1035bdeced75SVladimir Oltean struct mii_bus *bus; 1036bdeced75SVladimir Oltean int port; 1037bdeced75SVladimir Oltean int rc; 1038bdeced75SVladimir Oltean 1039bdeced75SVladimir Oltean felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 1040588d0550SIoana Ciornei sizeof(struct lynx_pcs *), 1041bdeced75SVladimir Oltean GFP_KERNEL); 1042bdeced75SVladimir Oltean if (!felix->pcs) { 1043bdeced75SVladimir Oltean dev_err(dev, "failed to allocate array for PCS PHYs\n"); 1044bdeced75SVladimir Oltean return -ENOMEM; 1045bdeced75SVladimir Oltean } 1046bdeced75SVladimir Oltean 1047b4024c9eSClaudiu Manoil memcpy(&res, felix->info->imdio_res, sizeof(res)); 1048b4024c9eSClaudiu Manoil res.flags = IORESOURCE_MEM; 1049375e1314SVladimir Oltean res.start += felix->imdio_base; 1050375e1314SVladimir Oltean res.end += felix->imdio_base; 1051bdeced75SVladimir Oltean 1052b4024c9eSClaudiu Manoil imdio_regs = devm_ioremap_resource(dev, &res); 1053a180be79SGuobin Huang if (IS_ERR(imdio_regs)) 1054bdeced75SVladimir Oltean return PTR_ERR(imdio_regs); 1055bdeced75SVladimir Oltean 1056bdeced75SVladimir Oltean hw = enetc_hw_alloc(dev, imdio_regs); 1057bdeced75SVladimir Oltean if (IS_ERR(hw)) { 1058bdeced75SVladimir Oltean dev_err(dev, "failed to allocate ENETC HW structure\n"); 1059bdeced75SVladimir Oltean return PTR_ERR(hw); 1060bdeced75SVladimir Oltean } 1061bdeced75SVladimir Oltean 1062bdeced75SVladimir Oltean bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv)); 1063bdeced75SVladimir Oltean if (!bus) 1064bdeced75SVladimir Oltean return -ENOMEM; 1065bdeced75SVladimir Oltean 1066bdeced75SVladimir Oltean bus->name = "VSC9959 internal MDIO bus"; 1067bdeced75SVladimir Oltean bus->read = enetc_mdio_read; 1068bdeced75SVladimir Oltean bus->write = enetc_mdio_write; 1069bdeced75SVladimir Oltean bus->parent = dev; 1070bdeced75SVladimir Oltean mdio_priv = bus->priv; 1071bdeced75SVladimir Oltean mdio_priv->hw = hw; 1072bdeced75SVladimir Oltean /* This gets added to imdio_regs, which already maps addresses 1073bdeced75SVladimir Oltean * starting with the proper offset. 1074bdeced75SVladimir Oltean */ 1075bdeced75SVladimir Oltean mdio_priv->mdio_base = 0; 1076bdeced75SVladimir Oltean snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1077bdeced75SVladimir Oltean 1078bdeced75SVladimir Oltean /* Needed in order to initialize the bus mutex lock */ 1079bdeced75SVladimir Oltean rc = mdiobus_register(bus); 1080bdeced75SVladimir Oltean if (rc < 0) { 1081bdeced75SVladimir Oltean dev_err(dev, "failed to register MDIO bus\n"); 1082bdeced75SVladimir Oltean return rc; 1083bdeced75SVladimir Oltean } 1084bdeced75SVladimir Oltean 1085bdeced75SVladimir Oltean felix->imdio = bus; 1086bdeced75SVladimir Oltean 1087bdeced75SVladimir Oltean for (port = 0; port < felix->info->num_ports; port++) { 1088bdeced75SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 1089588d0550SIoana Ciornei struct mdio_device *pcs; 1090588d0550SIoana Ciornei struct lynx_pcs *lynx; 1091bdeced75SVladimir Oltean 1092588d0550SIoana Ciornei if (dsa_is_unused_port(felix->ds, port)) 1093588d0550SIoana Ciornei continue; 1094bdeced75SVladimir Oltean 1095588d0550SIoana Ciornei if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1096588d0550SIoana Ciornei continue; 1097588d0550SIoana Ciornei 1098588d0550SIoana Ciornei pcs = mdio_device_create(felix->imdio, port); 1099bdeced75SVladimir Oltean if (IS_ERR(pcs)) 1100bdeced75SVladimir Oltean continue; 1101bdeced75SVladimir Oltean 1102588d0550SIoana Ciornei lynx = lynx_pcs_create(pcs); 1103588d0550SIoana Ciornei if (!lynx) { 1104588d0550SIoana Ciornei mdio_device_free(pcs); 1105588d0550SIoana Ciornei continue; 1106588d0550SIoana Ciornei } 1107588d0550SIoana Ciornei 1108588d0550SIoana Ciornei felix->pcs[port] = lynx; 1109bdeced75SVladimir Oltean 1110bdeced75SVladimir Oltean dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1111bdeced75SVladimir Oltean } 1112bdeced75SVladimir Oltean 1113bdeced75SVladimir Oltean return 0; 1114bdeced75SVladimir Oltean } 1115bdeced75SVladimir Oltean 1116ccfdbab5SVladimir Oltean static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1117bdeced75SVladimir Oltean { 1118bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1119bdeced75SVladimir Oltean int port; 1120bdeced75SVladimir Oltean 1121bdeced75SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) { 1122588d0550SIoana Ciornei struct lynx_pcs *pcs = felix->pcs[port]; 1123bdeced75SVladimir Oltean 1124bdeced75SVladimir Oltean if (!pcs) 1125bdeced75SVladimir Oltean continue; 1126bdeced75SVladimir Oltean 1127588d0550SIoana Ciornei mdio_device_free(pcs->mdio); 1128588d0550SIoana Ciornei lynx_pcs_destroy(pcs); 1129bdeced75SVladimir Oltean } 1130bdeced75SVladimir Oltean mdiobus_unregister(felix->imdio); 1131bdeced75SVladimir Oltean } 1132bdeced75SVladimir Oltean 1133de143c0eSXiaoliang Yang static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1134de143c0eSXiaoliang Yang u32 speed) 1135de143c0eSXiaoliang Yang { 1136dba1e466SXiaoliang Yang u8 tas_speed; 1137dba1e466SXiaoliang Yang 1138dba1e466SXiaoliang Yang switch (speed) { 1139dba1e466SXiaoliang Yang case SPEED_10: 1140dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_10; 1141dba1e466SXiaoliang Yang break; 1142dba1e466SXiaoliang Yang case SPEED_100: 1143dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_100; 1144dba1e466SXiaoliang Yang break; 1145dba1e466SXiaoliang Yang case SPEED_1000: 1146dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_1000; 1147dba1e466SXiaoliang Yang break; 1148dba1e466SXiaoliang Yang case SPEED_2500: 1149dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_2500; 1150dba1e466SXiaoliang Yang break; 1151dba1e466SXiaoliang Yang default: 1152dba1e466SXiaoliang Yang tas_speed = OCELOT_SPEED_1000; 1153dba1e466SXiaoliang Yang break; 1154dba1e466SXiaoliang Yang } 1155dba1e466SXiaoliang Yang 1156de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1157dba1e466SXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1158de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED_M, 1159de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1160de143c0eSXiaoliang Yang } 1161de143c0eSXiaoliang Yang 1162de143c0eSXiaoliang Yang static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1163de143c0eSXiaoliang Yang u64 cycle_time, 1164de143c0eSXiaoliang Yang struct timespec64 *new_base_ts) 1165de143c0eSXiaoliang Yang { 1166de143c0eSXiaoliang Yang struct timespec64 ts; 1167de143c0eSXiaoliang Yang ktime_t new_base_time; 1168de143c0eSXiaoliang Yang ktime_t current_time; 1169de143c0eSXiaoliang Yang 1170de143c0eSXiaoliang Yang ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1171de143c0eSXiaoliang Yang current_time = timespec64_to_ktime(ts); 1172de143c0eSXiaoliang Yang new_base_time = base_time; 1173de143c0eSXiaoliang Yang 1174de143c0eSXiaoliang Yang if (base_time < current_time) { 1175de143c0eSXiaoliang Yang u64 nr_of_cycles = current_time - base_time; 1176de143c0eSXiaoliang Yang 1177de143c0eSXiaoliang Yang do_div(nr_of_cycles, cycle_time); 1178de143c0eSXiaoliang Yang new_base_time += cycle_time * (nr_of_cycles + 1); 1179de143c0eSXiaoliang Yang } 1180de143c0eSXiaoliang Yang 1181de143c0eSXiaoliang Yang *new_base_ts = ktime_to_timespec64(new_base_time); 1182de143c0eSXiaoliang Yang } 1183de143c0eSXiaoliang Yang 1184de143c0eSXiaoliang Yang static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1185de143c0eSXiaoliang Yang { 1186de143c0eSXiaoliang Yang return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1187de143c0eSXiaoliang Yang } 1188de143c0eSXiaoliang Yang 1189de143c0eSXiaoliang Yang static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1190de143c0eSXiaoliang Yang struct tc_taprio_sched_entry *entry) 1191de143c0eSXiaoliang Yang { 1192de143c0eSXiaoliang Yang ocelot_write(ocelot, 1193de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1194de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1195de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1); 1196de143c0eSXiaoliang Yang ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1197de143c0eSXiaoliang Yang } 1198de143c0eSXiaoliang Yang 1199de143c0eSXiaoliang Yang static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1200de143c0eSXiaoliang Yang struct tc_taprio_qopt_offload *taprio) 1201de143c0eSXiaoliang Yang { 1202de143c0eSXiaoliang Yang struct timespec64 base_ts; 1203de143c0eSXiaoliang Yang int ret, i; 1204de143c0eSXiaoliang Yang u32 val; 1205de143c0eSXiaoliang Yang 1206de143c0eSXiaoliang Yang if (!taprio->enable) { 1207de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1208de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF), 1209de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1210de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE_M, 1211de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1212de143c0eSXiaoliang Yang 1213de143c0eSXiaoliang Yang return 0; 1214de143c0eSXiaoliang Yang } 1215de143c0eSXiaoliang Yang 1216de143c0eSXiaoliang Yang if (taprio->cycle_time > NSEC_PER_SEC || 1217de143c0eSXiaoliang Yang taprio->cycle_time_extension >= NSEC_PER_SEC) 1218de143c0eSXiaoliang Yang return -EINVAL; 1219de143c0eSXiaoliang Yang 1220de143c0eSXiaoliang Yang if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) 1221de143c0eSXiaoliang Yang return -ERANGE; 1222de143c0eSXiaoliang Yang 1223297c4de6SMichael Walle /* Enable guard band. The switch will schedule frames without taking 1224297c4de6SMichael Walle * their length into account. Thus we'll always need to enable the 1225297c4de6SMichael Walle * guard band which reserves the time of a maximum sized frame at the 1226297c4de6SMichael Walle * end of the time window. 1227297c4de6SMichael Walle * 1228297c4de6SMichael Walle * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1229297c4de6SMichael Walle * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1230297c4de6SMichael Walle * operate on the port number. 1231316bcffeSXiaoliang Yang */ 1232297c4de6SMichael Walle ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1233297c4de6SMichael Walle QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1234de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1235de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1236de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 1237de143c0eSXiaoliang Yang 1238de143c0eSXiaoliang Yang /* Hardware errata - Admin config could not be overwritten if 1239de143c0eSXiaoliang Yang * config is pending, need reset the TAS module 1240de143c0eSXiaoliang Yang */ 1241de143c0eSXiaoliang Yang val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1242de143c0eSXiaoliang Yang if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) 1243de143c0eSXiaoliang Yang return -EBUSY; 1244de143c0eSXiaoliang Yang 1245de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1246de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1247de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1248de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1249de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1250de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1251de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1252de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1253de143c0eSXiaoliang Yang 1254de143c0eSXiaoliang Yang vsc9959_new_base_time(ocelot, taprio->base_time, 1255de143c0eSXiaoliang Yang taprio->cycle_time, &base_ts); 1256de143c0eSXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1257de143c0eSXiaoliang Yang ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1258de143c0eSXiaoliang Yang val = upper_32_bits(base_ts.tv_sec); 1259de143c0eSXiaoliang Yang ocelot_write(ocelot, 1260de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1261de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1262de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3); 1263de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1264de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1265de143c0eSXiaoliang Yang 1266de143c0eSXiaoliang Yang for (i = 0; i < taprio->num_entries; i++) 1267de143c0eSXiaoliang Yang vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1268de143c0eSXiaoliang Yang 1269de143c0eSXiaoliang Yang ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1270de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1271de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 1272de143c0eSXiaoliang Yang 1273de143c0eSXiaoliang Yang ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1274de143c0eSXiaoliang Yang !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1275de143c0eSXiaoliang Yang 10, 100000); 1276de143c0eSXiaoliang Yang 1277de143c0eSXiaoliang Yang return ret; 1278de143c0eSXiaoliang Yang } 1279de143c0eSXiaoliang Yang 12800fbabf87SXiaoliang Yang static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 12810fbabf87SXiaoliang Yang struct tc_cbs_qopt_offload *cbs_qopt) 12820fbabf87SXiaoliang Yang { 12830fbabf87SXiaoliang Yang struct ocelot *ocelot = ds->priv; 12840fbabf87SXiaoliang Yang int port_ix = port * 8 + cbs_qopt->queue; 12850fbabf87SXiaoliang Yang u32 rate, burst; 12860fbabf87SXiaoliang Yang 12870fbabf87SXiaoliang Yang if (cbs_qopt->queue >= ds->num_tx_queues) 12880fbabf87SXiaoliang Yang return -EINVAL; 12890fbabf87SXiaoliang Yang 12900fbabf87SXiaoliang Yang if (!cbs_qopt->enable) { 12910fbabf87SXiaoliang Yang ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 12920fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(0), 12930fbabf87SXiaoliang Yang QSYS_CIR_CFG, port_ix); 12940fbabf87SXiaoliang Yang 12950fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 12960fbabf87SXiaoliang Yang QSYS_SE_CFG, port_ix); 12970fbabf87SXiaoliang Yang 12980fbabf87SXiaoliang Yang return 0; 12990fbabf87SXiaoliang Yang } 13000fbabf87SXiaoliang Yang 13010fbabf87SXiaoliang Yang /* Rate unit is 100 kbps */ 13020fbabf87SXiaoliang Yang rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 13030fbabf87SXiaoliang Yang /* Avoid using zero rate */ 13040fbabf87SXiaoliang Yang rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 13050fbabf87SXiaoliang Yang /* Burst unit is 4kB */ 13060fbabf87SXiaoliang Yang burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 13070fbabf87SXiaoliang Yang /* Avoid using zero burst size */ 1308b014d043SColin Ian King burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 13090fbabf87SXiaoliang Yang ocelot_write_gix(ocelot, 13100fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_RATE(rate) | 13110fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(burst), 13120fbabf87SXiaoliang Yang QSYS_CIR_CFG, 13130fbabf87SXiaoliang Yang port_ix); 13140fbabf87SXiaoliang Yang 13150fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot, 13160fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE(0) | 13170fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA, 13180fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA | 13190fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE_M, 13200fbabf87SXiaoliang Yang QSYS_SE_CFG, 13210fbabf87SXiaoliang Yang port_ix); 13220fbabf87SXiaoliang Yang 13230fbabf87SXiaoliang Yang return 0; 13240fbabf87SXiaoliang Yang } 13250fbabf87SXiaoliang Yang 1326de143c0eSXiaoliang Yang static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1327de143c0eSXiaoliang Yang enum tc_setup_type type, 1328de143c0eSXiaoliang Yang void *type_data) 1329de143c0eSXiaoliang Yang { 1330de143c0eSXiaoliang Yang struct ocelot *ocelot = ds->priv; 1331de143c0eSXiaoliang Yang 1332de143c0eSXiaoliang Yang switch (type) { 1333de143c0eSXiaoliang Yang case TC_SETUP_QDISC_TAPRIO: 1334de143c0eSXiaoliang Yang return vsc9959_qos_port_tas_set(ocelot, port, type_data); 13350fbabf87SXiaoliang Yang case TC_SETUP_QDISC_CBS: 13360fbabf87SXiaoliang Yang return vsc9959_qos_port_cbs_set(ds, port, type_data); 1337de143c0eSXiaoliang Yang default: 1338de143c0eSXiaoliang Yang return -EOPNOTSUPP; 1339de143c0eSXiaoliang Yang } 1340de143c0eSXiaoliang Yang } 1341de143c0eSXiaoliang Yang 13427d4b564dSXiaoliang Yang #define VSC9959_PSFP_SFID_MAX 175 13437d4b564dSXiaoliang Yang #define VSC9959_PSFP_GATE_ID_MAX 183 13447d4b564dSXiaoliang Yang #define VSC9959_PSFP_POLICER_MAX 383 134523ae3a78SXiaoliang Yang #define VSC9959_PSFP_GATE_LIST_NUM 4 134623ae3a78SXiaoliang Yang #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 13477d4b564dSXiaoliang Yang 13487d4b564dSXiaoliang Yang struct felix_stream { 13497d4b564dSXiaoliang Yang struct list_head list; 13507d4b564dSXiaoliang Yang unsigned long id; 13517d4b564dSXiaoliang Yang u8 dmac[ETH_ALEN]; 13527d4b564dSXiaoliang Yang u16 vid; 13537d4b564dSXiaoliang Yang s8 prio; 13547d4b564dSXiaoliang Yang u8 sfid_valid; 13557d4b564dSXiaoliang Yang u8 ssid_valid; 13567d4b564dSXiaoliang Yang u32 sfid; 13577d4b564dSXiaoliang Yang u32 ssid; 13587d4b564dSXiaoliang Yang }; 13597d4b564dSXiaoliang Yang 13607d4b564dSXiaoliang Yang struct felix_stream_filter { 13617d4b564dSXiaoliang Yang struct list_head list; 13627d4b564dSXiaoliang Yang refcount_t refcount; 13637d4b564dSXiaoliang Yang u32 index; 13647d4b564dSXiaoliang Yang u8 enable; 13657d4b564dSXiaoliang Yang u8 sg_valid; 13667d4b564dSXiaoliang Yang u32 sgid; 13677d4b564dSXiaoliang Yang u8 fm_valid; 13687d4b564dSXiaoliang Yang u32 fmid; 13697d4b564dSXiaoliang Yang u8 prio_valid; 13707d4b564dSXiaoliang Yang u8 prio; 13717d4b564dSXiaoliang Yang u32 maxsdu; 13727d4b564dSXiaoliang Yang }; 13737d4b564dSXiaoliang Yang 13747d4b564dSXiaoliang Yang struct felix_stream_filter_counters { 13757d4b564dSXiaoliang Yang u32 match; 13767d4b564dSXiaoliang Yang u32 not_pass_gate; 13777d4b564dSXiaoliang Yang u32 not_pass_sdu; 13787d4b564dSXiaoliang Yang u32 red; 13797d4b564dSXiaoliang Yang }; 13807d4b564dSXiaoliang Yang 138123ae3a78SXiaoliang Yang struct felix_stream_gate { 138223ae3a78SXiaoliang Yang u32 index; 138323ae3a78SXiaoliang Yang u8 enable; 138423ae3a78SXiaoliang Yang u8 ipv_valid; 138523ae3a78SXiaoliang Yang u8 init_ipv; 138623ae3a78SXiaoliang Yang u64 basetime; 138723ae3a78SXiaoliang Yang u64 cycletime; 138823ae3a78SXiaoliang Yang u64 cycletime_ext; 138923ae3a78SXiaoliang Yang u32 num_entries; 139023ae3a78SXiaoliang Yang struct action_gate_entry entries[0]; 139123ae3a78SXiaoliang Yang }; 139223ae3a78SXiaoliang Yang 139323ae3a78SXiaoliang Yang struct felix_stream_gate_entry { 139423ae3a78SXiaoliang Yang struct list_head list; 139523ae3a78SXiaoliang Yang refcount_t refcount; 139623ae3a78SXiaoliang Yang u32 index; 139723ae3a78SXiaoliang Yang }; 139823ae3a78SXiaoliang Yang 13997d4b564dSXiaoliang Yang static int vsc9959_stream_identify(struct flow_cls_offload *f, 14007d4b564dSXiaoliang Yang struct felix_stream *stream) 14017d4b564dSXiaoliang Yang { 14027d4b564dSXiaoliang Yang struct flow_rule *rule = flow_cls_offload_flow_rule(f); 14037d4b564dSXiaoliang Yang struct flow_dissector *dissector = rule->match.dissector; 14047d4b564dSXiaoliang Yang 14057d4b564dSXiaoliang Yang if (dissector->used_keys & 14067d4b564dSXiaoliang Yang ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 14077d4b564dSXiaoliang Yang BIT(FLOW_DISSECTOR_KEY_BASIC) | 14087d4b564dSXiaoliang Yang BIT(FLOW_DISSECTOR_KEY_VLAN) | 14097d4b564dSXiaoliang Yang BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 14107d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14117d4b564dSXiaoliang Yang 14127d4b564dSXiaoliang Yang if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 14137d4b564dSXiaoliang Yang struct flow_match_eth_addrs match; 14147d4b564dSXiaoliang Yang 14157d4b564dSXiaoliang Yang flow_rule_match_eth_addrs(rule, &match); 14167d4b564dSXiaoliang Yang ether_addr_copy(stream->dmac, match.key->dst); 14177d4b564dSXiaoliang Yang if (!is_zero_ether_addr(match.mask->src)) 14187d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14197d4b564dSXiaoliang Yang } else { 14207d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14217d4b564dSXiaoliang Yang } 14227d4b564dSXiaoliang Yang 14237d4b564dSXiaoliang Yang if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 14247d4b564dSXiaoliang Yang struct flow_match_vlan match; 14257d4b564dSXiaoliang Yang 14267d4b564dSXiaoliang Yang flow_rule_match_vlan(rule, &match); 14277d4b564dSXiaoliang Yang if (match.mask->vlan_priority) 14287d4b564dSXiaoliang Yang stream->prio = match.key->vlan_priority; 14297d4b564dSXiaoliang Yang else 14307d4b564dSXiaoliang Yang stream->prio = -1; 14317d4b564dSXiaoliang Yang 14327d4b564dSXiaoliang Yang if (!match.mask->vlan_id) 14337d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14347d4b564dSXiaoliang Yang stream->vid = match.key->vlan_id; 14357d4b564dSXiaoliang Yang } else { 14367d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14377d4b564dSXiaoliang Yang } 14387d4b564dSXiaoliang Yang 14397d4b564dSXiaoliang Yang stream->id = f->cookie; 14407d4b564dSXiaoliang Yang 14417d4b564dSXiaoliang Yang return 0; 14427d4b564dSXiaoliang Yang } 14437d4b564dSXiaoliang Yang 14447d4b564dSXiaoliang Yang static int vsc9959_mact_stream_set(struct ocelot *ocelot, 14457d4b564dSXiaoliang Yang struct felix_stream *stream, 14467d4b564dSXiaoliang Yang struct netlink_ext_ack *extack) 14477d4b564dSXiaoliang Yang { 14487d4b564dSXiaoliang Yang enum macaccess_entry_type type; 14497d4b564dSXiaoliang Yang int ret, sfid, ssid; 14507d4b564dSXiaoliang Yang u32 vid, dst_idx; 14517d4b564dSXiaoliang Yang u8 mac[ETH_ALEN]; 14527d4b564dSXiaoliang Yang 14537d4b564dSXiaoliang Yang ether_addr_copy(mac, stream->dmac); 14547d4b564dSXiaoliang Yang vid = stream->vid; 14557d4b564dSXiaoliang Yang 14567d4b564dSXiaoliang Yang /* Stream identification desn't support to add a stream with non 14577d4b564dSXiaoliang Yang * existent MAC (The MAC entry has not been learned in MAC table). 14587d4b564dSXiaoliang Yang */ 14597d4b564dSXiaoliang Yang ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 14607d4b564dSXiaoliang Yang if (ret) { 14617d4b564dSXiaoliang Yang if (extack) 14627d4b564dSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 14637d4b564dSXiaoliang Yang return -EOPNOTSUPP; 14647d4b564dSXiaoliang Yang } 14657d4b564dSXiaoliang Yang 14667d4b564dSXiaoliang Yang if ((stream->sfid_valid || stream->ssid_valid) && 14677d4b564dSXiaoliang Yang type == ENTRYTYPE_NORMAL) 14687d4b564dSXiaoliang Yang type = ENTRYTYPE_LOCKED; 14697d4b564dSXiaoliang Yang 14707d4b564dSXiaoliang Yang sfid = stream->sfid_valid ? stream->sfid : -1; 14717d4b564dSXiaoliang Yang ssid = stream->ssid_valid ? stream->ssid : -1; 14727d4b564dSXiaoliang Yang 14737d4b564dSXiaoliang Yang ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 14747d4b564dSXiaoliang Yang sfid, ssid); 14757d4b564dSXiaoliang Yang 14767d4b564dSXiaoliang Yang return ret; 14777d4b564dSXiaoliang Yang } 14787d4b564dSXiaoliang Yang 14797d4b564dSXiaoliang Yang static struct felix_stream * 14807d4b564dSXiaoliang Yang vsc9959_stream_table_lookup(struct list_head *stream_list, 14817d4b564dSXiaoliang Yang struct felix_stream *stream) 14827d4b564dSXiaoliang Yang { 14837d4b564dSXiaoliang Yang struct felix_stream *tmp; 14847d4b564dSXiaoliang Yang 14857d4b564dSXiaoliang Yang list_for_each_entry(tmp, stream_list, list) 14867d4b564dSXiaoliang Yang if (ether_addr_equal(tmp->dmac, stream->dmac) && 14877d4b564dSXiaoliang Yang tmp->vid == stream->vid) 14887d4b564dSXiaoliang Yang return tmp; 14897d4b564dSXiaoliang Yang 14907d4b564dSXiaoliang Yang return NULL; 14917d4b564dSXiaoliang Yang } 14927d4b564dSXiaoliang Yang 14937d4b564dSXiaoliang Yang static int vsc9959_stream_table_add(struct ocelot *ocelot, 14947d4b564dSXiaoliang Yang struct list_head *stream_list, 14957d4b564dSXiaoliang Yang struct felix_stream *stream, 14967d4b564dSXiaoliang Yang struct netlink_ext_ack *extack) 14977d4b564dSXiaoliang Yang { 14987d4b564dSXiaoliang Yang struct felix_stream *stream_entry; 14997d4b564dSXiaoliang Yang int ret; 15007d4b564dSXiaoliang Yang 15017d4b564dSXiaoliang Yang stream_entry = kzalloc(sizeof(*stream_entry), GFP_KERNEL); 15027d4b564dSXiaoliang Yang if (!stream_entry) 15037d4b564dSXiaoliang Yang return -ENOMEM; 15047d4b564dSXiaoliang Yang 15057d4b564dSXiaoliang Yang memcpy(stream_entry, stream, sizeof(*stream_entry)); 15067d4b564dSXiaoliang Yang 15077d4b564dSXiaoliang Yang ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 15087d4b564dSXiaoliang Yang if (ret) { 15097d4b564dSXiaoliang Yang kfree(stream_entry); 15107d4b564dSXiaoliang Yang return ret; 15117d4b564dSXiaoliang Yang } 15127d4b564dSXiaoliang Yang 15137d4b564dSXiaoliang Yang list_add_tail(&stream_entry->list, stream_list); 15147d4b564dSXiaoliang Yang 15157d4b564dSXiaoliang Yang return 0; 15167d4b564dSXiaoliang Yang } 15177d4b564dSXiaoliang Yang 15187d4b564dSXiaoliang Yang static struct felix_stream * 15197d4b564dSXiaoliang Yang vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 15207d4b564dSXiaoliang Yang { 15217d4b564dSXiaoliang Yang struct felix_stream *tmp; 15227d4b564dSXiaoliang Yang 15237d4b564dSXiaoliang Yang list_for_each_entry(tmp, stream_list, list) 15247d4b564dSXiaoliang Yang if (tmp->id == id) 15257d4b564dSXiaoliang Yang return tmp; 15267d4b564dSXiaoliang Yang 15277d4b564dSXiaoliang Yang return NULL; 15287d4b564dSXiaoliang Yang } 15297d4b564dSXiaoliang Yang 15307d4b564dSXiaoliang Yang static void vsc9959_stream_table_del(struct ocelot *ocelot, 15317d4b564dSXiaoliang Yang struct felix_stream *stream) 15327d4b564dSXiaoliang Yang { 15337d4b564dSXiaoliang Yang vsc9959_mact_stream_set(ocelot, stream, NULL); 15347d4b564dSXiaoliang Yang 15357d4b564dSXiaoliang Yang list_del(&stream->list); 15367d4b564dSXiaoliang Yang kfree(stream); 15377d4b564dSXiaoliang Yang } 15387d4b564dSXiaoliang Yang 15397d4b564dSXiaoliang Yang static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 15407d4b564dSXiaoliang Yang { 15417d4b564dSXiaoliang Yang return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 15427d4b564dSXiaoliang Yang } 15437d4b564dSXiaoliang Yang 15447d4b564dSXiaoliang Yang static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 15457d4b564dSXiaoliang Yang struct felix_stream_filter *sfi) 15467d4b564dSXiaoliang Yang { 15477d4b564dSXiaoliang Yang u32 val; 15487d4b564dSXiaoliang Yang 15497d4b564dSXiaoliang Yang if (sfi->index > VSC9959_PSFP_SFID_MAX) 15507d4b564dSXiaoliang Yang return -EINVAL; 15517d4b564dSXiaoliang Yang 15527d4b564dSXiaoliang Yang if (!sfi->enable) { 15537d4b564dSXiaoliang Yang ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 15547d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX); 15557d4b564dSXiaoliang Yang 15567d4b564dSXiaoliang Yang val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 15577d4b564dSXiaoliang Yang ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 15587d4b564dSXiaoliang Yang 15597d4b564dSXiaoliang Yang return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 15607d4b564dSXiaoliang Yang (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 15617d4b564dSXiaoliang Yang 10, 100000); 15627d4b564dSXiaoliang Yang } 15637d4b564dSXiaoliang Yang 15647d4b564dSXiaoliang Yang if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 15657d4b564dSXiaoliang Yang sfi->fmid > VSC9959_PSFP_POLICER_MAX) 15667d4b564dSXiaoliang Yang return -EINVAL; 15677d4b564dSXiaoliang Yang 15687d4b564dSXiaoliang Yang ocelot_write(ocelot, 15697d4b564dSXiaoliang Yang (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 15707d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 15717d4b564dSXiaoliang Yang (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 15727d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 15737d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 15747d4b564dSXiaoliang Yang ANA_TABLES_SFIDTIDX); 15757d4b564dSXiaoliang Yang 15767d4b564dSXiaoliang Yang ocelot_write(ocelot, 15777d4b564dSXiaoliang Yang (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 15787d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 15797d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 15807d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 15817d4b564dSXiaoliang Yang ANA_TABLES_SFIDACCESS); 15827d4b564dSXiaoliang Yang 15837d4b564dSXiaoliang Yang return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 15847d4b564dSXiaoliang Yang (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 15857d4b564dSXiaoliang Yang 10, 100000); 15867d4b564dSXiaoliang Yang } 15877d4b564dSXiaoliang Yang 15887d4b564dSXiaoliang Yang static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 15897d4b564dSXiaoliang Yang struct felix_stream_filter *sfi) 15907d4b564dSXiaoliang Yang { 15917d4b564dSXiaoliang Yang struct felix_stream_filter *sfi_entry, *tmp; 15927d4b564dSXiaoliang Yang struct list_head *pos, *q, *last; 15937d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 15947d4b564dSXiaoliang Yang u32 insert = 0; 15957d4b564dSXiaoliang Yang int ret; 15967d4b564dSXiaoliang Yang 15977d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 15987d4b564dSXiaoliang Yang last = &psfp->sfi_list; 15997d4b564dSXiaoliang Yang 16007d4b564dSXiaoliang Yang list_for_each_safe(pos, q, &psfp->sfi_list) { 16017d4b564dSXiaoliang Yang tmp = list_entry(pos, struct felix_stream_filter, list); 16027d4b564dSXiaoliang Yang if (sfi->sg_valid == tmp->sg_valid && 16037d4b564dSXiaoliang Yang sfi->fm_valid == tmp->fm_valid && 16047d4b564dSXiaoliang Yang tmp->sgid == sfi->sgid && 16057d4b564dSXiaoliang Yang tmp->fmid == sfi->fmid) { 16067d4b564dSXiaoliang Yang sfi->index = tmp->index; 16077d4b564dSXiaoliang Yang refcount_inc(&tmp->refcount); 16087d4b564dSXiaoliang Yang return 0; 16097d4b564dSXiaoliang Yang } 16107d4b564dSXiaoliang Yang /* Make sure that the index is increasing in order. */ 16117d4b564dSXiaoliang Yang if (tmp->index == insert) { 16127d4b564dSXiaoliang Yang last = pos; 16137d4b564dSXiaoliang Yang insert++; 16147d4b564dSXiaoliang Yang } 16157d4b564dSXiaoliang Yang } 16167d4b564dSXiaoliang Yang sfi->index = insert; 16177d4b564dSXiaoliang Yang 16187d4b564dSXiaoliang Yang sfi_entry = kzalloc(sizeof(*sfi_entry), GFP_KERNEL); 16197d4b564dSXiaoliang Yang if (!sfi_entry) 16207d4b564dSXiaoliang Yang return -ENOMEM; 16217d4b564dSXiaoliang Yang 16227d4b564dSXiaoliang Yang memcpy(sfi_entry, sfi, sizeof(*sfi_entry)); 16237d4b564dSXiaoliang Yang refcount_set(&sfi_entry->refcount, 1); 16247d4b564dSXiaoliang Yang 16257d4b564dSXiaoliang Yang ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 16267d4b564dSXiaoliang Yang if (ret) { 16277d4b564dSXiaoliang Yang kfree(sfi_entry); 16287d4b564dSXiaoliang Yang return ret; 16297d4b564dSXiaoliang Yang } 16307d4b564dSXiaoliang Yang 16317d4b564dSXiaoliang Yang list_add(&sfi_entry->list, last); 16327d4b564dSXiaoliang Yang 16337d4b564dSXiaoliang Yang return 0; 16347d4b564dSXiaoliang Yang } 16357d4b564dSXiaoliang Yang 163623ae3a78SXiaoliang Yang static struct felix_stream_filter * 163723ae3a78SXiaoliang Yang vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 163823ae3a78SXiaoliang Yang { 163923ae3a78SXiaoliang Yang struct felix_stream_filter *tmp; 164023ae3a78SXiaoliang Yang 164123ae3a78SXiaoliang Yang list_for_each_entry(tmp, sfi_list, list) 164223ae3a78SXiaoliang Yang if (tmp->index == index) 164323ae3a78SXiaoliang Yang return tmp; 164423ae3a78SXiaoliang Yang 164523ae3a78SXiaoliang Yang return NULL; 164623ae3a78SXiaoliang Yang } 164723ae3a78SXiaoliang Yang 16487d4b564dSXiaoliang Yang static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 16497d4b564dSXiaoliang Yang { 16507d4b564dSXiaoliang Yang struct felix_stream_filter *tmp, *n; 16517d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 16527d4b564dSXiaoliang Yang u8 z; 16537d4b564dSXiaoliang Yang 16547d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 16557d4b564dSXiaoliang Yang 16567d4b564dSXiaoliang Yang list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 16577d4b564dSXiaoliang Yang if (tmp->index == index) { 16587d4b564dSXiaoliang Yang z = refcount_dec_and_test(&tmp->refcount); 16597d4b564dSXiaoliang Yang if (z) { 16607d4b564dSXiaoliang Yang tmp->enable = 0; 16617d4b564dSXiaoliang Yang vsc9959_psfp_sfi_set(ocelot, tmp); 16627d4b564dSXiaoliang Yang list_del(&tmp->list); 16637d4b564dSXiaoliang Yang kfree(tmp); 16647d4b564dSXiaoliang Yang } 16657d4b564dSXiaoliang Yang break; 16667d4b564dSXiaoliang Yang } 16677d4b564dSXiaoliang Yang } 16687d4b564dSXiaoliang Yang 166923ae3a78SXiaoliang Yang static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 167023ae3a78SXiaoliang Yang struct felix_stream_gate *sgi) 167123ae3a78SXiaoliang Yang { 167223ae3a78SXiaoliang Yang sgi->index = entry->gate.index; 167323ae3a78SXiaoliang Yang sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 167423ae3a78SXiaoliang Yang sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 167523ae3a78SXiaoliang Yang sgi->basetime = entry->gate.basetime; 167623ae3a78SXiaoliang Yang sgi->cycletime = entry->gate.cycletime; 167723ae3a78SXiaoliang Yang sgi->num_entries = entry->gate.num_entries; 167823ae3a78SXiaoliang Yang sgi->enable = 1; 167923ae3a78SXiaoliang Yang 168023ae3a78SXiaoliang Yang memcpy(sgi->entries, entry->gate.entries, 168123ae3a78SXiaoliang Yang entry->gate.num_entries * sizeof(struct action_gate_entry)); 168223ae3a78SXiaoliang Yang } 168323ae3a78SXiaoliang Yang 168423ae3a78SXiaoliang Yang static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 168523ae3a78SXiaoliang Yang { 168623ae3a78SXiaoliang Yang return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 168723ae3a78SXiaoliang Yang } 168823ae3a78SXiaoliang Yang 168923ae3a78SXiaoliang Yang static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 169023ae3a78SXiaoliang Yang struct felix_stream_gate *sgi) 169123ae3a78SXiaoliang Yang { 169223ae3a78SXiaoliang Yang struct action_gate_entry *e; 169323ae3a78SXiaoliang Yang struct timespec64 base_ts; 169423ae3a78SXiaoliang Yang u32 interval_sum = 0; 169523ae3a78SXiaoliang Yang u32 val; 169623ae3a78SXiaoliang Yang int i; 169723ae3a78SXiaoliang Yang 169823ae3a78SXiaoliang Yang if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 169923ae3a78SXiaoliang Yang return -EINVAL; 170023ae3a78SXiaoliang Yang 170123ae3a78SXiaoliang Yang ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 170223ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL); 170323ae3a78SXiaoliang Yang 170423ae3a78SXiaoliang Yang if (!sgi->enable) { 170523ae3a78SXiaoliang Yang ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 170623ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 170723ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_GATE_ENABLE, 170823ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3); 170923ae3a78SXiaoliang Yang 171023ae3a78SXiaoliang Yang return 0; 171123ae3a78SXiaoliang Yang } 171223ae3a78SXiaoliang Yang 171323ae3a78SXiaoliang Yang if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 171423ae3a78SXiaoliang Yang sgi->cycletime > NSEC_PER_SEC) 171523ae3a78SXiaoliang Yang return -EINVAL; 171623ae3a78SXiaoliang Yang 171723ae3a78SXiaoliang Yang if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 171823ae3a78SXiaoliang Yang return -EINVAL; 171923ae3a78SXiaoliang Yang 172023ae3a78SXiaoliang Yang vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 172123ae3a78SXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 172223ae3a78SXiaoliang Yang val = lower_32_bits(base_ts.tv_sec); 172323ae3a78SXiaoliang Yang ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 172423ae3a78SXiaoliang Yang 172523ae3a78SXiaoliang Yang val = upper_32_bits(base_ts.tv_sec); 172623ae3a78SXiaoliang Yang ocelot_write(ocelot, 172723ae3a78SXiaoliang Yang (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 172823ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 172923ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_GATE_ENABLE | 173023ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 173123ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 173223ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 173323ae3a78SXiaoliang Yang ANA_SG_CONFIG_REG_3); 173423ae3a78SXiaoliang Yang 173523ae3a78SXiaoliang Yang ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 173623ae3a78SXiaoliang Yang 173723ae3a78SXiaoliang Yang e = sgi->entries; 173823ae3a78SXiaoliang Yang for (i = 0; i < sgi->num_entries; i++) { 173923ae3a78SXiaoliang Yang u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 174023ae3a78SXiaoliang Yang 174123ae3a78SXiaoliang Yang ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 174223ae3a78SXiaoliang Yang (e[i].gate_state ? 174323ae3a78SXiaoliang Yang ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 174423ae3a78SXiaoliang Yang ANA_SG_GCL_GS_CONFIG, i); 174523ae3a78SXiaoliang Yang 174623ae3a78SXiaoliang Yang interval_sum += e[i].interval; 174723ae3a78SXiaoliang Yang ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 174823ae3a78SXiaoliang Yang } 174923ae3a78SXiaoliang Yang 175023ae3a78SXiaoliang Yang ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 175123ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 175223ae3a78SXiaoliang Yang ANA_SG_ACCESS_CTRL); 175323ae3a78SXiaoliang Yang 175423ae3a78SXiaoliang Yang return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 175523ae3a78SXiaoliang Yang (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 175623ae3a78SXiaoliang Yang 10, 100000); 175723ae3a78SXiaoliang Yang } 175823ae3a78SXiaoliang Yang 175923ae3a78SXiaoliang Yang static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 176023ae3a78SXiaoliang Yang struct felix_stream_gate *sgi) 176123ae3a78SXiaoliang Yang { 176223ae3a78SXiaoliang Yang struct felix_stream_gate_entry *tmp; 176323ae3a78SXiaoliang Yang struct ocelot_psfp_list *psfp; 176423ae3a78SXiaoliang Yang int ret; 176523ae3a78SXiaoliang Yang 176623ae3a78SXiaoliang Yang psfp = &ocelot->psfp; 176723ae3a78SXiaoliang Yang 176823ae3a78SXiaoliang Yang list_for_each_entry(tmp, &psfp->sgi_list, list) 176923ae3a78SXiaoliang Yang if (tmp->index == sgi->index) { 177023ae3a78SXiaoliang Yang refcount_inc(&tmp->refcount); 177123ae3a78SXiaoliang Yang return 0; 177223ae3a78SXiaoliang Yang } 177323ae3a78SXiaoliang Yang 177423ae3a78SXiaoliang Yang tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 177523ae3a78SXiaoliang Yang if (!tmp) 177623ae3a78SXiaoliang Yang return -ENOMEM; 177723ae3a78SXiaoliang Yang 177823ae3a78SXiaoliang Yang ret = vsc9959_psfp_sgi_set(ocelot, sgi); 177923ae3a78SXiaoliang Yang if (ret) { 178023ae3a78SXiaoliang Yang kfree(tmp); 178123ae3a78SXiaoliang Yang return ret; 178223ae3a78SXiaoliang Yang } 178323ae3a78SXiaoliang Yang 178423ae3a78SXiaoliang Yang tmp->index = sgi->index; 178523ae3a78SXiaoliang Yang refcount_set(&tmp->refcount, 1); 178623ae3a78SXiaoliang Yang list_add_tail(&tmp->list, &psfp->sgi_list); 178723ae3a78SXiaoliang Yang 178823ae3a78SXiaoliang Yang return 0; 178923ae3a78SXiaoliang Yang } 179023ae3a78SXiaoliang Yang 179123ae3a78SXiaoliang Yang static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 179223ae3a78SXiaoliang Yang u32 index) 179323ae3a78SXiaoliang Yang { 179423ae3a78SXiaoliang Yang struct felix_stream_gate_entry *tmp, *n; 179523ae3a78SXiaoliang Yang struct felix_stream_gate sgi = {0}; 179623ae3a78SXiaoliang Yang struct ocelot_psfp_list *psfp; 179723ae3a78SXiaoliang Yang u8 z; 179823ae3a78SXiaoliang Yang 179923ae3a78SXiaoliang Yang psfp = &ocelot->psfp; 180023ae3a78SXiaoliang Yang 180123ae3a78SXiaoliang Yang list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 180223ae3a78SXiaoliang Yang if (tmp->index == index) { 180323ae3a78SXiaoliang Yang z = refcount_dec_and_test(&tmp->refcount); 180423ae3a78SXiaoliang Yang if (z) { 180523ae3a78SXiaoliang Yang sgi.index = index; 180623ae3a78SXiaoliang Yang sgi.enable = 0; 180723ae3a78SXiaoliang Yang vsc9959_psfp_sgi_set(ocelot, &sgi); 180823ae3a78SXiaoliang Yang list_del(&tmp->list); 180923ae3a78SXiaoliang Yang kfree(tmp); 181023ae3a78SXiaoliang Yang } 181123ae3a78SXiaoliang Yang break; 181223ae3a78SXiaoliang Yang } 181323ae3a78SXiaoliang Yang } 181423ae3a78SXiaoliang Yang 18157d4b564dSXiaoliang Yang static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index, 18167d4b564dSXiaoliang Yang struct felix_stream_filter_counters *counters) 18177d4b564dSXiaoliang Yang { 18187d4b564dSXiaoliang Yang ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index), 18197d4b564dSXiaoliang Yang SYS_STAT_CFG_STAT_VIEW_M, 18207d4b564dSXiaoliang Yang SYS_STAT_CFG); 18217d4b564dSXiaoliang Yang 18227d4b564dSXiaoliang Yang counters->match = ocelot_read_gix(ocelot, SYS_CNT, 0x200); 18237d4b564dSXiaoliang Yang counters->not_pass_gate = ocelot_read_gix(ocelot, SYS_CNT, 0x201); 18247d4b564dSXiaoliang Yang counters->not_pass_sdu = ocelot_read_gix(ocelot, SYS_CNT, 0x202); 18257d4b564dSXiaoliang Yang counters->red = ocelot_read_gix(ocelot, SYS_CNT, 0x203); 18267d4b564dSXiaoliang Yang 18277d4b564dSXiaoliang Yang /* Clear the PSFP counter. */ 18287d4b564dSXiaoliang Yang ocelot_write(ocelot, 18297d4b564dSXiaoliang Yang SYS_STAT_CFG_STAT_VIEW(index) | 18307d4b564dSXiaoliang Yang SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 18317d4b564dSXiaoliang Yang SYS_STAT_CFG); 18327d4b564dSXiaoliang Yang } 18337d4b564dSXiaoliang Yang 18347d4b564dSXiaoliang Yang static int vsc9959_psfp_filter_add(struct ocelot *ocelot, 18357d4b564dSXiaoliang Yang struct flow_cls_offload *f) 18367d4b564dSXiaoliang Yang { 18377d4b564dSXiaoliang Yang struct netlink_ext_ack *extack = f->common.extack; 18387d4b564dSXiaoliang Yang struct felix_stream_filter sfi = {0}; 18397d4b564dSXiaoliang Yang const struct flow_action_entry *a; 18407d4b564dSXiaoliang Yang struct felix_stream *stream_entry; 18417d4b564dSXiaoliang Yang struct felix_stream stream = {0}; 184223ae3a78SXiaoliang Yang struct felix_stream_gate *sgi; 18437d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 184423ae3a78SXiaoliang Yang int ret, i, size; 18457d4b564dSXiaoliang Yang 18467d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 18477d4b564dSXiaoliang Yang 18487d4b564dSXiaoliang Yang ret = vsc9959_stream_identify(f, &stream); 18497d4b564dSXiaoliang Yang if (ret) { 18507d4b564dSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 18517d4b564dSXiaoliang Yang return ret; 18527d4b564dSXiaoliang Yang } 18537d4b564dSXiaoliang Yang 18547d4b564dSXiaoliang Yang flow_action_for_each(i, a, &f->rule->action) { 18557d4b564dSXiaoliang Yang switch (a->id) { 18567d4b564dSXiaoliang Yang case FLOW_ACTION_GATE: 185723ae3a78SXiaoliang Yang size = struct_size(sgi, entries, a->gate.num_entries); 185823ae3a78SXiaoliang Yang sgi = kzalloc(size, GFP_KERNEL); 185923ae3a78SXiaoliang Yang vsc9959_psfp_parse_gate(a, sgi); 186023ae3a78SXiaoliang Yang ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 186123ae3a78SXiaoliang Yang if (ret) { 186223ae3a78SXiaoliang Yang kfree(sgi); 186323ae3a78SXiaoliang Yang return ret; 186423ae3a78SXiaoliang Yang } 186523ae3a78SXiaoliang Yang sfi.sg_valid = 1; 186623ae3a78SXiaoliang Yang sfi.sgid = sgi->index; 186723ae3a78SXiaoliang Yang kfree(sgi); 186823ae3a78SXiaoliang Yang break; 18697d4b564dSXiaoliang Yang case FLOW_ACTION_POLICE: 18707d4b564dSXiaoliang Yang default: 18717d4b564dSXiaoliang Yang return -EOPNOTSUPP; 18727d4b564dSXiaoliang Yang } 18737d4b564dSXiaoliang Yang } 18747d4b564dSXiaoliang Yang 18757d4b564dSXiaoliang Yang /* Check if stream is set. */ 18767d4b564dSXiaoliang Yang stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 18777d4b564dSXiaoliang Yang if (stream_entry) { 18787d4b564dSXiaoliang Yang NL_SET_ERR_MSG_MOD(extack, "This stream is already added"); 187923ae3a78SXiaoliang Yang ret = -EEXIST; 188023ae3a78SXiaoliang Yang goto err; 18817d4b564dSXiaoliang Yang } 18827d4b564dSXiaoliang Yang 18837d4b564dSXiaoliang Yang sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 18847d4b564dSXiaoliang Yang sfi.prio = (sfi.prio_valid ? stream.prio : 0); 18857d4b564dSXiaoliang Yang sfi.enable = 1; 18867d4b564dSXiaoliang Yang 18877d4b564dSXiaoliang Yang ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 18887d4b564dSXiaoliang Yang if (ret) 188923ae3a78SXiaoliang Yang goto err; 18907d4b564dSXiaoliang Yang 18917d4b564dSXiaoliang Yang stream.sfid = sfi.index; 18927d4b564dSXiaoliang Yang stream.sfid_valid = 1; 18937d4b564dSXiaoliang Yang ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 18947d4b564dSXiaoliang Yang &stream, extack); 189523ae3a78SXiaoliang Yang if (ret) { 18967d4b564dSXiaoliang Yang vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 189723ae3a78SXiaoliang Yang goto err; 189823ae3a78SXiaoliang Yang } 189923ae3a78SXiaoliang Yang 190023ae3a78SXiaoliang Yang return 0; 190123ae3a78SXiaoliang Yang 190223ae3a78SXiaoliang Yang err: 190323ae3a78SXiaoliang Yang if (sfi.sg_valid) 190423ae3a78SXiaoliang Yang vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 19057d4b564dSXiaoliang Yang 19067d4b564dSXiaoliang Yang return ret; 19077d4b564dSXiaoliang Yang } 19087d4b564dSXiaoliang Yang 19097d4b564dSXiaoliang Yang static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 19107d4b564dSXiaoliang Yang struct flow_cls_offload *f) 19117d4b564dSXiaoliang Yang { 191223ae3a78SXiaoliang Yang static struct felix_stream_filter *sfi; 19137d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 19147d4b564dSXiaoliang Yang struct felix_stream *stream; 19157d4b564dSXiaoliang Yang 19167d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 19177d4b564dSXiaoliang Yang 19187d4b564dSXiaoliang Yang stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 19197d4b564dSXiaoliang Yang if (!stream) 19207d4b564dSXiaoliang Yang return -ENOMEM; 19217d4b564dSXiaoliang Yang 192223ae3a78SXiaoliang Yang sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 192323ae3a78SXiaoliang Yang if (!sfi) 192423ae3a78SXiaoliang Yang return -ENOMEM; 192523ae3a78SXiaoliang Yang 192623ae3a78SXiaoliang Yang if (sfi->sg_valid) 192723ae3a78SXiaoliang Yang vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 192823ae3a78SXiaoliang Yang 19297d4b564dSXiaoliang Yang vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 19307d4b564dSXiaoliang Yang 19317d4b564dSXiaoliang Yang stream->sfid_valid = 0; 19327d4b564dSXiaoliang Yang vsc9959_stream_table_del(ocelot, stream); 19337d4b564dSXiaoliang Yang 19347d4b564dSXiaoliang Yang return 0; 19357d4b564dSXiaoliang Yang } 19367d4b564dSXiaoliang Yang 19377d4b564dSXiaoliang Yang static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 19387d4b564dSXiaoliang Yang struct flow_cls_offload *f, 19397d4b564dSXiaoliang Yang struct flow_stats *stats) 19407d4b564dSXiaoliang Yang { 19417d4b564dSXiaoliang Yang struct felix_stream_filter_counters counters; 19427d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp; 19437d4b564dSXiaoliang Yang struct felix_stream *stream; 19447d4b564dSXiaoliang Yang 19457d4b564dSXiaoliang Yang psfp = &ocelot->psfp; 19467d4b564dSXiaoliang Yang stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 19477d4b564dSXiaoliang Yang if (!stream) 19487d4b564dSXiaoliang Yang return -ENOMEM; 19497d4b564dSXiaoliang Yang 19507d4b564dSXiaoliang Yang vsc9959_psfp_counters_get(ocelot, stream->sfid, &counters); 19517d4b564dSXiaoliang Yang 19527d4b564dSXiaoliang Yang stats->pkts = counters.match; 19537d4b564dSXiaoliang Yang stats->drops = counters.not_pass_gate + counters.not_pass_sdu + 19547d4b564dSXiaoliang Yang counters.red; 19557d4b564dSXiaoliang Yang 19567d4b564dSXiaoliang Yang return 0; 19577d4b564dSXiaoliang Yang } 19587d4b564dSXiaoliang Yang 19597d4b564dSXiaoliang Yang static void vsc9959_psfp_init(struct ocelot *ocelot) 19607d4b564dSXiaoliang Yang { 19617d4b564dSXiaoliang Yang struct ocelot_psfp_list *psfp = &ocelot->psfp; 19627d4b564dSXiaoliang Yang 19637d4b564dSXiaoliang Yang INIT_LIST_HEAD(&psfp->stream_list); 19647d4b564dSXiaoliang Yang INIT_LIST_HEAD(&psfp->sfi_list); 19657d4b564dSXiaoliang Yang INIT_LIST_HEAD(&psfp->sgi_list); 19667d4b564dSXiaoliang Yang } 19677d4b564dSXiaoliang Yang 19687d4b564dSXiaoliang Yang static const struct ocelot_ops vsc9959_ops = { 19697d4b564dSXiaoliang Yang .reset = vsc9959_reset, 19707d4b564dSXiaoliang Yang .wm_enc = vsc9959_wm_enc, 19717d4b564dSXiaoliang Yang .wm_dec = vsc9959_wm_dec, 19727d4b564dSXiaoliang Yang .wm_stat = vsc9959_wm_stat, 19737d4b564dSXiaoliang Yang .port_to_netdev = felix_port_to_netdev, 19747d4b564dSXiaoliang Yang .netdev_to_port = felix_netdev_to_port, 19757d4b564dSXiaoliang Yang .psfp_init = vsc9959_psfp_init, 19767d4b564dSXiaoliang Yang .psfp_filter_add = vsc9959_psfp_filter_add, 19777d4b564dSXiaoliang Yang .psfp_filter_del = vsc9959_psfp_filter_del, 19787d4b564dSXiaoliang Yang .psfp_stats_get = vsc9959_psfp_stats_get, 19797d4b564dSXiaoliang Yang }; 19807d4b564dSXiaoliang Yang 1981375e1314SVladimir Oltean static const struct felix_info felix_info_vsc9959 = { 198256051948SVladimir Oltean .target_io_res = vsc9959_target_io_res, 198356051948SVladimir Oltean .port_io_res = vsc9959_port_io_res, 1984bdeced75SVladimir Oltean .imdio_res = &vsc9959_imdio_res, 198556051948SVladimir Oltean .regfields = vsc9959_regfields, 198656051948SVladimir Oltean .map = vsc9959_regmap, 198756051948SVladimir Oltean .ops = &vsc9959_ops, 198856051948SVladimir Oltean .stats_layout = vsc9959_stats_layout, 198956051948SVladimir Oltean .num_stats = ARRAY_SIZE(vsc9959_stats_layout), 199007d985eeSVladimir Oltean .vcap = vsc9959_vcap_props, 1991*77043c37SXiaoliang Yang .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 1992*77043c37SXiaoliang Yang .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 1993*77043c37SXiaoliang Yang .vcap_pol_base2 = 0, 1994*77043c37SXiaoliang Yang .vcap_pol_max2 = 0, 199521ce7f3eSVladimir Oltean .num_mact_rows = 2048, 199656051948SVladimir Oltean .num_ports = 6, 199770d39a6eSVladimir Oltean .num_tx_queues = OCELOT_NUM_TC, 1998bdeced75SVladimir Oltean .switch_pci_bar = 4, 1999bdeced75SVladimir Oltean .imdio_pci_bar = 0, 2000c8c0ba4fSVladimir Oltean .quirk_no_xtr_irq = true, 20012ac7c6c5SVladimir Oltean .ptp_caps = &vsc9959_ptp_caps, 2002bdeced75SVladimir Oltean .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2003bdeced75SVladimir Oltean .mdio_bus_free = vsc9959_mdio_bus_free, 2004375e1314SVladimir Oltean .phylink_validate = vsc9959_phylink_validate, 2005bdeced75SVladimir Oltean .prevalidate_phy_mode = vsc9959_prevalidate_phy_mode, 2006de143c0eSXiaoliang Yang .port_setup_tc = vsc9959_port_setup_tc, 2007de143c0eSXiaoliang Yang .port_sched_speed_set = vsc9959_sched_speed_set, 200856051948SVladimir Oltean }; 2009375e1314SVladimir Oltean 2010375e1314SVladimir Oltean static irqreturn_t felix_irq_handler(int irq, void *data) 2011375e1314SVladimir Oltean { 2012375e1314SVladimir Oltean struct ocelot *ocelot = (struct ocelot *)data; 2013375e1314SVladimir Oltean 2014375e1314SVladimir Oltean /* The INTB interrupt is used for both PTP TX timestamp interrupt 2015375e1314SVladimir Oltean * and preemption status change interrupt on each port. 2016375e1314SVladimir Oltean * 2017375e1314SVladimir Oltean * - Get txtstamp if have 2018375e1314SVladimir Oltean * - TODO: handle preemption. Without handling it, driver may get 2019375e1314SVladimir Oltean * interrupt storm. 2020375e1314SVladimir Oltean */ 2021375e1314SVladimir Oltean 2022375e1314SVladimir Oltean ocelot_get_txtstamp(ocelot); 2023375e1314SVladimir Oltean 2024375e1314SVladimir Oltean return IRQ_HANDLED; 2025375e1314SVladimir Oltean } 2026375e1314SVladimir Oltean 2027375e1314SVladimir Oltean static int felix_pci_probe(struct pci_dev *pdev, 2028375e1314SVladimir Oltean const struct pci_device_id *id) 2029375e1314SVladimir Oltean { 2030375e1314SVladimir Oltean struct dsa_switch *ds; 2031375e1314SVladimir Oltean struct ocelot *ocelot; 2032375e1314SVladimir Oltean struct felix *felix; 2033375e1314SVladimir Oltean int err; 2034375e1314SVladimir Oltean 2035375e1314SVladimir Oltean if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 2036375e1314SVladimir Oltean dev_info(&pdev->dev, "device is disabled, skipping\n"); 2037375e1314SVladimir Oltean return -ENODEV; 2038375e1314SVladimir Oltean } 2039375e1314SVladimir Oltean 2040375e1314SVladimir Oltean err = pci_enable_device(pdev); 2041375e1314SVladimir Oltean if (err) { 2042375e1314SVladimir Oltean dev_err(&pdev->dev, "device enable failed\n"); 2043375e1314SVladimir Oltean goto err_pci_enable; 2044375e1314SVladimir Oltean } 2045375e1314SVladimir Oltean 2046375e1314SVladimir Oltean felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 2047375e1314SVladimir Oltean if (!felix) { 2048375e1314SVladimir Oltean err = -ENOMEM; 2049375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 2050375e1314SVladimir Oltean goto err_alloc_felix; 2051375e1314SVladimir Oltean } 2052375e1314SVladimir Oltean 2053375e1314SVladimir Oltean pci_set_drvdata(pdev, felix); 2054375e1314SVladimir Oltean ocelot = &felix->ocelot; 2055375e1314SVladimir Oltean ocelot->dev = &pdev->dev; 205670d39a6eSVladimir Oltean ocelot->num_flooding_pgids = OCELOT_NUM_TC; 2057375e1314SVladimir Oltean felix->info = &felix_info_vsc9959; 2058375e1314SVladimir Oltean felix->switch_base = pci_resource_start(pdev, 2059375e1314SVladimir Oltean felix->info->switch_pci_bar); 2060375e1314SVladimir Oltean felix->imdio_base = pci_resource_start(pdev, 2061375e1314SVladimir Oltean felix->info->imdio_pci_bar); 2062375e1314SVladimir Oltean 2063375e1314SVladimir Oltean pci_set_master(pdev); 2064375e1314SVladimir Oltean 2065375e1314SVladimir Oltean err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 2066375e1314SVladimir Oltean &felix_irq_handler, IRQF_ONESHOT, 2067375e1314SVladimir Oltean "felix-intb", ocelot); 2068375e1314SVladimir Oltean if (err) { 2069375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to request irq\n"); 2070375e1314SVladimir Oltean goto err_alloc_irq; 2071375e1314SVladimir Oltean } 2072375e1314SVladimir Oltean 2073375e1314SVladimir Oltean ocelot->ptp = 1; 2074375e1314SVladimir Oltean 2075375e1314SVladimir Oltean ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 2076375e1314SVladimir Oltean if (!ds) { 2077375e1314SVladimir Oltean err = -ENOMEM; 2078375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 2079375e1314SVladimir Oltean goto err_alloc_ds; 2080375e1314SVladimir Oltean } 2081375e1314SVladimir Oltean 2082375e1314SVladimir Oltean ds->dev = &pdev->dev; 2083375e1314SVladimir Oltean ds->num_ports = felix->info->num_ports; 2084375e1314SVladimir Oltean ds->num_tx_queues = felix->info->num_tx_queues; 2085375e1314SVladimir Oltean ds->ops = &felix_switch_ops; 2086375e1314SVladimir Oltean ds->priv = ocelot; 2087375e1314SVladimir Oltean felix->ds = ds; 2088adb3dccfSVladimir Oltean felix->tag_proto = DSA_TAG_PROTO_OCELOT; 2089375e1314SVladimir Oltean 2090375e1314SVladimir Oltean err = dsa_register_switch(ds); 2091375e1314SVladimir Oltean if (err) { 2092375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err); 2093375e1314SVladimir Oltean goto err_register_ds; 2094375e1314SVladimir Oltean } 2095375e1314SVladimir Oltean 2096375e1314SVladimir Oltean return 0; 2097375e1314SVladimir Oltean 2098375e1314SVladimir Oltean err_register_ds: 2099375e1314SVladimir Oltean kfree(ds); 2100375e1314SVladimir Oltean err_alloc_ds: 2101375e1314SVladimir Oltean err_alloc_irq: 2102375e1314SVladimir Oltean kfree(felix); 2103537e2b88SVladimir Oltean err_alloc_felix: 2104375e1314SVladimir Oltean pci_disable_device(pdev); 2105375e1314SVladimir Oltean err_pci_enable: 2106375e1314SVladimir Oltean return err; 2107375e1314SVladimir Oltean } 2108375e1314SVladimir Oltean 2109375e1314SVladimir Oltean static void felix_pci_remove(struct pci_dev *pdev) 2110375e1314SVladimir Oltean { 21110650bf52SVladimir Oltean struct felix *felix = pci_get_drvdata(pdev); 2112375e1314SVladimir Oltean 21130650bf52SVladimir Oltean if (!felix) 21140650bf52SVladimir Oltean return; 2115375e1314SVladimir Oltean 2116375e1314SVladimir Oltean dsa_unregister_switch(felix->ds); 2117375e1314SVladimir Oltean 2118375e1314SVladimir Oltean kfree(felix->ds); 2119375e1314SVladimir Oltean kfree(felix); 2120375e1314SVladimir Oltean 2121375e1314SVladimir Oltean pci_disable_device(pdev); 21220650bf52SVladimir Oltean 21230650bf52SVladimir Oltean pci_set_drvdata(pdev, NULL); 21240650bf52SVladimir Oltean } 21250650bf52SVladimir Oltean 21260650bf52SVladimir Oltean static void felix_pci_shutdown(struct pci_dev *pdev) 21270650bf52SVladimir Oltean { 21280650bf52SVladimir Oltean struct felix *felix = pci_get_drvdata(pdev); 21290650bf52SVladimir Oltean 21300650bf52SVladimir Oltean if (!felix) 21310650bf52SVladimir Oltean return; 21320650bf52SVladimir Oltean 21330650bf52SVladimir Oltean dsa_switch_shutdown(felix->ds); 21340650bf52SVladimir Oltean 21350650bf52SVladimir Oltean pci_set_drvdata(pdev, NULL); 2136375e1314SVladimir Oltean } 2137375e1314SVladimir Oltean 2138375e1314SVladimir Oltean static struct pci_device_id felix_ids[] = { 2139375e1314SVladimir Oltean { 2140375e1314SVladimir Oltean /* NXP LS1028A */ 2141375e1314SVladimir Oltean PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 2142375e1314SVladimir Oltean }, 2143375e1314SVladimir Oltean { 0, } 2144375e1314SVladimir Oltean }; 2145375e1314SVladimir Oltean MODULE_DEVICE_TABLE(pci, felix_ids); 2146375e1314SVladimir Oltean 2147d60bc62dSVladimir Oltean static struct pci_driver felix_vsc9959_pci_driver = { 2148375e1314SVladimir Oltean .name = "mscc_felix", 2149375e1314SVladimir Oltean .id_table = felix_ids, 2150375e1314SVladimir Oltean .probe = felix_pci_probe, 2151375e1314SVladimir Oltean .remove = felix_pci_remove, 21520650bf52SVladimir Oltean .shutdown = felix_pci_shutdown, 2153375e1314SVladimir Oltean }; 2154d60bc62dSVladimir Oltean module_pci_driver(felix_vsc9959_pci_driver); 2155d60bc62dSVladimir Oltean 2156d60bc62dSVladimir Oltean MODULE_DESCRIPTION("Felix Switch driver"); 2157d60bc62dSVladimir Oltean MODULE_LICENSE("GPL v2"); 2158