156051948SVladimir Oltean // SPDX-License-Identifier: (GPL-2.0 OR MIT) 256051948SVladimir Oltean /* Copyright 2017 Microsemi Corporation 356051948SVladimir Oltean * Copyright 2018-2019 NXP Semiconductors 456051948SVladimir Oltean */ 5bdeced75SVladimir Oltean #include <linux/fsl/enetc_mdio.h> 6de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_qsys.h> 707d985eeSVladimir Oltean #include <soc/mscc/ocelot_vcap.h> 8de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_ptp.h> 956051948SVladimir Oltean #include <soc/mscc/ocelot_sys.h> 1056051948SVladimir Oltean #include <soc/mscc/ocelot.h> 1167c24049SVladimir Oltean #include <linux/packing.h> 12588d0550SIoana Ciornei #include <linux/pcs-lynx.h> 13de143c0eSXiaoliang Yang #include <net/pkt_sched.h> 1456051948SVladimir Oltean #include <linux/iopoll.h> 1516659b81SMichael Walle #include <linux/mdio.h> 1656051948SVladimir Oltean #include <linux/pci.h> 1756051948SVladimir Oltean #include "felix.h" 1856051948SVladimir Oltean 1907d985eeSVladimir Oltean #define VSC9959_VCAP_IS2_CNT 1024 2007d985eeSVladimir Oltean #define VSC9959_VCAP_IS2_ENTRY_WIDTH 376 2107d985eeSVladimir Oltean #define VSC9959_VCAP_PORT_CNT 6 22de143c0eSXiaoliang Yang #define VSC9959_TAS_GCL_ENTRY_MAX 63 23de143c0eSXiaoliang Yang 2456051948SVladimir Oltean static const u32 vsc9959_ana_regmap[] = { 2556051948SVladimir Oltean REG(ANA_ADVLEARN, 0x0089a0), 2656051948SVladimir Oltean REG(ANA_VLANMASK, 0x0089a4), 2756051948SVladimir Oltean REG_RESERVED(ANA_PORT_B_DOMAIN), 2856051948SVladimir Oltean REG(ANA_ANAGEFIL, 0x0089ac), 2956051948SVladimir Oltean REG(ANA_ANEVENTS, 0x0089b0), 3056051948SVladimir Oltean REG(ANA_STORMLIMIT_BURST, 0x0089b4), 3156051948SVladimir Oltean REG(ANA_STORMLIMIT_CFG, 0x0089b8), 3256051948SVladimir Oltean REG(ANA_ISOLATED_PORTS, 0x0089c8), 3356051948SVladimir Oltean REG(ANA_COMMUNITY_PORTS, 0x0089cc), 3456051948SVladimir Oltean REG(ANA_AUTOAGE, 0x0089d0), 3556051948SVladimir Oltean REG(ANA_MACTOPTIONS, 0x0089d4), 3656051948SVladimir Oltean REG(ANA_LEARNDISC, 0x0089d8), 3756051948SVladimir Oltean REG(ANA_AGENCTRL, 0x0089dc), 3856051948SVladimir Oltean REG(ANA_MIRRORPORTS, 0x0089e0), 3956051948SVladimir Oltean REG(ANA_EMIRRORPORTS, 0x0089e4), 4056051948SVladimir Oltean REG(ANA_FLOODING, 0x0089e8), 4156051948SVladimir Oltean REG(ANA_FLOODING_IPMC, 0x008a08), 4256051948SVladimir Oltean REG(ANA_SFLOW_CFG, 0x008a0c), 4356051948SVladimir Oltean REG(ANA_PORT_MODE, 0x008a28), 4456051948SVladimir Oltean REG(ANA_CUT_THRU_CFG, 0x008a48), 4556051948SVladimir Oltean REG(ANA_PGID_PGID, 0x008400), 4656051948SVladimir Oltean REG(ANA_TABLES_ANMOVED, 0x007f1c), 4756051948SVladimir Oltean REG(ANA_TABLES_MACHDATA, 0x007f20), 4856051948SVladimir Oltean REG(ANA_TABLES_MACLDATA, 0x007f24), 4956051948SVladimir Oltean REG(ANA_TABLES_STREAMDATA, 0x007f28), 5056051948SVladimir Oltean REG(ANA_TABLES_MACACCESS, 0x007f2c), 5156051948SVladimir Oltean REG(ANA_TABLES_MACTINDX, 0x007f30), 5256051948SVladimir Oltean REG(ANA_TABLES_VLANACCESS, 0x007f34), 5356051948SVladimir Oltean REG(ANA_TABLES_VLANTIDX, 0x007f38), 5456051948SVladimir Oltean REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 5556051948SVladimir Oltean REG(ANA_TABLES_ISDXTIDX, 0x007f40), 5656051948SVladimir Oltean REG(ANA_TABLES_ENTRYLIM, 0x007f00), 5756051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 5856051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 5956051948SVladimir Oltean REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 6056051948SVladimir Oltean REG(ANA_TABLES_STREAMTIDX, 0x007f50), 6156051948SVladimir Oltean REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 6256051948SVladimir Oltean REG(ANA_TABLES_SEQ_MASK, 0x007f58), 6356051948SVladimir Oltean REG(ANA_TABLES_SFID_MASK, 0x007f5c), 6456051948SVladimir Oltean REG(ANA_TABLES_SFIDACCESS, 0x007f60), 6556051948SVladimir Oltean REG(ANA_TABLES_SFIDTIDX, 0x007f64), 6656051948SVladimir Oltean REG(ANA_MSTI_STATE, 0x008600), 6756051948SVladimir Oltean REG(ANA_OAM_UPM_LM_CNT, 0x008000), 6856051948SVladimir Oltean REG(ANA_SG_ACCESS_CTRL, 0x008a64), 6956051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 7056051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 7156051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 7256051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 7356051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 7456051948SVladimir Oltean REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 7556051948SVladimir Oltean REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 7656051948SVladimir Oltean REG(ANA_SG_STATUS_REG_1, 0x008980), 7756051948SVladimir Oltean REG(ANA_SG_STATUS_REG_2, 0x008984), 7856051948SVladimir Oltean REG(ANA_SG_STATUS_REG_3, 0x008988), 7956051948SVladimir Oltean REG(ANA_PORT_VLAN_CFG, 0x007800), 8056051948SVladimir Oltean REG(ANA_PORT_DROP_CFG, 0x007804), 8156051948SVladimir Oltean REG(ANA_PORT_QOS_CFG, 0x007808), 8256051948SVladimir Oltean REG(ANA_PORT_VCAP_CFG, 0x00780c), 8356051948SVladimir Oltean REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 8456051948SVladimir Oltean REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 8556051948SVladimir Oltean REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 8656051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 8756051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 8856051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 8956051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 9056051948SVladimir Oltean REG(ANA_PORT_PORT_CFG, 0x007870), 9156051948SVladimir Oltean REG(ANA_PORT_POL_CFG, 0x007874), 9256051948SVladimir Oltean REG(ANA_PORT_PTP_CFG, 0x007878), 9356051948SVladimir Oltean REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 9456051948SVladimir Oltean REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 9556051948SVladimir Oltean REG(ANA_PORT_SFID_CFG, 0x007884), 9656051948SVladimir Oltean REG(ANA_PFC_PFC_CFG, 0x008800), 9756051948SVladimir Oltean REG_RESERVED(ANA_PFC_PFC_TIMER), 9856051948SVladimir Oltean REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 9956051948SVladimir Oltean REG_RESERVED(ANA_IPT_IPT), 10056051948SVladimir Oltean REG_RESERVED(ANA_PPT_PPT), 10156051948SVladimir Oltean REG_RESERVED(ANA_FID_MAP_FID_MAP), 10256051948SVladimir Oltean REG(ANA_AGGR_CFG, 0x008a68), 10356051948SVladimir Oltean REG(ANA_CPUQ_CFG, 0x008a6c), 10456051948SVladimir Oltean REG_RESERVED(ANA_CPUQ_CFG2), 10556051948SVladimir Oltean REG(ANA_CPUQ_8021_CFG, 0x008a74), 10656051948SVladimir Oltean REG(ANA_DSCP_CFG, 0x008ab4), 10756051948SVladimir Oltean REG(ANA_DSCP_REWR_CFG, 0x008bb4), 10856051948SVladimir Oltean REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 10956051948SVladimir Oltean REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 11056051948SVladimir Oltean REG_RESERVED(ANA_VRAP_CFG), 11156051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_DATA), 11256051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_MASK), 11356051948SVladimir Oltean REG(ANA_DISCARD_CFG, 0x008c40), 11456051948SVladimir Oltean REG(ANA_FID_CFG, 0x008c44), 11556051948SVladimir Oltean REG(ANA_POL_PIR_CFG, 0x004000), 11656051948SVladimir Oltean REG(ANA_POL_CIR_CFG, 0x004004), 11756051948SVladimir Oltean REG(ANA_POL_MODE_CFG, 0x004008), 11856051948SVladimir Oltean REG(ANA_POL_PIR_STATE, 0x00400c), 11956051948SVladimir Oltean REG(ANA_POL_CIR_STATE, 0x004010), 12056051948SVladimir Oltean REG_RESERVED(ANA_POL_STATE), 12156051948SVladimir Oltean REG(ANA_POL_FLOWC, 0x008c48), 12256051948SVladimir Oltean REG(ANA_POL_HYST, 0x008cb4), 12356051948SVladimir Oltean REG_RESERVED(ANA_POL_MISC_CFG), 12456051948SVladimir Oltean }; 12556051948SVladimir Oltean 12656051948SVladimir Oltean static const u32 vsc9959_qs_regmap[] = { 12756051948SVladimir Oltean REG(QS_XTR_GRP_CFG, 0x000000), 12856051948SVladimir Oltean REG(QS_XTR_RD, 0x000008), 12956051948SVladimir Oltean REG(QS_XTR_FRM_PRUNING, 0x000010), 13056051948SVladimir Oltean REG(QS_XTR_FLUSH, 0x000018), 13156051948SVladimir Oltean REG(QS_XTR_DATA_PRESENT, 0x00001c), 13256051948SVladimir Oltean REG(QS_XTR_CFG, 0x000020), 13356051948SVladimir Oltean REG(QS_INJ_GRP_CFG, 0x000024), 13456051948SVladimir Oltean REG(QS_INJ_WR, 0x00002c), 13556051948SVladimir Oltean REG(QS_INJ_CTRL, 0x000034), 13656051948SVladimir Oltean REG(QS_INJ_STATUS, 0x00003c), 13756051948SVladimir Oltean REG(QS_INJ_ERR, 0x000040), 13856051948SVladimir Oltean REG_RESERVED(QS_INH_DBG), 13956051948SVladimir Oltean }; 14056051948SVladimir Oltean 14156051948SVladimir Oltean static const u32 vsc9959_s2_regmap[] = { 14256051948SVladimir Oltean REG(S2_CORE_UPDATE_CTRL, 0x000000), 14356051948SVladimir Oltean REG(S2_CORE_MV_CFG, 0x000004), 14456051948SVladimir Oltean REG(S2_CACHE_ENTRY_DAT, 0x000008), 14556051948SVladimir Oltean REG(S2_CACHE_MASK_DAT, 0x000108), 14656051948SVladimir Oltean REG(S2_CACHE_ACTION_DAT, 0x000208), 14756051948SVladimir Oltean REG(S2_CACHE_CNT_DAT, 0x000308), 14856051948SVladimir Oltean REG(S2_CACHE_TG_DAT, 0x000388), 14956051948SVladimir Oltean }; 15056051948SVladimir Oltean 15156051948SVladimir Oltean static const u32 vsc9959_qsys_regmap[] = { 15256051948SVladimir Oltean REG(QSYS_PORT_MODE, 0x00f460), 15356051948SVladimir Oltean REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 15456051948SVladimir Oltean REG(QSYS_STAT_CNT_CFG, 0x00f49c), 15556051948SVladimir Oltean REG(QSYS_EEE_CFG, 0x00f4a0), 15656051948SVladimir Oltean REG(QSYS_EEE_THRES, 0x00f4b8), 15756051948SVladimir Oltean REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 15856051948SVladimir Oltean REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 15956051948SVladimir Oltean REG(QSYS_SW_STATUS, 0x00f4c4), 16056051948SVladimir Oltean REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 16156051948SVladimir Oltean REG_RESERVED(QSYS_PAD_CFG), 16256051948SVladimir Oltean REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 16356051948SVladimir Oltean REG_RESERVED(QSYS_QMAP), 16456051948SVladimir Oltean REG_RESERVED(QSYS_ISDX_SGRP), 16556051948SVladimir Oltean REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 16656051948SVladimir Oltean REG(QSYS_TFRM_MISC, 0x00f50c), 16756051948SVladimir Oltean REG(QSYS_TFRM_PORT_DLY, 0x00f510), 16856051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 16956051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 17056051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 17156051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 17256051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 17356051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 17456051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 17556051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 17656051948SVladimir Oltean REG(QSYS_RED_PROFILE, 0x00f534), 17756051948SVladimir Oltean REG(QSYS_RES_QOS_MODE, 0x00f574), 17856051948SVladimir Oltean REG(QSYS_RES_CFG, 0x00c000), 17956051948SVladimir Oltean REG(QSYS_RES_STAT, 0x00c004), 18056051948SVladimir Oltean REG(QSYS_EGR_DROP_MODE, 0x00f578), 18156051948SVladimir Oltean REG(QSYS_EQ_CTRL, 0x00f57c), 18256051948SVladimir Oltean REG_RESERVED(QSYS_EVENTS_CORE), 18356051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 18456051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 18556051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 18656051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 18756051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 18856051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 18956051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 19056051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 19156051948SVladimir Oltean REG(QSYS_PREEMPTION_CFG, 0x00f664), 1920fbabf87SXiaoliang Yang REG(QSYS_CIR_CFG, 0x000000), 19356051948SVladimir Oltean REG(QSYS_EIR_CFG, 0x000004), 19456051948SVladimir Oltean REG(QSYS_SE_CFG, 0x000008), 19556051948SVladimir Oltean REG(QSYS_SE_DWRR_CFG, 0x00000c), 19656051948SVladimir Oltean REG_RESERVED(QSYS_SE_CONNECT), 19756051948SVladimir Oltean REG(QSYS_SE_DLB_SENSE, 0x000040), 19856051948SVladimir Oltean REG(QSYS_CIR_STATE, 0x000044), 19956051948SVladimir Oltean REG(QSYS_EIR_STATE, 0x000048), 20056051948SVladimir Oltean REG_RESERVED(QSYS_SE_STATE), 20156051948SVladimir Oltean REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 20256051948SVladimir Oltean REG(QSYS_TAG_CONFIG, 0x00f680), 20356051948SVladimir Oltean REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 20456051948SVladimir Oltean REG(QSYS_PORT_MAX_SDU, 0x00f69c), 20556051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 20656051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 20756051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 20856051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 20956051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 21056051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_1, 0x00f454), 21156051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_2, 0x00f458), 21256051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 21356051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 21456051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 21556051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 21656051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 21756051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 21856051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 21956051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 22056051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 22156051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 22256051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 22356051948SVladimir Oltean }; 22456051948SVladimir Oltean 22556051948SVladimir Oltean static const u32 vsc9959_rew_regmap[] = { 22656051948SVladimir Oltean REG(REW_PORT_VLAN_CFG, 0x000000), 22756051948SVladimir Oltean REG(REW_TAG_CFG, 0x000004), 22856051948SVladimir Oltean REG(REW_PORT_CFG, 0x000008), 22956051948SVladimir Oltean REG(REW_DSCP_CFG, 0x00000c), 23056051948SVladimir Oltean REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 23156051948SVladimir Oltean REG(REW_PTP_CFG, 0x000050), 23256051948SVladimir Oltean REG(REW_PTP_DLY1_CFG, 0x000054), 23356051948SVladimir Oltean REG(REW_RED_TAG_CFG, 0x000058), 23456051948SVladimir Oltean REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 23556051948SVladimir Oltean REG(REW_DSCP_REMAP_CFG, 0x000510), 23656051948SVladimir Oltean REG_RESERVED(REW_STAT_CFG), 23756051948SVladimir Oltean REG_RESERVED(REW_REW_STICKY), 23856051948SVladimir Oltean REG_RESERVED(REW_PPT), 23956051948SVladimir Oltean }; 24056051948SVladimir Oltean 24156051948SVladimir Oltean static const u32 vsc9959_sys_regmap[] = { 24256051948SVladimir Oltean REG(SYS_COUNT_RX_OCTETS, 0x000000), 24356051948SVladimir Oltean REG(SYS_COUNT_RX_MULTICAST, 0x000008), 24456051948SVladimir Oltean REG(SYS_COUNT_RX_SHORTS, 0x000010), 24556051948SVladimir Oltean REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 24656051948SVladimir Oltean REG(SYS_COUNT_RX_JABBERS, 0x000018), 24756051948SVladimir Oltean REG(SYS_COUNT_RX_64, 0x000024), 24856051948SVladimir Oltean REG(SYS_COUNT_RX_65_127, 0x000028), 24956051948SVladimir Oltean REG(SYS_COUNT_RX_128_255, 0x00002c), 25056051948SVladimir Oltean REG(SYS_COUNT_RX_256_1023, 0x000030), 25156051948SVladimir Oltean REG(SYS_COUNT_RX_1024_1526, 0x000034), 25256051948SVladimir Oltean REG(SYS_COUNT_RX_1527_MAX, 0x000038), 25356051948SVladimir Oltean REG(SYS_COUNT_RX_LONGS, 0x000044), 25456051948SVladimir Oltean REG(SYS_COUNT_TX_OCTETS, 0x000200), 25556051948SVladimir Oltean REG(SYS_COUNT_TX_COLLISION, 0x000210), 25656051948SVladimir Oltean REG(SYS_COUNT_TX_DROPS, 0x000214), 25756051948SVladimir Oltean REG(SYS_COUNT_TX_64, 0x00021c), 25856051948SVladimir Oltean REG(SYS_COUNT_TX_65_127, 0x000220), 25956051948SVladimir Oltean REG(SYS_COUNT_TX_128_511, 0x000224), 26056051948SVladimir Oltean REG(SYS_COUNT_TX_512_1023, 0x000228), 26156051948SVladimir Oltean REG(SYS_COUNT_TX_1024_1526, 0x00022c), 26256051948SVladimir Oltean REG(SYS_COUNT_TX_1527_MAX, 0x000230), 26356051948SVladimir Oltean REG(SYS_COUNT_TX_AGING, 0x000278), 26456051948SVladimir Oltean REG(SYS_RESET_CFG, 0x000e00), 26556051948SVladimir Oltean REG(SYS_SR_ETYPE_CFG, 0x000e04), 26656051948SVladimir Oltean REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 26756051948SVladimir Oltean REG(SYS_PORT_MODE, 0x000e0c), 26856051948SVladimir Oltean REG(SYS_FRONT_PORT_MODE, 0x000e2c), 26956051948SVladimir Oltean REG(SYS_FRM_AGING, 0x000e44), 27056051948SVladimir Oltean REG(SYS_STAT_CFG, 0x000e48), 27156051948SVladimir Oltean REG(SYS_SW_STATUS, 0x000e4c), 27256051948SVladimir Oltean REG_RESERVED(SYS_MISC_CFG), 27356051948SVladimir Oltean REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 27456051948SVladimir Oltean REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 27556051948SVladimir Oltean REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 27656051948SVladimir Oltean REG(SYS_PAUSE_CFG, 0x000ea0), 27756051948SVladimir Oltean REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 27856051948SVladimir Oltean REG(SYS_ATOP, 0x000ec0), 27956051948SVladimir Oltean REG(SYS_ATOP_TOT_CFG, 0x000edc), 28056051948SVladimir Oltean REG(SYS_MAC_FC_CFG, 0x000ee0), 28156051948SVladimir Oltean REG(SYS_MMGT, 0x000ef8), 28256051948SVladimir Oltean REG_RESERVED(SYS_MMGT_FAST), 28356051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_DIF), 28456051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_CORE), 28556051948SVladimir Oltean REG_RESERVED(SYS_CNT), 28656051948SVladimir Oltean REG(SYS_PTP_STATUS, 0x000f14), 28756051948SVladimir Oltean REG(SYS_PTP_TXSTAMP, 0x000f18), 28856051948SVladimir Oltean REG(SYS_PTP_NXT, 0x000f1c), 28956051948SVladimir Oltean REG(SYS_PTP_CFG, 0x000f20), 29056051948SVladimir Oltean REG(SYS_RAM_INIT, 0x000f24), 29156051948SVladimir Oltean REG_RESERVED(SYS_CM_ADDR), 29256051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_WR), 29356051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_RD), 29456051948SVladimir Oltean REG_RESERVED(SYS_CM_OP), 29556051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA), 29656051948SVladimir Oltean }; 29756051948SVladimir Oltean 2985df66c48SYangbo Lu static const u32 vsc9959_ptp_regmap[] = { 2995df66c48SYangbo Lu REG(PTP_PIN_CFG, 0x000000), 3005df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 3015df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 3025df66c48SYangbo Lu REG(PTP_PIN_TOD_NSEC, 0x00000c), 30394aca082SYangbo Lu REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 30494aca082SYangbo Lu REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 3055df66c48SYangbo Lu REG(PTP_CFG_MISC, 0x0000a0), 3065df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 3075df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 3085df66c48SYangbo Lu }; 3095df66c48SYangbo Lu 31056051948SVladimir Oltean static const u32 vsc9959_gcb_regmap[] = { 31156051948SVladimir Oltean REG(GCB_SOFT_RST, 0x000004), 31256051948SVladimir Oltean }; 31356051948SVladimir Oltean 31491c724cfSVladimir Oltean static const u32 vsc9959_dev_gmii_regmap[] = { 31591c724cfSVladimir Oltean REG(DEV_CLOCK_CFG, 0x0), 31691c724cfSVladimir Oltean REG(DEV_PORT_MISC, 0x4), 31791c724cfSVladimir Oltean REG(DEV_EVENTS, 0x8), 31891c724cfSVladimir Oltean REG(DEV_EEE_CFG, 0xc), 31991c724cfSVladimir Oltean REG(DEV_RX_PATH_DELAY, 0x10), 32091c724cfSVladimir Oltean REG(DEV_TX_PATH_DELAY, 0x14), 32191c724cfSVladimir Oltean REG(DEV_PTP_PREDICT_CFG, 0x18), 32291c724cfSVladimir Oltean REG(DEV_MAC_ENA_CFG, 0x1c), 32391c724cfSVladimir Oltean REG(DEV_MAC_MODE_CFG, 0x20), 32491c724cfSVladimir Oltean REG(DEV_MAC_MAXLEN_CFG, 0x24), 32591c724cfSVladimir Oltean REG(DEV_MAC_TAGS_CFG, 0x28), 32691c724cfSVladimir Oltean REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 32791c724cfSVladimir Oltean REG(DEV_MAC_IFG_CFG, 0x30), 32891c724cfSVladimir Oltean REG(DEV_MAC_HDX_CFG, 0x34), 32991c724cfSVladimir Oltean REG(DEV_MAC_DBG_CFG, 0x38), 33091c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 33191c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 33291c724cfSVladimir Oltean REG(DEV_MAC_STICKY, 0x44), 33391c724cfSVladimir Oltean REG_RESERVED(PCS1G_CFG), 33491c724cfSVladimir Oltean REG_RESERVED(PCS1G_MODE_CFG), 33591c724cfSVladimir Oltean REG_RESERVED(PCS1G_SD_CFG), 33691c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_CFG), 33791c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_CFG), 33891c724cfSVladimir Oltean REG_RESERVED(PCS1G_LB_CFG), 33991c724cfSVladimir Oltean REG_RESERVED(PCS1G_DBG_CFG), 34091c724cfSVladimir Oltean REG_RESERVED(PCS1G_CDET_CFG), 34191c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_STATUS), 34291c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_STATUS), 34391c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_STATUS), 34491c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_DOWN_CNT), 34591c724cfSVladimir Oltean REG_RESERVED(PCS1G_STICKY), 34691c724cfSVladimir Oltean REG_RESERVED(PCS1G_DEBUG_STATUS), 34791c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_CFG), 34891c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 34991c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_STATUS), 35091c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 35191c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_STATUS), 35291c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_CFG), 35391c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_STATUS), 35491c724cfSVladimir Oltean }; 35591c724cfSVladimir Oltean 35691c724cfSVladimir Oltean static const u32 *vsc9959_regmap[TARGET_MAX] = { 35756051948SVladimir Oltean [ANA] = vsc9959_ana_regmap, 35856051948SVladimir Oltean [QS] = vsc9959_qs_regmap, 35956051948SVladimir Oltean [QSYS] = vsc9959_qsys_regmap, 36056051948SVladimir Oltean [REW] = vsc9959_rew_regmap, 36156051948SVladimir Oltean [SYS] = vsc9959_sys_regmap, 36256051948SVladimir Oltean [S2] = vsc9959_s2_regmap, 3635df66c48SYangbo Lu [PTP] = vsc9959_ptp_regmap, 36456051948SVladimir Oltean [GCB] = vsc9959_gcb_regmap, 36591c724cfSVladimir Oltean [DEV_GMII] = vsc9959_dev_gmii_regmap, 36656051948SVladimir Oltean }; 36756051948SVladimir Oltean 368b4024c9eSClaudiu Manoil /* Addresses are relative to the PCI device's base address */ 36991c724cfSVladimir Oltean static const struct resource vsc9959_target_io_res[TARGET_MAX] = { 37056051948SVladimir Oltean [ANA] = { 37156051948SVladimir Oltean .start = 0x0280000, 37256051948SVladimir Oltean .end = 0x028ffff, 37356051948SVladimir Oltean .name = "ana", 37456051948SVladimir Oltean }, 37556051948SVladimir Oltean [QS] = { 37656051948SVladimir Oltean .start = 0x0080000, 37756051948SVladimir Oltean .end = 0x00800ff, 37856051948SVladimir Oltean .name = "qs", 37956051948SVladimir Oltean }, 38056051948SVladimir Oltean [QSYS] = { 38156051948SVladimir Oltean .start = 0x0200000, 38256051948SVladimir Oltean .end = 0x021ffff, 38356051948SVladimir Oltean .name = "qsys", 38456051948SVladimir Oltean }, 38556051948SVladimir Oltean [REW] = { 38656051948SVladimir Oltean .start = 0x0030000, 38756051948SVladimir Oltean .end = 0x003ffff, 38856051948SVladimir Oltean .name = "rew", 38956051948SVladimir Oltean }, 39056051948SVladimir Oltean [SYS] = { 39156051948SVladimir Oltean .start = 0x0010000, 39256051948SVladimir Oltean .end = 0x001ffff, 39356051948SVladimir Oltean .name = "sys", 39456051948SVladimir Oltean }, 39556051948SVladimir Oltean [S2] = { 39656051948SVladimir Oltean .start = 0x0060000, 39756051948SVladimir Oltean .end = 0x00603ff, 39856051948SVladimir Oltean .name = "s2", 39956051948SVladimir Oltean }, 4005df66c48SYangbo Lu [PTP] = { 4015df66c48SYangbo Lu .start = 0x0090000, 4025df66c48SYangbo Lu .end = 0x00900cb, 4035df66c48SYangbo Lu .name = "ptp", 4045df66c48SYangbo Lu }, 40556051948SVladimir Oltean [GCB] = { 40656051948SVladimir Oltean .start = 0x0070000, 40756051948SVladimir Oltean .end = 0x00701ff, 40856051948SVladimir Oltean .name = "devcpu_gcb", 40956051948SVladimir Oltean }, 41056051948SVladimir Oltean }; 41156051948SVladimir Oltean 412b4024c9eSClaudiu Manoil static const struct resource vsc9959_port_io_res[] = { 41356051948SVladimir Oltean { 41456051948SVladimir Oltean .start = 0x0100000, 41556051948SVladimir Oltean .end = 0x010ffff, 41656051948SVladimir Oltean .name = "port0", 41756051948SVladimir Oltean }, 41856051948SVladimir Oltean { 41956051948SVladimir Oltean .start = 0x0110000, 42056051948SVladimir Oltean .end = 0x011ffff, 42156051948SVladimir Oltean .name = "port1", 42256051948SVladimir Oltean }, 42356051948SVladimir Oltean { 42456051948SVladimir Oltean .start = 0x0120000, 42556051948SVladimir Oltean .end = 0x012ffff, 42656051948SVladimir Oltean .name = "port2", 42756051948SVladimir Oltean }, 42856051948SVladimir Oltean { 42956051948SVladimir Oltean .start = 0x0130000, 43056051948SVladimir Oltean .end = 0x013ffff, 43156051948SVladimir Oltean .name = "port3", 43256051948SVladimir Oltean }, 43356051948SVladimir Oltean { 43456051948SVladimir Oltean .start = 0x0140000, 43556051948SVladimir Oltean .end = 0x014ffff, 43656051948SVladimir Oltean .name = "port4", 43756051948SVladimir Oltean }, 43856051948SVladimir Oltean { 43956051948SVladimir Oltean .start = 0x0150000, 44056051948SVladimir Oltean .end = 0x015ffff, 44156051948SVladimir Oltean .name = "port5", 44256051948SVladimir Oltean }, 44356051948SVladimir Oltean }; 44456051948SVladimir Oltean 445bdeced75SVladimir Oltean /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 446bdeced75SVladimir Oltean * SGMII/QSGMII MAC PCS can be found. 447bdeced75SVladimir Oltean */ 448b4024c9eSClaudiu Manoil static const struct resource vsc9959_imdio_res = { 449bdeced75SVladimir Oltean .start = 0x8030, 450bdeced75SVladimir Oltean .end = 0x8040, 451bdeced75SVladimir Oltean .name = "imdio", 452bdeced75SVladimir Oltean }; 453bdeced75SVladimir Oltean 4542789658fSMaxim Kochetkov static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 45556051948SVladimir Oltean [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 45656051948SVladimir Oltean [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 45756051948SVladimir Oltean [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 45856051948SVladimir Oltean [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 45956051948SVladimir Oltean [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 46056051948SVladimir Oltean [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 46156051948SVladimir Oltean [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 46256051948SVladimir Oltean [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 46356051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 46456051948SVladimir Oltean [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 46556051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 46656051948SVladimir Oltean [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 46756051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 46856051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 46956051948SVladimir Oltean [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 47056051948SVladimir Oltean [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 47156051948SVladimir Oltean [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 47256051948SVladimir Oltean [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 47356051948SVladimir Oltean [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 47456051948SVladimir Oltean [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 47556051948SVladimir Oltean [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 47656051948SVladimir Oltean [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 47756051948SVladimir Oltean [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 47856051948SVladimir Oltean [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 47956051948SVladimir Oltean [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 48056051948SVladimir Oltean [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 48156051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 48256051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 48356051948SVladimir Oltean [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 48456051948SVladimir Oltean [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 48556051948SVladimir Oltean [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 48656051948SVladimir Oltean [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 48756051948SVladimir Oltean [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 488886e1387SVladimir Oltean /* Replicated per number of ports (7), register size 4 per port */ 489886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 490886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 491886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 492886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 493886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 494886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 495886e1387SVladimir Oltean [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 496886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 497886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 498886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 499541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 500541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 501541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 50256051948SVladimir Oltean }; 50356051948SVladimir Oltean 50456051948SVladimir Oltean static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 50556051948SVladimir Oltean { .offset = 0x00, .name = "rx_octets", }, 50656051948SVladimir Oltean { .offset = 0x01, .name = "rx_unicast", }, 50756051948SVladimir Oltean { .offset = 0x02, .name = "rx_multicast", }, 50856051948SVladimir Oltean { .offset = 0x03, .name = "rx_broadcast", }, 50956051948SVladimir Oltean { .offset = 0x04, .name = "rx_shorts", }, 51056051948SVladimir Oltean { .offset = 0x05, .name = "rx_fragments", }, 51156051948SVladimir Oltean { .offset = 0x06, .name = "rx_jabbers", }, 51256051948SVladimir Oltean { .offset = 0x07, .name = "rx_crc_align_errs", }, 51356051948SVladimir Oltean { .offset = 0x08, .name = "rx_sym_errs", }, 51456051948SVladimir Oltean { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 51556051948SVladimir Oltean { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 51656051948SVladimir Oltean { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 51756051948SVladimir Oltean { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 51856051948SVladimir Oltean { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 51956051948SVladimir Oltean { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 52056051948SVladimir Oltean { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 52156051948SVladimir Oltean { .offset = 0x10, .name = "rx_pause", }, 52256051948SVladimir Oltean { .offset = 0x11, .name = "rx_control", }, 52356051948SVladimir Oltean { .offset = 0x12, .name = "rx_longs", }, 52456051948SVladimir Oltean { .offset = 0x13, .name = "rx_classified_drops", }, 52556051948SVladimir Oltean { .offset = 0x14, .name = "rx_red_prio_0", }, 52656051948SVladimir Oltean { .offset = 0x15, .name = "rx_red_prio_1", }, 52756051948SVladimir Oltean { .offset = 0x16, .name = "rx_red_prio_2", }, 52856051948SVladimir Oltean { .offset = 0x17, .name = "rx_red_prio_3", }, 52956051948SVladimir Oltean { .offset = 0x18, .name = "rx_red_prio_4", }, 53056051948SVladimir Oltean { .offset = 0x19, .name = "rx_red_prio_5", }, 53156051948SVladimir Oltean { .offset = 0x1A, .name = "rx_red_prio_6", }, 53256051948SVladimir Oltean { .offset = 0x1B, .name = "rx_red_prio_7", }, 53356051948SVladimir Oltean { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 53456051948SVladimir Oltean { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 53556051948SVladimir Oltean { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 53656051948SVladimir Oltean { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 53756051948SVladimir Oltean { .offset = 0x20, .name = "rx_yellow_prio_4", }, 53856051948SVladimir Oltean { .offset = 0x21, .name = "rx_yellow_prio_5", }, 53956051948SVladimir Oltean { .offset = 0x22, .name = "rx_yellow_prio_6", }, 54056051948SVladimir Oltean { .offset = 0x23, .name = "rx_yellow_prio_7", }, 54156051948SVladimir Oltean { .offset = 0x24, .name = "rx_green_prio_0", }, 54256051948SVladimir Oltean { .offset = 0x25, .name = "rx_green_prio_1", }, 54356051948SVladimir Oltean { .offset = 0x26, .name = "rx_green_prio_2", }, 54456051948SVladimir Oltean { .offset = 0x27, .name = "rx_green_prio_3", }, 54556051948SVladimir Oltean { .offset = 0x28, .name = "rx_green_prio_4", }, 54656051948SVladimir Oltean { .offset = 0x29, .name = "rx_green_prio_5", }, 54756051948SVladimir Oltean { .offset = 0x2A, .name = "rx_green_prio_6", }, 54856051948SVladimir Oltean { .offset = 0x2B, .name = "rx_green_prio_7", }, 54956051948SVladimir Oltean { .offset = 0x80, .name = "tx_octets", }, 55056051948SVladimir Oltean { .offset = 0x81, .name = "tx_unicast", }, 55156051948SVladimir Oltean { .offset = 0x82, .name = "tx_multicast", }, 55256051948SVladimir Oltean { .offset = 0x83, .name = "tx_broadcast", }, 55356051948SVladimir Oltean { .offset = 0x84, .name = "tx_collision", }, 55456051948SVladimir Oltean { .offset = 0x85, .name = "tx_drops", }, 55556051948SVladimir Oltean { .offset = 0x86, .name = "tx_pause", }, 55656051948SVladimir Oltean { .offset = 0x87, .name = "tx_frames_below_65_octets", }, 55756051948SVladimir Oltean { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, 55856051948SVladimir Oltean { .offset = 0x89, .name = "tx_frames_128_255_octets", }, 55956051948SVladimir Oltean { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, 56056051948SVladimir Oltean { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, 56156051948SVladimir Oltean { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, 56256051948SVladimir Oltean { .offset = 0x8E, .name = "tx_yellow_prio_0", }, 56356051948SVladimir Oltean { .offset = 0x8F, .name = "tx_yellow_prio_1", }, 56456051948SVladimir Oltean { .offset = 0x90, .name = "tx_yellow_prio_2", }, 56556051948SVladimir Oltean { .offset = 0x91, .name = "tx_yellow_prio_3", }, 56656051948SVladimir Oltean { .offset = 0x92, .name = "tx_yellow_prio_4", }, 56756051948SVladimir Oltean { .offset = 0x93, .name = "tx_yellow_prio_5", }, 56856051948SVladimir Oltean { .offset = 0x94, .name = "tx_yellow_prio_6", }, 56956051948SVladimir Oltean { .offset = 0x95, .name = "tx_yellow_prio_7", }, 57056051948SVladimir Oltean { .offset = 0x96, .name = "tx_green_prio_0", }, 57156051948SVladimir Oltean { .offset = 0x97, .name = "tx_green_prio_1", }, 57256051948SVladimir Oltean { .offset = 0x98, .name = "tx_green_prio_2", }, 57356051948SVladimir Oltean { .offset = 0x99, .name = "tx_green_prio_3", }, 57456051948SVladimir Oltean { .offset = 0x9A, .name = "tx_green_prio_4", }, 57556051948SVladimir Oltean { .offset = 0x9B, .name = "tx_green_prio_5", }, 57656051948SVladimir Oltean { .offset = 0x9C, .name = "tx_green_prio_6", }, 57756051948SVladimir Oltean { .offset = 0x9D, .name = "tx_green_prio_7", }, 57856051948SVladimir Oltean { .offset = 0x9E, .name = "tx_aged", }, 57956051948SVladimir Oltean { .offset = 0x100, .name = "drop_local", }, 58056051948SVladimir Oltean { .offset = 0x101, .name = "drop_tail", }, 58156051948SVladimir Oltean { .offset = 0x102, .name = "drop_yellow_prio_0", }, 58256051948SVladimir Oltean { .offset = 0x103, .name = "drop_yellow_prio_1", }, 58356051948SVladimir Oltean { .offset = 0x104, .name = "drop_yellow_prio_2", }, 58456051948SVladimir Oltean { .offset = 0x105, .name = "drop_yellow_prio_3", }, 58556051948SVladimir Oltean { .offset = 0x106, .name = "drop_yellow_prio_4", }, 58656051948SVladimir Oltean { .offset = 0x107, .name = "drop_yellow_prio_5", }, 58756051948SVladimir Oltean { .offset = 0x108, .name = "drop_yellow_prio_6", }, 58856051948SVladimir Oltean { .offset = 0x109, .name = "drop_yellow_prio_7", }, 58956051948SVladimir Oltean { .offset = 0x10A, .name = "drop_green_prio_0", }, 59056051948SVladimir Oltean { .offset = 0x10B, .name = "drop_green_prio_1", }, 59156051948SVladimir Oltean { .offset = 0x10C, .name = "drop_green_prio_2", }, 59256051948SVladimir Oltean { .offset = 0x10D, .name = "drop_green_prio_3", }, 59356051948SVladimir Oltean { .offset = 0x10E, .name = "drop_green_prio_4", }, 59456051948SVladimir Oltean { .offset = 0x10F, .name = "drop_green_prio_5", }, 59556051948SVladimir Oltean { .offset = 0x110, .name = "drop_green_prio_6", }, 59656051948SVladimir Oltean { .offset = 0x111, .name = "drop_green_prio_7", }, 59756051948SVladimir Oltean }; 59856051948SVladimir Oltean 5993ab4ceb6SVladimir Oltean static struct vcap_field vsc9959_vcap_is2_keys[] = { 60007d985eeSVladimir Oltean /* Common: 41 bits */ 60107d985eeSVladimir Oltean [VCAP_IS2_TYPE] = { 0, 4}, 60207d985eeSVladimir Oltean [VCAP_IS2_HK_FIRST] = { 4, 1}, 60307d985eeSVladimir Oltean [VCAP_IS2_HK_PAG] = { 5, 8}, 60407d985eeSVladimir Oltean [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 60507d985eeSVladimir Oltean [VCAP_IS2_HK_RSV2] = { 20, 1}, 60607d985eeSVladimir Oltean [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 60707d985eeSVladimir Oltean [VCAP_IS2_HK_L2_MC] = { 22, 1}, 60807d985eeSVladimir Oltean [VCAP_IS2_HK_L2_BC] = { 23, 1}, 60907d985eeSVladimir Oltean [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 61007d985eeSVladimir Oltean [VCAP_IS2_HK_VID] = { 25, 12}, 61107d985eeSVladimir Oltean [VCAP_IS2_HK_DEI] = { 37, 1}, 61207d985eeSVladimir Oltean [VCAP_IS2_HK_PCP] = { 38, 3}, 61307d985eeSVladimir Oltean /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 61407d985eeSVladimir Oltean [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 61507d985eeSVladimir Oltean [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 61607d985eeSVladimir Oltean /* MAC_ETYPE (TYPE=000) */ 61707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 61807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 61907d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 62007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 62107d985eeSVladimir Oltean /* MAC_LLC (TYPE=001) */ 62207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 62307d985eeSVladimir Oltean /* MAC_SNAP (TYPE=010) */ 62407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 62507d985eeSVladimir Oltean /* MAC_ARP (TYPE=011) */ 62607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 62707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 62807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 62907d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 63007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 63107d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 63207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 63307d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 63407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 63507d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 63607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 63707d985eeSVladimir Oltean /* IP4_TCP_UDP / IP4_OTHER common */ 63807d985eeSVladimir Oltean [VCAP_IS2_HK_IP4] = { 41, 1}, 63907d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 64007d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 64107d985eeSVladimir Oltean [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 64207d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 64307d985eeSVladimir Oltean [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 64407d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 64507d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 64607d985eeSVladimir Oltean [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 64707d985eeSVladimir Oltean /* IP4_TCP_UDP (TYPE=100) */ 64807d985eeSVladimir Oltean [VCAP_IS2_HK_TCP] = {119, 1}, 64907d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SPORT] = {120, 16}, 65007d985eeSVladimir Oltean [VCAP_IS2_HK_L4_DPORT] = {136, 16}, 65107d985eeSVladimir Oltean [VCAP_IS2_HK_L4_RNG] = {152, 8}, 65207d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 65307d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 65407d985eeSVladimir Oltean [VCAP_IS2_HK_L4_URG] = {162, 1}, 65507d985eeSVladimir Oltean [VCAP_IS2_HK_L4_ACK] = {163, 1}, 65607d985eeSVladimir Oltean [VCAP_IS2_HK_L4_PSH] = {164, 1}, 65707d985eeSVladimir Oltean [VCAP_IS2_HK_L4_RST] = {165, 1}, 65807d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SYN] = {166, 1}, 65907d985eeSVladimir Oltean [VCAP_IS2_HK_L4_FIN] = {167, 1}, 66007d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 66107d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 66207d985eeSVladimir Oltean /* IP4_OTHER (TYPE=101) */ 66307d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 66407d985eeSVladimir Oltean [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 66507d985eeSVladimir Oltean /* IP6_STD (TYPE=110) */ 66607d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 66707d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 66807d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 66907d985eeSVladimir Oltean /* OAM (TYPE=111) */ 67007d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 67107d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_VER] = {144, 5}, 67207d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 67307d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 67407d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 67507d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 67607d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 67707d985eeSVladimir Oltean }; 67807d985eeSVladimir Oltean 6793ab4ceb6SVladimir Oltean static struct vcap_field vsc9959_vcap_is2_actions[] = { 68007d985eeSVladimir Oltean [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 68107d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 68207d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 68307d985eeSVladimir Oltean [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 68407d985eeSVladimir Oltean [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 68507d985eeSVladimir Oltean [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 68607d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 68707d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 68807d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 68907d985eeSVladimir Oltean [VCAP_IS2_ACT_PORT_MASK] = { 20, 11}, 69007d985eeSVladimir Oltean [VCAP_IS2_ACT_REW_OP] = { 31, 9}, 69107d985eeSVladimir Oltean [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1}, 69207d985eeSVladimir Oltean [VCAP_IS2_ACT_RSV] = { 41, 2}, 69307d985eeSVladimir Oltean [VCAP_IS2_ACT_ACL_ID] = { 43, 6}, 69407d985eeSVladimir Oltean [VCAP_IS2_ACT_HIT_CNT] = { 49, 32}, 69507d985eeSVladimir Oltean }; 69607d985eeSVladimir Oltean 69707d985eeSVladimir Oltean static const struct vcap_props vsc9959_vcap_props[] = { 69807d985eeSVladimir Oltean [VCAP_IS2] = { 69907d985eeSVladimir Oltean .tg_width = 2, 70007d985eeSVladimir Oltean .sw_count = 4, 70107d985eeSVladimir Oltean .entry_count = VSC9959_VCAP_IS2_CNT, 70207d985eeSVladimir Oltean .entry_width = VSC9959_VCAP_IS2_ENTRY_WIDTH, 70307d985eeSVladimir Oltean .action_count = VSC9959_VCAP_IS2_CNT + 70407d985eeSVladimir Oltean VSC9959_VCAP_PORT_CNT + 2, 70507d985eeSVladimir Oltean .action_width = 89, 70607d985eeSVladimir Oltean .action_type_width = 1, 70707d985eeSVladimir Oltean .action_table = { 70807d985eeSVladimir Oltean [IS2_ACTION_TYPE_NORMAL] = { 70907d985eeSVladimir Oltean .width = 44, 71007d985eeSVladimir Oltean .count = 2 71107d985eeSVladimir Oltean }, 71207d985eeSVladimir Oltean [IS2_ACTION_TYPE_SMAC_SIP] = { 71307d985eeSVladimir Oltean .width = 6, 71407d985eeSVladimir Oltean .count = 4 71507d985eeSVladimir Oltean }, 71607d985eeSVladimir Oltean }, 71707d985eeSVladimir Oltean .counter_words = 4, 71807d985eeSVladimir Oltean .counter_width = 32, 71907d985eeSVladimir Oltean }, 72007d985eeSVladimir Oltean }; 72107d985eeSVladimir Oltean 72256051948SVladimir Oltean #define VSC9959_INIT_TIMEOUT 50000 72356051948SVladimir Oltean #define VSC9959_GCB_RST_SLEEP 100 72456051948SVladimir Oltean #define VSC9959_SYS_RAMINIT_SLEEP 80 72556051948SVladimir Oltean 72656051948SVladimir Oltean static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 72756051948SVladimir Oltean { 72856051948SVladimir Oltean int val; 72956051948SVladimir Oltean 73075cea9cbSVladimir Oltean ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 73156051948SVladimir Oltean 73256051948SVladimir Oltean return val; 73356051948SVladimir Oltean } 73456051948SVladimir Oltean 73556051948SVladimir Oltean static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 73656051948SVladimir Oltean { 73756051948SVladimir Oltean return ocelot_read(ocelot, SYS_RAM_INIT); 73856051948SVladimir Oltean } 73956051948SVladimir Oltean 74056051948SVladimir Oltean static int vsc9959_reset(struct ocelot *ocelot) 74156051948SVladimir Oltean { 74256051948SVladimir Oltean int val, err; 74356051948SVladimir Oltean 74456051948SVladimir Oltean /* soft-reset the switch core */ 74575cea9cbSVladimir Oltean ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 74656051948SVladimir Oltean 74756051948SVladimir Oltean err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 74856051948SVladimir Oltean VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 74956051948SVladimir Oltean if (err) { 75056051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch core reset\n"); 75156051948SVladimir Oltean return err; 75256051948SVladimir Oltean } 75356051948SVladimir Oltean 75456051948SVladimir Oltean /* initialize switch mem ~40us */ 75556051948SVladimir Oltean ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 75656051948SVladimir Oltean err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 75756051948SVladimir Oltean VSC9959_SYS_RAMINIT_SLEEP, 75856051948SVladimir Oltean VSC9959_INIT_TIMEOUT); 75956051948SVladimir Oltean if (err) { 76056051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch sram init\n"); 76156051948SVladimir Oltean return err; 76256051948SVladimir Oltean } 76356051948SVladimir Oltean 76456051948SVladimir Oltean /* enable switch core */ 76575cea9cbSVladimir Oltean ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 76656051948SVladimir Oltean 76756051948SVladimir Oltean return 0; 76856051948SVladimir Oltean } 76956051948SVladimir Oltean 770375e1314SVladimir Oltean static void vsc9959_phylink_validate(struct ocelot *ocelot, int port, 771375e1314SVladimir Oltean unsigned long *supported, 772375e1314SVladimir Oltean struct phylink_link_state *state) 773375e1314SVladimir Oltean { 774375e1314SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 775375e1314SVladimir Oltean __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 776375e1314SVladimir Oltean 777375e1314SVladimir Oltean if (state->interface != PHY_INTERFACE_MODE_NA && 778375e1314SVladimir Oltean state->interface != ocelot_port->phy_mode) { 779375e1314SVladimir Oltean bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 780375e1314SVladimir Oltean return; 781375e1314SVladimir Oltean } 782375e1314SVladimir Oltean 783375e1314SVladimir Oltean phylink_set_port_modes(mask); 784375e1314SVladimir Oltean phylink_set(mask, Autoneg); 785375e1314SVladimir Oltean phylink_set(mask, Pause); 786375e1314SVladimir Oltean phylink_set(mask, Asym_Pause); 787375e1314SVladimir Oltean phylink_set(mask, 10baseT_Half); 788375e1314SVladimir Oltean phylink_set(mask, 10baseT_Full); 789375e1314SVladimir Oltean phylink_set(mask, 100baseT_Half); 790375e1314SVladimir Oltean phylink_set(mask, 100baseT_Full); 791375e1314SVladimir Oltean phylink_set(mask, 1000baseT_Half); 792375e1314SVladimir Oltean phylink_set(mask, 1000baseT_Full); 793375e1314SVladimir Oltean 794375e1314SVladimir Oltean if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 795375e1314SVladimir Oltean state->interface == PHY_INTERFACE_MODE_2500BASEX || 796375e1314SVladimir Oltean state->interface == PHY_INTERFACE_MODE_USXGMII) { 797375e1314SVladimir Oltean phylink_set(mask, 2500baseT_Full); 798375e1314SVladimir Oltean phylink_set(mask, 2500baseX_Full); 799375e1314SVladimir Oltean } 800375e1314SVladimir Oltean 801375e1314SVladimir Oltean bitmap_and(supported, supported, mask, 802375e1314SVladimir Oltean __ETHTOOL_LINK_MODE_MASK_NBITS); 803375e1314SVladimir Oltean bitmap_and(state->advertising, state->advertising, mask, 804375e1314SVladimir Oltean __ETHTOOL_LINK_MODE_MASK_NBITS); 805375e1314SVladimir Oltean } 806375e1314SVladimir Oltean 807bdeced75SVladimir Oltean static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port, 808bdeced75SVladimir Oltean phy_interface_t phy_mode) 809bdeced75SVladimir Oltean { 810bdeced75SVladimir Oltean switch (phy_mode) { 81128a134f5SVladimir Oltean case PHY_INTERFACE_MODE_INTERNAL: 812bdeced75SVladimir Oltean if (port != 4 && port != 5) 813bdeced75SVladimir Oltean return -ENOTSUPP; 814bdeced75SVladimir Oltean return 0; 815bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 816bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 817bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 818bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 819bdeced75SVladimir Oltean /* Not supported on internal to-CPU ports */ 820bdeced75SVladimir Oltean if (port == 4 || port == 5) 821bdeced75SVladimir Oltean return -ENOTSUPP; 822bdeced75SVladimir Oltean return 0; 823bdeced75SVladimir Oltean default: 824bdeced75SVladimir Oltean return -ENOTSUPP; 825bdeced75SVladimir Oltean } 826bdeced75SVladimir Oltean } 827bdeced75SVladimir Oltean 828aa92d836SMaxim Kochetkov /* Watermark encode 829aa92d836SMaxim Kochetkov * Bit 8: Unit; 0:1, 1:16 830aa92d836SMaxim Kochetkov * Bit 7-0: Value to be multiplied with unit 831aa92d836SMaxim Kochetkov */ 832aa92d836SMaxim Kochetkov static u16 vsc9959_wm_enc(u16 value) 833aa92d836SMaxim Kochetkov { 834aa92d836SMaxim Kochetkov if (value >= BIT(8)) 835aa92d836SMaxim Kochetkov return BIT(8) | (value / 16); 836aa92d836SMaxim Kochetkov 837aa92d836SMaxim Kochetkov return value; 838aa92d836SMaxim Kochetkov } 839aa92d836SMaxim Kochetkov 84056051948SVladimir Oltean static const struct ocelot_ops vsc9959_ops = { 84156051948SVladimir Oltean .reset = vsc9959_reset, 842aa92d836SMaxim Kochetkov .wm_enc = vsc9959_wm_enc, 84356051948SVladimir Oltean }; 84456051948SVladimir Oltean 845bdeced75SVladimir Oltean static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 846bdeced75SVladimir Oltean { 847bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 848bdeced75SVladimir Oltean struct enetc_mdio_priv *mdio_priv; 849bdeced75SVladimir Oltean struct device *dev = ocelot->dev; 850bdeced75SVladimir Oltean void __iomem *imdio_regs; 851b4024c9eSClaudiu Manoil struct resource res; 852bdeced75SVladimir Oltean struct enetc_hw *hw; 853bdeced75SVladimir Oltean struct mii_bus *bus; 854bdeced75SVladimir Oltean int port; 855bdeced75SVladimir Oltean int rc; 856bdeced75SVladimir Oltean 857bdeced75SVladimir Oltean felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 858588d0550SIoana Ciornei sizeof(struct lynx_pcs *), 859bdeced75SVladimir Oltean GFP_KERNEL); 860bdeced75SVladimir Oltean if (!felix->pcs) { 861bdeced75SVladimir Oltean dev_err(dev, "failed to allocate array for PCS PHYs\n"); 862bdeced75SVladimir Oltean return -ENOMEM; 863bdeced75SVladimir Oltean } 864bdeced75SVladimir Oltean 865b4024c9eSClaudiu Manoil memcpy(&res, felix->info->imdio_res, sizeof(res)); 866b4024c9eSClaudiu Manoil res.flags = IORESOURCE_MEM; 867375e1314SVladimir Oltean res.start += felix->imdio_base; 868375e1314SVladimir Oltean res.end += felix->imdio_base; 869bdeced75SVladimir Oltean 870b4024c9eSClaudiu Manoil imdio_regs = devm_ioremap_resource(dev, &res); 871bdeced75SVladimir Oltean if (IS_ERR(imdio_regs)) { 872bdeced75SVladimir Oltean dev_err(dev, "failed to map internal MDIO registers\n"); 873bdeced75SVladimir Oltean return PTR_ERR(imdio_regs); 874bdeced75SVladimir Oltean } 875bdeced75SVladimir Oltean 876bdeced75SVladimir Oltean hw = enetc_hw_alloc(dev, imdio_regs); 877bdeced75SVladimir Oltean if (IS_ERR(hw)) { 878bdeced75SVladimir Oltean dev_err(dev, "failed to allocate ENETC HW structure\n"); 879bdeced75SVladimir Oltean return PTR_ERR(hw); 880bdeced75SVladimir Oltean } 881bdeced75SVladimir Oltean 882bdeced75SVladimir Oltean bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv)); 883bdeced75SVladimir Oltean if (!bus) 884bdeced75SVladimir Oltean return -ENOMEM; 885bdeced75SVladimir Oltean 886bdeced75SVladimir Oltean bus->name = "VSC9959 internal MDIO bus"; 887bdeced75SVladimir Oltean bus->read = enetc_mdio_read; 888bdeced75SVladimir Oltean bus->write = enetc_mdio_write; 889bdeced75SVladimir Oltean bus->parent = dev; 890bdeced75SVladimir Oltean mdio_priv = bus->priv; 891bdeced75SVladimir Oltean mdio_priv->hw = hw; 892bdeced75SVladimir Oltean /* This gets added to imdio_regs, which already maps addresses 893bdeced75SVladimir Oltean * starting with the proper offset. 894bdeced75SVladimir Oltean */ 895bdeced75SVladimir Oltean mdio_priv->mdio_base = 0; 896bdeced75SVladimir Oltean snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 897bdeced75SVladimir Oltean 898bdeced75SVladimir Oltean /* Needed in order to initialize the bus mutex lock */ 899bdeced75SVladimir Oltean rc = mdiobus_register(bus); 900bdeced75SVladimir Oltean if (rc < 0) { 901bdeced75SVladimir Oltean dev_err(dev, "failed to register MDIO bus\n"); 902bdeced75SVladimir Oltean return rc; 903bdeced75SVladimir Oltean } 904bdeced75SVladimir Oltean 905bdeced75SVladimir Oltean felix->imdio = bus; 906bdeced75SVladimir Oltean 907bdeced75SVladimir Oltean for (port = 0; port < felix->info->num_ports; port++) { 908bdeced75SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 909588d0550SIoana Ciornei struct mdio_device *pcs; 910588d0550SIoana Ciornei struct lynx_pcs *lynx; 911bdeced75SVladimir Oltean 912588d0550SIoana Ciornei if (dsa_is_unused_port(felix->ds, port)) 913588d0550SIoana Ciornei continue; 914bdeced75SVladimir Oltean 915588d0550SIoana Ciornei if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 916588d0550SIoana Ciornei continue; 917588d0550SIoana Ciornei 918588d0550SIoana Ciornei pcs = mdio_device_create(felix->imdio, port); 919bdeced75SVladimir Oltean if (IS_ERR(pcs)) 920bdeced75SVladimir Oltean continue; 921bdeced75SVladimir Oltean 922588d0550SIoana Ciornei lynx = lynx_pcs_create(pcs); 923588d0550SIoana Ciornei if (!lynx) { 924588d0550SIoana Ciornei mdio_device_free(pcs); 925588d0550SIoana Ciornei continue; 926588d0550SIoana Ciornei } 927588d0550SIoana Ciornei 928588d0550SIoana Ciornei felix->pcs[port] = lynx; 929bdeced75SVladimir Oltean 930bdeced75SVladimir Oltean dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 931bdeced75SVladimir Oltean } 932bdeced75SVladimir Oltean 933bdeced75SVladimir Oltean return 0; 934bdeced75SVladimir Oltean } 935bdeced75SVladimir Oltean 93684705fc1SMaxim Kochetkov void vsc9959_mdio_bus_free(struct ocelot *ocelot) 937bdeced75SVladimir Oltean { 938bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 939bdeced75SVladimir Oltean int port; 940bdeced75SVladimir Oltean 941bdeced75SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) { 942588d0550SIoana Ciornei struct lynx_pcs *pcs = felix->pcs[port]; 943bdeced75SVladimir Oltean 944bdeced75SVladimir Oltean if (!pcs) 945bdeced75SVladimir Oltean continue; 946bdeced75SVladimir Oltean 947588d0550SIoana Ciornei mdio_device_free(pcs->mdio); 948588d0550SIoana Ciornei lynx_pcs_destroy(pcs); 949bdeced75SVladimir Oltean } 950bdeced75SVladimir Oltean mdiobus_unregister(felix->imdio); 951bdeced75SVladimir Oltean } 952bdeced75SVladimir Oltean 953de143c0eSXiaoliang Yang static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 954de143c0eSXiaoliang Yang u32 speed) 955de143c0eSXiaoliang Yang { 956de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 957de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED(speed), 958de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED_M, 959de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 960de143c0eSXiaoliang Yang } 961de143c0eSXiaoliang Yang 962de143c0eSXiaoliang Yang static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 963de143c0eSXiaoliang Yang u64 cycle_time, 964de143c0eSXiaoliang Yang struct timespec64 *new_base_ts) 965de143c0eSXiaoliang Yang { 966de143c0eSXiaoliang Yang struct timespec64 ts; 967de143c0eSXiaoliang Yang ktime_t new_base_time; 968de143c0eSXiaoliang Yang ktime_t current_time; 969de143c0eSXiaoliang Yang 970de143c0eSXiaoliang Yang ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 971de143c0eSXiaoliang Yang current_time = timespec64_to_ktime(ts); 972de143c0eSXiaoliang Yang new_base_time = base_time; 973de143c0eSXiaoliang Yang 974de143c0eSXiaoliang Yang if (base_time < current_time) { 975de143c0eSXiaoliang Yang u64 nr_of_cycles = current_time - base_time; 976de143c0eSXiaoliang Yang 977de143c0eSXiaoliang Yang do_div(nr_of_cycles, cycle_time); 978de143c0eSXiaoliang Yang new_base_time += cycle_time * (nr_of_cycles + 1); 979de143c0eSXiaoliang Yang } 980de143c0eSXiaoliang Yang 981de143c0eSXiaoliang Yang *new_base_ts = ktime_to_timespec64(new_base_time); 982de143c0eSXiaoliang Yang } 983de143c0eSXiaoliang Yang 984de143c0eSXiaoliang Yang static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 985de143c0eSXiaoliang Yang { 986de143c0eSXiaoliang Yang return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 987de143c0eSXiaoliang Yang } 988de143c0eSXiaoliang Yang 989de143c0eSXiaoliang Yang static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 990de143c0eSXiaoliang Yang struct tc_taprio_sched_entry *entry) 991de143c0eSXiaoliang Yang { 992de143c0eSXiaoliang Yang ocelot_write(ocelot, 993de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 994de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 995de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1); 996de143c0eSXiaoliang Yang ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 997de143c0eSXiaoliang Yang } 998de143c0eSXiaoliang Yang 999de143c0eSXiaoliang Yang static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1000de143c0eSXiaoliang Yang struct tc_taprio_qopt_offload *taprio) 1001de143c0eSXiaoliang Yang { 1002de143c0eSXiaoliang Yang struct timespec64 base_ts; 1003de143c0eSXiaoliang Yang int ret, i; 1004de143c0eSXiaoliang Yang u32 val; 1005de143c0eSXiaoliang Yang 1006de143c0eSXiaoliang Yang if (!taprio->enable) { 1007de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1008de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF), 1009de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1010de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE_M, 1011de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1012de143c0eSXiaoliang Yang 1013de143c0eSXiaoliang Yang return 0; 1014de143c0eSXiaoliang Yang } 1015de143c0eSXiaoliang Yang 1016de143c0eSXiaoliang Yang if (taprio->cycle_time > NSEC_PER_SEC || 1017de143c0eSXiaoliang Yang taprio->cycle_time_extension >= NSEC_PER_SEC) 1018de143c0eSXiaoliang Yang return -EINVAL; 1019de143c0eSXiaoliang Yang 1020de143c0eSXiaoliang Yang if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) 1021de143c0eSXiaoliang Yang return -ERANGE; 1022de143c0eSXiaoliang Yang 1023de143c0eSXiaoliang Yang ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1024de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1025de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1026de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1027de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 1028de143c0eSXiaoliang Yang 1029de143c0eSXiaoliang Yang /* Hardware errata - Admin config could not be overwritten if 1030de143c0eSXiaoliang Yang * config is pending, need reset the TAS module 1031de143c0eSXiaoliang Yang */ 1032de143c0eSXiaoliang Yang val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1033de143c0eSXiaoliang Yang if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) 1034de143c0eSXiaoliang Yang return -EBUSY; 1035de143c0eSXiaoliang Yang 1036de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1037de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1038de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1039de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1040de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1041de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1042de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1043de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1044de143c0eSXiaoliang Yang 1045de143c0eSXiaoliang Yang vsc9959_new_base_time(ocelot, taprio->base_time, 1046de143c0eSXiaoliang Yang taprio->cycle_time, &base_ts); 1047de143c0eSXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1048de143c0eSXiaoliang Yang ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1049de143c0eSXiaoliang Yang val = upper_32_bits(base_ts.tv_sec); 1050de143c0eSXiaoliang Yang ocelot_write(ocelot, 1051de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1052de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1053de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3); 1054de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1055de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1056de143c0eSXiaoliang Yang 1057de143c0eSXiaoliang Yang for (i = 0; i < taprio->num_entries; i++) 1058de143c0eSXiaoliang Yang vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1059de143c0eSXiaoliang Yang 1060de143c0eSXiaoliang Yang ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1061de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1062de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 1063de143c0eSXiaoliang Yang 1064de143c0eSXiaoliang Yang ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1065de143c0eSXiaoliang Yang !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1066de143c0eSXiaoliang Yang 10, 100000); 1067de143c0eSXiaoliang Yang 1068de143c0eSXiaoliang Yang return ret; 1069de143c0eSXiaoliang Yang } 1070de143c0eSXiaoliang Yang 10710fbabf87SXiaoliang Yang static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 10720fbabf87SXiaoliang Yang struct tc_cbs_qopt_offload *cbs_qopt) 10730fbabf87SXiaoliang Yang { 10740fbabf87SXiaoliang Yang struct ocelot *ocelot = ds->priv; 10750fbabf87SXiaoliang Yang int port_ix = port * 8 + cbs_qopt->queue; 10760fbabf87SXiaoliang Yang u32 rate, burst; 10770fbabf87SXiaoliang Yang 10780fbabf87SXiaoliang Yang if (cbs_qopt->queue >= ds->num_tx_queues) 10790fbabf87SXiaoliang Yang return -EINVAL; 10800fbabf87SXiaoliang Yang 10810fbabf87SXiaoliang Yang if (!cbs_qopt->enable) { 10820fbabf87SXiaoliang Yang ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 10830fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(0), 10840fbabf87SXiaoliang Yang QSYS_CIR_CFG, port_ix); 10850fbabf87SXiaoliang Yang 10860fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 10870fbabf87SXiaoliang Yang QSYS_SE_CFG, port_ix); 10880fbabf87SXiaoliang Yang 10890fbabf87SXiaoliang Yang return 0; 10900fbabf87SXiaoliang Yang } 10910fbabf87SXiaoliang Yang 10920fbabf87SXiaoliang Yang /* Rate unit is 100 kbps */ 10930fbabf87SXiaoliang Yang rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 10940fbabf87SXiaoliang Yang /* Avoid using zero rate */ 10950fbabf87SXiaoliang Yang rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 10960fbabf87SXiaoliang Yang /* Burst unit is 4kB */ 10970fbabf87SXiaoliang Yang burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 10980fbabf87SXiaoliang Yang /* Avoid using zero burst size */ 1099b014d043SColin Ian King burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 11000fbabf87SXiaoliang Yang ocelot_write_gix(ocelot, 11010fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_RATE(rate) | 11020fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(burst), 11030fbabf87SXiaoliang Yang QSYS_CIR_CFG, 11040fbabf87SXiaoliang Yang port_ix); 11050fbabf87SXiaoliang Yang 11060fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot, 11070fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE(0) | 11080fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA, 11090fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA | 11100fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE_M, 11110fbabf87SXiaoliang Yang QSYS_SE_CFG, 11120fbabf87SXiaoliang Yang port_ix); 11130fbabf87SXiaoliang Yang 11140fbabf87SXiaoliang Yang return 0; 11150fbabf87SXiaoliang Yang } 11160fbabf87SXiaoliang Yang 1117de143c0eSXiaoliang Yang static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1118de143c0eSXiaoliang Yang enum tc_setup_type type, 1119de143c0eSXiaoliang Yang void *type_data) 1120de143c0eSXiaoliang Yang { 1121de143c0eSXiaoliang Yang struct ocelot *ocelot = ds->priv; 1122de143c0eSXiaoliang Yang 1123de143c0eSXiaoliang Yang switch (type) { 1124de143c0eSXiaoliang Yang case TC_SETUP_QDISC_TAPRIO: 1125de143c0eSXiaoliang Yang return vsc9959_qos_port_tas_set(ocelot, port, type_data); 11260fbabf87SXiaoliang Yang case TC_SETUP_QDISC_CBS: 11270fbabf87SXiaoliang Yang return vsc9959_qos_port_cbs_set(ds, port, type_data); 1128de143c0eSXiaoliang Yang default: 1129de143c0eSXiaoliang Yang return -EOPNOTSUPP; 1130de143c0eSXiaoliang Yang } 1131de143c0eSXiaoliang Yang } 1132de143c0eSXiaoliang Yang 113367c24049SVladimir Oltean static void vsc9959_xmit_template_populate(struct ocelot *ocelot, int port) 113467c24049SVladimir Oltean { 113567c24049SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 113667c24049SVladimir Oltean u8 *template = ocelot_port->xmit_template; 113767c24049SVladimir Oltean u64 bypass, dest, src; 113867c24049SVladimir Oltean 113967c24049SVladimir Oltean /* Set the source port as the CPU port module and not the 114067c24049SVladimir Oltean * NPI port 114167c24049SVladimir Oltean */ 114267c24049SVladimir Oltean src = ocelot->num_phys_ports; 114367c24049SVladimir Oltean dest = BIT(port); 114467c24049SVladimir Oltean bypass = true; 114567c24049SVladimir Oltean 114667c24049SVladimir Oltean packing(template, &bypass, 127, 127, OCELOT_TAG_LEN, PACK, 0); 114767c24049SVladimir Oltean packing(template, &dest, 68, 56, OCELOT_TAG_LEN, PACK, 0); 114867c24049SVladimir Oltean packing(template, &src, 46, 43, OCELOT_TAG_LEN, PACK, 0); 114967c24049SVladimir Oltean } 115067c24049SVladimir Oltean 1151375e1314SVladimir Oltean static const struct felix_info felix_info_vsc9959 = { 115256051948SVladimir Oltean .target_io_res = vsc9959_target_io_res, 115356051948SVladimir Oltean .port_io_res = vsc9959_port_io_res, 1154bdeced75SVladimir Oltean .imdio_res = &vsc9959_imdio_res, 115556051948SVladimir Oltean .regfields = vsc9959_regfields, 115656051948SVladimir Oltean .map = vsc9959_regmap, 115756051948SVladimir Oltean .ops = &vsc9959_ops, 115856051948SVladimir Oltean .stats_layout = vsc9959_stats_layout, 115956051948SVladimir Oltean .num_stats = ARRAY_SIZE(vsc9959_stats_layout), 116007d985eeSVladimir Oltean .vcap_is2_keys = vsc9959_vcap_is2_keys, 116107d985eeSVladimir Oltean .vcap_is2_actions = vsc9959_vcap_is2_actions, 116207d985eeSVladimir Oltean .vcap = vsc9959_vcap_props, 116356051948SVladimir Oltean .shared_queue_sz = 128 * 1024, 116421ce7f3eSVladimir Oltean .num_mact_rows = 2048, 116556051948SVladimir Oltean .num_ports = 6, 1166de143c0eSXiaoliang Yang .num_tx_queues = FELIX_NUM_TC, 1167bdeced75SVladimir Oltean .switch_pci_bar = 4, 1168bdeced75SVladimir Oltean .imdio_pci_bar = 0, 1169bdeced75SVladimir Oltean .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 1170bdeced75SVladimir Oltean .mdio_bus_free = vsc9959_mdio_bus_free, 1171375e1314SVladimir Oltean .phylink_validate = vsc9959_phylink_validate, 1172bdeced75SVladimir Oltean .prevalidate_phy_mode = vsc9959_prevalidate_phy_mode, 1173de143c0eSXiaoliang Yang .port_setup_tc = vsc9959_port_setup_tc, 1174de143c0eSXiaoliang Yang .port_sched_speed_set = vsc9959_sched_speed_set, 117567c24049SVladimir Oltean .xmit_template_populate = vsc9959_xmit_template_populate, 117656051948SVladimir Oltean }; 1177375e1314SVladimir Oltean 1178375e1314SVladimir Oltean static irqreturn_t felix_irq_handler(int irq, void *data) 1179375e1314SVladimir Oltean { 1180375e1314SVladimir Oltean struct ocelot *ocelot = (struct ocelot *)data; 1181375e1314SVladimir Oltean 1182375e1314SVladimir Oltean /* The INTB interrupt is used for both PTP TX timestamp interrupt 1183375e1314SVladimir Oltean * and preemption status change interrupt on each port. 1184375e1314SVladimir Oltean * 1185375e1314SVladimir Oltean * - Get txtstamp if have 1186375e1314SVladimir Oltean * - TODO: handle preemption. Without handling it, driver may get 1187375e1314SVladimir Oltean * interrupt storm. 1188375e1314SVladimir Oltean */ 1189375e1314SVladimir Oltean 1190375e1314SVladimir Oltean ocelot_get_txtstamp(ocelot); 1191375e1314SVladimir Oltean 1192375e1314SVladimir Oltean return IRQ_HANDLED; 1193375e1314SVladimir Oltean } 1194375e1314SVladimir Oltean 1195375e1314SVladimir Oltean static int felix_pci_probe(struct pci_dev *pdev, 1196375e1314SVladimir Oltean const struct pci_device_id *id) 1197375e1314SVladimir Oltean { 1198375e1314SVladimir Oltean struct dsa_switch *ds; 1199375e1314SVladimir Oltean struct ocelot *ocelot; 1200375e1314SVladimir Oltean struct felix *felix; 1201375e1314SVladimir Oltean int err; 1202375e1314SVladimir Oltean 1203375e1314SVladimir Oltean if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 1204375e1314SVladimir Oltean dev_info(&pdev->dev, "device is disabled, skipping\n"); 1205375e1314SVladimir Oltean return -ENODEV; 1206375e1314SVladimir Oltean } 1207375e1314SVladimir Oltean 1208375e1314SVladimir Oltean err = pci_enable_device(pdev); 1209375e1314SVladimir Oltean if (err) { 1210375e1314SVladimir Oltean dev_err(&pdev->dev, "device enable failed\n"); 1211375e1314SVladimir Oltean goto err_pci_enable; 1212375e1314SVladimir Oltean } 1213375e1314SVladimir Oltean 1214375e1314SVladimir Oltean /* set up for high or low dma */ 1215375e1314SVladimir Oltean err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1216375e1314SVladimir Oltean if (err) { 1217375e1314SVladimir Oltean err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1218375e1314SVladimir Oltean if (err) { 1219375e1314SVladimir Oltean dev_err(&pdev->dev, 1220375e1314SVladimir Oltean "DMA configuration failed: 0x%x\n", err); 1221375e1314SVladimir Oltean goto err_dma; 1222375e1314SVladimir Oltean } 1223375e1314SVladimir Oltean } 1224375e1314SVladimir Oltean 1225375e1314SVladimir Oltean felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 1226375e1314SVladimir Oltean if (!felix) { 1227375e1314SVladimir Oltean err = -ENOMEM; 1228375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 1229375e1314SVladimir Oltean goto err_alloc_felix; 1230375e1314SVladimir Oltean } 1231375e1314SVladimir Oltean 1232375e1314SVladimir Oltean pci_set_drvdata(pdev, felix); 1233375e1314SVladimir Oltean ocelot = &felix->ocelot; 1234375e1314SVladimir Oltean ocelot->dev = &pdev->dev; 1235375e1314SVladimir Oltean felix->info = &felix_info_vsc9959; 1236375e1314SVladimir Oltean felix->switch_base = pci_resource_start(pdev, 1237375e1314SVladimir Oltean felix->info->switch_pci_bar); 1238375e1314SVladimir Oltean felix->imdio_base = pci_resource_start(pdev, 1239375e1314SVladimir Oltean felix->info->imdio_pci_bar); 1240375e1314SVladimir Oltean 1241375e1314SVladimir Oltean pci_set_master(pdev); 1242375e1314SVladimir Oltean 1243375e1314SVladimir Oltean err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 1244375e1314SVladimir Oltean &felix_irq_handler, IRQF_ONESHOT, 1245375e1314SVladimir Oltean "felix-intb", ocelot); 1246375e1314SVladimir Oltean if (err) { 1247375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to request irq\n"); 1248375e1314SVladimir Oltean goto err_alloc_irq; 1249375e1314SVladimir Oltean } 1250375e1314SVladimir Oltean 1251375e1314SVladimir Oltean ocelot->ptp = 1; 1252375e1314SVladimir Oltean 1253375e1314SVladimir Oltean ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 1254375e1314SVladimir Oltean if (!ds) { 1255375e1314SVladimir Oltean err = -ENOMEM; 1256375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 1257375e1314SVladimir Oltean goto err_alloc_ds; 1258375e1314SVladimir Oltean } 1259375e1314SVladimir Oltean 1260375e1314SVladimir Oltean ds->dev = &pdev->dev; 1261375e1314SVladimir Oltean ds->num_ports = felix->info->num_ports; 1262375e1314SVladimir Oltean ds->num_tx_queues = felix->info->num_tx_queues; 1263375e1314SVladimir Oltean ds->ops = &felix_switch_ops; 1264375e1314SVladimir Oltean ds->priv = ocelot; 1265375e1314SVladimir Oltean felix->ds = ds; 1266375e1314SVladimir Oltean 1267375e1314SVladimir Oltean err = dsa_register_switch(ds); 1268375e1314SVladimir Oltean if (err) { 1269375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err); 1270375e1314SVladimir Oltean goto err_register_ds; 1271375e1314SVladimir Oltean } 1272375e1314SVladimir Oltean 1273375e1314SVladimir Oltean return 0; 1274375e1314SVladimir Oltean 1275375e1314SVladimir Oltean err_register_ds: 1276375e1314SVladimir Oltean kfree(ds); 1277375e1314SVladimir Oltean err_alloc_ds: 1278375e1314SVladimir Oltean err_alloc_irq: 1279375e1314SVladimir Oltean err_alloc_felix: 1280375e1314SVladimir Oltean kfree(felix); 1281375e1314SVladimir Oltean err_dma: 1282375e1314SVladimir Oltean pci_disable_device(pdev); 1283375e1314SVladimir Oltean err_pci_enable: 1284375e1314SVladimir Oltean return err; 1285375e1314SVladimir Oltean } 1286375e1314SVladimir Oltean 1287375e1314SVladimir Oltean static void felix_pci_remove(struct pci_dev *pdev) 1288375e1314SVladimir Oltean { 1289375e1314SVladimir Oltean struct felix *felix; 1290375e1314SVladimir Oltean 1291375e1314SVladimir Oltean felix = pci_get_drvdata(pdev); 1292375e1314SVladimir Oltean 1293375e1314SVladimir Oltean dsa_unregister_switch(felix->ds); 1294375e1314SVladimir Oltean 1295375e1314SVladimir Oltean kfree(felix->ds); 1296375e1314SVladimir Oltean kfree(felix); 1297375e1314SVladimir Oltean 1298375e1314SVladimir Oltean pci_disable_device(pdev); 1299375e1314SVladimir Oltean } 1300375e1314SVladimir Oltean 1301375e1314SVladimir Oltean static struct pci_device_id felix_ids[] = { 1302375e1314SVladimir Oltean { 1303375e1314SVladimir Oltean /* NXP LS1028A */ 1304375e1314SVladimir Oltean PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 1305375e1314SVladimir Oltean }, 1306375e1314SVladimir Oltean { 0, } 1307375e1314SVladimir Oltean }; 1308375e1314SVladimir Oltean MODULE_DEVICE_TABLE(pci, felix_ids); 1309375e1314SVladimir Oltean 1310375e1314SVladimir Oltean struct pci_driver felix_vsc9959_pci_driver = { 1311375e1314SVladimir Oltean .name = "mscc_felix", 1312375e1314SVladimir Oltean .id_table = felix_ids, 1313375e1314SVladimir Oltean .probe = felix_pci_probe, 1314375e1314SVladimir Oltean .remove = felix_pci_remove, 1315375e1314SVladimir Oltean }; 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