156051948SVladimir Oltean // SPDX-License-Identifier: (GPL-2.0 OR MIT) 256051948SVladimir Oltean /* Copyright 2017 Microsemi Corporation 356051948SVladimir Oltean * Copyright 2018-2019 NXP Semiconductors 456051948SVladimir Oltean */ 5bdeced75SVladimir Oltean #include <linux/fsl/enetc_mdio.h> 6de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_qsys.h> 707d985eeSVladimir Oltean #include <soc/mscc/ocelot_vcap.h> 8de143c0eSXiaoliang Yang #include <soc/mscc/ocelot_ptp.h> 956051948SVladimir Oltean #include <soc/mscc/ocelot_sys.h> 1056051948SVladimir Oltean #include <soc/mscc/ocelot.h> 1167c24049SVladimir Oltean #include <linux/packing.h> 12de143c0eSXiaoliang Yang #include <net/pkt_sched.h> 1356051948SVladimir Oltean #include <linux/iopoll.h> 1416659b81SMichael Walle #include <linux/mdio.h> 1556051948SVladimir Oltean #include <linux/pci.h> 1656051948SVladimir Oltean #include "felix.h" 1756051948SVladimir Oltean 1807d985eeSVladimir Oltean #define VSC9959_VCAP_IS2_CNT 1024 1907d985eeSVladimir Oltean #define VSC9959_VCAP_IS2_ENTRY_WIDTH 376 2007d985eeSVladimir Oltean #define VSC9959_VCAP_PORT_CNT 6 21de143c0eSXiaoliang Yang #define VSC9959_TAS_GCL_ENTRY_MAX 63 22de143c0eSXiaoliang Yang 2356051948SVladimir Oltean static const u32 vsc9959_ana_regmap[] = { 2456051948SVladimir Oltean REG(ANA_ADVLEARN, 0x0089a0), 2556051948SVladimir Oltean REG(ANA_VLANMASK, 0x0089a4), 2656051948SVladimir Oltean REG_RESERVED(ANA_PORT_B_DOMAIN), 2756051948SVladimir Oltean REG(ANA_ANAGEFIL, 0x0089ac), 2856051948SVladimir Oltean REG(ANA_ANEVENTS, 0x0089b0), 2956051948SVladimir Oltean REG(ANA_STORMLIMIT_BURST, 0x0089b4), 3056051948SVladimir Oltean REG(ANA_STORMLIMIT_CFG, 0x0089b8), 3156051948SVladimir Oltean REG(ANA_ISOLATED_PORTS, 0x0089c8), 3256051948SVladimir Oltean REG(ANA_COMMUNITY_PORTS, 0x0089cc), 3356051948SVladimir Oltean REG(ANA_AUTOAGE, 0x0089d0), 3456051948SVladimir Oltean REG(ANA_MACTOPTIONS, 0x0089d4), 3556051948SVladimir Oltean REG(ANA_LEARNDISC, 0x0089d8), 3656051948SVladimir Oltean REG(ANA_AGENCTRL, 0x0089dc), 3756051948SVladimir Oltean REG(ANA_MIRRORPORTS, 0x0089e0), 3856051948SVladimir Oltean REG(ANA_EMIRRORPORTS, 0x0089e4), 3956051948SVladimir Oltean REG(ANA_FLOODING, 0x0089e8), 4056051948SVladimir Oltean REG(ANA_FLOODING_IPMC, 0x008a08), 4156051948SVladimir Oltean REG(ANA_SFLOW_CFG, 0x008a0c), 4256051948SVladimir Oltean REG(ANA_PORT_MODE, 0x008a28), 4356051948SVladimir Oltean REG(ANA_CUT_THRU_CFG, 0x008a48), 4456051948SVladimir Oltean REG(ANA_PGID_PGID, 0x008400), 4556051948SVladimir Oltean REG(ANA_TABLES_ANMOVED, 0x007f1c), 4656051948SVladimir Oltean REG(ANA_TABLES_MACHDATA, 0x007f20), 4756051948SVladimir Oltean REG(ANA_TABLES_MACLDATA, 0x007f24), 4856051948SVladimir Oltean REG(ANA_TABLES_STREAMDATA, 0x007f28), 4956051948SVladimir Oltean REG(ANA_TABLES_MACACCESS, 0x007f2c), 5056051948SVladimir Oltean REG(ANA_TABLES_MACTINDX, 0x007f30), 5156051948SVladimir Oltean REG(ANA_TABLES_VLANACCESS, 0x007f34), 5256051948SVladimir Oltean REG(ANA_TABLES_VLANTIDX, 0x007f38), 5356051948SVladimir Oltean REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 5456051948SVladimir Oltean REG(ANA_TABLES_ISDXTIDX, 0x007f40), 5556051948SVladimir Oltean REG(ANA_TABLES_ENTRYLIM, 0x007f00), 5656051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 5756051948SVladimir Oltean REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 5856051948SVladimir Oltean REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 5956051948SVladimir Oltean REG(ANA_TABLES_STREAMTIDX, 0x007f50), 6056051948SVladimir Oltean REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 6156051948SVladimir Oltean REG(ANA_TABLES_SEQ_MASK, 0x007f58), 6256051948SVladimir Oltean REG(ANA_TABLES_SFID_MASK, 0x007f5c), 6356051948SVladimir Oltean REG(ANA_TABLES_SFIDACCESS, 0x007f60), 6456051948SVladimir Oltean REG(ANA_TABLES_SFIDTIDX, 0x007f64), 6556051948SVladimir Oltean REG(ANA_MSTI_STATE, 0x008600), 6656051948SVladimir Oltean REG(ANA_OAM_UPM_LM_CNT, 0x008000), 6756051948SVladimir Oltean REG(ANA_SG_ACCESS_CTRL, 0x008a64), 6856051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 6956051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 7056051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 7156051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 7256051948SVladimir Oltean REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 7356051948SVladimir Oltean REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 7456051948SVladimir Oltean REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 7556051948SVladimir Oltean REG(ANA_SG_STATUS_REG_1, 0x008980), 7656051948SVladimir Oltean REG(ANA_SG_STATUS_REG_2, 0x008984), 7756051948SVladimir Oltean REG(ANA_SG_STATUS_REG_3, 0x008988), 7856051948SVladimir Oltean REG(ANA_PORT_VLAN_CFG, 0x007800), 7956051948SVladimir Oltean REG(ANA_PORT_DROP_CFG, 0x007804), 8056051948SVladimir Oltean REG(ANA_PORT_QOS_CFG, 0x007808), 8156051948SVladimir Oltean REG(ANA_PORT_VCAP_CFG, 0x00780c), 8256051948SVladimir Oltean REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 8356051948SVladimir Oltean REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 8456051948SVladimir Oltean REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 8556051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 8656051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 8756051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 8856051948SVladimir Oltean REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 8956051948SVladimir Oltean REG(ANA_PORT_PORT_CFG, 0x007870), 9056051948SVladimir Oltean REG(ANA_PORT_POL_CFG, 0x007874), 9156051948SVladimir Oltean REG(ANA_PORT_PTP_CFG, 0x007878), 9256051948SVladimir Oltean REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 9356051948SVladimir Oltean REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 9456051948SVladimir Oltean REG(ANA_PORT_SFID_CFG, 0x007884), 9556051948SVladimir Oltean REG(ANA_PFC_PFC_CFG, 0x008800), 9656051948SVladimir Oltean REG_RESERVED(ANA_PFC_PFC_TIMER), 9756051948SVladimir Oltean REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 9856051948SVladimir Oltean REG_RESERVED(ANA_IPT_IPT), 9956051948SVladimir Oltean REG_RESERVED(ANA_PPT_PPT), 10056051948SVladimir Oltean REG_RESERVED(ANA_FID_MAP_FID_MAP), 10156051948SVladimir Oltean REG(ANA_AGGR_CFG, 0x008a68), 10256051948SVladimir Oltean REG(ANA_CPUQ_CFG, 0x008a6c), 10356051948SVladimir Oltean REG_RESERVED(ANA_CPUQ_CFG2), 10456051948SVladimir Oltean REG(ANA_CPUQ_8021_CFG, 0x008a74), 10556051948SVladimir Oltean REG(ANA_DSCP_CFG, 0x008ab4), 10656051948SVladimir Oltean REG(ANA_DSCP_REWR_CFG, 0x008bb4), 10756051948SVladimir Oltean REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 10856051948SVladimir Oltean REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 10956051948SVladimir Oltean REG_RESERVED(ANA_VRAP_CFG), 11056051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_DATA), 11156051948SVladimir Oltean REG_RESERVED(ANA_VRAP_HDR_MASK), 11256051948SVladimir Oltean REG(ANA_DISCARD_CFG, 0x008c40), 11356051948SVladimir Oltean REG(ANA_FID_CFG, 0x008c44), 11456051948SVladimir Oltean REG(ANA_POL_PIR_CFG, 0x004000), 11556051948SVladimir Oltean REG(ANA_POL_CIR_CFG, 0x004004), 11656051948SVladimir Oltean REG(ANA_POL_MODE_CFG, 0x004008), 11756051948SVladimir Oltean REG(ANA_POL_PIR_STATE, 0x00400c), 11856051948SVladimir Oltean REG(ANA_POL_CIR_STATE, 0x004010), 11956051948SVladimir Oltean REG_RESERVED(ANA_POL_STATE), 12056051948SVladimir Oltean REG(ANA_POL_FLOWC, 0x008c48), 12156051948SVladimir Oltean REG(ANA_POL_HYST, 0x008cb4), 12256051948SVladimir Oltean REG_RESERVED(ANA_POL_MISC_CFG), 12356051948SVladimir Oltean }; 12456051948SVladimir Oltean 12556051948SVladimir Oltean static const u32 vsc9959_qs_regmap[] = { 12656051948SVladimir Oltean REG(QS_XTR_GRP_CFG, 0x000000), 12756051948SVladimir Oltean REG(QS_XTR_RD, 0x000008), 12856051948SVladimir Oltean REG(QS_XTR_FRM_PRUNING, 0x000010), 12956051948SVladimir Oltean REG(QS_XTR_FLUSH, 0x000018), 13056051948SVladimir Oltean REG(QS_XTR_DATA_PRESENT, 0x00001c), 13156051948SVladimir Oltean REG(QS_XTR_CFG, 0x000020), 13256051948SVladimir Oltean REG(QS_INJ_GRP_CFG, 0x000024), 13356051948SVladimir Oltean REG(QS_INJ_WR, 0x00002c), 13456051948SVladimir Oltean REG(QS_INJ_CTRL, 0x000034), 13556051948SVladimir Oltean REG(QS_INJ_STATUS, 0x00003c), 13656051948SVladimir Oltean REG(QS_INJ_ERR, 0x000040), 13756051948SVladimir Oltean REG_RESERVED(QS_INH_DBG), 13856051948SVladimir Oltean }; 13956051948SVladimir Oltean 14056051948SVladimir Oltean static const u32 vsc9959_s2_regmap[] = { 14156051948SVladimir Oltean REG(S2_CORE_UPDATE_CTRL, 0x000000), 14256051948SVladimir Oltean REG(S2_CORE_MV_CFG, 0x000004), 14356051948SVladimir Oltean REG(S2_CACHE_ENTRY_DAT, 0x000008), 14456051948SVladimir Oltean REG(S2_CACHE_MASK_DAT, 0x000108), 14556051948SVladimir Oltean REG(S2_CACHE_ACTION_DAT, 0x000208), 14656051948SVladimir Oltean REG(S2_CACHE_CNT_DAT, 0x000308), 14756051948SVladimir Oltean REG(S2_CACHE_TG_DAT, 0x000388), 14856051948SVladimir Oltean }; 14956051948SVladimir Oltean 15056051948SVladimir Oltean static const u32 vsc9959_qsys_regmap[] = { 15156051948SVladimir Oltean REG(QSYS_PORT_MODE, 0x00f460), 15256051948SVladimir Oltean REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 15356051948SVladimir Oltean REG(QSYS_STAT_CNT_CFG, 0x00f49c), 15456051948SVladimir Oltean REG(QSYS_EEE_CFG, 0x00f4a0), 15556051948SVladimir Oltean REG(QSYS_EEE_THRES, 0x00f4b8), 15656051948SVladimir Oltean REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 15756051948SVladimir Oltean REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 15856051948SVladimir Oltean REG(QSYS_SW_STATUS, 0x00f4c4), 15956051948SVladimir Oltean REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 16056051948SVladimir Oltean REG_RESERVED(QSYS_PAD_CFG), 16156051948SVladimir Oltean REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 16256051948SVladimir Oltean REG_RESERVED(QSYS_QMAP), 16356051948SVladimir Oltean REG_RESERVED(QSYS_ISDX_SGRP), 16456051948SVladimir Oltean REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 16556051948SVladimir Oltean REG(QSYS_TFRM_MISC, 0x00f50c), 16656051948SVladimir Oltean REG(QSYS_TFRM_PORT_DLY, 0x00f510), 16756051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 16856051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 16956051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 17056051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 17156051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 17256051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 17356051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 17456051948SVladimir Oltean REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 17556051948SVladimir Oltean REG(QSYS_RED_PROFILE, 0x00f534), 17656051948SVladimir Oltean REG(QSYS_RES_QOS_MODE, 0x00f574), 17756051948SVladimir Oltean REG(QSYS_RES_CFG, 0x00c000), 17856051948SVladimir Oltean REG(QSYS_RES_STAT, 0x00c004), 17956051948SVladimir Oltean REG(QSYS_EGR_DROP_MODE, 0x00f578), 18056051948SVladimir Oltean REG(QSYS_EQ_CTRL, 0x00f57c), 18156051948SVladimir Oltean REG_RESERVED(QSYS_EVENTS_CORE), 18256051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 18356051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 18456051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 18556051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 18656051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 18756051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 18856051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 18956051948SVladimir Oltean REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 19056051948SVladimir Oltean REG(QSYS_PREEMPTION_CFG, 0x00f664), 1910fbabf87SXiaoliang Yang REG(QSYS_CIR_CFG, 0x000000), 19256051948SVladimir Oltean REG(QSYS_EIR_CFG, 0x000004), 19356051948SVladimir Oltean REG(QSYS_SE_CFG, 0x000008), 19456051948SVladimir Oltean REG(QSYS_SE_DWRR_CFG, 0x00000c), 19556051948SVladimir Oltean REG_RESERVED(QSYS_SE_CONNECT), 19656051948SVladimir Oltean REG(QSYS_SE_DLB_SENSE, 0x000040), 19756051948SVladimir Oltean REG(QSYS_CIR_STATE, 0x000044), 19856051948SVladimir Oltean REG(QSYS_EIR_STATE, 0x000048), 19956051948SVladimir Oltean REG_RESERVED(QSYS_SE_STATE), 20056051948SVladimir Oltean REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 20156051948SVladimir Oltean REG(QSYS_TAG_CONFIG, 0x00f680), 20256051948SVladimir Oltean REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 20356051948SVladimir Oltean REG(QSYS_PORT_MAX_SDU, 0x00f69c), 20456051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 20556051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 20656051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 20756051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 20856051948SVladimir Oltean REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 20956051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_1, 0x00f454), 21056051948SVladimir Oltean REG(QSYS_GCL_CFG_REG_2, 0x00f458), 21156051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 21256051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 21356051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 21456051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 21556051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 21656051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 21756051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 21856051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 21956051948SVladimir Oltean REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 22056051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 22156051948SVladimir Oltean REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 22256051948SVladimir Oltean }; 22356051948SVladimir Oltean 22456051948SVladimir Oltean static const u32 vsc9959_rew_regmap[] = { 22556051948SVladimir Oltean REG(REW_PORT_VLAN_CFG, 0x000000), 22656051948SVladimir Oltean REG(REW_TAG_CFG, 0x000004), 22756051948SVladimir Oltean REG(REW_PORT_CFG, 0x000008), 22856051948SVladimir Oltean REG(REW_DSCP_CFG, 0x00000c), 22956051948SVladimir Oltean REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 23056051948SVladimir Oltean REG(REW_PTP_CFG, 0x000050), 23156051948SVladimir Oltean REG(REW_PTP_DLY1_CFG, 0x000054), 23256051948SVladimir Oltean REG(REW_RED_TAG_CFG, 0x000058), 23356051948SVladimir Oltean REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 23456051948SVladimir Oltean REG(REW_DSCP_REMAP_CFG, 0x000510), 23556051948SVladimir Oltean REG_RESERVED(REW_STAT_CFG), 23656051948SVladimir Oltean REG_RESERVED(REW_REW_STICKY), 23756051948SVladimir Oltean REG_RESERVED(REW_PPT), 23856051948SVladimir Oltean }; 23956051948SVladimir Oltean 24056051948SVladimir Oltean static const u32 vsc9959_sys_regmap[] = { 24156051948SVladimir Oltean REG(SYS_COUNT_RX_OCTETS, 0x000000), 24256051948SVladimir Oltean REG(SYS_COUNT_RX_MULTICAST, 0x000008), 24356051948SVladimir Oltean REG(SYS_COUNT_RX_SHORTS, 0x000010), 24456051948SVladimir Oltean REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 24556051948SVladimir Oltean REG(SYS_COUNT_RX_JABBERS, 0x000018), 24656051948SVladimir Oltean REG(SYS_COUNT_RX_64, 0x000024), 24756051948SVladimir Oltean REG(SYS_COUNT_RX_65_127, 0x000028), 24856051948SVladimir Oltean REG(SYS_COUNT_RX_128_255, 0x00002c), 24956051948SVladimir Oltean REG(SYS_COUNT_RX_256_1023, 0x000030), 25056051948SVladimir Oltean REG(SYS_COUNT_RX_1024_1526, 0x000034), 25156051948SVladimir Oltean REG(SYS_COUNT_RX_1527_MAX, 0x000038), 25256051948SVladimir Oltean REG(SYS_COUNT_RX_LONGS, 0x000044), 25356051948SVladimir Oltean REG(SYS_COUNT_TX_OCTETS, 0x000200), 25456051948SVladimir Oltean REG(SYS_COUNT_TX_COLLISION, 0x000210), 25556051948SVladimir Oltean REG(SYS_COUNT_TX_DROPS, 0x000214), 25656051948SVladimir Oltean REG(SYS_COUNT_TX_64, 0x00021c), 25756051948SVladimir Oltean REG(SYS_COUNT_TX_65_127, 0x000220), 25856051948SVladimir Oltean REG(SYS_COUNT_TX_128_511, 0x000224), 25956051948SVladimir Oltean REG(SYS_COUNT_TX_512_1023, 0x000228), 26056051948SVladimir Oltean REG(SYS_COUNT_TX_1024_1526, 0x00022c), 26156051948SVladimir Oltean REG(SYS_COUNT_TX_1527_MAX, 0x000230), 26256051948SVladimir Oltean REG(SYS_COUNT_TX_AGING, 0x000278), 26356051948SVladimir Oltean REG(SYS_RESET_CFG, 0x000e00), 26456051948SVladimir Oltean REG(SYS_SR_ETYPE_CFG, 0x000e04), 26556051948SVladimir Oltean REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 26656051948SVladimir Oltean REG(SYS_PORT_MODE, 0x000e0c), 26756051948SVladimir Oltean REG(SYS_FRONT_PORT_MODE, 0x000e2c), 26856051948SVladimir Oltean REG(SYS_FRM_AGING, 0x000e44), 26956051948SVladimir Oltean REG(SYS_STAT_CFG, 0x000e48), 27056051948SVladimir Oltean REG(SYS_SW_STATUS, 0x000e4c), 27156051948SVladimir Oltean REG_RESERVED(SYS_MISC_CFG), 27256051948SVladimir Oltean REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 27356051948SVladimir Oltean REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 27456051948SVladimir Oltean REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 27556051948SVladimir Oltean REG(SYS_PAUSE_CFG, 0x000ea0), 27656051948SVladimir Oltean REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 27756051948SVladimir Oltean REG(SYS_ATOP, 0x000ec0), 27856051948SVladimir Oltean REG(SYS_ATOP_TOT_CFG, 0x000edc), 27956051948SVladimir Oltean REG(SYS_MAC_FC_CFG, 0x000ee0), 28056051948SVladimir Oltean REG(SYS_MMGT, 0x000ef8), 28156051948SVladimir Oltean REG_RESERVED(SYS_MMGT_FAST), 28256051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_DIF), 28356051948SVladimir Oltean REG_RESERVED(SYS_EVENTS_CORE), 28456051948SVladimir Oltean REG_RESERVED(SYS_CNT), 28556051948SVladimir Oltean REG(SYS_PTP_STATUS, 0x000f14), 28656051948SVladimir Oltean REG(SYS_PTP_TXSTAMP, 0x000f18), 28756051948SVladimir Oltean REG(SYS_PTP_NXT, 0x000f1c), 28856051948SVladimir Oltean REG(SYS_PTP_CFG, 0x000f20), 28956051948SVladimir Oltean REG(SYS_RAM_INIT, 0x000f24), 29056051948SVladimir Oltean REG_RESERVED(SYS_CM_ADDR), 29156051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_WR), 29256051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA_RD), 29356051948SVladimir Oltean REG_RESERVED(SYS_CM_OP), 29456051948SVladimir Oltean REG_RESERVED(SYS_CM_DATA), 29556051948SVladimir Oltean }; 29656051948SVladimir Oltean 2975df66c48SYangbo Lu static const u32 vsc9959_ptp_regmap[] = { 2985df66c48SYangbo Lu REG(PTP_PIN_CFG, 0x000000), 2995df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 3005df66c48SYangbo Lu REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 3015df66c48SYangbo Lu REG(PTP_PIN_TOD_NSEC, 0x00000c), 30294aca082SYangbo Lu REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 30394aca082SYangbo Lu REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 3045df66c48SYangbo Lu REG(PTP_CFG_MISC, 0x0000a0), 3055df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 3065df66c48SYangbo Lu REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 3075df66c48SYangbo Lu }; 3085df66c48SYangbo Lu 30956051948SVladimir Oltean static const u32 vsc9959_gcb_regmap[] = { 31056051948SVladimir Oltean REG(GCB_SOFT_RST, 0x000004), 31156051948SVladimir Oltean }; 31256051948SVladimir Oltean 31391c724cfSVladimir Oltean static const u32 vsc9959_dev_gmii_regmap[] = { 31491c724cfSVladimir Oltean REG(DEV_CLOCK_CFG, 0x0), 31591c724cfSVladimir Oltean REG(DEV_PORT_MISC, 0x4), 31691c724cfSVladimir Oltean REG(DEV_EVENTS, 0x8), 31791c724cfSVladimir Oltean REG(DEV_EEE_CFG, 0xc), 31891c724cfSVladimir Oltean REG(DEV_RX_PATH_DELAY, 0x10), 31991c724cfSVladimir Oltean REG(DEV_TX_PATH_DELAY, 0x14), 32091c724cfSVladimir Oltean REG(DEV_PTP_PREDICT_CFG, 0x18), 32191c724cfSVladimir Oltean REG(DEV_MAC_ENA_CFG, 0x1c), 32291c724cfSVladimir Oltean REG(DEV_MAC_MODE_CFG, 0x20), 32391c724cfSVladimir Oltean REG(DEV_MAC_MAXLEN_CFG, 0x24), 32491c724cfSVladimir Oltean REG(DEV_MAC_TAGS_CFG, 0x28), 32591c724cfSVladimir Oltean REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 32691c724cfSVladimir Oltean REG(DEV_MAC_IFG_CFG, 0x30), 32791c724cfSVladimir Oltean REG(DEV_MAC_HDX_CFG, 0x34), 32891c724cfSVladimir Oltean REG(DEV_MAC_DBG_CFG, 0x38), 32991c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 33091c724cfSVladimir Oltean REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 33191c724cfSVladimir Oltean REG(DEV_MAC_STICKY, 0x44), 33291c724cfSVladimir Oltean REG_RESERVED(PCS1G_CFG), 33391c724cfSVladimir Oltean REG_RESERVED(PCS1G_MODE_CFG), 33491c724cfSVladimir Oltean REG_RESERVED(PCS1G_SD_CFG), 33591c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_CFG), 33691c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_CFG), 33791c724cfSVladimir Oltean REG_RESERVED(PCS1G_LB_CFG), 33891c724cfSVladimir Oltean REG_RESERVED(PCS1G_DBG_CFG), 33991c724cfSVladimir Oltean REG_RESERVED(PCS1G_CDET_CFG), 34091c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_STATUS), 34191c724cfSVladimir Oltean REG_RESERVED(PCS1G_ANEG_NP_STATUS), 34291c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_STATUS), 34391c724cfSVladimir Oltean REG_RESERVED(PCS1G_LINK_DOWN_CNT), 34491c724cfSVladimir Oltean REG_RESERVED(PCS1G_STICKY), 34591c724cfSVladimir Oltean REG_RESERVED(PCS1G_DEBUG_STATUS), 34691c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_CFG), 34791c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 34891c724cfSVladimir Oltean REG_RESERVED(PCS1G_LPI_STATUS), 34991c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 35091c724cfSVladimir Oltean REG_RESERVED(PCS1G_TSTPAT_STATUS), 35191c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_CFG), 35291c724cfSVladimir Oltean REG_RESERVED(DEV_PCS_FX100_STATUS), 35391c724cfSVladimir Oltean }; 35491c724cfSVladimir Oltean 35591c724cfSVladimir Oltean static const u32 *vsc9959_regmap[TARGET_MAX] = { 35656051948SVladimir Oltean [ANA] = vsc9959_ana_regmap, 35756051948SVladimir Oltean [QS] = vsc9959_qs_regmap, 35856051948SVladimir Oltean [QSYS] = vsc9959_qsys_regmap, 35956051948SVladimir Oltean [REW] = vsc9959_rew_regmap, 36056051948SVladimir Oltean [SYS] = vsc9959_sys_regmap, 36156051948SVladimir Oltean [S2] = vsc9959_s2_regmap, 3625df66c48SYangbo Lu [PTP] = vsc9959_ptp_regmap, 36356051948SVladimir Oltean [GCB] = vsc9959_gcb_regmap, 36491c724cfSVladimir Oltean [DEV_GMII] = vsc9959_dev_gmii_regmap, 36556051948SVladimir Oltean }; 36656051948SVladimir Oltean 367b4024c9eSClaudiu Manoil /* Addresses are relative to the PCI device's base address */ 36891c724cfSVladimir Oltean static const struct resource vsc9959_target_io_res[TARGET_MAX] = { 36956051948SVladimir Oltean [ANA] = { 37056051948SVladimir Oltean .start = 0x0280000, 37156051948SVladimir Oltean .end = 0x028ffff, 37256051948SVladimir Oltean .name = "ana", 37356051948SVladimir Oltean }, 37456051948SVladimir Oltean [QS] = { 37556051948SVladimir Oltean .start = 0x0080000, 37656051948SVladimir Oltean .end = 0x00800ff, 37756051948SVladimir Oltean .name = "qs", 37856051948SVladimir Oltean }, 37956051948SVladimir Oltean [QSYS] = { 38056051948SVladimir Oltean .start = 0x0200000, 38156051948SVladimir Oltean .end = 0x021ffff, 38256051948SVladimir Oltean .name = "qsys", 38356051948SVladimir Oltean }, 38456051948SVladimir Oltean [REW] = { 38556051948SVladimir Oltean .start = 0x0030000, 38656051948SVladimir Oltean .end = 0x003ffff, 38756051948SVladimir Oltean .name = "rew", 38856051948SVladimir Oltean }, 38956051948SVladimir Oltean [SYS] = { 39056051948SVladimir Oltean .start = 0x0010000, 39156051948SVladimir Oltean .end = 0x001ffff, 39256051948SVladimir Oltean .name = "sys", 39356051948SVladimir Oltean }, 39456051948SVladimir Oltean [S2] = { 39556051948SVladimir Oltean .start = 0x0060000, 39656051948SVladimir Oltean .end = 0x00603ff, 39756051948SVladimir Oltean .name = "s2", 39856051948SVladimir Oltean }, 3995df66c48SYangbo Lu [PTP] = { 4005df66c48SYangbo Lu .start = 0x0090000, 4015df66c48SYangbo Lu .end = 0x00900cb, 4025df66c48SYangbo Lu .name = "ptp", 4035df66c48SYangbo Lu }, 40456051948SVladimir Oltean [GCB] = { 40556051948SVladimir Oltean .start = 0x0070000, 40656051948SVladimir Oltean .end = 0x00701ff, 40756051948SVladimir Oltean .name = "devcpu_gcb", 40856051948SVladimir Oltean }, 40956051948SVladimir Oltean }; 41056051948SVladimir Oltean 411b4024c9eSClaudiu Manoil static const struct resource vsc9959_port_io_res[] = { 41256051948SVladimir Oltean { 41356051948SVladimir Oltean .start = 0x0100000, 41456051948SVladimir Oltean .end = 0x010ffff, 41556051948SVladimir Oltean .name = "port0", 41656051948SVladimir Oltean }, 41756051948SVladimir Oltean { 41856051948SVladimir Oltean .start = 0x0110000, 41956051948SVladimir Oltean .end = 0x011ffff, 42056051948SVladimir Oltean .name = "port1", 42156051948SVladimir Oltean }, 42256051948SVladimir Oltean { 42356051948SVladimir Oltean .start = 0x0120000, 42456051948SVladimir Oltean .end = 0x012ffff, 42556051948SVladimir Oltean .name = "port2", 42656051948SVladimir Oltean }, 42756051948SVladimir Oltean { 42856051948SVladimir Oltean .start = 0x0130000, 42956051948SVladimir Oltean .end = 0x013ffff, 43056051948SVladimir Oltean .name = "port3", 43156051948SVladimir Oltean }, 43256051948SVladimir Oltean { 43356051948SVladimir Oltean .start = 0x0140000, 43456051948SVladimir Oltean .end = 0x014ffff, 43556051948SVladimir Oltean .name = "port4", 43656051948SVladimir Oltean }, 43756051948SVladimir Oltean { 43856051948SVladimir Oltean .start = 0x0150000, 43956051948SVladimir Oltean .end = 0x015ffff, 44056051948SVladimir Oltean .name = "port5", 44156051948SVladimir Oltean }, 44256051948SVladimir Oltean }; 44356051948SVladimir Oltean 444bdeced75SVladimir Oltean /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 445bdeced75SVladimir Oltean * SGMII/QSGMII MAC PCS can be found. 446bdeced75SVladimir Oltean */ 447b4024c9eSClaudiu Manoil static const struct resource vsc9959_imdio_res = { 448bdeced75SVladimir Oltean .start = 0x8030, 449bdeced75SVladimir Oltean .end = 0x8040, 450bdeced75SVladimir Oltean .name = "imdio", 451bdeced75SVladimir Oltean }; 452bdeced75SVladimir Oltean 4532789658fSMaxim Kochetkov static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 45456051948SVladimir Oltean [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 45556051948SVladimir Oltean [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 45656051948SVladimir Oltean [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 45756051948SVladimir Oltean [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 45856051948SVladimir Oltean [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 45956051948SVladimir Oltean [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 46056051948SVladimir Oltean [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 46156051948SVladimir Oltean [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 46256051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 46356051948SVladimir Oltean [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 46456051948SVladimir Oltean [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 46556051948SVladimir Oltean [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 46656051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 46756051948SVladimir Oltean [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 46856051948SVladimir Oltean [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 46956051948SVladimir Oltean [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 47056051948SVladimir Oltean [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 47156051948SVladimir Oltean [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 47256051948SVladimir Oltean [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 47356051948SVladimir Oltean [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 47456051948SVladimir Oltean [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 47556051948SVladimir Oltean [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 47656051948SVladimir Oltean [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 47756051948SVladimir Oltean [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 47856051948SVladimir Oltean [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 47956051948SVladimir Oltean [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 48056051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 48156051948SVladimir Oltean [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 48256051948SVladimir Oltean [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 48356051948SVladimir Oltean [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 48456051948SVladimir Oltean [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 48556051948SVladimir Oltean [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 48656051948SVladimir Oltean [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 487886e1387SVladimir Oltean /* Replicated per number of ports (7), register size 4 per port */ 488886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 489886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 490886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 491886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 492886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 493886e1387SVladimir Oltean [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 494886e1387SVladimir Oltean [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 495886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 496886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 497886e1387SVladimir Oltean [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 498541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 499541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 500541132f0SMaxim Kochetkov [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 50156051948SVladimir Oltean }; 50256051948SVladimir Oltean 50356051948SVladimir Oltean static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 50456051948SVladimir Oltean { .offset = 0x00, .name = "rx_octets", }, 50556051948SVladimir Oltean { .offset = 0x01, .name = "rx_unicast", }, 50656051948SVladimir Oltean { .offset = 0x02, .name = "rx_multicast", }, 50756051948SVladimir Oltean { .offset = 0x03, .name = "rx_broadcast", }, 50856051948SVladimir Oltean { .offset = 0x04, .name = "rx_shorts", }, 50956051948SVladimir Oltean { .offset = 0x05, .name = "rx_fragments", }, 51056051948SVladimir Oltean { .offset = 0x06, .name = "rx_jabbers", }, 51156051948SVladimir Oltean { .offset = 0x07, .name = "rx_crc_align_errs", }, 51256051948SVladimir Oltean { .offset = 0x08, .name = "rx_sym_errs", }, 51356051948SVladimir Oltean { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 51456051948SVladimir Oltean { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 51556051948SVladimir Oltean { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 51656051948SVladimir Oltean { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 51756051948SVladimir Oltean { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 51856051948SVladimir Oltean { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 51956051948SVladimir Oltean { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 52056051948SVladimir Oltean { .offset = 0x10, .name = "rx_pause", }, 52156051948SVladimir Oltean { .offset = 0x11, .name = "rx_control", }, 52256051948SVladimir Oltean { .offset = 0x12, .name = "rx_longs", }, 52356051948SVladimir Oltean { .offset = 0x13, .name = "rx_classified_drops", }, 52456051948SVladimir Oltean { .offset = 0x14, .name = "rx_red_prio_0", }, 52556051948SVladimir Oltean { .offset = 0x15, .name = "rx_red_prio_1", }, 52656051948SVladimir Oltean { .offset = 0x16, .name = "rx_red_prio_2", }, 52756051948SVladimir Oltean { .offset = 0x17, .name = "rx_red_prio_3", }, 52856051948SVladimir Oltean { .offset = 0x18, .name = "rx_red_prio_4", }, 52956051948SVladimir Oltean { .offset = 0x19, .name = "rx_red_prio_5", }, 53056051948SVladimir Oltean { .offset = 0x1A, .name = "rx_red_prio_6", }, 53156051948SVladimir Oltean { .offset = 0x1B, .name = "rx_red_prio_7", }, 53256051948SVladimir Oltean { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 53356051948SVladimir Oltean { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 53456051948SVladimir Oltean { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 53556051948SVladimir Oltean { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 53656051948SVladimir Oltean { .offset = 0x20, .name = "rx_yellow_prio_4", }, 53756051948SVladimir Oltean { .offset = 0x21, .name = "rx_yellow_prio_5", }, 53856051948SVladimir Oltean { .offset = 0x22, .name = "rx_yellow_prio_6", }, 53956051948SVladimir Oltean { .offset = 0x23, .name = "rx_yellow_prio_7", }, 54056051948SVladimir Oltean { .offset = 0x24, .name = "rx_green_prio_0", }, 54156051948SVladimir Oltean { .offset = 0x25, .name = "rx_green_prio_1", }, 54256051948SVladimir Oltean { .offset = 0x26, .name = "rx_green_prio_2", }, 54356051948SVladimir Oltean { .offset = 0x27, .name = "rx_green_prio_3", }, 54456051948SVladimir Oltean { .offset = 0x28, .name = "rx_green_prio_4", }, 54556051948SVladimir Oltean { .offset = 0x29, .name = "rx_green_prio_5", }, 54656051948SVladimir Oltean { .offset = 0x2A, .name = "rx_green_prio_6", }, 54756051948SVladimir Oltean { .offset = 0x2B, .name = "rx_green_prio_7", }, 54856051948SVladimir Oltean { .offset = 0x80, .name = "tx_octets", }, 54956051948SVladimir Oltean { .offset = 0x81, .name = "tx_unicast", }, 55056051948SVladimir Oltean { .offset = 0x82, .name = "tx_multicast", }, 55156051948SVladimir Oltean { .offset = 0x83, .name = "tx_broadcast", }, 55256051948SVladimir Oltean { .offset = 0x84, .name = "tx_collision", }, 55356051948SVladimir Oltean { .offset = 0x85, .name = "tx_drops", }, 55456051948SVladimir Oltean { .offset = 0x86, .name = "tx_pause", }, 55556051948SVladimir Oltean { .offset = 0x87, .name = "tx_frames_below_65_octets", }, 55656051948SVladimir Oltean { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, 55756051948SVladimir Oltean { .offset = 0x89, .name = "tx_frames_128_255_octets", }, 55856051948SVladimir Oltean { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, 55956051948SVladimir Oltean { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, 56056051948SVladimir Oltean { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, 56156051948SVladimir Oltean { .offset = 0x8E, .name = "tx_yellow_prio_0", }, 56256051948SVladimir Oltean { .offset = 0x8F, .name = "tx_yellow_prio_1", }, 56356051948SVladimir Oltean { .offset = 0x90, .name = "tx_yellow_prio_2", }, 56456051948SVladimir Oltean { .offset = 0x91, .name = "tx_yellow_prio_3", }, 56556051948SVladimir Oltean { .offset = 0x92, .name = "tx_yellow_prio_4", }, 56656051948SVladimir Oltean { .offset = 0x93, .name = "tx_yellow_prio_5", }, 56756051948SVladimir Oltean { .offset = 0x94, .name = "tx_yellow_prio_6", }, 56856051948SVladimir Oltean { .offset = 0x95, .name = "tx_yellow_prio_7", }, 56956051948SVladimir Oltean { .offset = 0x96, .name = "tx_green_prio_0", }, 57056051948SVladimir Oltean { .offset = 0x97, .name = "tx_green_prio_1", }, 57156051948SVladimir Oltean { .offset = 0x98, .name = "tx_green_prio_2", }, 57256051948SVladimir Oltean { .offset = 0x99, .name = "tx_green_prio_3", }, 57356051948SVladimir Oltean { .offset = 0x9A, .name = "tx_green_prio_4", }, 57456051948SVladimir Oltean { .offset = 0x9B, .name = "tx_green_prio_5", }, 57556051948SVladimir Oltean { .offset = 0x9C, .name = "tx_green_prio_6", }, 57656051948SVladimir Oltean { .offset = 0x9D, .name = "tx_green_prio_7", }, 57756051948SVladimir Oltean { .offset = 0x9E, .name = "tx_aged", }, 57856051948SVladimir Oltean { .offset = 0x100, .name = "drop_local", }, 57956051948SVladimir Oltean { .offset = 0x101, .name = "drop_tail", }, 58056051948SVladimir Oltean { .offset = 0x102, .name = "drop_yellow_prio_0", }, 58156051948SVladimir Oltean { .offset = 0x103, .name = "drop_yellow_prio_1", }, 58256051948SVladimir Oltean { .offset = 0x104, .name = "drop_yellow_prio_2", }, 58356051948SVladimir Oltean { .offset = 0x105, .name = "drop_yellow_prio_3", }, 58456051948SVladimir Oltean { .offset = 0x106, .name = "drop_yellow_prio_4", }, 58556051948SVladimir Oltean { .offset = 0x107, .name = "drop_yellow_prio_5", }, 58656051948SVladimir Oltean { .offset = 0x108, .name = "drop_yellow_prio_6", }, 58756051948SVladimir Oltean { .offset = 0x109, .name = "drop_yellow_prio_7", }, 58856051948SVladimir Oltean { .offset = 0x10A, .name = "drop_green_prio_0", }, 58956051948SVladimir Oltean { .offset = 0x10B, .name = "drop_green_prio_1", }, 59056051948SVladimir Oltean { .offset = 0x10C, .name = "drop_green_prio_2", }, 59156051948SVladimir Oltean { .offset = 0x10D, .name = "drop_green_prio_3", }, 59256051948SVladimir Oltean { .offset = 0x10E, .name = "drop_green_prio_4", }, 59356051948SVladimir Oltean { .offset = 0x10F, .name = "drop_green_prio_5", }, 59456051948SVladimir Oltean { .offset = 0x110, .name = "drop_green_prio_6", }, 59556051948SVladimir Oltean { .offset = 0x111, .name = "drop_green_prio_7", }, 59656051948SVladimir Oltean }; 59756051948SVladimir Oltean 5983ab4ceb6SVladimir Oltean static struct vcap_field vsc9959_vcap_is2_keys[] = { 59907d985eeSVladimir Oltean /* Common: 41 bits */ 60007d985eeSVladimir Oltean [VCAP_IS2_TYPE] = { 0, 4}, 60107d985eeSVladimir Oltean [VCAP_IS2_HK_FIRST] = { 4, 1}, 60207d985eeSVladimir Oltean [VCAP_IS2_HK_PAG] = { 5, 8}, 60307d985eeSVladimir Oltean [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 60407d985eeSVladimir Oltean [VCAP_IS2_HK_RSV2] = { 20, 1}, 60507d985eeSVladimir Oltean [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 60607d985eeSVladimir Oltean [VCAP_IS2_HK_L2_MC] = { 22, 1}, 60707d985eeSVladimir Oltean [VCAP_IS2_HK_L2_BC] = { 23, 1}, 60807d985eeSVladimir Oltean [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 60907d985eeSVladimir Oltean [VCAP_IS2_HK_VID] = { 25, 12}, 61007d985eeSVladimir Oltean [VCAP_IS2_HK_DEI] = { 37, 1}, 61107d985eeSVladimir Oltean [VCAP_IS2_HK_PCP] = { 38, 3}, 61207d985eeSVladimir Oltean /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 61307d985eeSVladimir Oltean [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 61407d985eeSVladimir Oltean [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 61507d985eeSVladimir Oltean /* MAC_ETYPE (TYPE=000) */ 61607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 61707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 61807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 61907d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 62007d985eeSVladimir Oltean /* MAC_LLC (TYPE=001) */ 62107d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 62207d985eeSVladimir Oltean /* MAC_SNAP (TYPE=010) */ 62307d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 62407d985eeSVladimir Oltean /* MAC_ARP (TYPE=011) */ 62507d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 62607d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 62707d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 62807d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 62907d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 63007d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 63107d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 63207d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 63307d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 63407d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 63507d985eeSVladimir Oltean [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 63607d985eeSVladimir Oltean /* IP4_TCP_UDP / IP4_OTHER common */ 63707d985eeSVladimir Oltean [VCAP_IS2_HK_IP4] = { 41, 1}, 63807d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 63907d985eeSVladimir Oltean [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 64007d985eeSVladimir Oltean [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 64107d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 64207d985eeSVladimir Oltean [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 64307d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 64407d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 64507d985eeSVladimir Oltean [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 64607d985eeSVladimir Oltean /* IP4_TCP_UDP (TYPE=100) */ 64707d985eeSVladimir Oltean [VCAP_IS2_HK_TCP] = {119, 1}, 64807d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SPORT] = {120, 16}, 64907d985eeSVladimir Oltean [VCAP_IS2_HK_L4_DPORT] = {136, 16}, 65007d985eeSVladimir Oltean [VCAP_IS2_HK_L4_RNG] = {152, 8}, 65107d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 65207d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 65307d985eeSVladimir Oltean [VCAP_IS2_HK_L4_URG] = {162, 1}, 65407d985eeSVladimir Oltean [VCAP_IS2_HK_L4_ACK] = {163, 1}, 65507d985eeSVladimir Oltean [VCAP_IS2_HK_L4_PSH] = {164, 1}, 65607d985eeSVladimir Oltean [VCAP_IS2_HK_L4_RST] = {165, 1}, 65707d985eeSVladimir Oltean [VCAP_IS2_HK_L4_SYN] = {166, 1}, 65807d985eeSVladimir Oltean [VCAP_IS2_HK_L4_FIN] = {167, 1}, 65907d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 66007d985eeSVladimir Oltean [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 66107d985eeSVladimir Oltean /* IP4_OTHER (TYPE=101) */ 66207d985eeSVladimir Oltean [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 66307d985eeSVladimir Oltean [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 66407d985eeSVladimir Oltean /* IP6_STD (TYPE=110) */ 66507d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 66607d985eeSVladimir Oltean [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 66707d985eeSVladimir Oltean [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 66807d985eeSVladimir Oltean /* OAM (TYPE=111) */ 66907d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 67007d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_VER] = {144, 5}, 67107d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 67207d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 67307d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 67407d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 67507d985eeSVladimir Oltean [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 67607d985eeSVladimir Oltean }; 67707d985eeSVladimir Oltean 6783ab4ceb6SVladimir Oltean static struct vcap_field vsc9959_vcap_is2_actions[] = { 67907d985eeSVladimir Oltean [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 68007d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 68107d985eeSVladimir Oltean [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 68207d985eeSVladimir Oltean [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 68307d985eeSVladimir Oltean [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 68407d985eeSVladimir Oltean [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 68507d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 68607d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 68707d985eeSVladimir Oltean [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 68807d985eeSVladimir Oltean [VCAP_IS2_ACT_PORT_MASK] = { 20, 11}, 68907d985eeSVladimir Oltean [VCAP_IS2_ACT_REW_OP] = { 31, 9}, 69007d985eeSVladimir Oltean [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1}, 69107d985eeSVladimir Oltean [VCAP_IS2_ACT_RSV] = { 41, 2}, 69207d985eeSVladimir Oltean [VCAP_IS2_ACT_ACL_ID] = { 43, 6}, 69307d985eeSVladimir Oltean [VCAP_IS2_ACT_HIT_CNT] = { 49, 32}, 69407d985eeSVladimir Oltean }; 69507d985eeSVladimir Oltean 69607d985eeSVladimir Oltean static const struct vcap_props vsc9959_vcap_props[] = { 69707d985eeSVladimir Oltean [VCAP_IS2] = { 69807d985eeSVladimir Oltean .tg_width = 2, 69907d985eeSVladimir Oltean .sw_count = 4, 70007d985eeSVladimir Oltean .entry_count = VSC9959_VCAP_IS2_CNT, 70107d985eeSVladimir Oltean .entry_width = VSC9959_VCAP_IS2_ENTRY_WIDTH, 70207d985eeSVladimir Oltean .action_count = VSC9959_VCAP_IS2_CNT + 70307d985eeSVladimir Oltean VSC9959_VCAP_PORT_CNT + 2, 70407d985eeSVladimir Oltean .action_width = 89, 70507d985eeSVladimir Oltean .action_type_width = 1, 70607d985eeSVladimir Oltean .action_table = { 70707d985eeSVladimir Oltean [IS2_ACTION_TYPE_NORMAL] = { 70807d985eeSVladimir Oltean .width = 44, 70907d985eeSVladimir Oltean .count = 2 71007d985eeSVladimir Oltean }, 71107d985eeSVladimir Oltean [IS2_ACTION_TYPE_SMAC_SIP] = { 71207d985eeSVladimir Oltean .width = 6, 71307d985eeSVladimir Oltean .count = 4 71407d985eeSVladimir Oltean }, 71507d985eeSVladimir Oltean }, 71607d985eeSVladimir Oltean .counter_words = 4, 71707d985eeSVladimir Oltean .counter_width = 32, 71807d985eeSVladimir Oltean }, 71907d985eeSVladimir Oltean }; 72007d985eeSVladimir Oltean 72156051948SVladimir Oltean #define VSC9959_INIT_TIMEOUT 50000 72256051948SVladimir Oltean #define VSC9959_GCB_RST_SLEEP 100 72356051948SVladimir Oltean #define VSC9959_SYS_RAMINIT_SLEEP 80 72456051948SVladimir Oltean 72556051948SVladimir Oltean static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 72656051948SVladimir Oltean { 72756051948SVladimir Oltean int val; 72856051948SVladimir Oltean 72956051948SVladimir Oltean regmap_field_read(ocelot->regfields[GCB_SOFT_RST_SWC_RST], &val); 73056051948SVladimir Oltean 73156051948SVladimir Oltean return val; 73256051948SVladimir Oltean } 73356051948SVladimir Oltean 73456051948SVladimir Oltean static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 73556051948SVladimir Oltean { 73656051948SVladimir Oltean return ocelot_read(ocelot, SYS_RAM_INIT); 73756051948SVladimir Oltean } 73856051948SVladimir Oltean 73956051948SVladimir Oltean static int vsc9959_reset(struct ocelot *ocelot) 74056051948SVladimir Oltean { 74156051948SVladimir Oltean int val, err; 74256051948SVladimir Oltean 74356051948SVladimir Oltean /* soft-reset the switch core */ 74456051948SVladimir Oltean regmap_field_write(ocelot->regfields[GCB_SOFT_RST_SWC_RST], 1); 74556051948SVladimir Oltean 74656051948SVladimir Oltean err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 74756051948SVladimir Oltean VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 74856051948SVladimir Oltean if (err) { 74956051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch core reset\n"); 75056051948SVladimir Oltean return err; 75156051948SVladimir Oltean } 75256051948SVladimir Oltean 75356051948SVladimir Oltean /* initialize switch mem ~40us */ 75456051948SVladimir Oltean ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 75556051948SVladimir Oltean err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 75656051948SVladimir Oltean VSC9959_SYS_RAMINIT_SLEEP, 75756051948SVladimir Oltean VSC9959_INIT_TIMEOUT); 75856051948SVladimir Oltean if (err) { 75956051948SVladimir Oltean dev_err(ocelot->dev, "timeout: switch sram init\n"); 76056051948SVladimir Oltean return err; 76156051948SVladimir Oltean } 76256051948SVladimir Oltean 76356051948SVladimir Oltean /* enable switch core */ 76456051948SVladimir Oltean regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 76556051948SVladimir Oltean 76656051948SVladimir Oltean return 0; 76756051948SVladimir Oltean } 76856051948SVladimir Oltean 769bdeced75SVladimir Oltean /* We enable SGMII AN only when the PHY has managed = "in-band-status" in the 770bdeced75SVladimir Oltean * device tree. If we are in MLO_AN_PHY mode, we program directly state->speed 771bdeced75SVladimir Oltean * into the PCS, which is retrieved out-of-band over MDIO. This also has the 772bdeced75SVladimir Oltean * benefit of working with SGMII fixed-links, like downstream switches, where 773bdeced75SVladimir Oltean * both link partners attempt to operate as AN slaves and therefore AN never 774bdeced75SVladimir Oltean * completes. But it also has the disadvantage that some PHY chips don't pass 775bdeced75SVladimir Oltean * traffic if SGMII AN is enabled but not completed (acknowledged by us), so 776bdeced75SVladimir Oltean * setting MLO_AN_INBAND is actually required for those. 777bdeced75SVladimir Oltean */ 7787e14a2dcSVladimir Oltean static void vsc9959_pcs_config_sgmii(struct phy_device *pcs, 779bdeced75SVladimir Oltean unsigned int link_an_mode, 780bdeced75SVladimir Oltean const struct phylink_link_state *state) 781bdeced75SVladimir Oltean { 7828c6123e1SAlex Marginean int bmsr, bmcr; 7838c6123e1SAlex Marginean 7848c6123e1SAlex Marginean /* Some PHYs like VSC8234 don't like it when AN restarts on 7858c6123e1SAlex Marginean * their system side and they restart line side AN too, going 7868c6123e1SAlex Marginean * into an endless link up/down loop. Don't restart PCS AN if 7878c6123e1SAlex Marginean * link is up already. 7888c6123e1SAlex Marginean * We do check that AN is enabled just in case this is the 1st 7898c6123e1SAlex Marginean * call, PCS detects a carrier but AN is disabled from power on 7908c6123e1SAlex Marginean * or by boot loader. 7918c6123e1SAlex Marginean */ 7928c6123e1SAlex Marginean bmcr = phy_read(pcs, MII_BMCR); 7938c6123e1SAlex Marginean if (bmcr < 0) 7948c6123e1SAlex Marginean return; 7958c6123e1SAlex Marginean 7968c6123e1SAlex Marginean bmsr = phy_read(pcs, MII_BMSR); 7978c6123e1SAlex Marginean if (bmsr < 0) 7988c6123e1SAlex Marginean return; 7998c6123e1SAlex Marginean 8008c6123e1SAlex Marginean if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_LSTATUS)) 8018c6123e1SAlex Marginean return; 8028c6123e1SAlex Marginean 803bdeced75SVladimir Oltean /* SGMII spec requires tx_config_Reg[15:0] to be exactly 0x4001 804bdeced75SVladimir Oltean * for the MAC PCS in order to acknowledge the AN. 805bdeced75SVladimir Oltean */ 806bdeced75SVladimir Oltean phy_write(pcs, MII_ADVERTISE, ADVERTISE_SGMII | 807bdeced75SVladimir Oltean ADVERTISE_LPACK); 808bdeced75SVladimir Oltean 809bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_IF_MODE, 810bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_SGMII_EN | 811bdeced75SVladimir Oltean ENETC_PCS_IF_MODE_USE_SGMII_AN); 812bdeced75SVladimir Oltean 813bdeced75SVladimir Oltean /* Adjust link timer for SGMII */ 814bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_LINK_TIMER1, 815bdeced75SVladimir Oltean ENETC_PCS_LINK_TIMER1_VAL); 816bdeced75SVladimir Oltean phy_write(pcs, ENETC_PCS_LINK_TIMER2, 817bdeced75SVladimir Oltean ENETC_PCS_LINK_TIMER2_VAL); 818bdeced75SVladimir Oltean 8193f2628d6SVladimir Oltean phy_set_bits(pcs, MII_BMCR, BMCR_ANENABLE); 820bdeced75SVladimir Oltean } 821bdeced75SVladimir Oltean 8227e14a2dcSVladimir Oltean static void vsc9959_pcs_config_usxgmii(struct phy_device *pcs, 823bdeced75SVladimir Oltean unsigned int link_an_mode, 824bdeced75SVladimir Oltean const struct phylink_link_state *state) 825bdeced75SVladimir Oltean { 826bdeced75SVladimir Oltean /* Configure device ability for the USXGMII Replicator */ 827bdeced75SVladimir Oltean phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_ADVERTISE, 82816659b81SMichael Walle MDIO_USXGMII_2500FULL | 82916659b81SMichael Walle MDIO_USXGMII_LINK | 830bdeced75SVladimir Oltean ADVERTISE_SGMII | 83116659b81SMichael Walle ADVERTISE_LPACK); 832bdeced75SVladimir Oltean } 833bdeced75SVladimir Oltean 83484705fc1SMaxim Kochetkov void vsc9959_pcs_config(struct ocelot *ocelot, int port, 835bdeced75SVladimir Oltean unsigned int link_an_mode, 836bdeced75SVladimir Oltean const struct phylink_link_state *state) 837bdeced75SVladimir Oltean { 838bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 839bdeced75SVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 840bdeced75SVladimir Oltean 841bdeced75SVladimir Oltean if (!pcs) 842bdeced75SVladimir Oltean return; 843bdeced75SVladimir Oltean 844bdeced75SVladimir Oltean /* The PCS does not implement the BMSR register fully, so capability 845bdeced75SVladimir Oltean * detection via genphy_read_abilities does not work. Since we can get 846bdeced75SVladimir Oltean * the PHY config word from the LPA register though, there is still 847bdeced75SVladimir Oltean * value in using the generic phy_resolve_aneg_linkmode function. So 848bdeced75SVladimir Oltean * populate the supported and advertising link modes manually here. 849bdeced75SVladimir Oltean */ 850bdeced75SVladimir Oltean linkmode_set_bit_array(phy_basic_ports_array, 851bdeced75SVladimir Oltean ARRAY_SIZE(phy_basic_ports_array), 852bdeced75SVladimir Oltean pcs->supported); 853b1c7b874SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, pcs->supported); 854bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, pcs->supported); 855b1c7b874SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, pcs->supported); 856bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pcs->supported); 857b1c7b874SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, pcs->supported); 858bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, pcs->supported); 859bdeced75SVladimir Oltean if (pcs->interface == PHY_INTERFACE_MODE_2500BASEX || 860bdeced75SVladimir Oltean pcs->interface == PHY_INTERFACE_MODE_USXGMII) 861bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 862bdeced75SVladimir Oltean pcs->supported); 863bdeced75SVladimir Oltean if (pcs->interface != PHY_INTERFACE_MODE_2500BASEX) 864bdeced75SVladimir Oltean linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 865bdeced75SVladimir Oltean pcs->supported); 866bdeced75SVladimir Oltean phy_advertise_supported(pcs); 867bdeced75SVladimir Oltean 8687e14a2dcSVladimir Oltean if (!phylink_autoneg_inband(link_an_mode)) 8697e14a2dcSVladimir Oltean return; 8707e14a2dcSVladimir Oltean 871bdeced75SVladimir Oltean switch (pcs->interface) { 872bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 873bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 8747e14a2dcSVladimir Oltean vsc9959_pcs_config_sgmii(pcs, link_an_mode, state); 875bdeced75SVladimir Oltean break; 876bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 8777e14a2dcSVladimir Oltean phydev_err(pcs, "AN not supported on 3.125GHz SerDes lane\n"); 878bdeced75SVladimir Oltean break; 879bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 8807e14a2dcSVladimir Oltean vsc9959_pcs_config_usxgmii(pcs, link_an_mode, state); 8817e14a2dcSVladimir Oltean break; 8827e14a2dcSVladimir Oltean default: 8837e14a2dcSVladimir Oltean dev_err(ocelot->dev, "Unsupported link mode %s\n", 8847e14a2dcSVladimir Oltean phy_modes(pcs->interface)); 8857e14a2dcSVladimir Oltean } 8867e14a2dcSVladimir Oltean } 8877e14a2dcSVladimir Oltean 8887e14a2dcSVladimir Oltean static void vsc9959_pcs_link_up_sgmii(struct phy_device *pcs, 8897e14a2dcSVladimir Oltean unsigned int link_an_mode, 8907e14a2dcSVladimir Oltean int speed, int duplex) 8917e14a2dcSVladimir Oltean { 8927e14a2dcSVladimir Oltean u16 if_mode = ENETC_PCS_IF_MODE_SGMII_EN; 8937e14a2dcSVladimir Oltean 8947e14a2dcSVladimir Oltean switch (speed) { 8957e14a2dcSVladimir Oltean case SPEED_1000: 8967e14a2dcSVladimir Oltean if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_1000); 8977e14a2dcSVladimir Oltean break; 8987e14a2dcSVladimir Oltean case SPEED_100: 8997e14a2dcSVladimir Oltean if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_100); 9007e14a2dcSVladimir Oltean break; 9017e14a2dcSVladimir Oltean case SPEED_10: 9027e14a2dcSVladimir Oltean if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_10); 9037e14a2dcSVladimir Oltean break; 9047e14a2dcSVladimir Oltean default: 9057e14a2dcSVladimir Oltean phydev_err(pcs, "Invalid PCS speed %d\n", speed); 9067e14a2dcSVladimir Oltean return; 9077e14a2dcSVladimir Oltean } 9087e14a2dcSVladimir Oltean 9097e14a2dcSVladimir Oltean if (duplex == DUPLEX_HALF) 9107e14a2dcSVladimir Oltean if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF; 9117e14a2dcSVladimir Oltean 9127e14a2dcSVladimir Oltean phy_write(pcs, ENETC_PCS_IF_MODE, if_mode); 9137e14a2dcSVladimir Oltean phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE); 9147e14a2dcSVladimir Oltean } 9157e14a2dcSVladimir Oltean 9167e14a2dcSVladimir Oltean /* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane 9177e14a2dcSVladimir Oltean * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have 9187e14a2dcSVladimir Oltean * auto-negotiation of any link parameters. Electrically it is compatible with 9197e14a2dcSVladimir Oltean * a single lane of XAUI. 9207e14a2dcSVladimir Oltean * The hardware reference manual wants to call this mode SGMII, but it isn't 9217e14a2dcSVladimir Oltean * really, since the fundamental features of SGMII: 9227e14a2dcSVladimir Oltean * - Downgrading the link speed by duplicating symbols 9237e14a2dcSVladimir Oltean * - Auto-negotiation 9247e14a2dcSVladimir Oltean * are not there. 9257e14a2dcSVladimir Oltean * The speed is configured at 1000 in the IF_MODE and BMCR MDIO registers 9267e14a2dcSVladimir Oltean * because the clock frequency is actually given by a PLL configured in the 9277e14a2dcSVladimir Oltean * Reset Configuration Word (RCW). 9287e14a2dcSVladimir Oltean * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o 9297e14a2dcSVladimir Oltean * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a 9307e14a2dcSVladimir Oltean * lower link speed on line side, the system-side interface remains fixed at 9317e14a2dcSVladimir Oltean * 2500 Mbps and we do rate adaptation through pause frames. 9327e14a2dcSVladimir Oltean */ 9337e14a2dcSVladimir Oltean static void vsc9959_pcs_link_up_2500basex(struct phy_device *pcs, 9347e14a2dcSVladimir Oltean unsigned int link_an_mode, 9357e14a2dcSVladimir Oltean int speed, int duplex) 9367e14a2dcSVladimir Oltean { 9377e14a2dcSVladimir Oltean u16 if_mode = ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500) | 9387e14a2dcSVladimir Oltean ENETC_PCS_IF_MODE_SGMII_EN; 9397e14a2dcSVladimir Oltean 9407e14a2dcSVladimir Oltean if (duplex == DUPLEX_HALF) 9417e14a2dcSVladimir Oltean if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF; 9427e14a2dcSVladimir Oltean 9437e14a2dcSVladimir Oltean phy_write(pcs, ENETC_PCS_IF_MODE, if_mode); 9447e14a2dcSVladimir Oltean phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE); 9457e14a2dcSVladimir Oltean } 9467e14a2dcSVladimir Oltean 94784705fc1SMaxim Kochetkov void vsc9959_pcs_link_up(struct ocelot *ocelot, int port, 9487e14a2dcSVladimir Oltean unsigned int link_an_mode, 9497e14a2dcSVladimir Oltean phy_interface_t interface, 9507e14a2dcSVladimir Oltean int speed, int duplex) 9517e14a2dcSVladimir Oltean { 9527e14a2dcSVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 9537e14a2dcSVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 9547e14a2dcSVladimir Oltean 9557e14a2dcSVladimir Oltean if (!pcs) 9567e14a2dcSVladimir Oltean return; 9577e14a2dcSVladimir Oltean 9587e14a2dcSVladimir Oltean if (phylink_autoneg_inband(link_an_mode)) 9597e14a2dcSVladimir Oltean return; 9607e14a2dcSVladimir Oltean 9617e14a2dcSVladimir Oltean switch (interface) { 9627e14a2dcSVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 9637e14a2dcSVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 9647e14a2dcSVladimir Oltean vsc9959_pcs_link_up_sgmii(pcs, link_an_mode, speed, duplex); 9657e14a2dcSVladimir Oltean break; 9667e14a2dcSVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 9677e14a2dcSVladimir Oltean vsc9959_pcs_link_up_2500basex(pcs, link_an_mode, speed, 9687e14a2dcSVladimir Oltean duplex); 9697e14a2dcSVladimir Oltean break; 9707e14a2dcSVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 9717e14a2dcSVladimir Oltean phydev_err(pcs, "USXGMII only supports in-band AN for now\n"); 972bdeced75SVladimir Oltean break; 973bdeced75SVladimir Oltean default: 974bdeced75SVladimir Oltean dev_err(ocelot->dev, "Unsupported link mode %s\n", 975bdeced75SVladimir Oltean phy_modes(pcs->interface)); 976bdeced75SVladimir Oltean } 977bdeced75SVladimir Oltean } 978bdeced75SVladimir Oltean 979bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_resolve(struct phy_device *pcs, 980bdeced75SVladimir Oltean struct phylink_link_state *state) 981bdeced75SVladimir Oltean { 982bdeced75SVladimir Oltean state->an_complete = pcs->autoneg_complete; 983bdeced75SVladimir Oltean state->an_enabled = pcs->autoneg; 984bdeced75SVladimir Oltean state->link = pcs->link; 985bdeced75SVladimir Oltean state->duplex = pcs->duplex; 986bdeced75SVladimir Oltean state->speed = pcs->speed; 987bdeced75SVladimir Oltean /* SGMII AN does not negotiate flow control, but that's ok, 988bdeced75SVladimir Oltean * since phylink already knows that, and does: 989bdeced75SVladimir Oltean * link_state.pause |= pl->phy_state.pause; 990bdeced75SVladimir Oltean */ 991bdeced75SVladimir Oltean state->pause = MLO_PAUSE_NONE; 992bdeced75SVladimir Oltean 993bdeced75SVladimir Oltean phydev_dbg(pcs, 994bdeced75SVladimir Oltean "mode=%s/%s/%s adv=%*pb lpa=%*pb link=%u an_enabled=%u an_complete=%u\n", 995bdeced75SVladimir Oltean phy_modes(pcs->interface), 996bdeced75SVladimir Oltean phy_speed_to_str(pcs->speed), 997bdeced75SVladimir Oltean phy_duplex_to_str(pcs->duplex), 998bdeced75SVladimir Oltean __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->advertising, 999bdeced75SVladimir Oltean __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->lp_advertising, 1000bdeced75SVladimir Oltean pcs->link, pcs->autoneg, pcs->autoneg_complete); 1001bdeced75SVladimir Oltean } 1002bdeced75SVladimir Oltean 1003bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_sgmii(struct phy_device *pcs, 1004bdeced75SVladimir Oltean struct phylink_link_state *state) 1005bdeced75SVladimir Oltean { 1006bdeced75SVladimir Oltean int err; 1007bdeced75SVladimir Oltean 1008bdeced75SVladimir Oltean err = genphy_update_link(pcs); 1009bdeced75SVladimir Oltean if (err < 0) 1010bdeced75SVladimir Oltean return; 1011bdeced75SVladimir Oltean 1012bdeced75SVladimir Oltean if (pcs->autoneg_complete) { 1013bdeced75SVladimir Oltean u16 lpa = phy_read(pcs, MII_LPA); 1014bdeced75SVladimir Oltean 1015bdeced75SVladimir Oltean mii_lpa_to_linkmode_lpa_sgmii(pcs->lp_advertising, lpa); 1016bdeced75SVladimir Oltean 1017bdeced75SVladimir Oltean phy_resolve_aneg_linkmode(pcs); 1018bdeced75SVladimir Oltean } 1019bdeced75SVladimir Oltean } 1020bdeced75SVladimir Oltean 1021bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_2500basex(struct phy_device *pcs, 1022bdeced75SVladimir Oltean struct phylink_link_state *state) 1023bdeced75SVladimir Oltean { 1024bdeced75SVladimir Oltean int err; 1025bdeced75SVladimir Oltean 1026bdeced75SVladimir Oltean err = genphy_update_link(pcs); 1027bdeced75SVladimir Oltean if (err < 0) 1028bdeced75SVladimir Oltean return; 1029bdeced75SVladimir Oltean 1030bdeced75SVladimir Oltean pcs->speed = SPEED_2500; 1031bdeced75SVladimir Oltean pcs->asym_pause = true; 1032bdeced75SVladimir Oltean pcs->pause = true; 1033bdeced75SVladimir Oltean } 1034bdeced75SVladimir Oltean 1035bdeced75SVladimir Oltean static void vsc9959_pcs_link_state_usxgmii(struct phy_device *pcs, 1036bdeced75SVladimir Oltean struct phylink_link_state *state) 1037bdeced75SVladimir Oltean { 1038bdeced75SVladimir Oltean int status, lpa; 1039bdeced75SVladimir Oltean 1040bdeced75SVladimir Oltean status = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_BMSR); 1041bdeced75SVladimir Oltean if (status < 0) 1042bdeced75SVladimir Oltean return; 1043bdeced75SVladimir Oltean 1044bdeced75SVladimir Oltean pcs->autoneg = true; 104516659b81SMichael Walle pcs->autoneg_complete = !!(status & BMSR_ANEGCOMPLETE); 104616659b81SMichael Walle pcs->link = !!(status & BMSR_LSTATUS); 1047bdeced75SVladimir Oltean 1048bdeced75SVladimir Oltean if (!pcs->link || !pcs->autoneg_complete) 1049bdeced75SVladimir Oltean return; 1050bdeced75SVladimir Oltean 1051bdeced75SVladimir Oltean lpa = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_LPA); 1052bdeced75SVladimir Oltean if (lpa < 0) 1053bdeced75SVladimir Oltean return; 1054bdeced75SVladimir Oltean 105516659b81SMichael Walle switch (lpa & MDIO_USXGMII_SPD_MASK) { 105616659b81SMichael Walle case MDIO_USXGMII_10: 1057bdeced75SVladimir Oltean pcs->speed = SPEED_10; 1058bdeced75SVladimir Oltean break; 105916659b81SMichael Walle case MDIO_USXGMII_100: 1060bdeced75SVladimir Oltean pcs->speed = SPEED_100; 1061bdeced75SVladimir Oltean break; 106216659b81SMichael Walle case MDIO_USXGMII_1000: 1063bdeced75SVladimir Oltean pcs->speed = SPEED_1000; 1064bdeced75SVladimir Oltean break; 106516659b81SMichael Walle case MDIO_USXGMII_2500: 1066bdeced75SVladimir Oltean pcs->speed = SPEED_2500; 1067bdeced75SVladimir Oltean break; 1068bdeced75SVladimir Oltean default: 1069bdeced75SVladimir Oltean break; 1070bdeced75SVladimir Oltean } 1071bdeced75SVladimir Oltean 107216659b81SMichael Walle if (lpa & MDIO_USXGMII_FULL_DUPLEX) 1073bdeced75SVladimir Oltean pcs->duplex = DUPLEX_FULL; 1074bdeced75SVladimir Oltean else 1075bdeced75SVladimir Oltean pcs->duplex = DUPLEX_HALF; 1076bdeced75SVladimir Oltean } 1077bdeced75SVladimir Oltean 107884705fc1SMaxim Kochetkov void vsc9959_pcs_link_state(struct ocelot *ocelot, int port, 1079bdeced75SVladimir Oltean struct phylink_link_state *state) 1080bdeced75SVladimir Oltean { 1081bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1082bdeced75SVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 1083bdeced75SVladimir Oltean 1084bdeced75SVladimir Oltean if (!pcs) 1085bdeced75SVladimir Oltean return; 1086bdeced75SVladimir Oltean 1087bdeced75SVladimir Oltean pcs->speed = SPEED_UNKNOWN; 1088bdeced75SVladimir Oltean pcs->duplex = DUPLEX_UNKNOWN; 1089bdeced75SVladimir Oltean pcs->pause = 0; 1090bdeced75SVladimir Oltean pcs->asym_pause = 0; 1091bdeced75SVladimir Oltean 1092bdeced75SVladimir Oltean switch (pcs->interface) { 1093bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 1094bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 1095bdeced75SVladimir Oltean vsc9959_pcs_link_state_sgmii(pcs, state); 1096bdeced75SVladimir Oltean break; 1097bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 1098bdeced75SVladimir Oltean vsc9959_pcs_link_state_2500basex(pcs, state); 1099bdeced75SVladimir Oltean break; 1100bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 1101bdeced75SVladimir Oltean vsc9959_pcs_link_state_usxgmii(pcs, state); 1102bdeced75SVladimir Oltean break; 1103bdeced75SVladimir Oltean default: 1104bdeced75SVladimir Oltean return; 1105bdeced75SVladimir Oltean } 1106bdeced75SVladimir Oltean 1107bdeced75SVladimir Oltean vsc9959_pcs_link_state_resolve(pcs, state); 1108bdeced75SVladimir Oltean } 1109bdeced75SVladimir Oltean 1110375e1314SVladimir Oltean static void vsc9959_phylink_validate(struct ocelot *ocelot, int port, 1111375e1314SVladimir Oltean unsigned long *supported, 1112375e1314SVladimir Oltean struct phylink_link_state *state) 1113375e1314SVladimir Oltean { 1114375e1314SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 1115375e1314SVladimir Oltean __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1116375e1314SVladimir Oltean 1117375e1314SVladimir Oltean if (state->interface != PHY_INTERFACE_MODE_NA && 1118375e1314SVladimir Oltean state->interface != ocelot_port->phy_mode) { 1119375e1314SVladimir Oltean bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1120375e1314SVladimir Oltean return; 1121375e1314SVladimir Oltean } 1122375e1314SVladimir Oltean 1123375e1314SVladimir Oltean phylink_set_port_modes(mask); 1124375e1314SVladimir Oltean phylink_set(mask, Autoneg); 1125375e1314SVladimir Oltean phylink_set(mask, Pause); 1126375e1314SVladimir Oltean phylink_set(mask, Asym_Pause); 1127375e1314SVladimir Oltean phylink_set(mask, 10baseT_Half); 1128375e1314SVladimir Oltean phylink_set(mask, 10baseT_Full); 1129375e1314SVladimir Oltean phylink_set(mask, 100baseT_Half); 1130375e1314SVladimir Oltean phylink_set(mask, 100baseT_Full); 1131375e1314SVladimir Oltean phylink_set(mask, 1000baseT_Half); 1132375e1314SVladimir Oltean phylink_set(mask, 1000baseT_Full); 1133375e1314SVladimir Oltean 1134375e1314SVladimir Oltean if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 1135375e1314SVladimir Oltean state->interface == PHY_INTERFACE_MODE_2500BASEX || 1136375e1314SVladimir Oltean state->interface == PHY_INTERFACE_MODE_USXGMII) { 1137375e1314SVladimir Oltean phylink_set(mask, 2500baseT_Full); 1138375e1314SVladimir Oltean phylink_set(mask, 2500baseX_Full); 1139375e1314SVladimir Oltean } 1140375e1314SVladimir Oltean 1141375e1314SVladimir Oltean bitmap_and(supported, supported, mask, 1142375e1314SVladimir Oltean __ETHTOOL_LINK_MODE_MASK_NBITS); 1143375e1314SVladimir Oltean bitmap_and(state->advertising, state->advertising, mask, 1144375e1314SVladimir Oltean __ETHTOOL_LINK_MODE_MASK_NBITS); 1145375e1314SVladimir Oltean } 1146375e1314SVladimir Oltean 1147bdeced75SVladimir Oltean static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port, 1148bdeced75SVladimir Oltean phy_interface_t phy_mode) 1149bdeced75SVladimir Oltean { 1150bdeced75SVladimir Oltean switch (phy_mode) { 115128a134f5SVladimir Oltean case PHY_INTERFACE_MODE_INTERNAL: 1152bdeced75SVladimir Oltean if (port != 4 && port != 5) 1153bdeced75SVladimir Oltean return -ENOTSUPP; 1154bdeced75SVladimir Oltean return 0; 1155bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_SGMII: 1156bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_QSGMII: 1157bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_USXGMII: 1158bdeced75SVladimir Oltean case PHY_INTERFACE_MODE_2500BASEX: 1159bdeced75SVladimir Oltean /* Not supported on internal to-CPU ports */ 1160bdeced75SVladimir Oltean if (port == 4 || port == 5) 1161bdeced75SVladimir Oltean return -ENOTSUPP; 1162bdeced75SVladimir Oltean return 0; 1163bdeced75SVladimir Oltean default: 1164bdeced75SVladimir Oltean return -ENOTSUPP; 1165bdeced75SVladimir Oltean } 1166bdeced75SVladimir Oltean } 1167bdeced75SVladimir Oltean 1168aa92d836SMaxim Kochetkov /* Watermark encode 1169aa92d836SMaxim Kochetkov * Bit 8: Unit; 0:1, 1:16 1170aa92d836SMaxim Kochetkov * Bit 7-0: Value to be multiplied with unit 1171aa92d836SMaxim Kochetkov */ 1172aa92d836SMaxim Kochetkov static u16 vsc9959_wm_enc(u16 value) 1173aa92d836SMaxim Kochetkov { 1174aa92d836SMaxim Kochetkov if (value >= BIT(8)) 1175aa92d836SMaxim Kochetkov return BIT(8) | (value / 16); 1176aa92d836SMaxim Kochetkov 1177aa92d836SMaxim Kochetkov return value; 1178aa92d836SMaxim Kochetkov } 1179aa92d836SMaxim Kochetkov 118056051948SVladimir Oltean static const struct ocelot_ops vsc9959_ops = { 118156051948SVladimir Oltean .reset = vsc9959_reset, 1182aa92d836SMaxim Kochetkov .wm_enc = vsc9959_wm_enc, 118356051948SVladimir Oltean }; 118456051948SVladimir Oltean 1185bdeced75SVladimir Oltean static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 1186bdeced75SVladimir Oltean { 1187bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1188bdeced75SVladimir Oltean struct enetc_mdio_priv *mdio_priv; 1189bdeced75SVladimir Oltean struct device *dev = ocelot->dev; 1190bdeced75SVladimir Oltean void __iomem *imdio_regs; 1191b4024c9eSClaudiu Manoil struct resource res; 1192bdeced75SVladimir Oltean struct enetc_hw *hw; 1193bdeced75SVladimir Oltean struct mii_bus *bus; 1194bdeced75SVladimir Oltean int port; 1195bdeced75SVladimir Oltean int rc; 1196bdeced75SVladimir Oltean 1197bdeced75SVladimir Oltean felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 1198bdeced75SVladimir Oltean sizeof(struct phy_device *), 1199bdeced75SVladimir Oltean GFP_KERNEL); 1200bdeced75SVladimir Oltean if (!felix->pcs) { 1201bdeced75SVladimir Oltean dev_err(dev, "failed to allocate array for PCS PHYs\n"); 1202bdeced75SVladimir Oltean return -ENOMEM; 1203bdeced75SVladimir Oltean } 1204bdeced75SVladimir Oltean 1205b4024c9eSClaudiu Manoil memcpy(&res, felix->info->imdio_res, sizeof(res)); 1206b4024c9eSClaudiu Manoil res.flags = IORESOURCE_MEM; 1207375e1314SVladimir Oltean res.start += felix->imdio_base; 1208375e1314SVladimir Oltean res.end += felix->imdio_base; 1209bdeced75SVladimir Oltean 1210b4024c9eSClaudiu Manoil imdio_regs = devm_ioremap_resource(dev, &res); 1211bdeced75SVladimir Oltean if (IS_ERR(imdio_regs)) { 1212bdeced75SVladimir Oltean dev_err(dev, "failed to map internal MDIO registers\n"); 1213bdeced75SVladimir Oltean return PTR_ERR(imdio_regs); 1214bdeced75SVladimir Oltean } 1215bdeced75SVladimir Oltean 1216bdeced75SVladimir Oltean hw = enetc_hw_alloc(dev, imdio_regs); 1217bdeced75SVladimir Oltean if (IS_ERR(hw)) { 1218bdeced75SVladimir Oltean dev_err(dev, "failed to allocate ENETC HW structure\n"); 1219bdeced75SVladimir Oltean return PTR_ERR(hw); 1220bdeced75SVladimir Oltean } 1221bdeced75SVladimir Oltean 1222bdeced75SVladimir Oltean bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv)); 1223bdeced75SVladimir Oltean if (!bus) 1224bdeced75SVladimir Oltean return -ENOMEM; 1225bdeced75SVladimir Oltean 1226bdeced75SVladimir Oltean bus->name = "VSC9959 internal MDIO bus"; 1227bdeced75SVladimir Oltean bus->read = enetc_mdio_read; 1228bdeced75SVladimir Oltean bus->write = enetc_mdio_write; 1229bdeced75SVladimir Oltean bus->parent = dev; 1230bdeced75SVladimir Oltean mdio_priv = bus->priv; 1231bdeced75SVladimir Oltean mdio_priv->hw = hw; 1232bdeced75SVladimir Oltean /* This gets added to imdio_regs, which already maps addresses 1233bdeced75SVladimir Oltean * starting with the proper offset. 1234bdeced75SVladimir Oltean */ 1235bdeced75SVladimir Oltean mdio_priv->mdio_base = 0; 1236bdeced75SVladimir Oltean snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1237bdeced75SVladimir Oltean 1238bdeced75SVladimir Oltean /* Needed in order to initialize the bus mutex lock */ 1239bdeced75SVladimir Oltean rc = mdiobus_register(bus); 1240bdeced75SVladimir Oltean if (rc < 0) { 1241bdeced75SVladimir Oltean dev_err(dev, "failed to register MDIO bus\n"); 1242bdeced75SVladimir Oltean return rc; 1243bdeced75SVladimir Oltean } 1244bdeced75SVladimir Oltean 1245bdeced75SVladimir Oltean felix->imdio = bus; 1246bdeced75SVladimir Oltean 1247bdeced75SVladimir Oltean for (port = 0; port < felix->info->num_ports; port++) { 1248bdeced75SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 1249bdeced75SVladimir Oltean struct phy_device *pcs; 1250bdeced75SVladimir Oltean bool is_c45 = false; 1251bdeced75SVladimir Oltean 1252bdeced75SVladimir Oltean if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_USXGMII) 1253bdeced75SVladimir Oltean is_c45 = true; 1254bdeced75SVladimir Oltean 1255bdeced75SVladimir Oltean pcs = get_phy_device(felix->imdio, port, is_c45); 1256bdeced75SVladimir Oltean if (IS_ERR(pcs)) 1257bdeced75SVladimir Oltean continue; 1258bdeced75SVladimir Oltean 1259bdeced75SVladimir Oltean pcs->interface = ocelot_port->phy_mode; 1260bdeced75SVladimir Oltean felix->pcs[port] = pcs; 1261bdeced75SVladimir Oltean 1262bdeced75SVladimir Oltean dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1263bdeced75SVladimir Oltean } 1264bdeced75SVladimir Oltean 1265bdeced75SVladimir Oltean return 0; 1266bdeced75SVladimir Oltean } 1267bdeced75SVladimir Oltean 126884705fc1SMaxim Kochetkov void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1269bdeced75SVladimir Oltean { 1270bdeced75SVladimir Oltean struct felix *felix = ocelot_to_felix(ocelot); 1271bdeced75SVladimir Oltean int port; 1272bdeced75SVladimir Oltean 1273bdeced75SVladimir Oltean for (port = 0; port < ocelot->num_phys_ports; port++) { 1274bdeced75SVladimir Oltean struct phy_device *pcs = felix->pcs[port]; 1275bdeced75SVladimir Oltean 1276bdeced75SVladimir Oltean if (!pcs) 1277bdeced75SVladimir Oltean continue; 1278bdeced75SVladimir Oltean 1279bdeced75SVladimir Oltean put_device(&pcs->mdio.dev); 1280bdeced75SVladimir Oltean } 1281bdeced75SVladimir Oltean mdiobus_unregister(felix->imdio); 1282bdeced75SVladimir Oltean } 1283bdeced75SVladimir Oltean 1284de143c0eSXiaoliang Yang static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1285de143c0eSXiaoliang Yang u32 speed) 1286de143c0eSXiaoliang Yang { 1287de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1288de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED(speed), 1289de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_LINK_SPEED_M, 1290de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1291de143c0eSXiaoliang Yang } 1292de143c0eSXiaoliang Yang 1293de143c0eSXiaoliang Yang static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1294de143c0eSXiaoliang Yang u64 cycle_time, 1295de143c0eSXiaoliang Yang struct timespec64 *new_base_ts) 1296de143c0eSXiaoliang Yang { 1297de143c0eSXiaoliang Yang struct timespec64 ts; 1298de143c0eSXiaoliang Yang ktime_t new_base_time; 1299de143c0eSXiaoliang Yang ktime_t current_time; 1300de143c0eSXiaoliang Yang 1301de143c0eSXiaoliang Yang ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1302de143c0eSXiaoliang Yang current_time = timespec64_to_ktime(ts); 1303de143c0eSXiaoliang Yang new_base_time = base_time; 1304de143c0eSXiaoliang Yang 1305de143c0eSXiaoliang Yang if (base_time < current_time) { 1306de143c0eSXiaoliang Yang u64 nr_of_cycles = current_time - base_time; 1307de143c0eSXiaoliang Yang 1308de143c0eSXiaoliang Yang do_div(nr_of_cycles, cycle_time); 1309de143c0eSXiaoliang Yang new_base_time += cycle_time * (nr_of_cycles + 1); 1310de143c0eSXiaoliang Yang } 1311de143c0eSXiaoliang Yang 1312de143c0eSXiaoliang Yang *new_base_ts = ktime_to_timespec64(new_base_time); 1313de143c0eSXiaoliang Yang } 1314de143c0eSXiaoliang Yang 1315de143c0eSXiaoliang Yang static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1316de143c0eSXiaoliang Yang { 1317de143c0eSXiaoliang Yang return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1318de143c0eSXiaoliang Yang } 1319de143c0eSXiaoliang Yang 1320de143c0eSXiaoliang Yang static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1321de143c0eSXiaoliang Yang struct tc_taprio_sched_entry *entry) 1322de143c0eSXiaoliang Yang { 1323de143c0eSXiaoliang Yang ocelot_write(ocelot, 1324de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1325de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1326de143c0eSXiaoliang Yang QSYS_GCL_CFG_REG_1); 1327de143c0eSXiaoliang Yang ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1328de143c0eSXiaoliang Yang } 1329de143c0eSXiaoliang Yang 1330de143c0eSXiaoliang Yang static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1331de143c0eSXiaoliang Yang struct tc_taprio_qopt_offload *taprio) 1332de143c0eSXiaoliang Yang { 1333de143c0eSXiaoliang Yang struct timespec64 base_ts; 1334de143c0eSXiaoliang Yang int ret, i; 1335de143c0eSXiaoliang Yang u32 val; 1336de143c0eSXiaoliang Yang 1337de143c0eSXiaoliang Yang if (!taprio->enable) { 1338de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1339de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF), 1340de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1341de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE_M, 1342de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1343de143c0eSXiaoliang Yang 1344de143c0eSXiaoliang Yang return 0; 1345de143c0eSXiaoliang Yang } 1346de143c0eSXiaoliang Yang 1347de143c0eSXiaoliang Yang if (taprio->cycle_time > NSEC_PER_SEC || 1348de143c0eSXiaoliang Yang taprio->cycle_time_extension >= NSEC_PER_SEC) 1349de143c0eSXiaoliang Yang return -EINVAL; 1350de143c0eSXiaoliang Yang 1351de143c0eSXiaoliang Yang if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) 1352de143c0eSXiaoliang Yang return -ERANGE; 1353de143c0eSXiaoliang Yang 1354de143c0eSXiaoliang Yang ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1355de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1356de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1357de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1358de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 1359de143c0eSXiaoliang Yang 1360de143c0eSXiaoliang Yang /* Hardware errata - Admin config could not be overwritten if 1361de143c0eSXiaoliang Yang * config is pending, need reset the TAS module 1362de143c0eSXiaoliang Yang */ 1363de143c0eSXiaoliang Yang val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1364de143c0eSXiaoliang Yang if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) 1365de143c0eSXiaoliang Yang return -EBUSY; 1366de143c0eSXiaoliang Yang 1367de143c0eSXiaoliang Yang ocelot_rmw_rix(ocelot, 1368de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1369de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1370de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1371de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_ENABLE | 1372de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1373de143c0eSXiaoliang Yang QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1374de143c0eSXiaoliang Yang QSYS_TAG_CONFIG, port); 1375de143c0eSXiaoliang Yang 1376de143c0eSXiaoliang Yang vsc9959_new_base_time(ocelot, taprio->base_time, 1377de143c0eSXiaoliang Yang taprio->cycle_time, &base_ts); 1378de143c0eSXiaoliang Yang ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1379de143c0eSXiaoliang Yang ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1380de143c0eSXiaoliang Yang val = upper_32_bits(base_ts.tv_sec); 1381de143c0eSXiaoliang Yang ocelot_write(ocelot, 1382de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1383de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1384de143c0eSXiaoliang Yang QSYS_PARAM_CFG_REG_3); 1385de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1386de143c0eSXiaoliang Yang ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1387de143c0eSXiaoliang Yang 1388de143c0eSXiaoliang Yang for (i = 0; i < taprio->num_entries; i++) 1389de143c0eSXiaoliang Yang vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1390de143c0eSXiaoliang Yang 1391de143c0eSXiaoliang Yang ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1392de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1393de143c0eSXiaoliang Yang QSYS_TAS_PARAM_CFG_CTRL); 1394de143c0eSXiaoliang Yang 1395de143c0eSXiaoliang Yang ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1396de143c0eSXiaoliang Yang !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1397de143c0eSXiaoliang Yang 10, 100000); 1398de143c0eSXiaoliang Yang 1399de143c0eSXiaoliang Yang return ret; 1400de143c0eSXiaoliang Yang } 1401de143c0eSXiaoliang Yang 14020fbabf87SXiaoliang Yang static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 14030fbabf87SXiaoliang Yang struct tc_cbs_qopt_offload *cbs_qopt) 14040fbabf87SXiaoliang Yang { 14050fbabf87SXiaoliang Yang struct ocelot *ocelot = ds->priv; 14060fbabf87SXiaoliang Yang int port_ix = port * 8 + cbs_qopt->queue; 14070fbabf87SXiaoliang Yang u32 rate, burst; 14080fbabf87SXiaoliang Yang 14090fbabf87SXiaoliang Yang if (cbs_qopt->queue >= ds->num_tx_queues) 14100fbabf87SXiaoliang Yang return -EINVAL; 14110fbabf87SXiaoliang Yang 14120fbabf87SXiaoliang Yang if (!cbs_qopt->enable) { 14130fbabf87SXiaoliang Yang ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 14140fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(0), 14150fbabf87SXiaoliang Yang QSYS_CIR_CFG, port_ix); 14160fbabf87SXiaoliang Yang 14170fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 14180fbabf87SXiaoliang Yang QSYS_SE_CFG, port_ix); 14190fbabf87SXiaoliang Yang 14200fbabf87SXiaoliang Yang return 0; 14210fbabf87SXiaoliang Yang } 14220fbabf87SXiaoliang Yang 14230fbabf87SXiaoliang Yang /* Rate unit is 100 kbps */ 14240fbabf87SXiaoliang Yang rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 14250fbabf87SXiaoliang Yang /* Avoid using zero rate */ 14260fbabf87SXiaoliang Yang rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 14270fbabf87SXiaoliang Yang /* Burst unit is 4kB */ 14280fbabf87SXiaoliang Yang burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 14290fbabf87SXiaoliang Yang /* Avoid using zero burst size */ 1430b014d043SColin Ian King burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 14310fbabf87SXiaoliang Yang ocelot_write_gix(ocelot, 14320fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_RATE(rate) | 14330fbabf87SXiaoliang Yang QSYS_CIR_CFG_CIR_BURST(burst), 14340fbabf87SXiaoliang Yang QSYS_CIR_CFG, 14350fbabf87SXiaoliang Yang port_ix); 14360fbabf87SXiaoliang Yang 14370fbabf87SXiaoliang Yang ocelot_rmw_gix(ocelot, 14380fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE(0) | 14390fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA, 14400fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_AVB_ENA | 14410fbabf87SXiaoliang Yang QSYS_SE_CFG_SE_FRM_MODE_M, 14420fbabf87SXiaoliang Yang QSYS_SE_CFG, 14430fbabf87SXiaoliang Yang port_ix); 14440fbabf87SXiaoliang Yang 14450fbabf87SXiaoliang Yang return 0; 14460fbabf87SXiaoliang Yang } 14470fbabf87SXiaoliang Yang 1448de143c0eSXiaoliang Yang static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1449de143c0eSXiaoliang Yang enum tc_setup_type type, 1450de143c0eSXiaoliang Yang void *type_data) 1451de143c0eSXiaoliang Yang { 1452de143c0eSXiaoliang Yang struct ocelot *ocelot = ds->priv; 1453de143c0eSXiaoliang Yang 1454de143c0eSXiaoliang Yang switch (type) { 1455de143c0eSXiaoliang Yang case TC_SETUP_QDISC_TAPRIO: 1456de143c0eSXiaoliang Yang return vsc9959_qos_port_tas_set(ocelot, port, type_data); 14570fbabf87SXiaoliang Yang case TC_SETUP_QDISC_CBS: 14580fbabf87SXiaoliang Yang return vsc9959_qos_port_cbs_set(ds, port, type_data); 1459de143c0eSXiaoliang Yang default: 1460de143c0eSXiaoliang Yang return -EOPNOTSUPP; 1461de143c0eSXiaoliang Yang } 1462de143c0eSXiaoliang Yang } 1463de143c0eSXiaoliang Yang 146467c24049SVladimir Oltean static void vsc9959_xmit_template_populate(struct ocelot *ocelot, int port) 146567c24049SVladimir Oltean { 146667c24049SVladimir Oltean struct ocelot_port *ocelot_port = ocelot->ports[port]; 146767c24049SVladimir Oltean u8 *template = ocelot_port->xmit_template; 146867c24049SVladimir Oltean u64 bypass, dest, src; 146967c24049SVladimir Oltean 147067c24049SVladimir Oltean /* Set the source port as the CPU port module and not the 147167c24049SVladimir Oltean * NPI port 147267c24049SVladimir Oltean */ 147367c24049SVladimir Oltean src = ocelot->num_phys_ports; 147467c24049SVladimir Oltean dest = BIT(port); 147567c24049SVladimir Oltean bypass = true; 147667c24049SVladimir Oltean 147767c24049SVladimir Oltean packing(template, &bypass, 127, 127, OCELOT_TAG_LEN, PACK, 0); 147867c24049SVladimir Oltean packing(template, &dest, 68, 56, OCELOT_TAG_LEN, PACK, 0); 147967c24049SVladimir Oltean packing(template, &src, 46, 43, OCELOT_TAG_LEN, PACK, 0); 148067c24049SVladimir Oltean } 148167c24049SVladimir Oltean 1482375e1314SVladimir Oltean static const struct felix_info felix_info_vsc9959 = { 148356051948SVladimir Oltean .target_io_res = vsc9959_target_io_res, 148456051948SVladimir Oltean .port_io_res = vsc9959_port_io_res, 1485bdeced75SVladimir Oltean .imdio_res = &vsc9959_imdio_res, 148656051948SVladimir Oltean .regfields = vsc9959_regfields, 148756051948SVladimir Oltean .map = vsc9959_regmap, 148856051948SVladimir Oltean .ops = &vsc9959_ops, 148956051948SVladimir Oltean .stats_layout = vsc9959_stats_layout, 149056051948SVladimir Oltean .num_stats = ARRAY_SIZE(vsc9959_stats_layout), 149107d985eeSVladimir Oltean .vcap_is2_keys = vsc9959_vcap_is2_keys, 149207d985eeSVladimir Oltean .vcap_is2_actions = vsc9959_vcap_is2_actions, 149307d985eeSVladimir Oltean .vcap = vsc9959_vcap_props, 149456051948SVladimir Oltean .shared_queue_sz = 128 * 1024, 149521ce7f3eSVladimir Oltean .num_mact_rows = 2048, 149656051948SVladimir Oltean .num_ports = 6, 1497de143c0eSXiaoliang Yang .num_tx_queues = FELIX_NUM_TC, 1498bdeced75SVladimir Oltean .switch_pci_bar = 4, 1499bdeced75SVladimir Oltean .imdio_pci_bar = 0, 1500bdeced75SVladimir Oltean .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 1501bdeced75SVladimir Oltean .mdio_bus_free = vsc9959_mdio_bus_free, 15027e14a2dcSVladimir Oltean .pcs_config = vsc9959_pcs_config, 15037e14a2dcSVladimir Oltean .pcs_link_up = vsc9959_pcs_link_up, 1504bdeced75SVladimir Oltean .pcs_link_state = vsc9959_pcs_link_state, 1505375e1314SVladimir Oltean .phylink_validate = vsc9959_phylink_validate, 1506bdeced75SVladimir Oltean .prevalidate_phy_mode = vsc9959_prevalidate_phy_mode, 1507de143c0eSXiaoliang Yang .port_setup_tc = vsc9959_port_setup_tc, 1508de143c0eSXiaoliang Yang .port_sched_speed_set = vsc9959_sched_speed_set, 150967c24049SVladimir Oltean .xmit_template_populate = vsc9959_xmit_template_populate, 151056051948SVladimir Oltean }; 1511375e1314SVladimir Oltean 1512375e1314SVladimir Oltean static irqreturn_t felix_irq_handler(int irq, void *data) 1513375e1314SVladimir Oltean { 1514375e1314SVladimir Oltean struct ocelot *ocelot = (struct ocelot *)data; 1515375e1314SVladimir Oltean 1516375e1314SVladimir Oltean /* The INTB interrupt is used for both PTP TX timestamp interrupt 1517375e1314SVladimir Oltean * and preemption status change interrupt on each port. 1518375e1314SVladimir Oltean * 1519375e1314SVladimir Oltean * - Get txtstamp if have 1520375e1314SVladimir Oltean * - TODO: handle preemption. Without handling it, driver may get 1521375e1314SVladimir Oltean * interrupt storm. 1522375e1314SVladimir Oltean */ 1523375e1314SVladimir Oltean 1524375e1314SVladimir Oltean ocelot_get_txtstamp(ocelot); 1525375e1314SVladimir Oltean 1526375e1314SVladimir Oltean return IRQ_HANDLED; 1527375e1314SVladimir Oltean } 1528375e1314SVladimir Oltean 1529375e1314SVladimir Oltean static int felix_pci_probe(struct pci_dev *pdev, 1530375e1314SVladimir Oltean const struct pci_device_id *id) 1531375e1314SVladimir Oltean { 1532375e1314SVladimir Oltean struct dsa_switch *ds; 1533375e1314SVladimir Oltean struct ocelot *ocelot; 1534375e1314SVladimir Oltean struct felix *felix; 1535375e1314SVladimir Oltean int err; 1536375e1314SVladimir Oltean 1537375e1314SVladimir Oltean if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 1538375e1314SVladimir Oltean dev_info(&pdev->dev, "device is disabled, skipping\n"); 1539375e1314SVladimir Oltean return -ENODEV; 1540375e1314SVladimir Oltean } 1541375e1314SVladimir Oltean 1542375e1314SVladimir Oltean err = pci_enable_device(pdev); 1543375e1314SVladimir Oltean if (err) { 1544375e1314SVladimir Oltean dev_err(&pdev->dev, "device enable failed\n"); 1545375e1314SVladimir Oltean goto err_pci_enable; 1546375e1314SVladimir Oltean } 1547375e1314SVladimir Oltean 1548375e1314SVladimir Oltean /* set up for high or low dma */ 1549375e1314SVladimir Oltean err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1550375e1314SVladimir Oltean if (err) { 1551375e1314SVladimir Oltean err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1552375e1314SVladimir Oltean if (err) { 1553375e1314SVladimir Oltean dev_err(&pdev->dev, 1554375e1314SVladimir Oltean "DMA configuration failed: 0x%x\n", err); 1555375e1314SVladimir Oltean goto err_dma; 1556375e1314SVladimir Oltean } 1557375e1314SVladimir Oltean } 1558375e1314SVladimir Oltean 1559375e1314SVladimir Oltean felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 1560375e1314SVladimir Oltean if (!felix) { 1561375e1314SVladimir Oltean err = -ENOMEM; 1562375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 1563375e1314SVladimir Oltean goto err_alloc_felix; 1564375e1314SVladimir Oltean } 1565375e1314SVladimir Oltean 1566375e1314SVladimir Oltean pci_set_drvdata(pdev, felix); 1567375e1314SVladimir Oltean ocelot = &felix->ocelot; 1568375e1314SVladimir Oltean ocelot->dev = &pdev->dev; 1569375e1314SVladimir Oltean felix->info = &felix_info_vsc9959; 1570375e1314SVladimir Oltean felix->switch_base = pci_resource_start(pdev, 1571375e1314SVladimir Oltean felix->info->switch_pci_bar); 1572375e1314SVladimir Oltean felix->imdio_base = pci_resource_start(pdev, 1573375e1314SVladimir Oltean felix->info->imdio_pci_bar); 1574375e1314SVladimir Oltean 1575375e1314SVladimir Oltean pci_set_master(pdev); 1576375e1314SVladimir Oltean 1577375e1314SVladimir Oltean err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 1578375e1314SVladimir Oltean &felix_irq_handler, IRQF_ONESHOT, 1579375e1314SVladimir Oltean "felix-intb", ocelot); 1580375e1314SVladimir Oltean if (err) { 1581375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to request irq\n"); 1582375e1314SVladimir Oltean goto err_alloc_irq; 1583375e1314SVladimir Oltean } 1584375e1314SVladimir Oltean 1585375e1314SVladimir Oltean ocelot->ptp = 1; 1586375e1314SVladimir Oltean 1587375e1314SVladimir Oltean ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 1588375e1314SVladimir Oltean if (!ds) { 1589375e1314SVladimir Oltean err = -ENOMEM; 1590375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 1591375e1314SVladimir Oltean goto err_alloc_ds; 1592375e1314SVladimir Oltean } 1593375e1314SVladimir Oltean 1594375e1314SVladimir Oltean ds->dev = &pdev->dev; 1595375e1314SVladimir Oltean ds->num_ports = felix->info->num_ports; 1596375e1314SVladimir Oltean ds->num_tx_queues = felix->info->num_tx_queues; 1597375e1314SVladimir Oltean ds->ops = &felix_switch_ops; 1598375e1314SVladimir Oltean ds->priv = ocelot; 1599375e1314SVladimir Oltean felix->ds = ds; 1600375e1314SVladimir Oltean 1601375e1314SVladimir Oltean err = dsa_register_switch(ds); 1602375e1314SVladimir Oltean if (err) { 1603375e1314SVladimir Oltean dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err); 1604375e1314SVladimir Oltean goto err_register_ds; 1605375e1314SVladimir Oltean } 1606375e1314SVladimir Oltean 1607375e1314SVladimir Oltean return 0; 1608375e1314SVladimir Oltean 1609375e1314SVladimir Oltean err_register_ds: 1610375e1314SVladimir Oltean kfree(ds); 1611375e1314SVladimir Oltean err_alloc_ds: 1612375e1314SVladimir Oltean err_alloc_irq: 1613375e1314SVladimir Oltean err_alloc_felix: 1614375e1314SVladimir Oltean kfree(felix); 1615375e1314SVladimir Oltean err_dma: 1616375e1314SVladimir Oltean pci_disable_device(pdev); 1617375e1314SVladimir Oltean err_pci_enable: 1618375e1314SVladimir Oltean return err; 1619375e1314SVladimir Oltean } 1620375e1314SVladimir Oltean 1621375e1314SVladimir Oltean static void felix_pci_remove(struct pci_dev *pdev) 1622375e1314SVladimir Oltean { 1623375e1314SVladimir Oltean struct felix *felix; 1624375e1314SVladimir Oltean 1625375e1314SVladimir Oltean felix = pci_get_drvdata(pdev); 1626375e1314SVladimir Oltean 1627375e1314SVladimir Oltean dsa_unregister_switch(felix->ds); 1628375e1314SVladimir Oltean 1629375e1314SVladimir Oltean kfree(felix->ds); 1630375e1314SVladimir Oltean kfree(felix); 1631375e1314SVladimir Oltean 1632375e1314SVladimir Oltean pci_disable_device(pdev); 1633375e1314SVladimir Oltean } 1634375e1314SVladimir Oltean 1635375e1314SVladimir Oltean static struct pci_device_id felix_ids[] = { 1636375e1314SVladimir Oltean { 1637375e1314SVladimir Oltean /* NXP LS1028A */ 1638375e1314SVladimir Oltean PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 1639375e1314SVladimir Oltean }, 1640375e1314SVladimir Oltean { 0, } 1641375e1314SVladimir Oltean }; 1642375e1314SVladimir Oltean MODULE_DEVICE_TABLE(pci, felix_ids); 1643375e1314SVladimir Oltean 1644375e1314SVladimir Oltean struct pci_driver felix_vsc9959_pci_driver = { 1645375e1314SVladimir Oltean .name = "mscc_felix", 1646375e1314SVladimir Oltean .id_table = felix_ids, 1647375e1314SVladimir Oltean .probe = felix_pci_probe, 1648375e1314SVladimir Oltean .remove = felix_pci_remove, 1649375e1314SVladimir Oltean }; 1650