1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2019-2021 NXP 3 * 4 * This is an umbrella module for all network switches that are 5 * register-compatible with Ocelot and that perform I/O to their host CPU 6 * through an NPI (Node Processor Interface) Ethernet port. 7 */ 8 #include <uapi/linux/if_bridge.h> 9 #include <soc/mscc/ocelot_vcap.h> 10 #include <soc/mscc/ocelot_qsys.h> 11 #include <soc/mscc/ocelot_sys.h> 12 #include <soc/mscc/ocelot_dev.h> 13 #include <soc/mscc/ocelot_ana.h> 14 #include <soc/mscc/ocelot_ptp.h> 15 #include <soc/mscc/ocelot.h> 16 #include <linux/dsa/8021q.h> 17 #include <linux/dsa/ocelot.h> 18 #include <linux/platform_device.h> 19 #include <linux/ptp_classify.h> 20 #include <linux/module.h> 21 #include <linux/of_net.h> 22 #include <linux/pci.h> 23 #include <linux/of.h> 24 #include <net/pkt_sched.h> 25 #include <net/dsa.h> 26 #include "felix.h" 27 28 /* Translate the DSA database API into the ocelot switch library API, 29 * which uses VID 0 for all ports that aren't part of a bridge, 30 * and expects the bridge_dev to be NULL in that case. 31 */ 32 static struct net_device *felix_classify_db(struct dsa_db db) 33 { 34 switch (db.type) { 35 case DSA_DB_PORT: 36 case DSA_DB_LAG: 37 return NULL; 38 case DSA_DB_BRIDGE: 39 return db.bridge.dev; 40 default: 41 return ERR_PTR(-EOPNOTSUPP); 42 } 43 } 44 45 /* We are called before felix_npi_port_init(), so ocelot->npi is -1. */ 46 static int felix_migrate_fdbs_to_npi_port(struct dsa_switch *ds, int port, 47 const unsigned char *addr, u16 vid, 48 struct dsa_db db) 49 { 50 struct net_device *bridge_dev = felix_classify_db(db); 51 struct ocelot *ocelot = ds->priv; 52 int cpu = ocelot->num_phys_ports; 53 int err; 54 55 err = ocelot_fdb_del(ocelot, port, addr, vid, bridge_dev); 56 if (err) 57 return err; 58 59 return ocelot_fdb_add(ocelot, cpu, addr, vid, bridge_dev); 60 } 61 62 static int felix_migrate_mdbs_to_npi_port(struct dsa_switch *ds, int port, 63 const unsigned char *addr, u16 vid, 64 struct dsa_db db) 65 { 66 struct net_device *bridge_dev = felix_classify_db(db); 67 struct switchdev_obj_port_mdb mdb; 68 struct ocelot *ocelot = ds->priv; 69 int cpu = ocelot->num_phys_ports; 70 int err; 71 72 memset(&mdb, 0, sizeof(mdb)); 73 ether_addr_copy(mdb.addr, addr); 74 mdb.vid = vid; 75 76 err = ocelot_port_mdb_del(ocelot, port, &mdb, bridge_dev); 77 if (err) 78 return err; 79 80 return ocelot_port_mdb_add(ocelot, cpu, &mdb, bridge_dev); 81 } 82 83 static void felix_migrate_pgid_bit(struct dsa_switch *ds, int from, int to, 84 int pgid) 85 { 86 struct ocelot *ocelot = ds->priv; 87 bool on; 88 u32 val; 89 90 val = ocelot_read_rix(ocelot, ANA_PGID_PGID, pgid); 91 on = !!(val & BIT(from)); 92 val &= ~BIT(from); 93 if (on) 94 val |= BIT(to); 95 else 96 val &= ~BIT(to); 97 98 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, pgid); 99 } 100 101 static void felix_migrate_flood_to_npi_port(struct dsa_switch *ds, int port) 102 { 103 struct ocelot *ocelot = ds->priv; 104 105 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_UC); 106 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_MC); 107 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_BC); 108 } 109 110 static void 111 felix_migrate_flood_to_tag_8021q_port(struct dsa_switch *ds, int port) 112 { 113 struct ocelot *ocelot = ds->priv; 114 115 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_UC); 116 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_MC); 117 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_BC); 118 } 119 120 /* ocelot->npi was already set to -1 by felix_npi_port_deinit, so 121 * ocelot_fdb_add() will not redirect FDB entries towards the 122 * CPU port module here, which is what we want. 123 */ 124 static int 125 felix_migrate_fdbs_to_tag_8021q_port(struct dsa_switch *ds, int port, 126 const unsigned char *addr, u16 vid, 127 struct dsa_db db) 128 { 129 struct net_device *bridge_dev = felix_classify_db(db); 130 struct ocelot *ocelot = ds->priv; 131 int cpu = ocelot->num_phys_ports; 132 int err; 133 134 err = ocelot_fdb_del(ocelot, cpu, addr, vid, bridge_dev); 135 if (err) 136 return err; 137 138 return ocelot_fdb_add(ocelot, port, addr, vid, bridge_dev); 139 } 140 141 static int 142 felix_migrate_mdbs_to_tag_8021q_port(struct dsa_switch *ds, int port, 143 const unsigned char *addr, u16 vid, 144 struct dsa_db db) 145 { 146 struct net_device *bridge_dev = felix_classify_db(db); 147 struct switchdev_obj_port_mdb mdb; 148 struct ocelot *ocelot = ds->priv; 149 int cpu = ocelot->num_phys_ports; 150 int err; 151 152 memset(&mdb, 0, sizeof(mdb)); 153 ether_addr_copy(mdb.addr, addr); 154 mdb.vid = vid; 155 156 err = ocelot_port_mdb_del(ocelot, cpu, &mdb, bridge_dev); 157 if (err) 158 return err; 159 160 return ocelot_port_mdb_add(ocelot, port, &mdb, bridge_dev); 161 } 162 163 /* Set up VCAP ES0 rules for pushing a tag_8021q VLAN towards the CPU such that 164 * the tagger can perform RX source port identification. 165 */ 166 static int felix_tag_8021q_vlan_add_rx(struct felix *felix, int port, u16 vid) 167 { 168 struct ocelot_vcap_filter *outer_tagging_rule; 169 struct ocelot *ocelot = &felix->ocelot; 170 struct dsa_switch *ds = felix->ds; 171 int key_length, upstream, err; 172 173 key_length = ocelot->vcap[VCAP_ES0].keys[VCAP_ES0_IGR_PORT].length; 174 upstream = dsa_upstream_port(ds, port); 175 176 outer_tagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), 177 GFP_KERNEL); 178 if (!outer_tagging_rule) 179 return -ENOMEM; 180 181 outer_tagging_rule->key_type = OCELOT_VCAP_KEY_ANY; 182 outer_tagging_rule->prio = 1; 183 outer_tagging_rule->id.cookie = OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port); 184 outer_tagging_rule->id.tc_offload = false; 185 outer_tagging_rule->block_id = VCAP_ES0; 186 outer_tagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 187 outer_tagging_rule->lookup = 0; 188 outer_tagging_rule->ingress_port.value = port; 189 outer_tagging_rule->ingress_port.mask = GENMASK(key_length - 1, 0); 190 outer_tagging_rule->egress_port.value = upstream; 191 outer_tagging_rule->egress_port.mask = GENMASK(key_length - 1, 0); 192 outer_tagging_rule->action.push_outer_tag = OCELOT_ES0_TAG; 193 outer_tagging_rule->action.tag_a_tpid_sel = OCELOT_TAG_TPID_SEL_8021AD; 194 outer_tagging_rule->action.tag_a_vid_sel = 1; 195 outer_tagging_rule->action.vid_a_val = vid; 196 197 err = ocelot_vcap_filter_add(ocelot, outer_tagging_rule, NULL); 198 if (err) 199 kfree(outer_tagging_rule); 200 201 return err; 202 } 203 204 static int felix_tag_8021q_vlan_del_rx(struct felix *felix, int port, u16 vid) 205 { 206 struct ocelot_vcap_filter *outer_tagging_rule; 207 struct ocelot_vcap_block *block_vcap_es0; 208 struct ocelot *ocelot = &felix->ocelot; 209 210 block_vcap_es0 = &ocelot->block[VCAP_ES0]; 211 212 outer_tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_es0, 213 port, false); 214 if (!outer_tagging_rule) 215 return -ENOENT; 216 217 return ocelot_vcap_filter_del(ocelot, outer_tagging_rule); 218 } 219 220 /* Set up VCAP IS1 rules for stripping the tag_8021q VLAN on TX and VCAP IS2 221 * rules for steering those tagged packets towards the correct destination port 222 */ 223 static int felix_tag_8021q_vlan_add_tx(struct felix *felix, int port, u16 vid) 224 { 225 struct ocelot_vcap_filter *untagging_rule, *redirect_rule; 226 struct ocelot *ocelot = &felix->ocelot; 227 struct dsa_switch *ds = felix->ds; 228 int upstream, err; 229 230 untagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); 231 if (!untagging_rule) 232 return -ENOMEM; 233 234 redirect_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); 235 if (!redirect_rule) { 236 kfree(untagging_rule); 237 return -ENOMEM; 238 } 239 240 upstream = dsa_upstream_port(ds, port); 241 242 untagging_rule->key_type = OCELOT_VCAP_KEY_ANY; 243 untagging_rule->ingress_port_mask = BIT(upstream); 244 untagging_rule->vlan.vid.value = vid; 245 untagging_rule->vlan.vid.mask = VLAN_VID_MASK; 246 untagging_rule->prio = 1; 247 untagging_rule->id.cookie = OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port); 248 untagging_rule->id.tc_offload = false; 249 untagging_rule->block_id = VCAP_IS1; 250 untagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 251 untagging_rule->lookup = 0; 252 untagging_rule->action.vlan_pop_cnt_ena = true; 253 untagging_rule->action.vlan_pop_cnt = 1; 254 untagging_rule->action.pag_override_mask = 0xff; 255 untagging_rule->action.pag_val = port; 256 257 err = ocelot_vcap_filter_add(ocelot, untagging_rule, NULL); 258 if (err) { 259 kfree(untagging_rule); 260 kfree(redirect_rule); 261 return err; 262 } 263 264 redirect_rule->key_type = OCELOT_VCAP_KEY_ANY; 265 redirect_rule->ingress_port_mask = BIT(upstream); 266 redirect_rule->pag = port; 267 redirect_rule->prio = 1; 268 redirect_rule->id.cookie = OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port); 269 redirect_rule->id.tc_offload = false; 270 redirect_rule->block_id = VCAP_IS2; 271 redirect_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 272 redirect_rule->lookup = 0; 273 redirect_rule->action.mask_mode = OCELOT_MASK_MODE_REDIRECT; 274 redirect_rule->action.port_mask = BIT(port); 275 276 err = ocelot_vcap_filter_add(ocelot, redirect_rule, NULL); 277 if (err) { 278 ocelot_vcap_filter_del(ocelot, untagging_rule); 279 kfree(redirect_rule); 280 return err; 281 } 282 283 return 0; 284 } 285 286 static int felix_tag_8021q_vlan_del_tx(struct felix *felix, int port, u16 vid) 287 { 288 struct ocelot_vcap_filter *untagging_rule, *redirect_rule; 289 struct ocelot_vcap_block *block_vcap_is1; 290 struct ocelot_vcap_block *block_vcap_is2; 291 struct ocelot *ocelot = &felix->ocelot; 292 int err; 293 294 block_vcap_is1 = &ocelot->block[VCAP_IS1]; 295 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 296 297 untagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is1, 298 port, false); 299 if (!untagging_rule) 300 return -ENOENT; 301 302 err = ocelot_vcap_filter_del(ocelot, untagging_rule); 303 if (err) 304 return err; 305 306 redirect_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, 307 port, false); 308 if (!redirect_rule) 309 return -ENOENT; 310 311 return ocelot_vcap_filter_del(ocelot, redirect_rule); 312 } 313 314 static int felix_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 315 u16 flags) 316 { 317 struct ocelot *ocelot = ds->priv; 318 int err; 319 320 /* tag_8021q.c assumes we are implementing this via port VLAN 321 * membership, which we aren't. So we don't need to add any VCAP filter 322 * for the CPU port. 323 */ 324 if (!dsa_is_user_port(ds, port)) 325 return 0; 326 327 err = felix_tag_8021q_vlan_add_rx(ocelot_to_felix(ocelot), port, vid); 328 if (err) 329 return err; 330 331 err = felix_tag_8021q_vlan_add_tx(ocelot_to_felix(ocelot), port, vid); 332 if (err) { 333 felix_tag_8021q_vlan_del_rx(ocelot_to_felix(ocelot), port, vid); 334 return err; 335 } 336 337 return 0; 338 } 339 340 static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 341 { 342 struct ocelot *ocelot = ds->priv; 343 int err; 344 345 if (!dsa_is_user_port(ds, port)) 346 return 0; 347 348 err = felix_tag_8021q_vlan_del_rx(ocelot_to_felix(ocelot), port, vid); 349 if (err) 350 return err; 351 352 err = felix_tag_8021q_vlan_del_tx(ocelot_to_felix(ocelot), port, vid); 353 if (err) { 354 felix_tag_8021q_vlan_add_rx(ocelot_to_felix(ocelot), port, vid); 355 return err; 356 } 357 358 return 0; 359 } 360 361 /* Alternatively to using the NPI functionality, that same hardware MAC 362 * connected internally to the enetc or fman DSA master can be configured to 363 * use the software-defined tag_8021q frame format. As far as the hardware is 364 * concerned, it thinks it is a "dumb switch" - the queues of the CPU port 365 * module are now disconnected from it, but can still be accessed through 366 * register-based MMIO. 367 */ 368 static void felix_8021q_cpu_port_init(struct ocelot *ocelot, int port) 369 { 370 mutex_lock(&ocelot->fwd_domain_lock); 371 372 ocelot_port_set_dsa_8021q_cpu(ocelot, port); 373 374 /* Overwrite PGID_CPU with the non-tagging port */ 375 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, PGID_CPU); 376 377 ocelot_apply_bridge_fwd_mask(ocelot, true); 378 379 mutex_unlock(&ocelot->fwd_domain_lock); 380 } 381 382 static void felix_8021q_cpu_port_deinit(struct ocelot *ocelot, int port) 383 { 384 mutex_lock(&ocelot->fwd_domain_lock); 385 386 ocelot_port_unset_dsa_8021q_cpu(ocelot, port); 387 388 /* Restore PGID_CPU */ 389 ocelot_write_rix(ocelot, BIT(ocelot->num_phys_ports), ANA_PGID_PGID, 390 PGID_CPU); 391 392 ocelot_apply_bridge_fwd_mask(ocelot, true); 393 394 mutex_unlock(&ocelot->fwd_domain_lock); 395 } 396 397 /* On switches with no extraction IRQ wired, trapped packets need to be 398 * replicated over Ethernet as well, otherwise we'd get no notification of 399 * their arrival when using the ocelot-8021q tagging protocol. 400 */ 401 static int felix_update_trapping_destinations(struct dsa_switch *ds, 402 bool using_tag_8021q) 403 { 404 struct ocelot *ocelot = ds->priv; 405 struct felix *felix = ocelot_to_felix(ocelot); 406 struct ocelot_vcap_filter *trap; 407 enum ocelot_mask_mode mask_mode; 408 unsigned long port_mask; 409 struct dsa_port *dp; 410 bool cpu_copy_ena; 411 int cpu = -1, err; 412 413 if (!felix->info->quirk_no_xtr_irq) 414 return 0; 415 416 /* Figure out the current CPU port */ 417 dsa_switch_for_each_cpu_port(dp, ds) { 418 cpu = dp->index; 419 break; 420 } 421 422 /* We are sure that "cpu" was found, otherwise 423 * dsa_tree_setup_default_cpu() would have failed earlier. 424 */ 425 426 /* Make sure all traps are set up for that destination */ 427 list_for_each_entry(trap, &ocelot->traps, trap_list) { 428 /* Figure out the current trapping destination */ 429 if (using_tag_8021q) { 430 /* Redirect to the tag_8021q CPU port. If timestamps 431 * are necessary, also copy trapped packets to the CPU 432 * port module. 433 */ 434 mask_mode = OCELOT_MASK_MODE_REDIRECT; 435 port_mask = BIT(cpu); 436 cpu_copy_ena = !!trap->take_ts; 437 } else { 438 /* Trap packets only to the CPU port module, which is 439 * redirected to the NPI port (the DSA CPU port) 440 */ 441 mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 442 port_mask = 0; 443 cpu_copy_ena = true; 444 } 445 446 if (trap->action.mask_mode == mask_mode && 447 trap->action.port_mask == port_mask && 448 trap->action.cpu_copy_ena == cpu_copy_ena) 449 continue; 450 451 trap->action.mask_mode = mask_mode; 452 trap->action.port_mask = port_mask; 453 trap->action.cpu_copy_ena = cpu_copy_ena; 454 455 err = ocelot_vcap_filter_replace(ocelot, trap); 456 if (err) 457 return err; 458 } 459 460 return 0; 461 } 462 463 static int felix_setup_tag_8021q(struct dsa_switch *ds, int cpu) 464 { 465 struct ocelot *ocelot = ds->priv; 466 struct dsa_port *dp; 467 int err; 468 469 felix_8021q_cpu_port_init(ocelot, cpu); 470 471 dsa_switch_for_each_available_port(dp, ds) { 472 /* This overwrites ocelot_init(): 473 * Do not forward BPDU frames to the CPU port module, 474 * for 2 reasons: 475 * - When these packets are injected from the tag_8021q 476 * CPU port, we want them to go out, not loop back 477 * into the system. 478 * - STP traffic ingressing on a user port should go to 479 * the tag_8021q CPU port, not to the hardware CPU 480 * port module. 481 */ 482 ocelot_write_gix(ocelot, 483 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0), 484 ANA_PORT_CPU_FWD_BPDU_CFG, dp->index); 485 } 486 487 err = dsa_tag_8021q_register(ds, htons(ETH_P_8021AD)); 488 if (err) 489 return err; 490 491 err = dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_tag_8021q_port); 492 if (err) 493 goto out_tag_8021q_unregister; 494 495 err = dsa_port_walk_mdbs(ds, cpu, felix_migrate_mdbs_to_tag_8021q_port); 496 if (err) 497 goto out_migrate_fdbs; 498 499 felix_migrate_flood_to_tag_8021q_port(ds, cpu); 500 501 err = felix_update_trapping_destinations(ds, true); 502 if (err) 503 goto out_migrate_flood; 504 505 /* The ownership of the CPU port module's queues might have just been 506 * transferred to the tag_8021q tagger from the NPI-based tagger. 507 * So there might still be all sorts of crap in the queues. On the 508 * other hand, the MMIO-based matching of PTP frames is very brittle, 509 * so we need to be careful that there are no extra frames to be 510 * dequeued over MMIO, since we would never know to discard them. 511 */ 512 ocelot_drain_cpu_queue(ocelot, 0); 513 514 return 0; 515 516 out_migrate_flood: 517 felix_migrate_flood_to_npi_port(ds, cpu); 518 dsa_port_walk_mdbs(ds, cpu, felix_migrate_mdbs_to_npi_port); 519 out_migrate_fdbs: 520 dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_npi_port); 521 out_tag_8021q_unregister: 522 dsa_tag_8021q_unregister(ds); 523 return err; 524 } 525 526 static void felix_teardown_tag_8021q(struct dsa_switch *ds, int cpu) 527 { 528 struct ocelot *ocelot = ds->priv; 529 struct dsa_port *dp; 530 int err; 531 532 err = felix_update_trapping_destinations(ds, false); 533 if (err) 534 dev_err(ds->dev, "felix_teardown_mmio_filtering returned %d", 535 err); 536 537 dsa_tag_8021q_unregister(ds); 538 539 dsa_switch_for_each_available_port(dp, ds) { 540 /* Restore the logic from ocelot_init: 541 * do not forward BPDU frames to the front ports. 542 */ 543 ocelot_write_gix(ocelot, 544 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 545 ANA_PORT_CPU_FWD_BPDU_CFG, 546 dp->index); 547 } 548 549 felix_8021q_cpu_port_deinit(ocelot, cpu); 550 } 551 552 /* The CPU port module is connected to the Node Processor Interface (NPI). This 553 * is the mode through which frames can be injected from and extracted to an 554 * external CPU, over Ethernet. In NXP SoCs, the "external CPU" is the ARM CPU 555 * running Linux, and this forms a DSA setup together with the enetc or fman 556 * DSA master. 557 */ 558 static void felix_npi_port_init(struct ocelot *ocelot, int port) 559 { 560 ocelot->npi = port; 561 562 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 563 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(port), 564 QSYS_EXT_CPU_CFG); 565 566 /* NPI port Injection/Extraction configuration */ 567 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 568 ocelot->npi_xtr_prefix); 569 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 570 ocelot->npi_inj_prefix); 571 572 /* Disable transmission of pause frames */ 573 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 574 } 575 576 static void felix_npi_port_deinit(struct ocelot *ocelot, int port) 577 { 578 /* Restore hardware defaults */ 579 int unused_port = ocelot->num_phys_ports + 2; 580 581 ocelot->npi = -1; 582 583 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPU_PORT(unused_port), 584 QSYS_EXT_CPU_CFG); 585 586 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 587 OCELOT_TAG_PREFIX_DISABLED); 588 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 589 OCELOT_TAG_PREFIX_DISABLED); 590 591 /* Enable transmission of pause frames */ 592 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 593 } 594 595 static int felix_setup_tag_npi(struct dsa_switch *ds, int cpu) 596 { 597 struct ocelot *ocelot = ds->priv; 598 int err; 599 600 err = dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_npi_port); 601 if (err) 602 return err; 603 604 err = dsa_port_walk_mdbs(ds, cpu, felix_migrate_mdbs_to_npi_port); 605 if (err) 606 goto out_migrate_fdbs; 607 608 felix_migrate_flood_to_npi_port(ds, cpu); 609 610 felix_npi_port_init(ocelot, cpu); 611 612 return 0; 613 614 out_migrate_fdbs: 615 dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_tag_8021q_port); 616 617 return err; 618 } 619 620 static void felix_teardown_tag_npi(struct dsa_switch *ds, int cpu) 621 { 622 struct ocelot *ocelot = ds->priv; 623 624 felix_npi_port_deinit(ocelot, cpu); 625 } 626 627 static int felix_set_tag_protocol(struct dsa_switch *ds, int cpu, 628 enum dsa_tag_protocol proto) 629 { 630 int err; 631 632 switch (proto) { 633 case DSA_TAG_PROTO_SEVILLE: 634 case DSA_TAG_PROTO_OCELOT: 635 err = felix_setup_tag_npi(ds, cpu); 636 break; 637 case DSA_TAG_PROTO_OCELOT_8021Q: 638 err = felix_setup_tag_8021q(ds, cpu); 639 break; 640 default: 641 err = -EPROTONOSUPPORT; 642 } 643 644 return err; 645 } 646 647 static void felix_del_tag_protocol(struct dsa_switch *ds, int cpu, 648 enum dsa_tag_protocol proto) 649 { 650 switch (proto) { 651 case DSA_TAG_PROTO_SEVILLE: 652 case DSA_TAG_PROTO_OCELOT: 653 felix_teardown_tag_npi(ds, cpu); 654 break; 655 case DSA_TAG_PROTO_OCELOT_8021Q: 656 felix_teardown_tag_8021q(ds, cpu); 657 break; 658 default: 659 break; 660 } 661 } 662 663 /* This always leaves the switch in a consistent state, because although the 664 * tag_8021q setup can fail, the NPI setup can't. So either the change is made, 665 * or the restoration is guaranteed to work. 666 */ 667 static int felix_change_tag_protocol(struct dsa_switch *ds, int cpu, 668 enum dsa_tag_protocol proto) 669 { 670 struct ocelot *ocelot = ds->priv; 671 struct felix *felix = ocelot_to_felix(ocelot); 672 enum dsa_tag_protocol old_proto = felix->tag_proto; 673 int err; 674 675 if (proto != DSA_TAG_PROTO_SEVILLE && 676 proto != DSA_TAG_PROTO_OCELOT && 677 proto != DSA_TAG_PROTO_OCELOT_8021Q) 678 return -EPROTONOSUPPORT; 679 680 felix_del_tag_protocol(ds, cpu, old_proto); 681 682 err = felix_set_tag_protocol(ds, cpu, proto); 683 if (err) { 684 felix_set_tag_protocol(ds, cpu, old_proto); 685 return err; 686 } 687 688 felix->tag_proto = proto; 689 690 return 0; 691 } 692 693 static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds, 694 int port, 695 enum dsa_tag_protocol mp) 696 { 697 struct ocelot *ocelot = ds->priv; 698 struct felix *felix = ocelot_to_felix(ocelot); 699 700 return felix->tag_proto; 701 } 702 703 static int felix_set_ageing_time(struct dsa_switch *ds, 704 unsigned int ageing_time) 705 { 706 struct ocelot *ocelot = ds->priv; 707 708 ocelot_set_ageing_time(ocelot, ageing_time); 709 710 return 0; 711 } 712 713 static void felix_port_fast_age(struct dsa_switch *ds, int port) 714 { 715 struct ocelot *ocelot = ds->priv; 716 int err; 717 718 err = ocelot_mact_flush(ocelot, port); 719 if (err) 720 dev_err(ds->dev, "Flushing MAC table on port %d returned %pe\n", 721 port, ERR_PTR(err)); 722 } 723 724 static int felix_fdb_dump(struct dsa_switch *ds, int port, 725 dsa_fdb_dump_cb_t *cb, void *data) 726 { 727 struct ocelot *ocelot = ds->priv; 728 729 return ocelot_fdb_dump(ocelot, port, cb, data); 730 } 731 732 static int felix_fdb_add(struct dsa_switch *ds, int port, 733 const unsigned char *addr, u16 vid, 734 struct dsa_db db) 735 { 736 struct net_device *bridge_dev = felix_classify_db(db); 737 struct ocelot *ocelot = ds->priv; 738 739 if (IS_ERR(bridge_dev)) 740 return PTR_ERR(bridge_dev); 741 742 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 743 dsa_fdb_present_in_other_db(ds, port, addr, vid, db)) 744 return 0; 745 746 return ocelot_fdb_add(ocelot, port, addr, vid, bridge_dev); 747 } 748 749 static int felix_fdb_del(struct dsa_switch *ds, int port, 750 const unsigned char *addr, u16 vid, 751 struct dsa_db db) 752 { 753 struct net_device *bridge_dev = felix_classify_db(db); 754 struct ocelot *ocelot = ds->priv; 755 756 if (IS_ERR(bridge_dev)) 757 return PTR_ERR(bridge_dev); 758 759 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 760 dsa_fdb_present_in_other_db(ds, port, addr, vid, db)) 761 return 0; 762 763 return ocelot_fdb_del(ocelot, port, addr, vid, bridge_dev); 764 } 765 766 static int felix_lag_fdb_add(struct dsa_switch *ds, struct dsa_lag lag, 767 const unsigned char *addr, u16 vid, 768 struct dsa_db db) 769 { 770 struct net_device *bridge_dev = felix_classify_db(db); 771 struct ocelot *ocelot = ds->priv; 772 773 if (IS_ERR(bridge_dev)) 774 return PTR_ERR(bridge_dev); 775 776 return ocelot_lag_fdb_add(ocelot, lag.dev, addr, vid, bridge_dev); 777 } 778 779 static int felix_lag_fdb_del(struct dsa_switch *ds, struct dsa_lag lag, 780 const unsigned char *addr, u16 vid, 781 struct dsa_db db) 782 { 783 struct net_device *bridge_dev = felix_classify_db(db); 784 struct ocelot *ocelot = ds->priv; 785 786 if (IS_ERR(bridge_dev)) 787 return PTR_ERR(bridge_dev); 788 789 return ocelot_lag_fdb_del(ocelot, lag.dev, addr, vid, bridge_dev); 790 } 791 792 static int felix_mdb_add(struct dsa_switch *ds, int port, 793 const struct switchdev_obj_port_mdb *mdb, 794 struct dsa_db db) 795 { 796 struct net_device *bridge_dev = felix_classify_db(db); 797 struct ocelot *ocelot = ds->priv; 798 799 if (IS_ERR(bridge_dev)) 800 return PTR_ERR(bridge_dev); 801 802 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 803 dsa_mdb_present_in_other_db(ds, port, mdb, db)) 804 return 0; 805 806 return ocelot_port_mdb_add(ocelot, port, mdb, bridge_dev); 807 } 808 809 static int felix_mdb_del(struct dsa_switch *ds, int port, 810 const struct switchdev_obj_port_mdb *mdb, 811 struct dsa_db db) 812 { 813 struct net_device *bridge_dev = felix_classify_db(db); 814 struct ocelot *ocelot = ds->priv; 815 816 if (IS_ERR(bridge_dev)) 817 return PTR_ERR(bridge_dev); 818 819 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 820 dsa_mdb_present_in_other_db(ds, port, mdb, db)) 821 return 0; 822 823 return ocelot_port_mdb_del(ocelot, port, mdb, bridge_dev); 824 } 825 826 static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port, 827 u8 state) 828 { 829 struct ocelot *ocelot = ds->priv; 830 831 return ocelot_bridge_stp_state_set(ocelot, port, state); 832 } 833 834 static int felix_pre_bridge_flags(struct dsa_switch *ds, int port, 835 struct switchdev_brport_flags val, 836 struct netlink_ext_ack *extack) 837 { 838 struct ocelot *ocelot = ds->priv; 839 840 return ocelot_port_pre_bridge_flags(ocelot, port, val); 841 } 842 843 static int felix_bridge_flags(struct dsa_switch *ds, int port, 844 struct switchdev_brport_flags val, 845 struct netlink_ext_ack *extack) 846 { 847 struct ocelot *ocelot = ds->priv; 848 849 ocelot_port_bridge_flags(ocelot, port, val); 850 851 return 0; 852 } 853 854 static int felix_bridge_join(struct dsa_switch *ds, int port, 855 struct dsa_bridge bridge, bool *tx_fwd_offload, 856 struct netlink_ext_ack *extack) 857 { 858 struct ocelot *ocelot = ds->priv; 859 860 return ocelot_port_bridge_join(ocelot, port, bridge.dev, bridge.num, 861 extack); 862 } 863 864 static void felix_bridge_leave(struct dsa_switch *ds, int port, 865 struct dsa_bridge bridge) 866 { 867 struct ocelot *ocelot = ds->priv; 868 869 ocelot_port_bridge_leave(ocelot, port, bridge.dev); 870 } 871 872 static int felix_lag_join(struct dsa_switch *ds, int port, 873 struct dsa_lag lag, 874 struct netdev_lag_upper_info *info) 875 { 876 struct ocelot *ocelot = ds->priv; 877 878 return ocelot_port_lag_join(ocelot, port, lag.dev, info); 879 } 880 881 static int felix_lag_leave(struct dsa_switch *ds, int port, 882 struct dsa_lag lag) 883 { 884 struct ocelot *ocelot = ds->priv; 885 886 ocelot_port_lag_leave(ocelot, port, lag.dev); 887 888 return 0; 889 } 890 891 static int felix_lag_change(struct dsa_switch *ds, int port) 892 { 893 struct dsa_port *dp = dsa_to_port(ds, port); 894 struct ocelot *ocelot = ds->priv; 895 896 ocelot_port_lag_change(ocelot, port, dp->lag_tx_enabled); 897 898 return 0; 899 } 900 901 static int felix_vlan_prepare(struct dsa_switch *ds, int port, 902 const struct switchdev_obj_port_vlan *vlan, 903 struct netlink_ext_ack *extack) 904 { 905 struct ocelot *ocelot = ds->priv; 906 u16 flags = vlan->flags; 907 908 /* Ocelot switches copy frames as-is to the CPU, so the flags: 909 * egress-untagged or not, pvid or not, make no difference. This 910 * behavior is already better than what DSA just tries to approximate 911 * when it installs the VLAN with the same flags on the CPU port. 912 * Just accept any configuration, and don't let ocelot deny installing 913 * multiple native VLANs on the NPI port, because the switch doesn't 914 * look at the port tag settings towards the NPI interface anyway. 915 */ 916 if (port == ocelot->npi) 917 return 0; 918 919 return ocelot_vlan_prepare(ocelot, port, vlan->vid, 920 flags & BRIDGE_VLAN_INFO_PVID, 921 flags & BRIDGE_VLAN_INFO_UNTAGGED, 922 extack); 923 } 924 925 static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 926 struct netlink_ext_ack *extack) 927 { 928 struct ocelot *ocelot = ds->priv; 929 930 return ocelot_port_vlan_filtering(ocelot, port, enabled, extack); 931 } 932 933 static int felix_vlan_add(struct dsa_switch *ds, int port, 934 const struct switchdev_obj_port_vlan *vlan, 935 struct netlink_ext_ack *extack) 936 { 937 struct ocelot *ocelot = ds->priv; 938 u16 flags = vlan->flags; 939 int err; 940 941 err = felix_vlan_prepare(ds, port, vlan, extack); 942 if (err) 943 return err; 944 945 return ocelot_vlan_add(ocelot, port, vlan->vid, 946 flags & BRIDGE_VLAN_INFO_PVID, 947 flags & BRIDGE_VLAN_INFO_UNTAGGED); 948 } 949 950 static int felix_vlan_del(struct dsa_switch *ds, int port, 951 const struct switchdev_obj_port_vlan *vlan) 952 { 953 struct ocelot *ocelot = ds->priv; 954 955 return ocelot_vlan_del(ocelot, port, vlan->vid); 956 } 957 958 static void felix_phylink_get_caps(struct dsa_switch *ds, int port, 959 struct phylink_config *config) 960 { 961 struct ocelot *ocelot = ds->priv; 962 963 /* This driver does not make use of the speed, duplex, pause or the 964 * advertisement in its mac_config, so it is safe to mark this driver 965 * as non-legacy. 966 */ 967 config->legacy_pre_march2020 = false; 968 969 __set_bit(ocelot->ports[port]->phy_mode, 970 config->supported_interfaces); 971 } 972 973 static void felix_phylink_validate(struct dsa_switch *ds, int port, 974 unsigned long *supported, 975 struct phylink_link_state *state) 976 { 977 struct ocelot *ocelot = ds->priv; 978 struct felix *felix = ocelot_to_felix(ocelot); 979 980 if (felix->info->phylink_validate) 981 felix->info->phylink_validate(ocelot, port, supported, state); 982 } 983 984 static struct phylink_pcs *felix_phylink_mac_select_pcs(struct dsa_switch *ds, 985 int port, 986 phy_interface_t iface) 987 { 988 struct ocelot *ocelot = ds->priv; 989 struct felix *felix = ocelot_to_felix(ocelot); 990 struct phylink_pcs *pcs = NULL; 991 992 if (felix->pcs && felix->pcs[port]) 993 pcs = felix->pcs[port]; 994 995 return pcs; 996 } 997 998 static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, 999 unsigned int link_an_mode, 1000 phy_interface_t interface) 1001 { 1002 struct ocelot *ocelot = ds->priv; 1003 1004 ocelot_phylink_mac_link_down(ocelot, port, link_an_mode, interface, 1005 FELIX_MAC_QUIRKS); 1006 } 1007 1008 static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, 1009 unsigned int link_an_mode, 1010 phy_interface_t interface, 1011 struct phy_device *phydev, 1012 int speed, int duplex, 1013 bool tx_pause, bool rx_pause) 1014 { 1015 struct ocelot *ocelot = ds->priv; 1016 struct felix *felix = ocelot_to_felix(ocelot); 1017 1018 ocelot_phylink_mac_link_up(ocelot, port, phydev, link_an_mode, 1019 interface, speed, duplex, tx_pause, rx_pause, 1020 FELIX_MAC_QUIRKS); 1021 1022 if (felix->info->port_sched_speed_set) 1023 felix->info->port_sched_speed_set(ocelot, port, speed); 1024 } 1025 1026 static void felix_port_qos_map_init(struct ocelot *ocelot, int port) 1027 { 1028 int i; 1029 1030 ocelot_rmw_gix(ocelot, 1031 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 1032 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 1033 ANA_PORT_QOS_CFG, 1034 port); 1035 1036 for (i = 0; i < OCELOT_NUM_TC * 2; i++) { 1037 ocelot_rmw_ix(ocelot, 1038 (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) | 1039 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i), 1040 ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL | 1041 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M, 1042 ANA_PORT_PCP_DEI_MAP, 1043 port, i); 1044 } 1045 } 1046 1047 static void felix_get_strings(struct dsa_switch *ds, int port, 1048 u32 stringset, u8 *data) 1049 { 1050 struct ocelot *ocelot = ds->priv; 1051 1052 return ocelot_get_strings(ocelot, port, stringset, data); 1053 } 1054 1055 static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 1056 { 1057 struct ocelot *ocelot = ds->priv; 1058 1059 ocelot_get_ethtool_stats(ocelot, port, data); 1060 } 1061 1062 static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset) 1063 { 1064 struct ocelot *ocelot = ds->priv; 1065 1066 return ocelot_get_sset_count(ocelot, port, sset); 1067 } 1068 1069 static int felix_get_ts_info(struct dsa_switch *ds, int port, 1070 struct ethtool_ts_info *info) 1071 { 1072 struct ocelot *ocelot = ds->priv; 1073 1074 return ocelot_get_ts_info(ocelot, port, info); 1075 } 1076 1077 static const u32 felix_phy_match_table[PHY_INTERFACE_MODE_MAX] = { 1078 [PHY_INTERFACE_MODE_INTERNAL] = OCELOT_PORT_MODE_INTERNAL, 1079 [PHY_INTERFACE_MODE_SGMII] = OCELOT_PORT_MODE_SGMII, 1080 [PHY_INTERFACE_MODE_QSGMII] = OCELOT_PORT_MODE_QSGMII, 1081 [PHY_INTERFACE_MODE_USXGMII] = OCELOT_PORT_MODE_USXGMII, 1082 [PHY_INTERFACE_MODE_2500BASEX] = OCELOT_PORT_MODE_2500BASEX, 1083 }; 1084 1085 static int felix_validate_phy_mode(struct felix *felix, int port, 1086 phy_interface_t phy_mode) 1087 { 1088 u32 modes = felix->info->port_modes[port]; 1089 1090 if (felix_phy_match_table[phy_mode] & modes) 1091 return 0; 1092 return -EOPNOTSUPP; 1093 } 1094 1095 static int felix_parse_ports_node(struct felix *felix, 1096 struct device_node *ports_node, 1097 phy_interface_t *port_phy_modes) 1098 { 1099 struct device *dev = felix->ocelot.dev; 1100 struct device_node *child; 1101 1102 for_each_available_child_of_node(ports_node, child) { 1103 phy_interface_t phy_mode; 1104 u32 port; 1105 int err; 1106 1107 /* Get switch port number from DT */ 1108 if (of_property_read_u32(child, "reg", &port) < 0) { 1109 dev_err(dev, "Port number not defined in device tree " 1110 "(property \"reg\")\n"); 1111 of_node_put(child); 1112 return -ENODEV; 1113 } 1114 1115 /* Get PHY mode from DT */ 1116 err = of_get_phy_mode(child, &phy_mode); 1117 if (err) { 1118 dev_err(dev, "Failed to read phy-mode or " 1119 "phy-interface-type property for port %d\n", 1120 port); 1121 of_node_put(child); 1122 return -ENODEV; 1123 } 1124 1125 err = felix_validate_phy_mode(felix, port, phy_mode); 1126 if (err < 0) { 1127 dev_err(dev, "Unsupported PHY mode %s on port %d\n", 1128 phy_modes(phy_mode), port); 1129 of_node_put(child); 1130 return err; 1131 } 1132 1133 port_phy_modes[port] = phy_mode; 1134 } 1135 1136 return 0; 1137 } 1138 1139 static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes) 1140 { 1141 struct device *dev = felix->ocelot.dev; 1142 struct device_node *switch_node; 1143 struct device_node *ports_node; 1144 int err; 1145 1146 switch_node = dev->of_node; 1147 1148 ports_node = of_get_child_by_name(switch_node, "ports"); 1149 if (!ports_node) 1150 ports_node = of_get_child_by_name(switch_node, "ethernet-ports"); 1151 if (!ports_node) { 1152 dev_err(dev, "Incorrect bindings: absent \"ports\" or \"ethernet-ports\" node\n"); 1153 return -ENODEV; 1154 } 1155 1156 err = felix_parse_ports_node(felix, ports_node, port_phy_modes); 1157 of_node_put(ports_node); 1158 1159 return err; 1160 } 1161 1162 static int felix_init_structs(struct felix *felix, int num_phys_ports) 1163 { 1164 struct ocelot *ocelot = &felix->ocelot; 1165 phy_interface_t *port_phy_modes; 1166 struct resource res; 1167 int port, i, err; 1168 1169 ocelot->num_phys_ports = num_phys_ports; 1170 ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports, 1171 sizeof(struct ocelot_port *), GFP_KERNEL); 1172 if (!ocelot->ports) 1173 return -ENOMEM; 1174 1175 ocelot->map = felix->info->map; 1176 ocelot->stats_layout = felix->info->stats_layout; 1177 ocelot->num_stats = felix->info->num_stats; 1178 ocelot->num_mact_rows = felix->info->num_mact_rows; 1179 ocelot->vcap = felix->info->vcap; 1180 ocelot->vcap_pol.base = felix->info->vcap_pol_base; 1181 ocelot->vcap_pol.max = felix->info->vcap_pol_max; 1182 ocelot->vcap_pol.base2 = felix->info->vcap_pol_base2; 1183 ocelot->vcap_pol.max2 = felix->info->vcap_pol_max2; 1184 ocelot->ops = felix->info->ops; 1185 ocelot->npi_inj_prefix = OCELOT_TAG_PREFIX_SHORT; 1186 ocelot->npi_xtr_prefix = OCELOT_TAG_PREFIX_SHORT; 1187 ocelot->devlink = felix->ds->devlink; 1188 1189 port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t), 1190 GFP_KERNEL); 1191 if (!port_phy_modes) 1192 return -ENOMEM; 1193 1194 err = felix_parse_dt(felix, port_phy_modes); 1195 if (err) { 1196 kfree(port_phy_modes); 1197 return err; 1198 } 1199 1200 for (i = 0; i < TARGET_MAX; i++) { 1201 struct regmap *target; 1202 1203 if (!felix->info->target_io_res[i].name) 1204 continue; 1205 1206 memcpy(&res, &felix->info->target_io_res[i], sizeof(res)); 1207 res.flags = IORESOURCE_MEM; 1208 res.start += felix->switch_base; 1209 res.end += felix->switch_base; 1210 1211 target = felix->info->init_regmap(ocelot, &res); 1212 if (IS_ERR(target)) { 1213 dev_err(ocelot->dev, 1214 "Failed to map device memory space\n"); 1215 kfree(port_phy_modes); 1216 return PTR_ERR(target); 1217 } 1218 1219 ocelot->targets[i] = target; 1220 } 1221 1222 err = ocelot_regfields_init(ocelot, felix->info->regfields); 1223 if (err) { 1224 dev_err(ocelot->dev, "failed to init reg fields map\n"); 1225 kfree(port_phy_modes); 1226 return err; 1227 } 1228 1229 for (port = 0; port < num_phys_ports; port++) { 1230 struct ocelot_port *ocelot_port; 1231 struct regmap *target; 1232 1233 ocelot_port = devm_kzalloc(ocelot->dev, 1234 sizeof(struct ocelot_port), 1235 GFP_KERNEL); 1236 if (!ocelot_port) { 1237 dev_err(ocelot->dev, 1238 "failed to allocate port memory\n"); 1239 kfree(port_phy_modes); 1240 return -ENOMEM; 1241 } 1242 1243 memcpy(&res, &felix->info->port_io_res[port], sizeof(res)); 1244 res.flags = IORESOURCE_MEM; 1245 res.start += felix->switch_base; 1246 res.end += felix->switch_base; 1247 1248 target = felix->info->init_regmap(ocelot, &res); 1249 if (IS_ERR(target)) { 1250 dev_err(ocelot->dev, 1251 "Failed to map memory space for port %d\n", 1252 port); 1253 kfree(port_phy_modes); 1254 return PTR_ERR(target); 1255 } 1256 1257 ocelot_port->phy_mode = port_phy_modes[port]; 1258 ocelot_port->ocelot = ocelot; 1259 ocelot_port->target = target; 1260 ocelot->ports[port] = ocelot_port; 1261 } 1262 1263 kfree(port_phy_modes); 1264 1265 if (felix->info->mdio_bus_alloc) { 1266 err = felix->info->mdio_bus_alloc(ocelot); 1267 if (err < 0) 1268 return err; 1269 } 1270 1271 return 0; 1272 } 1273 1274 static void ocelot_port_purge_txtstamp_skb(struct ocelot *ocelot, int port, 1275 struct sk_buff *skb) 1276 { 1277 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1278 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone; 1279 struct sk_buff *skb_match = NULL, *skb_tmp; 1280 unsigned long flags; 1281 1282 if (!clone) 1283 return; 1284 1285 spin_lock_irqsave(&ocelot_port->tx_skbs.lock, flags); 1286 1287 skb_queue_walk_safe(&ocelot_port->tx_skbs, skb, skb_tmp) { 1288 if (skb != clone) 1289 continue; 1290 __skb_unlink(skb, &ocelot_port->tx_skbs); 1291 skb_match = skb; 1292 break; 1293 } 1294 1295 spin_unlock_irqrestore(&ocelot_port->tx_skbs.lock, flags); 1296 1297 WARN_ONCE(!skb_match, 1298 "Could not find skb clone in TX timestamping list\n"); 1299 } 1300 1301 #define work_to_xmit_work(w) \ 1302 container_of((w), struct felix_deferred_xmit_work, work) 1303 1304 static void felix_port_deferred_xmit(struct kthread_work *work) 1305 { 1306 struct felix_deferred_xmit_work *xmit_work = work_to_xmit_work(work); 1307 struct dsa_switch *ds = xmit_work->dp->ds; 1308 struct sk_buff *skb = xmit_work->skb; 1309 u32 rew_op = ocelot_ptp_rew_op(skb); 1310 struct ocelot *ocelot = ds->priv; 1311 int port = xmit_work->dp->index; 1312 int retries = 10; 1313 1314 do { 1315 if (ocelot_can_inject(ocelot, 0)) 1316 break; 1317 1318 cpu_relax(); 1319 } while (--retries); 1320 1321 if (!retries) { 1322 dev_err(ocelot->dev, "port %d failed to inject skb\n", 1323 port); 1324 ocelot_port_purge_txtstamp_skb(ocelot, port, skb); 1325 kfree_skb(skb); 1326 return; 1327 } 1328 1329 ocelot_port_inject_frame(ocelot, port, 0, rew_op, skb); 1330 1331 consume_skb(skb); 1332 kfree(xmit_work); 1333 } 1334 1335 static int felix_connect_tag_protocol(struct dsa_switch *ds, 1336 enum dsa_tag_protocol proto) 1337 { 1338 struct ocelot_8021q_tagger_data *tagger_data; 1339 1340 switch (proto) { 1341 case DSA_TAG_PROTO_OCELOT_8021Q: 1342 tagger_data = ocelot_8021q_tagger_data(ds); 1343 tagger_data->xmit_work_fn = felix_port_deferred_xmit; 1344 return 0; 1345 case DSA_TAG_PROTO_OCELOT: 1346 case DSA_TAG_PROTO_SEVILLE: 1347 return 0; 1348 default: 1349 return -EPROTONOSUPPORT; 1350 } 1351 } 1352 1353 /* Hardware initialization done here so that we can allocate structures with 1354 * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing 1355 * us to allocate structures twice (leak memory) and map PCI memory twice 1356 * (which will not work). 1357 */ 1358 static int felix_setup(struct dsa_switch *ds) 1359 { 1360 struct ocelot *ocelot = ds->priv; 1361 struct felix *felix = ocelot_to_felix(ocelot); 1362 unsigned long cpu_flood; 1363 struct dsa_port *dp; 1364 int err; 1365 1366 err = felix_init_structs(felix, ds->num_ports); 1367 if (err) 1368 return err; 1369 1370 err = ocelot_init(ocelot); 1371 if (err) 1372 goto out_mdiobus_free; 1373 1374 if (ocelot->ptp) { 1375 err = ocelot_init_timestamp(ocelot, felix->info->ptp_caps); 1376 if (err) { 1377 dev_err(ocelot->dev, 1378 "Timestamp initialization failed\n"); 1379 ocelot->ptp = 0; 1380 } 1381 } 1382 1383 dsa_switch_for_each_available_port(dp, ds) { 1384 ocelot_init_port(ocelot, dp->index); 1385 1386 /* Set the default QoS Classification based on PCP and DEI 1387 * bits of vlan tag. 1388 */ 1389 felix_port_qos_map_init(ocelot, dp->index); 1390 } 1391 1392 err = ocelot_devlink_sb_register(ocelot); 1393 if (err) 1394 goto out_deinit_ports; 1395 1396 dsa_switch_for_each_cpu_port(dp, ds) { 1397 /* The initial tag protocol is NPI which always returns 0, so 1398 * there's no real point in checking for errors. 1399 */ 1400 felix_set_tag_protocol(ds, dp->index, felix->tag_proto); 1401 1402 /* Start off with flooding disabled towards the NPI port 1403 * (actually CPU port module). 1404 */ 1405 cpu_flood = ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)); 1406 ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_UC); 1407 ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_MC); 1408 1409 break; 1410 } 1411 1412 ds->mtu_enforcement_ingress = true; 1413 ds->assisted_learning_on_cpu_port = true; 1414 ds->fdb_isolation = true; 1415 ds->max_num_bridges = ds->num_ports; 1416 1417 return 0; 1418 1419 out_deinit_ports: 1420 dsa_switch_for_each_available_port(dp, ds) 1421 ocelot_deinit_port(ocelot, dp->index); 1422 1423 ocelot_deinit_timestamp(ocelot); 1424 ocelot_deinit(ocelot); 1425 1426 out_mdiobus_free: 1427 if (felix->info->mdio_bus_free) 1428 felix->info->mdio_bus_free(ocelot); 1429 1430 return err; 1431 } 1432 1433 static void felix_teardown(struct dsa_switch *ds) 1434 { 1435 struct ocelot *ocelot = ds->priv; 1436 struct felix *felix = ocelot_to_felix(ocelot); 1437 struct dsa_port *dp; 1438 1439 dsa_switch_for_each_cpu_port(dp, ds) { 1440 felix_del_tag_protocol(ds, dp->index, felix->tag_proto); 1441 break; 1442 } 1443 1444 dsa_switch_for_each_available_port(dp, ds) 1445 ocelot_deinit_port(ocelot, dp->index); 1446 1447 ocelot_devlink_sb_unregister(ocelot); 1448 ocelot_deinit_timestamp(ocelot); 1449 ocelot_deinit(ocelot); 1450 1451 if (felix->info->mdio_bus_free) 1452 felix->info->mdio_bus_free(ocelot); 1453 } 1454 1455 static int felix_hwtstamp_get(struct dsa_switch *ds, int port, 1456 struct ifreq *ifr) 1457 { 1458 struct ocelot *ocelot = ds->priv; 1459 1460 return ocelot_hwstamp_get(ocelot, port, ifr); 1461 } 1462 1463 static int felix_hwtstamp_set(struct dsa_switch *ds, int port, 1464 struct ifreq *ifr) 1465 { 1466 struct ocelot *ocelot = ds->priv; 1467 struct felix *felix = ocelot_to_felix(ocelot); 1468 bool using_tag_8021q; 1469 int err; 1470 1471 err = ocelot_hwstamp_set(ocelot, port, ifr); 1472 if (err) 1473 return err; 1474 1475 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q; 1476 1477 return felix_update_trapping_destinations(ds, using_tag_8021q); 1478 } 1479 1480 static bool felix_check_xtr_pkt(struct ocelot *ocelot) 1481 { 1482 struct felix *felix = ocelot_to_felix(ocelot); 1483 int err = 0, grp = 0; 1484 1485 if (felix->tag_proto != DSA_TAG_PROTO_OCELOT_8021Q) 1486 return false; 1487 1488 if (!felix->info->quirk_no_xtr_irq) 1489 return false; 1490 1491 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) { 1492 struct sk_buff *skb; 1493 unsigned int type; 1494 1495 err = ocelot_xtr_poll_frame(ocelot, grp, &skb); 1496 if (err) 1497 goto out; 1498 1499 /* We trap to the CPU port module all PTP frames, but 1500 * felix_rxtstamp() only gets called for event frames. 1501 * So we need to avoid sending duplicate general 1502 * message frames by running a second BPF classifier 1503 * here and dropping those. 1504 */ 1505 __skb_push(skb, ETH_HLEN); 1506 1507 type = ptp_classify_raw(skb); 1508 1509 __skb_pull(skb, ETH_HLEN); 1510 1511 if (type == PTP_CLASS_NONE) { 1512 kfree_skb(skb); 1513 continue; 1514 } 1515 1516 netif_rx(skb); 1517 } 1518 1519 out: 1520 if (err < 0) { 1521 dev_err_ratelimited(ocelot->dev, 1522 "Error during packet extraction: %pe\n", 1523 ERR_PTR(err)); 1524 ocelot_drain_cpu_queue(ocelot, 0); 1525 } 1526 1527 return true; 1528 } 1529 1530 static bool felix_rxtstamp(struct dsa_switch *ds, int port, 1531 struct sk_buff *skb, unsigned int type) 1532 { 1533 u32 tstamp_lo = OCELOT_SKB_CB(skb)->tstamp_lo; 1534 struct skb_shared_hwtstamps *shhwtstamps; 1535 struct ocelot *ocelot = ds->priv; 1536 struct timespec64 ts; 1537 u32 tstamp_hi; 1538 u64 tstamp; 1539 1540 /* If the "no XTR IRQ" workaround is in use, tell DSA to defer this skb 1541 * for RX timestamping. Then free it, and poll for its copy through 1542 * MMIO in the CPU port module, and inject that into the stack from 1543 * ocelot_xtr_poll(). 1544 */ 1545 if (felix_check_xtr_pkt(ocelot)) { 1546 kfree_skb(skb); 1547 return true; 1548 } 1549 1550 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1551 tstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 1552 1553 tstamp_hi = tstamp >> 32; 1554 if ((tstamp & 0xffffffff) < tstamp_lo) 1555 tstamp_hi--; 1556 1557 tstamp = ((u64)tstamp_hi << 32) | tstamp_lo; 1558 1559 shhwtstamps = skb_hwtstamps(skb); 1560 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1561 shhwtstamps->hwtstamp = tstamp; 1562 return false; 1563 } 1564 1565 static void felix_txtstamp(struct dsa_switch *ds, int port, 1566 struct sk_buff *skb) 1567 { 1568 struct ocelot *ocelot = ds->priv; 1569 struct sk_buff *clone = NULL; 1570 1571 if (!ocelot->ptp) 1572 return; 1573 1574 if (ocelot_port_txtstamp_request(ocelot, port, skb, &clone)) { 1575 dev_err_ratelimited(ds->dev, 1576 "port %d delivering skb without TX timestamp\n", 1577 port); 1578 return; 1579 } 1580 1581 if (clone) 1582 OCELOT_SKB_CB(skb)->clone = clone; 1583 } 1584 1585 static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1586 { 1587 struct ocelot *ocelot = ds->priv; 1588 1589 ocelot_port_set_maxlen(ocelot, port, new_mtu); 1590 1591 return 0; 1592 } 1593 1594 static int felix_get_max_mtu(struct dsa_switch *ds, int port) 1595 { 1596 struct ocelot *ocelot = ds->priv; 1597 1598 return ocelot_get_max_mtu(ocelot, port); 1599 } 1600 1601 static int felix_cls_flower_add(struct dsa_switch *ds, int port, 1602 struct flow_cls_offload *cls, bool ingress) 1603 { 1604 struct ocelot *ocelot = ds->priv; 1605 struct felix *felix = ocelot_to_felix(ocelot); 1606 bool using_tag_8021q; 1607 int err; 1608 1609 err = ocelot_cls_flower_replace(ocelot, port, cls, ingress); 1610 if (err) 1611 return err; 1612 1613 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q; 1614 1615 return felix_update_trapping_destinations(ds, using_tag_8021q); 1616 } 1617 1618 static int felix_cls_flower_del(struct dsa_switch *ds, int port, 1619 struct flow_cls_offload *cls, bool ingress) 1620 { 1621 struct ocelot *ocelot = ds->priv; 1622 1623 return ocelot_cls_flower_destroy(ocelot, port, cls, ingress); 1624 } 1625 1626 static int felix_cls_flower_stats(struct dsa_switch *ds, int port, 1627 struct flow_cls_offload *cls, bool ingress) 1628 { 1629 struct ocelot *ocelot = ds->priv; 1630 1631 return ocelot_cls_flower_stats(ocelot, port, cls, ingress); 1632 } 1633 1634 static int felix_port_policer_add(struct dsa_switch *ds, int port, 1635 struct dsa_mall_policer_tc_entry *policer) 1636 { 1637 struct ocelot *ocelot = ds->priv; 1638 struct ocelot_policer pol = { 1639 .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8, 1640 .burst = policer->burst, 1641 }; 1642 1643 return ocelot_port_policer_add(ocelot, port, &pol); 1644 } 1645 1646 static void felix_port_policer_del(struct dsa_switch *ds, int port) 1647 { 1648 struct ocelot *ocelot = ds->priv; 1649 1650 ocelot_port_policer_del(ocelot, port); 1651 } 1652 1653 static int felix_port_mirror_add(struct dsa_switch *ds, int port, 1654 struct dsa_mall_mirror_tc_entry *mirror, 1655 bool ingress, struct netlink_ext_ack *extack) 1656 { 1657 struct ocelot *ocelot = ds->priv; 1658 1659 return ocelot_port_mirror_add(ocelot, port, mirror->to_local_port, 1660 ingress, extack); 1661 } 1662 1663 static void felix_port_mirror_del(struct dsa_switch *ds, int port, 1664 struct dsa_mall_mirror_tc_entry *mirror) 1665 { 1666 struct ocelot *ocelot = ds->priv; 1667 1668 ocelot_port_mirror_del(ocelot, port, mirror->ingress); 1669 } 1670 1671 static int felix_port_setup_tc(struct dsa_switch *ds, int port, 1672 enum tc_setup_type type, 1673 void *type_data) 1674 { 1675 struct ocelot *ocelot = ds->priv; 1676 struct felix *felix = ocelot_to_felix(ocelot); 1677 1678 if (felix->info->port_setup_tc) 1679 return felix->info->port_setup_tc(ds, port, type, type_data); 1680 else 1681 return -EOPNOTSUPP; 1682 } 1683 1684 static int felix_sb_pool_get(struct dsa_switch *ds, unsigned int sb_index, 1685 u16 pool_index, 1686 struct devlink_sb_pool_info *pool_info) 1687 { 1688 struct ocelot *ocelot = ds->priv; 1689 1690 return ocelot_sb_pool_get(ocelot, sb_index, pool_index, pool_info); 1691 } 1692 1693 static int felix_sb_pool_set(struct dsa_switch *ds, unsigned int sb_index, 1694 u16 pool_index, u32 size, 1695 enum devlink_sb_threshold_type threshold_type, 1696 struct netlink_ext_ack *extack) 1697 { 1698 struct ocelot *ocelot = ds->priv; 1699 1700 return ocelot_sb_pool_set(ocelot, sb_index, pool_index, size, 1701 threshold_type, extack); 1702 } 1703 1704 static int felix_sb_port_pool_get(struct dsa_switch *ds, int port, 1705 unsigned int sb_index, u16 pool_index, 1706 u32 *p_threshold) 1707 { 1708 struct ocelot *ocelot = ds->priv; 1709 1710 return ocelot_sb_port_pool_get(ocelot, port, sb_index, pool_index, 1711 p_threshold); 1712 } 1713 1714 static int felix_sb_port_pool_set(struct dsa_switch *ds, int port, 1715 unsigned int sb_index, u16 pool_index, 1716 u32 threshold, struct netlink_ext_ack *extack) 1717 { 1718 struct ocelot *ocelot = ds->priv; 1719 1720 return ocelot_sb_port_pool_set(ocelot, port, sb_index, pool_index, 1721 threshold, extack); 1722 } 1723 1724 static int felix_sb_tc_pool_bind_get(struct dsa_switch *ds, int port, 1725 unsigned int sb_index, u16 tc_index, 1726 enum devlink_sb_pool_type pool_type, 1727 u16 *p_pool_index, u32 *p_threshold) 1728 { 1729 struct ocelot *ocelot = ds->priv; 1730 1731 return ocelot_sb_tc_pool_bind_get(ocelot, port, sb_index, tc_index, 1732 pool_type, p_pool_index, 1733 p_threshold); 1734 } 1735 1736 static int felix_sb_tc_pool_bind_set(struct dsa_switch *ds, int port, 1737 unsigned int sb_index, u16 tc_index, 1738 enum devlink_sb_pool_type pool_type, 1739 u16 pool_index, u32 threshold, 1740 struct netlink_ext_ack *extack) 1741 { 1742 struct ocelot *ocelot = ds->priv; 1743 1744 return ocelot_sb_tc_pool_bind_set(ocelot, port, sb_index, tc_index, 1745 pool_type, pool_index, threshold, 1746 extack); 1747 } 1748 1749 static int felix_sb_occ_snapshot(struct dsa_switch *ds, 1750 unsigned int sb_index) 1751 { 1752 struct ocelot *ocelot = ds->priv; 1753 1754 return ocelot_sb_occ_snapshot(ocelot, sb_index); 1755 } 1756 1757 static int felix_sb_occ_max_clear(struct dsa_switch *ds, 1758 unsigned int sb_index) 1759 { 1760 struct ocelot *ocelot = ds->priv; 1761 1762 return ocelot_sb_occ_max_clear(ocelot, sb_index); 1763 } 1764 1765 static int felix_sb_occ_port_pool_get(struct dsa_switch *ds, int port, 1766 unsigned int sb_index, u16 pool_index, 1767 u32 *p_cur, u32 *p_max) 1768 { 1769 struct ocelot *ocelot = ds->priv; 1770 1771 return ocelot_sb_occ_port_pool_get(ocelot, port, sb_index, pool_index, 1772 p_cur, p_max); 1773 } 1774 1775 static int felix_sb_occ_tc_port_bind_get(struct dsa_switch *ds, int port, 1776 unsigned int sb_index, u16 tc_index, 1777 enum devlink_sb_pool_type pool_type, 1778 u32 *p_cur, u32 *p_max) 1779 { 1780 struct ocelot *ocelot = ds->priv; 1781 1782 return ocelot_sb_occ_tc_port_bind_get(ocelot, port, sb_index, tc_index, 1783 pool_type, p_cur, p_max); 1784 } 1785 1786 static int felix_mrp_add(struct dsa_switch *ds, int port, 1787 const struct switchdev_obj_mrp *mrp) 1788 { 1789 struct ocelot *ocelot = ds->priv; 1790 1791 return ocelot_mrp_add(ocelot, port, mrp); 1792 } 1793 1794 static int felix_mrp_del(struct dsa_switch *ds, int port, 1795 const struct switchdev_obj_mrp *mrp) 1796 { 1797 struct ocelot *ocelot = ds->priv; 1798 1799 return ocelot_mrp_add(ocelot, port, mrp); 1800 } 1801 1802 static int 1803 felix_mrp_add_ring_role(struct dsa_switch *ds, int port, 1804 const struct switchdev_obj_ring_role_mrp *mrp) 1805 { 1806 struct ocelot *ocelot = ds->priv; 1807 1808 return ocelot_mrp_add_ring_role(ocelot, port, mrp); 1809 } 1810 1811 static int 1812 felix_mrp_del_ring_role(struct dsa_switch *ds, int port, 1813 const struct switchdev_obj_ring_role_mrp *mrp) 1814 { 1815 struct ocelot *ocelot = ds->priv; 1816 1817 return ocelot_mrp_del_ring_role(ocelot, port, mrp); 1818 } 1819 1820 static int felix_port_get_default_prio(struct dsa_switch *ds, int port) 1821 { 1822 struct ocelot *ocelot = ds->priv; 1823 1824 return ocelot_port_get_default_prio(ocelot, port); 1825 } 1826 1827 static int felix_port_set_default_prio(struct dsa_switch *ds, int port, 1828 u8 prio) 1829 { 1830 struct ocelot *ocelot = ds->priv; 1831 1832 return ocelot_port_set_default_prio(ocelot, port, prio); 1833 } 1834 1835 static int felix_port_get_dscp_prio(struct dsa_switch *ds, int port, u8 dscp) 1836 { 1837 struct ocelot *ocelot = ds->priv; 1838 1839 return ocelot_port_get_dscp_prio(ocelot, port, dscp); 1840 } 1841 1842 static int felix_port_add_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, 1843 u8 prio) 1844 { 1845 struct ocelot *ocelot = ds->priv; 1846 1847 return ocelot_port_add_dscp_prio(ocelot, port, dscp, prio); 1848 } 1849 1850 static int felix_port_del_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, 1851 u8 prio) 1852 { 1853 struct ocelot *ocelot = ds->priv; 1854 1855 return ocelot_port_del_dscp_prio(ocelot, port, dscp, prio); 1856 } 1857 1858 const struct dsa_switch_ops felix_switch_ops = { 1859 .get_tag_protocol = felix_get_tag_protocol, 1860 .change_tag_protocol = felix_change_tag_protocol, 1861 .connect_tag_protocol = felix_connect_tag_protocol, 1862 .setup = felix_setup, 1863 .teardown = felix_teardown, 1864 .set_ageing_time = felix_set_ageing_time, 1865 .get_strings = felix_get_strings, 1866 .get_ethtool_stats = felix_get_ethtool_stats, 1867 .get_sset_count = felix_get_sset_count, 1868 .get_ts_info = felix_get_ts_info, 1869 .phylink_get_caps = felix_phylink_get_caps, 1870 .phylink_validate = felix_phylink_validate, 1871 .phylink_mac_select_pcs = felix_phylink_mac_select_pcs, 1872 .phylink_mac_link_down = felix_phylink_mac_link_down, 1873 .phylink_mac_link_up = felix_phylink_mac_link_up, 1874 .port_fast_age = felix_port_fast_age, 1875 .port_fdb_dump = felix_fdb_dump, 1876 .port_fdb_add = felix_fdb_add, 1877 .port_fdb_del = felix_fdb_del, 1878 .lag_fdb_add = felix_lag_fdb_add, 1879 .lag_fdb_del = felix_lag_fdb_del, 1880 .port_mdb_add = felix_mdb_add, 1881 .port_mdb_del = felix_mdb_del, 1882 .port_pre_bridge_flags = felix_pre_bridge_flags, 1883 .port_bridge_flags = felix_bridge_flags, 1884 .port_bridge_join = felix_bridge_join, 1885 .port_bridge_leave = felix_bridge_leave, 1886 .port_lag_join = felix_lag_join, 1887 .port_lag_leave = felix_lag_leave, 1888 .port_lag_change = felix_lag_change, 1889 .port_stp_state_set = felix_bridge_stp_state_set, 1890 .port_vlan_filtering = felix_vlan_filtering, 1891 .port_vlan_add = felix_vlan_add, 1892 .port_vlan_del = felix_vlan_del, 1893 .port_hwtstamp_get = felix_hwtstamp_get, 1894 .port_hwtstamp_set = felix_hwtstamp_set, 1895 .port_rxtstamp = felix_rxtstamp, 1896 .port_txtstamp = felix_txtstamp, 1897 .port_change_mtu = felix_change_mtu, 1898 .port_max_mtu = felix_get_max_mtu, 1899 .port_policer_add = felix_port_policer_add, 1900 .port_policer_del = felix_port_policer_del, 1901 .port_mirror_add = felix_port_mirror_add, 1902 .port_mirror_del = felix_port_mirror_del, 1903 .cls_flower_add = felix_cls_flower_add, 1904 .cls_flower_del = felix_cls_flower_del, 1905 .cls_flower_stats = felix_cls_flower_stats, 1906 .port_setup_tc = felix_port_setup_tc, 1907 .devlink_sb_pool_get = felix_sb_pool_get, 1908 .devlink_sb_pool_set = felix_sb_pool_set, 1909 .devlink_sb_port_pool_get = felix_sb_port_pool_get, 1910 .devlink_sb_port_pool_set = felix_sb_port_pool_set, 1911 .devlink_sb_tc_pool_bind_get = felix_sb_tc_pool_bind_get, 1912 .devlink_sb_tc_pool_bind_set = felix_sb_tc_pool_bind_set, 1913 .devlink_sb_occ_snapshot = felix_sb_occ_snapshot, 1914 .devlink_sb_occ_max_clear = felix_sb_occ_max_clear, 1915 .devlink_sb_occ_port_pool_get = felix_sb_occ_port_pool_get, 1916 .devlink_sb_occ_tc_port_bind_get= felix_sb_occ_tc_port_bind_get, 1917 .port_mrp_add = felix_mrp_add, 1918 .port_mrp_del = felix_mrp_del, 1919 .port_mrp_add_ring_role = felix_mrp_add_ring_role, 1920 .port_mrp_del_ring_role = felix_mrp_del_ring_role, 1921 .tag_8021q_vlan_add = felix_tag_8021q_vlan_add, 1922 .tag_8021q_vlan_del = felix_tag_8021q_vlan_del, 1923 .port_get_default_prio = felix_port_get_default_prio, 1924 .port_set_default_prio = felix_port_set_default_prio, 1925 .port_get_dscp_prio = felix_port_get_dscp_prio, 1926 .port_add_dscp_prio = felix_port_add_dscp_prio, 1927 .port_del_dscp_prio = felix_port_del_dscp_prio, 1928 }; 1929 1930 struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port) 1931 { 1932 struct felix *felix = ocelot_to_felix(ocelot); 1933 struct dsa_switch *ds = felix->ds; 1934 1935 if (!dsa_is_user_port(ds, port)) 1936 return NULL; 1937 1938 return dsa_to_port(ds, port)->slave; 1939 } 1940 1941 int felix_netdev_to_port(struct net_device *dev) 1942 { 1943 struct dsa_port *dp; 1944 1945 dp = dsa_port_from_netdev(dev); 1946 if (IS_ERR(dp)) 1947 return -EINVAL; 1948 1949 return dp->index; 1950 } 1951