1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2019-2021 NXP 3 * 4 * This is an umbrella module for all network switches that are 5 * register-compatible with Ocelot and that perform I/O to their host CPU 6 * through an NPI (Node Processor Interface) Ethernet port. 7 */ 8 #include <uapi/linux/if_bridge.h> 9 #include <soc/mscc/ocelot_vcap.h> 10 #include <soc/mscc/ocelot_qsys.h> 11 #include <soc/mscc/ocelot_sys.h> 12 #include <soc/mscc/ocelot_dev.h> 13 #include <soc/mscc/ocelot_ana.h> 14 #include <soc/mscc/ocelot_ptp.h> 15 #include <soc/mscc/ocelot.h> 16 #include <linux/dsa/8021q.h> 17 #include <linux/dsa/ocelot.h> 18 #include <linux/platform_device.h> 19 #include <linux/ptp_classify.h> 20 #include <linux/module.h> 21 #include <linux/of_net.h> 22 #include <linux/pci.h> 23 #include <linux/of.h> 24 #include <net/pkt_sched.h> 25 #include <net/dsa.h> 26 #include "felix.h" 27 28 /* Translate the DSA database API into the ocelot switch library API, 29 * which uses VID 0 for all ports that aren't part of a bridge, 30 * and expects the bridge_dev to be NULL in that case. 31 */ 32 static struct net_device *felix_classify_db(struct dsa_db db) 33 { 34 switch (db.type) { 35 case DSA_DB_PORT: 36 case DSA_DB_LAG: 37 return NULL; 38 case DSA_DB_BRIDGE: 39 return db.bridge.dev; 40 default: 41 return ERR_PTR(-EOPNOTSUPP); 42 } 43 } 44 45 /* Set up VCAP ES0 rules for pushing a tag_8021q VLAN towards the CPU such that 46 * the tagger can perform RX source port identification. 47 */ 48 static int felix_tag_8021q_vlan_add_rx(struct dsa_switch *ds, int port, 49 int upstream, u16 vid) 50 { 51 struct ocelot_vcap_filter *outer_tagging_rule; 52 struct ocelot *ocelot = ds->priv; 53 unsigned long cookie; 54 int key_length, err; 55 56 key_length = ocelot->vcap[VCAP_ES0].keys[VCAP_ES0_IGR_PORT].length; 57 58 outer_tagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), 59 GFP_KERNEL); 60 if (!outer_tagging_rule) 61 return -ENOMEM; 62 63 cookie = OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port, upstream); 64 65 outer_tagging_rule->key_type = OCELOT_VCAP_KEY_ANY; 66 outer_tagging_rule->prio = 1; 67 outer_tagging_rule->id.cookie = cookie; 68 outer_tagging_rule->id.tc_offload = false; 69 outer_tagging_rule->block_id = VCAP_ES0; 70 outer_tagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 71 outer_tagging_rule->lookup = 0; 72 outer_tagging_rule->ingress_port.value = port; 73 outer_tagging_rule->ingress_port.mask = GENMASK(key_length - 1, 0); 74 outer_tagging_rule->egress_port.value = upstream; 75 outer_tagging_rule->egress_port.mask = GENMASK(key_length - 1, 0); 76 outer_tagging_rule->action.push_outer_tag = OCELOT_ES0_TAG; 77 outer_tagging_rule->action.tag_a_tpid_sel = OCELOT_TAG_TPID_SEL_8021AD; 78 outer_tagging_rule->action.tag_a_vid_sel = 1; 79 outer_tagging_rule->action.vid_a_val = vid; 80 81 err = ocelot_vcap_filter_add(ocelot, outer_tagging_rule, NULL); 82 if (err) 83 kfree(outer_tagging_rule); 84 85 return err; 86 } 87 88 static int felix_tag_8021q_vlan_del_rx(struct dsa_switch *ds, int port, 89 int upstream, u16 vid) 90 { 91 struct ocelot_vcap_filter *outer_tagging_rule; 92 struct ocelot_vcap_block *block_vcap_es0; 93 struct ocelot *ocelot = ds->priv; 94 unsigned long cookie; 95 96 block_vcap_es0 = &ocelot->block[VCAP_ES0]; 97 cookie = OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port, upstream); 98 99 outer_tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_es0, 100 cookie, false); 101 if (!outer_tagging_rule) 102 return -ENOENT; 103 104 return ocelot_vcap_filter_del(ocelot, outer_tagging_rule); 105 } 106 107 /* Set up VCAP IS1 rules for stripping the tag_8021q VLAN on TX and VCAP IS2 108 * rules for steering those tagged packets towards the correct destination port 109 */ 110 static int felix_tag_8021q_vlan_add_tx(struct dsa_switch *ds, int port, 111 u16 vid) 112 { 113 struct ocelot_vcap_filter *untagging_rule, *redirect_rule; 114 unsigned long cpu_ports = dsa_cpu_ports(ds); 115 struct ocelot *ocelot = ds->priv; 116 unsigned long cookie; 117 int err; 118 119 untagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); 120 if (!untagging_rule) 121 return -ENOMEM; 122 123 redirect_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); 124 if (!redirect_rule) { 125 kfree(untagging_rule); 126 return -ENOMEM; 127 } 128 129 cookie = OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port); 130 131 untagging_rule->key_type = OCELOT_VCAP_KEY_ANY; 132 untagging_rule->ingress_port_mask = cpu_ports; 133 untagging_rule->vlan.vid.value = vid; 134 untagging_rule->vlan.vid.mask = VLAN_VID_MASK; 135 untagging_rule->prio = 1; 136 untagging_rule->id.cookie = cookie; 137 untagging_rule->id.tc_offload = false; 138 untagging_rule->block_id = VCAP_IS1; 139 untagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 140 untagging_rule->lookup = 0; 141 untagging_rule->action.vlan_pop_cnt_ena = true; 142 untagging_rule->action.vlan_pop_cnt = 1; 143 untagging_rule->action.pag_override_mask = 0xff; 144 untagging_rule->action.pag_val = port; 145 146 err = ocelot_vcap_filter_add(ocelot, untagging_rule, NULL); 147 if (err) { 148 kfree(untagging_rule); 149 kfree(redirect_rule); 150 return err; 151 } 152 153 cookie = OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port); 154 155 redirect_rule->key_type = OCELOT_VCAP_KEY_ANY; 156 redirect_rule->ingress_port_mask = cpu_ports; 157 redirect_rule->pag = port; 158 redirect_rule->prio = 1; 159 redirect_rule->id.cookie = cookie; 160 redirect_rule->id.tc_offload = false; 161 redirect_rule->block_id = VCAP_IS2; 162 redirect_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 163 redirect_rule->lookup = 0; 164 redirect_rule->action.mask_mode = OCELOT_MASK_MODE_REDIRECT; 165 redirect_rule->action.port_mask = BIT(port); 166 167 err = ocelot_vcap_filter_add(ocelot, redirect_rule, NULL); 168 if (err) { 169 ocelot_vcap_filter_del(ocelot, untagging_rule); 170 kfree(redirect_rule); 171 return err; 172 } 173 174 return 0; 175 } 176 177 static int felix_tag_8021q_vlan_del_tx(struct dsa_switch *ds, int port, u16 vid) 178 { 179 struct ocelot_vcap_filter *untagging_rule, *redirect_rule; 180 struct ocelot_vcap_block *block_vcap_is1; 181 struct ocelot_vcap_block *block_vcap_is2; 182 struct ocelot *ocelot = ds->priv; 183 unsigned long cookie; 184 int err; 185 186 block_vcap_is1 = &ocelot->block[VCAP_IS1]; 187 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 188 189 cookie = OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port); 190 untagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is1, 191 cookie, false); 192 if (!untagging_rule) 193 return -ENOENT; 194 195 err = ocelot_vcap_filter_del(ocelot, untagging_rule); 196 if (err) 197 return err; 198 199 cookie = OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port); 200 redirect_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, 201 cookie, false); 202 if (!redirect_rule) 203 return -ENOENT; 204 205 return ocelot_vcap_filter_del(ocelot, redirect_rule); 206 } 207 208 static int felix_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 209 u16 flags) 210 { 211 struct dsa_port *cpu_dp; 212 int err; 213 214 /* tag_8021q.c assumes we are implementing this via port VLAN 215 * membership, which we aren't. So we don't need to add any VCAP filter 216 * for the CPU port. 217 */ 218 if (!dsa_is_user_port(ds, port)) 219 return 0; 220 221 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 222 err = felix_tag_8021q_vlan_add_rx(ds, port, cpu_dp->index, vid); 223 if (err) 224 return err; 225 } 226 227 err = felix_tag_8021q_vlan_add_tx(ds, port, vid); 228 if (err) 229 goto add_tx_failed; 230 231 return 0; 232 233 add_tx_failed: 234 dsa_switch_for_each_cpu_port(cpu_dp, ds) 235 felix_tag_8021q_vlan_del_rx(ds, port, cpu_dp->index, vid); 236 237 return err; 238 } 239 240 static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 241 { 242 struct dsa_port *cpu_dp; 243 int err; 244 245 if (!dsa_is_user_port(ds, port)) 246 return 0; 247 248 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 249 err = felix_tag_8021q_vlan_del_rx(ds, port, cpu_dp->index, vid); 250 if (err) 251 return err; 252 } 253 254 err = felix_tag_8021q_vlan_del_tx(ds, port, vid); 255 if (err) 256 goto del_tx_failed; 257 258 return 0; 259 260 del_tx_failed: 261 dsa_switch_for_each_cpu_port(cpu_dp, ds) 262 felix_tag_8021q_vlan_add_rx(ds, port, cpu_dp->index, vid); 263 264 return err; 265 } 266 267 static int felix_trap_get_cpu_port(struct dsa_switch *ds, 268 const struct ocelot_vcap_filter *trap) 269 { 270 struct dsa_port *dp; 271 int first_port; 272 273 if (WARN_ON(!trap->ingress_port_mask)) 274 return -1; 275 276 first_port = __ffs(trap->ingress_port_mask); 277 dp = dsa_to_port(ds, first_port); 278 279 return dp->cpu_dp->index; 280 } 281 282 /* On switches with no extraction IRQ wired, trapped packets need to be 283 * replicated over Ethernet as well, otherwise we'd get no notification of 284 * their arrival when using the ocelot-8021q tagging protocol. 285 */ 286 static int felix_update_trapping_destinations(struct dsa_switch *ds, 287 bool using_tag_8021q) 288 { 289 struct ocelot *ocelot = ds->priv; 290 struct felix *felix = ocelot_to_felix(ocelot); 291 struct ocelot_vcap_block *block_vcap_is2; 292 struct ocelot_vcap_filter *trap; 293 enum ocelot_mask_mode mask_mode; 294 unsigned long port_mask; 295 bool cpu_copy_ena; 296 int err; 297 298 if (!felix->info->quirk_no_xtr_irq) 299 return 0; 300 301 /* We are sure that "cpu" was found, otherwise 302 * dsa_tree_setup_default_cpu() would have failed earlier. 303 */ 304 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 305 306 /* Make sure all traps are set up for that destination */ 307 list_for_each_entry(trap, &block_vcap_is2->rules, list) { 308 if (!trap->is_trap) 309 continue; 310 311 /* Figure out the current trapping destination */ 312 if (using_tag_8021q) { 313 /* Redirect to the tag_8021q CPU port. If timestamps 314 * are necessary, also copy trapped packets to the CPU 315 * port module. 316 */ 317 mask_mode = OCELOT_MASK_MODE_REDIRECT; 318 port_mask = BIT(felix_trap_get_cpu_port(ds, trap)); 319 cpu_copy_ena = !!trap->take_ts; 320 } else { 321 /* Trap packets only to the CPU port module, which is 322 * redirected to the NPI port (the DSA CPU port) 323 */ 324 mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 325 port_mask = 0; 326 cpu_copy_ena = true; 327 } 328 329 if (trap->action.mask_mode == mask_mode && 330 trap->action.port_mask == port_mask && 331 trap->action.cpu_copy_ena == cpu_copy_ena) 332 continue; 333 334 trap->action.mask_mode = mask_mode; 335 trap->action.port_mask = port_mask; 336 trap->action.cpu_copy_ena = cpu_copy_ena; 337 338 err = ocelot_vcap_filter_replace(ocelot, trap); 339 if (err) 340 return err; 341 } 342 343 return 0; 344 } 345 346 /* The CPU port module is connected to the Node Processor Interface (NPI). This 347 * is the mode through which frames can be injected from and extracted to an 348 * external CPU, over Ethernet. In NXP SoCs, the "external CPU" is the ARM CPU 349 * running Linux, and this forms a DSA setup together with the enetc or fman 350 * DSA master. 351 */ 352 static void felix_npi_port_init(struct ocelot *ocelot, int port) 353 { 354 ocelot->npi = port; 355 356 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 357 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(port), 358 QSYS_EXT_CPU_CFG); 359 360 /* NPI port Injection/Extraction configuration */ 361 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 362 ocelot->npi_xtr_prefix); 363 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 364 ocelot->npi_inj_prefix); 365 366 /* Disable transmission of pause frames */ 367 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 368 } 369 370 static void felix_npi_port_deinit(struct ocelot *ocelot, int port) 371 { 372 /* Restore hardware defaults */ 373 int unused_port = ocelot->num_phys_ports + 2; 374 375 ocelot->npi = -1; 376 377 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPU_PORT(unused_port), 378 QSYS_EXT_CPU_CFG); 379 380 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 381 OCELOT_TAG_PREFIX_DISABLED); 382 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 383 OCELOT_TAG_PREFIX_DISABLED); 384 385 /* Enable transmission of pause frames */ 386 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 387 } 388 389 static int felix_tag_npi_setup(struct dsa_switch *ds) 390 { 391 struct dsa_port *dp, *first_cpu_dp = NULL; 392 struct ocelot *ocelot = ds->priv; 393 394 dsa_switch_for_each_user_port(dp, ds) { 395 if (first_cpu_dp && dp->cpu_dp != first_cpu_dp) { 396 dev_err(ds->dev, "Multiple NPI ports not supported\n"); 397 return -EINVAL; 398 } 399 400 first_cpu_dp = dp->cpu_dp; 401 } 402 403 if (!first_cpu_dp) 404 return -EINVAL; 405 406 felix_npi_port_init(ocelot, first_cpu_dp->index); 407 408 return 0; 409 } 410 411 static void felix_tag_npi_teardown(struct dsa_switch *ds) 412 { 413 struct ocelot *ocelot = ds->priv; 414 415 felix_npi_port_deinit(ocelot, ocelot->npi); 416 } 417 418 static unsigned long felix_tag_npi_get_host_fwd_mask(struct dsa_switch *ds) 419 { 420 struct ocelot *ocelot = ds->priv; 421 422 return BIT(ocelot->num_phys_ports); 423 } 424 425 /* Alternatively to using the NPI functionality, that same hardware MAC 426 * connected internally to the enetc or fman DSA master can be configured to 427 * use the software-defined tag_8021q frame format. As far as the hardware is 428 * concerned, it thinks it is a "dumb switch" - the queues of the CPU port 429 * module are now disconnected from it, but can still be accessed through 430 * register-based MMIO. 431 */ 432 static const struct felix_tag_proto_ops felix_tag_npi_proto_ops = { 433 .setup = felix_tag_npi_setup, 434 .teardown = felix_tag_npi_teardown, 435 .get_host_fwd_mask = felix_tag_npi_get_host_fwd_mask, 436 }; 437 438 static int felix_tag_8021q_setup(struct dsa_switch *ds) 439 { 440 struct ocelot *ocelot = ds->priv; 441 struct dsa_port *dp; 442 int err; 443 444 err = dsa_tag_8021q_register(ds, htons(ETH_P_8021AD)); 445 if (err) 446 return err; 447 448 dsa_switch_for_each_user_port(dp, ds) 449 ocelot_port_assign_dsa_8021q_cpu(ocelot, dp->index, 450 dp->cpu_dp->index); 451 452 dsa_switch_for_each_available_port(dp, ds) 453 /* This overwrites ocelot_init(): 454 * Do not forward BPDU frames to the CPU port module, 455 * for 2 reasons: 456 * - When these packets are injected from the tag_8021q 457 * CPU port, we want them to go out, not loop back 458 * into the system. 459 * - STP traffic ingressing on a user port should go to 460 * the tag_8021q CPU port, not to the hardware CPU 461 * port module. 462 */ 463 ocelot_write_gix(ocelot, 464 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0), 465 ANA_PORT_CPU_FWD_BPDU_CFG, dp->index); 466 467 /* The ownership of the CPU port module's queues might have just been 468 * transferred to the tag_8021q tagger from the NPI-based tagger. 469 * So there might still be all sorts of crap in the queues. On the 470 * other hand, the MMIO-based matching of PTP frames is very brittle, 471 * so we need to be careful that there are no extra frames to be 472 * dequeued over MMIO, since we would never know to discard them. 473 */ 474 ocelot_drain_cpu_queue(ocelot, 0); 475 476 return 0; 477 } 478 479 static void felix_tag_8021q_teardown(struct dsa_switch *ds) 480 { 481 struct ocelot *ocelot = ds->priv; 482 struct dsa_port *dp; 483 484 dsa_switch_for_each_available_port(dp, ds) 485 /* Restore the logic from ocelot_init: 486 * do not forward BPDU frames to the front ports. 487 */ 488 ocelot_write_gix(ocelot, 489 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 490 ANA_PORT_CPU_FWD_BPDU_CFG, 491 dp->index); 492 493 dsa_switch_for_each_user_port(dp, ds) 494 ocelot_port_unassign_dsa_8021q_cpu(ocelot, dp->index); 495 496 dsa_tag_8021q_unregister(ds); 497 } 498 499 static unsigned long felix_tag_8021q_get_host_fwd_mask(struct dsa_switch *ds) 500 { 501 return dsa_cpu_ports(ds); 502 } 503 504 static const struct felix_tag_proto_ops felix_tag_8021q_proto_ops = { 505 .setup = felix_tag_8021q_setup, 506 .teardown = felix_tag_8021q_teardown, 507 .get_host_fwd_mask = felix_tag_8021q_get_host_fwd_mask, 508 }; 509 510 static void felix_set_host_flood(struct dsa_switch *ds, unsigned long mask, 511 bool uc, bool mc, bool bc) 512 { 513 struct ocelot *ocelot = ds->priv; 514 unsigned long val; 515 516 val = uc ? mask : 0; 517 ocelot_rmw_rix(ocelot, val, mask, ANA_PGID_PGID, PGID_UC); 518 519 val = mc ? mask : 0; 520 ocelot_rmw_rix(ocelot, val, mask, ANA_PGID_PGID, PGID_MC); 521 ocelot_rmw_rix(ocelot, val, mask, ANA_PGID_PGID, PGID_MCIPV4); 522 ocelot_rmw_rix(ocelot, val, mask, ANA_PGID_PGID, PGID_MCIPV6); 523 524 val = bc ? mask : 0; 525 ocelot_rmw_rix(ocelot, val, mask, ANA_PGID_PGID, PGID_BC); 526 } 527 528 static void 529 felix_migrate_host_flood(struct dsa_switch *ds, 530 const struct felix_tag_proto_ops *proto_ops, 531 const struct felix_tag_proto_ops *old_proto_ops) 532 { 533 struct ocelot *ocelot = ds->priv; 534 struct felix *felix = ocelot_to_felix(ocelot); 535 unsigned long mask; 536 537 if (old_proto_ops) { 538 mask = old_proto_ops->get_host_fwd_mask(ds); 539 felix_set_host_flood(ds, mask, false, false, false); 540 } 541 542 mask = proto_ops->get_host_fwd_mask(ds); 543 felix_set_host_flood(ds, mask, !!felix->host_flood_uc_mask, 544 !!felix->host_flood_mc_mask, true); 545 } 546 547 static int felix_migrate_mdbs(struct dsa_switch *ds, 548 const struct felix_tag_proto_ops *proto_ops, 549 const struct felix_tag_proto_ops *old_proto_ops) 550 { 551 struct ocelot *ocelot = ds->priv; 552 unsigned long from, to; 553 554 if (!old_proto_ops) 555 return 0; 556 557 from = old_proto_ops->get_host_fwd_mask(ds); 558 to = proto_ops->get_host_fwd_mask(ds); 559 560 return ocelot_migrate_mdbs(ocelot, from, to); 561 } 562 563 /* Configure the shared hardware resources for a transition between 564 * @old_proto_ops and @proto_ops. 565 * Manual migration is needed because as far as DSA is concerned, no change of 566 * the CPU port is taking place here, just of the tagging protocol. 567 */ 568 static int 569 felix_tag_proto_setup_shared(struct dsa_switch *ds, 570 const struct felix_tag_proto_ops *proto_ops, 571 const struct felix_tag_proto_ops *old_proto_ops) 572 { 573 bool using_tag_8021q = (proto_ops == &felix_tag_8021q_proto_ops); 574 int err; 575 576 err = felix_migrate_mdbs(ds, proto_ops, old_proto_ops); 577 if (err) 578 return err; 579 580 felix_update_trapping_destinations(ds, using_tag_8021q); 581 582 felix_migrate_host_flood(ds, proto_ops, old_proto_ops); 583 584 return 0; 585 } 586 587 /* This always leaves the switch in a consistent state, because although the 588 * tag_8021q setup can fail, the NPI setup can't. So either the change is made, 589 * or the restoration is guaranteed to work. 590 */ 591 static int felix_change_tag_protocol(struct dsa_switch *ds, 592 enum dsa_tag_protocol proto) 593 { 594 const struct felix_tag_proto_ops *old_proto_ops, *proto_ops; 595 struct ocelot *ocelot = ds->priv; 596 struct felix *felix = ocelot_to_felix(ocelot); 597 int err; 598 599 switch (proto) { 600 case DSA_TAG_PROTO_SEVILLE: 601 case DSA_TAG_PROTO_OCELOT: 602 proto_ops = &felix_tag_npi_proto_ops; 603 break; 604 case DSA_TAG_PROTO_OCELOT_8021Q: 605 proto_ops = &felix_tag_8021q_proto_ops; 606 break; 607 default: 608 return -EPROTONOSUPPORT; 609 } 610 611 old_proto_ops = felix->tag_proto_ops; 612 613 err = proto_ops->setup(ds); 614 if (err) 615 goto setup_failed; 616 617 err = felix_tag_proto_setup_shared(ds, proto_ops, old_proto_ops); 618 if (err) 619 goto setup_shared_failed; 620 621 if (old_proto_ops) 622 old_proto_ops->teardown(ds); 623 624 felix->tag_proto_ops = proto_ops; 625 felix->tag_proto = proto; 626 627 return 0; 628 629 setup_shared_failed: 630 proto_ops->teardown(ds); 631 setup_failed: 632 return err; 633 } 634 635 static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds, 636 int port, 637 enum dsa_tag_protocol mp) 638 { 639 struct ocelot *ocelot = ds->priv; 640 struct felix *felix = ocelot_to_felix(ocelot); 641 642 return felix->tag_proto; 643 } 644 645 static void felix_port_set_host_flood(struct dsa_switch *ds, int port, 646 bool uc, bool mc) 647 { 648 struct ocelot *ocelot = ds->priv; 649 struct felix *felix = ocelot_to_felix(ocelot); 650 unsigned long mask; 651 652 if (uc) 653 felix->host_flood_uc_mask |= BIT(port); 654 else 655 felix->host_flood_uc_mask &= ~BIT(port); 656 657 if (mc) 658 felix->host_flood_mc_mask |= BIT(port); 659 else 660 felix->host_flood_mc_mask &= ~BIT(port); 661 662 mask = felix->tag_proto_ops->get_host_fwd_mask(ds); 663 felix_set_host_flood(ds, mask, !!felix->host_flood_uc_mask, 664 !!felix->host_flood_mc_mask, true); 665 } 666 667 static int felix_set_ageing_time(struct dsa_switch *ds, 668 unsigned int ageing_time) 669 { 670 struct ocelot *ocelot = ds->priv; 671 672 ocelot_set_ageing_time(ocelot, ageing_time); 673 674 return 0; 675 } 676 677 static void felix_port_fast_age(struct dsa_switch *ds, int port) 678 { 679 struct ocelot *ocelot = ds->priv; 680 int err; 681 682 err = ocelot_mact_flush(ocelot, port); 683 if (err) 684 dev_err(ds->dev, "Flushing MAC table on port %d returned %pe\n", 685 port, ERR_PTR(err)); 686 } 687 688 static int felix_fdb_dump(struct dsa_switch *ds, int port, 689 dsa_fdb_dump_cb_t *cb, void *data) 690 { 691 struct ocelot *ocelot = ds->priv; 692 693 return ocelot_fdb_dump(ocelot, port, cb, data); 694 } 695 696 static int felix_fdb_add(struct dsa_switch *ds, int port, 697 const unsigned char *addr, u16 vid, 698 struct dsa_db db) 699 { 700 struct net_device *bridge_dev = felix_classify_db(db); 701 struct dsa_port *dp = dsa_to_port(ds, port); 702 struct ocelot *ocelot = ds->priv; 703 704 if (IS_ERR(bridge_dev)) 705 return PTR_ERR(bridge_dev); 706 707 if (dsa_port_is_cpu(dp) && !bridge_dev && 708 dsa_fdb_present_in_other_db(ds, port, addr, vid, db)) 709 return 0; 710 711 if (dsa_port_is_cpu(dp)) 712 port = PGID_CPU; 713 714 return ocelot_fdb_add(ocelot, port, addr, vid, bridge_dev); 715 } 716 717 static int felix_fdb_del(struct dsa_switch *ds, int port, 718 const unsigned char *addr, u16 vid, 719 struct dsa_db db) 720 { 721 struct net_device *bridge_dev = felix_classify_db(db); 722 struct dsa_port *dp = dsa_to_port(ds, port); 723 struct ocelot *ocelot = ds->priv; 724 725 if (IS_ERR(bridge_dev)) 726 return PTR_ERR(bridge_dev); 727 728 if (dsa_port_is_cpu(dp) && !bridge_dev && 729 dsa_fdb_present_in_other_db(ds, port, addr, vid, db)) 730 return 0; 731 732 if (dsa_port_is_cpu(dp)) 733 port = PGID_CPU; 734 735 return ocelot_fdb_del(ocelot, port, addr, vid, bridge_dev); 736 } 737 738 static int felix_lag_fdb_add(struct dsa_switch *ds, struct dsa_lag lag, 739 const unsigned char *addr, u16 vid, 740 struct dsa_db db) 741 { 742 struct net_device *bridge_dev = felix_classify_db(db); 743 struct ocelot *ocelot = ds->priv; 744 745 if (IS_ERR(bridge_dev)) 746 return PTR_ERR(bridge_dev); 747 748 return ocelot_lag_fdb_add(ocelot, lag.dev, addr, vid, bridge_dev); 749 } 750 751 static int felix_lag_fdb_del(struct dsa_switch *ds, struct dsa_lag lag, 752 const unsigned char *addr, u16 vid, 753 struct dsa_db db) 754 { 755 struct net_device *bridge_dev = felix_classify_db(db); 756 struct ocelot *ocelot = ds->priv; 757 758 if (IS_ERR(bridge_dev)) 759 return PTR_ERR(bridge_dev); 760 761 return ocelot_lag_fdb_del(ocelot, lag.dev, addr, vid, bridge_dev); 762 } 763 764 static int felix_mdb_add(struct dsa_switch *ds, int port, 765 const struct switchdev_obj_port_mdb *mdb, 766 struct dsa_db db) 767 { 768 struct net_device *bridge_dev = felix_classify_db(db); 769 struct ocelot *ocelot = ds->priv; 770 771 if (IS_ERR(bridge_dev)) 772 return PTR_ERR(bridge_dev); 773 774 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 775 dsa_mdb_present_in_other_db(ds, port, mdb, db)) 776 return 0; 777 778 if (port == ocelot->npi) 779 port = ocelot->num_phys_ports; 780 781 return ocelot_port_mdb_add(ocelot, port, mdb, bridge_dev); 782 } 783 784 static int felix_mdb_del(struct dsa_switch *ds, int port, 785 const struct switchdev_obj_port_mdb *mdb, 786 struct dsa_db db) 787 { 788 struct net_device *bridge_dev = felix_classify_db(db); 789 struct ocelot *ocelot = ds->priv; 790 791 if (IS_ERR(bridge_dev)) 792 return PTR_ERR(bridge_dev); 793 794 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 795 dsa_mdb_present_in_other_db(ds, port, mdb, db)) 796 return 0; 797 798 if (port == ocelot->npi) 799 port = ocelot->num_phys_ports; 800 801 return ocelot_port_mdb_del(ocelot, port, mdb, bridge_dev); 802 } 803 804 static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port, 805 u8 state) 806 { 807 struct ocelot *ocelot = ds->priv; 808 809 return ocelot_bridge_stp_state_set(ocelot, port, state); 810 } 811 812 static int felix_pre_bridge_flags(struct dsa_switch *ds, int port, 813 struct switchdev_brport_flags val, 814 struct netlink_ext_ack *extack) 815 { 816 struct ocelot *ocelot = ds->priv; 817 818 return ocelot_port_pre_bridge_flags(ocelot, port, val); 819 } 820 821 static int felix_bridge_flags(struct dsa_switch *ds, int port, 822 struct switchdev_brport_flags val, 823 struct netlink_ext_ack *extack) 824 { 825 struct ocelot *ocelot = ds->priv; 826 827 if (port == ocelot->npi) 828 port = ocelot->num_phys_ports; 829 830 ocelot_port_bridge_flags(ocelot, port, val); 831 832 return 0; 833 } 834 835 static int felix_bridge_join(struct dsa_switch *ds, int port, 836 struct dsa_bridge bridge, bool *tx_fwd_offload, 837 struct netlink_ext_ack *extack) 838 { 839 struct ocelot *ocelot = ds->priv; 840 841 return ocelot_port_bridge_join(ocelot, port, bridge.dev, bridge.num, 842 extack); 843 } 844 845 static void felix_bridge_leave(struct dsa_switch *ds, int port, 846 struct dsa_bridge bridge) 847 { 848 struct ocelot *ocelot = ds->priv; 849 850 ocelot_port_bridge_leave(ocelot, port, bridge.dev); 851 } 852 853 static int felix_lag_join(struct dsa_switch *ds, int port, 854 struct dsa_lag lag, 855 struct netdev_lag_upper_info *info) 856 { 857 struct ocelot *ocelot = ds->priv; 858 859 return ocelot_port_lag_join(ocelot, port, lag.dev, info); 860 } 861 862 static int felix_lag_leave(struct dsa_switch *ds, int port, 863 struct dsa_lag lag) 864 { 865 struct ocelot *ocelot = ds->priv; 866 867 ocelot_port_lag_leave(ocelot, port, lag.dev); 868 869 return 0; 870 } 871 872 static int felix_lag_change(struct dsa_switch *ds, int port) 873 { 874 struct dsa_port *dp = dsa_to_port(ds, port); 875 struct ocelot *ocelot = ds->priv; 876 877 ocelot_port_lag_change(ocelot, port, dp->lag_tx_enabled); 878 879 return 0; 880 } 881 882 static int felix_vlan_prepare(struct dsa_switch *ds, int port, 883 const struct switchdev_obj_port_vlan *vlan, 884 struct netlink_ext_ack *extack) 885 { 886 struct ocelot *ocelot = ds->priv; 887 u16 flags = vlan->flags; 888 889 /* Ocelot switches copy frames as-is to the CPU, so the flags: 890 * egress-untagged or not, pvid or not, make no difference. This 891 * behavior is already better than what DSA just tries to approximate 892 * when it installs the VLAN with the same flags on the CPU port. 893 * Just accept any configuration, and don't let ocelot deny installing 894 * multiple native VLANs on the NPI port, because the switch doesn't 895 * look at the port tag settings towards the NPI interface anyway. 896 */ 897 if (port == ocelot->npi) 898 return 0; 899 900 return ocelot_vlan_prepare(ocelot, port, vlan->vid, 901 flags & BRIDGE_VLAN_INFO_PVID, 902 flags & BRIDGE_VLAN_INFO_UNTAGGED, 903 extack); 904 } 905 906 static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 907 struct netlink_ext_ack *extack) 908 { 909 struct ocelot *ocelot = ds->priv; 910 911 return ocelot_port_vlan_filtering(ocelot, port, enabled, extack); 912 } 913 914 static int felix_vlan_add(struct dsa_switch *ds, int port, 915 const struct switchdev_obj_port_vlan *vlan, 916 struct netlink_ext_ack *extack) 917 { 918 struct ocelot *ocelot = ds->priv; 919 u16 flags = vlan->flags; 920 int err; 921 922 err = felix_vlan_prepare(ds, port, vlan, extack); 923 if (err) 924 return err; 925 926 return ocelot_vlan_add(ocelot, port, vlan->vid, 927 flags & BRIDGE_VLAN_INFO_PVID, 928 flags & BRIDGE_VLAN_INFO_UNTAGGED); 929 } 930 931 static int felix_vlan_del(struct dsa_switch *ds, int port, 932 const struct switchdev_obj_port_vlan *vlan) 933 { 934 struct ocelot *ocelot = ds->priv; 935 936 return ocelot_vlan_del(ocelot, port, vlan->vid); 937 } 938 939 static void felix_phylink_get_caps(struct dsa_switch *ds, int port, 940 struct phylink_config *config) 941 { 942 struct ocelot *ocelot = ds->priv; 943 944 /* This driver does not make use of the speed, duplex, pause or the 945 * advertisement in its mac_config, so it is safe to mark this driver 946 * as non-legacy. 947 */ 948 config->legacy_pre_march2020 = false; 949 950 __set_bit(ocelot->ports[port]->phy_mode, 951 config->supported_interfaces); 952 } 953 954 static void felix_phylink_validate(struct dsa_switch *ds, int port, 955 unsigned long *supported, 956 struct phylink_link_state *state) 957 { 958 struct ocelot *ocelot = ds->priv; 959 struct felix *felix = ocelot_to_felix(ocelot); 960 961 if (felix->info->phylink_validate) 962 felix->info->phylink_validate(ocelot, port, supported, state); 963 } 964 965 static struct phylink_pcs *felix_phylink_mac_select_pcs(struct dsa_switch *ds, 966 int port, 967 phy_interface_t iface) 968 { 969 struct ocelot *ocelot = ds->priv; 970 struct felix *felix = ocelot_to_felix(ocelot); 971 struct phylink_pcs *pcs = NULL; 972 973 if (felix->pcs && felix->pcs[port]) 974 pcs = felix->pcs[port]; 975 976 return pcs; 977 } 978 979 static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, 980 unsigned int link_an_mode, 981 phy_interface_t interface) 982 { 983 struct ocelot *ocelot = ds->priv; 984 985 ocelot_phylink_mac_link_down(ocelot, port, link_an_mode, interface, 986 FELIX_MAC_QUIRKS); 987 } 988 989 static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, 990 unsigned int link_an_mode, 991 phy_interface_t interface, 992 struct phy_device *phydev, 993 int speed, int duplex, 994 bool tx_pause, bool rx_pause) 995 { 996 struct ocelot *ocelot = ds->priv; 997 struct felix *felix = ocelot_to_felix(ocelot); 998 999 ocelot_phylink_mac_link_up(ocelot, port, phydev, link_an_mode, 1000 interface, speed, duplex, tx_pause, rx_pause, 1001 FELIX_MAC_QUIRKS); 1002 1003 if (felix->info->port_sched_speed_set) 1004 felix->info->port_sched_speed_set(ocelot, port, speed); 1005 } 1006 1007 static void felix_port_qos_map_init(struct ocelot *ocelot, int port) 1008 { 1009 int i; 1010 1011 ocelot_rmw_gix(ocelot, 1012 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 1013 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 1014 ANA_PORT_QOS_CFG, 1015 port); 1016 1017 for (i = 0; i < OCELOT_NUM_TC * 2; i++) { 1018 ocelot_rmw_ix(ocelot, 1019 (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) | 1020 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i), 1021 ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL | 1022 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M, 1023 ANA_PORT_PCP_DEI_MAP, 1024 port, i); 1025 } 1026 } 1027 1028 static void felix_get_strings(struct dsa_switch *ds, int port, 1029 u32 stringset, u8 *data) 1030 { 1031 struct ocelot *ocelot = ds->priv; 1032 1033 return ocelot_get_strings(ocelot, port, stringset, data); 1034 } 1035 1036 static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 1037 { 1038 struct ocelot *ocelot = ds->priv; 1039 1040 ocelot_get_ethtool_stats(ocelot, port, data); 1041 } 1042 1043 static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset) 1044 { 1045 struct ocelot *ocelot = ds->priv; 1046 1047 return ocelot_get_sset_count(ocelot, port, sset); 1048 } 1049 1050 static int felix_get_ts_info(struct dsa_switch *ds, int port, 1051 struct ethtool_ts_info *info) 1052 { 1053 struct ocelot *ocelot = ds->priv; 1054 1055 return ocelot_get_ts_info(ocelot, port, info); 1056 } 1057 1058 static const u32 felix_phy_match_table[PHY_INTERFACE_MODE_MAX] = { 1059 [PHY_INTERFACE_MODE_INTERNAL] = OCELOT_PORT_MODE_INTERNAL, 1060 [PHY_INTERFACE_MODE_SGMII] = OCELOT_PORT_MODE_SGMII, 1061 [PHY_INTERFACE_MODE_QSGMII] = OCELOT_PORT_MODE_QSGMII, 1062 [PHY_INTERFACE_MODE_USXGMII] = OCELOT_PORT_MODE_USXGMII, 1063 [PHY_INTERFACE_MODE_1000BASEX] = OCELOT_PORT_MODE_1000BASEX, 1064 [PHY_INTERFACE_MODE_2500BASEX] = OCELOT_PORT_MODE_2500BASEX, 1065 }; 1066 1067 static int felix_validate_phy_mode(struct felix *felix, int port, 1068 phy_interface_t phy_mode) 1069 { 1070 u32 modes = felix->info->port_modes[port]; 1071 1072 if (felix_phy_match_table[phy_mode] & modes) 1073 return 0; 1074 return -EOPNOTSUPP; 1075 } 1076 1077 static int felix_parse_ports_node(struct felix *felix, 1078 struct device_node *ports_node, 1079 phy_interface_t *port_phy_modes) 1080 { 1081 struct device *dev = felix->ocelot.dev; 1082 struct device_node *child; 1083 1084 for_each_available_child_of_node(ports_node, child) { 1085 phy_interface_t phy_mode; 1086 u32 port; 1087 int err; 1088 1089 /* Get switch port number from DT */ 1090 if (of_property_read_u32(child, "reg", &port) < 0) { 1091 dev_err(dev, "Port number not defined in device tree " 1092 "(property \"reg\")\n"); 1093 of_node_put(child); 1094 return -ENODEV; 1095 } 1096 1097 /* Get PHY mode from DT */ 1098 err = of_get_phy_mode(child, &phy_mode); 1099 if (err) { 1100 dev_err(dev, "Failed to read phy-mode or " 1101 "phy-interface-type property for port %d\n", 1102 port); 1103 of_node_put(child); 1104 return -ENODEV; 1105 } 1106 1107 err = felix_validate_phy_mode(felix, port, phy_mode); 1108 if (err < 0) { 1109 dev_err(dev, "Unsupported PHY mode %s on port %d\n", 1110 phy_modes(phy_mode), port); 1111 of_node_put(child); 1112 return err; 1113 } 1114 1115 port_phy_modes[port] = phy_mode; 1116 } 1117 1118 return 0; 1119 } 1120 1121 static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes) 1122 { 1123 struct device *dev = felix->ocelot.dev; 1124 struct device_node *switch_node; 1125 struct device_node *ports_node; 1126 int err; 1127 1128 switch_node = dev->of_node; 1129 1130 ports_node = of_get_child_by_name(switch_node, "ports"); 1131 if (!ports_node) 1132 ports_node = of_get_child_by_name(switch_node, "ethernet-ports"); 1133 if (!ports_node) { 1134 dev_err(dev, "Incorrect bindings: absent \"ports\" or \"ethernet-ports\" node\n"); 1135 return -ENODEV; 1136 } 1137 1138 err = felix_parse_ports_node(felix, ports_node, port_phy_modes); 1139 of_node_put(ports_node); 1140 1141 return err; 1142 } 1143 1144 static int felix_init_structs(struct felix *felix, int num_phys_ports) 1145 { 1146 struct ocelot *ocelot = &felix->ocelot; 1147 phy_interface_t *port_phy_modes; 1148 struct resource res; 1149 int port, i, err; 1150 1151 ocelot->num_phys_ports = num_phys_ports; 1152 ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports, 1153 sizeof(struct ocelot_port *), GFP_KERNEL); 1154 if (!ocelot->ports) 1155 return -ENOMEM; 1156 1157 ocelot->map = felix->info->map; 1158 ocelot->stats_layout = felix->info->stats_layout; 1159 ocelot->num_mact_rows = felix->info->num_mact_rows; 1160 ocelot->vcap = felix->info->vcap; 1161 ocelot->vcap_pol.base = felix->info->vcap_pol_base; 1162 ocelot->vcap_pol.max = felix->info->vcap_pol_max; 1163 ocelot->vcap_pol.base2 = felix->info->vcap_pol_base2; 1164 ocelot->vcap_pol.max2 = felix->info->vcap_pol_max2; 1165 ocelot->ops = felix->info->ops; 1166 ocelot->npi_inj_prefix = OCELOT_TAG_PREFIX_SHORT; 1167 ocelot->npi_xtr_prefix = OCELOT_TAG_PREFIX_SHORT; 1168 ocelot->devlink = felix->ds->devlink; 1169 1170 port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t), 1171 GFP_KERNEL); 1172 if (!port_phy_modes) 1173 return -ENOMEM; 1174 1175 err = felix_parse_dt(felix, port_phy_modes); 1176 if (err) { 1177 kfree(port_phy_modes); 1178 return err; 1179 } 1180 1181 for (i = 0; i < TARGET_MAX; i++) { 1182 struct regmap *target; 1183 1184 if (!felix->info->target_io_res[i].name) 1185 continue; 1186 1187 memcpy(&res, &felix->info->target_io_res[i], sizeof(res)); 1188 res.flags = IORESOURCE_MEM; 1189 res.start += felix->switch_base; 1190 res.end += felix->switch_base; 1191 1192 target = felix->info->init_regmap(ocelot, &res); 1193 if (IS_ERR(target)) { 1194 dev_err(ocelot->dev, 1195 "Failed to map device memory space\n"); 1196 kfree(port_phy_modes); 1197 return PTR_ERR(target); 1198 } 1199 1200 ocelot->targets[i] = target; 1201 } 1202 1203 err = ocelot_regfields_init(ocelot, felix->info->regfields); 1204 if (err) { 1205 dev_err(ocelot->dev, "failed to init reg fields map\n"); 1206 kfree(port_phy_modes); 1207 return err; 1208 } 1209 1210 for (port = 0; port < num_phys_ports; port++) { 1211 struct ocelot_port *ocelot_port; 1212 struct regmap *target; 1213 1214 ocelot_port = devm_kzalloc(ocelot->dev, 1215 sizeof(struct ocelot_port), 1216 GFP_KERNEL); 1217 if (!ocelot_port) { 1218 dev_err(ocelot->dev, 1219 "failed to allocate port memory\n"); 1220 kfree(port_phy_modes); 1221 return -ENOMEM; 1222 } 1223 1224 memcpy(&res, &felix->info->port_io_res[port], sizeof(res)); 1225 res.flags = IORESOURCE_MEM; 1226 res.start += felix->switch_base; 1227 res.end += felix->switch_base; 1228 1229 target = felix->info->init_regmap(ocelot, &res); 1230 if (IS_ERR(target)) { 1231 dev_err(ocelot->dev, 1232 "Failed to map memory space for port %d\n", 1233 port); 1234 kfree(port_phy_modes); 1235 return PTR_ERR(target); 1236 } 1237 1238 ocelot_port->phy_mode = port_phy_modes[port]; 1239 ocelot_port->ocelot = ocelot; 1240 ocelot_port->target = target; 1241 ocelot_port->index = port; 1242 ocelot->ports[port] = ocelot_port; 1243 } 1244 1245 kfree(port_phy_modes); 1246 1247 if (felix->info->mdio_bus_alloc) { 1248 err = felix->info->mdio_bus_alloc(ocelot); 1249 if (err < 0) 1250 return err; 1251 } 1252 1253 return 0; 1254 } 1255 1256 static void ocelot_port_purge_txtstamp_skb(struct ocelot *ocelot, int port, 1257 struct sk_buff *skb) 1258 { 1259 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1260 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone; 1261 struct sk_buff *skb_match = NULL, *skb_tmp; 1262 unsigned long flags; 1263 1264 if (!clone) 1265 return; 1266 1267 spin_lock_irqsave(&ocelot_port->tx_skbs.lock, flags); 1268 1269 skb_queue_walk_safe(&ocelot_port->tx_skbs, skb, skb_tmp) { 1270 if (skb != clone) 1271 continue; 1272 __skb_unlink(skb, &ocelot_port->tx_skbs); 1273 skb_match = skb; 1274 break; 1275 } 1276 1277 spin_unlock_irqrestore(&ocelot_port->tx_skbs.lock, flags); 1278 1279 WARN_ONCE(!skb_match, 1280 "Could not find skb clone in TX timestamping list\n"); 1281 } 1282 1283 #define work_to_xmit_work(w) \ 1284 container_of((w), struct felix_deferred_xmit_work, work) 1285 1286 static void felix_port_deferred_xmit(struct kthread_work *work) 1287 { 1288 struct felix_deferred_xmit_work *xmit_work = work_to_xmit_work(work); 1289 struct dsa_switch *ds = xmit_work->dp->ds; 1290 struct sk_buff *skb = xmit_work->skb; 1291 u32 rew_op = ocelot_ptp_rew_op(skb); 1292 struct ocelot *ocelot = ds->priv; 1293 int port = xmit_work->dp->index; 1294 int retries = 10; 1295 1296 do { 1297 if (ocelot_can_inject(ocelot, 0)) 1298 break; 1299 1300 cpu_relax(); 1301 } while (--retries); 1302 1303 if (!retries) { 1304 dev_err(ocelot->dev, "port %d failed to inject skb\n", 1305 port); 1306 ocelot_port_purge_txtstamp_skb(ocelot, port, skb); 1307 kfree_skb(skb); 1308 return; 1309 } 1310 1311 ocelot_port_inject_frame(ocelot, port, 0, rew_op, skb); 1312 1313 consume_skb(skb); 1314 kfree(xmit_work); 1315 } 1316 1317 static int felix_connect_tag_protocol(struct dsa_switch *ds, 1318 enum dsa_tag_protocol proto) 1319 { 1320 struct ocelot_8021q_tagger_data *tagger_data; 1321 1322 switch (proto) { 1323 case DSA_TAG_PROTO_OCELOT_8021Q: 1324 tagger_data = ocelot_8021q_tagger_data(ds); 1325 tagger_data->xmit_work_fn = felix_port_deferred_xmit; 1326 return 0; 1327 case DSA_TAG_PROTO_OCELOT: 1328 case DSA_TAG_PROTO_SEVILLE: 1329 return 0; 1330 default: 1331 return -EPROTONOSUPPORT; 1332 } 1333 } 1334 1335 /* Hardware initialization done here so that we can allocate structures with 1336 * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing 1337 * us to allocate structures twice (leak memory) and map PCI memory twice 1338 * (which will not work). 1339 */ 1340 static int felix_setup(struct dsa_switch *ds) 1341 { 1342 struct ocelot *ocelot = ds->priv; 1343 struct felix *felix = ocelot_to_felix(ocelot); 1344 struct dsa_port *dp; 1345 int err; 1346 1347 err = felix_init_structs(felix, ds->num_ports); 1348 if (err) 1349 return err; 1350 1351 err = ocelot_init(ocelot); 1352 if (err) 1353 goto out_mdiobus_free; 1354 1355 if (ocelot->ptp) { 1356 err = ocelot_init_timestamp(ocelot, felix->info->ptp_caps); 1357 if (err) { 1358 dev_err(ocelot->dev, 1359 "Timestamp initialization failed\n"); 1360 ocelot->ptp = 0; 1361 } 1362 } 1363 1364 dsa_switch_for_each_available_port(dp, ds) { 1365 ocelot_init_port(ocelot, dp->index); 1366 1367 /* Set the default QoS Classification based on PCP and DEI 1368 * bits of vlan tag. 1369 */ 1370 felix_port_qos_map_init(ocelot, dp->index); 1371 } 1372 1373 err = ocelot_devlink_sb_register(ocelot); 1374 if (err) 1375 goto out_deinit_ports; 1376 1377 /* The initial tag protocol is NPI which won't fail during initial 1378 * setup, there's no real point in checking for errors. 1379 */ 1380 felix_change_tag_protocol(ds, felix->tag_proto); 1381 1382 ds->mtu_enforcement_ingress = true; 1383 ds->assisted_learning_on_cpu_port = true; 1384 ds->fdb_isolation = true; 1385 ds->max_num_bridges = ds->num_ports; 1386 1387 return 0; 1388 1389 out_deinit_ports: 1390 dsa_switch_for_each_available_port(dp, ds) 1391 ocelot_deinit_port(ocelot, dp->index); 1392 1393 ocelot_deinit_timestamp(ocelot); 1394 ocelot_deinit(ocelot); 1395 1396 out_mdiobus_free: 1397 if (felix->info->mdio_bus_free) 1398 felix->info->mdio_bus_free(ocelot); 1399 1400 return err; 1401 } 1402 1403 static void felix_teardown(struct dsa_switch *ds) 1404 { 1405 struct ocelot *ocelot = ds->priv; 1406 struct felix *felix = ocelot_to_felix(ocelot); 1407 struct dsa_port *dp; 1408 1409 if (felix->tag_proto_ops) 1410 felix->tag_proto_ops->teardown(ds); 1411 1412 dsa_switch_for_each_available_port(dp, ds) 1413 ocelot_deinit_port(ocelot, dp->index); 1414 1415 ocelot_devlink_sb_unregister(ocelot); 1416 ocelot_deinit_timestamp(ocelot); 1417 ocelot_deinit(ocelot); 1418 1419 if (felix->info->mdio_bus_free) 1420 felix->info->mdio_bus_free(ocelot); 1421 } 1422 1423 static int felix_hwtstamp_get(struct dsa_switch *ds, int port, 1424 struct ifreq *ifr) 1425 { 1426 struct ocelot *ocelot = ds->priv; 1427 1428 return ocelot_hwstamp_get(ocelot, port, ifr); 1429 } 1430 1431 static int felix_hwtstamp_set(struct dsa_switch *ds, int port, 1432 struct ifreq *ifr) 1433 { 1434 struct ocelot *ocelot = ds->priv; 1435 struct felix *felix = ocelot_to_felix(ocelot); 1436 bool using_tag_8021q; 1437 int err; 1438 1439 err = ocelot_hwstamp_set(ocelot, port, ifr); 1440 if (err) 1441 return err; 1442 1443 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q; 1444 1445 return felix_update_trapping_destinations(ds, using_tag_8021q); 1446 } 1447 1448 static bool felix_check_xtr_pkt(struct ocelot *ocelot) 1449 { 1450 struct felix *felix = ocelot_to_felix(ocelot); 1451 int err = 0, grp = 0; 1452 1453 if (felix->tag_proto != DSA_TAG_PROTO_OCELOT_8021Q) 1454 return false; 1455 1456 if (!felix->info->quirk_no_xtr_irq) 1457 return false; 1458 1459 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) { 1460 struct sk_buff *skb; 1461 unsigned int type; 1462 1463 err = ocelot_xtr_poll_frame(ocelot, grp, &skb); 1464 if (err) 1465 goto out; 1466 1467 /* We trap to the CPU port module all PTP frames, but 1468 * felix_rxtstamp() only gets called for event frames. 1469 * So we need to avoid sending duplicate general 1470 * message frames by running a second BPF classifier 1471 * here and dropping those. 1472 */ 1473 __skb_push(skb, ETH_HLEN); 1474 1475 type = ptp_classify_raw(skb); 1476 1477 __skb_pull(skb, ETH_HLEN); 1478 1479 if (type == PTP_CLASS_NONE) { 1480 kfree_skb(skb); 1481 continue; 1482 } 1483 1484 netif_rx(skb); 1485 } 1486 1487 out: 1488 if (err < 0) { 1489 dev_err_ratelimited(ocelot->dev, 1490 "Error during packet extraction: %pe\n", 1491 ERR_PTR(err)); 1492 ocelot_drain_cpu_queue(ocelot, 0); 1493 } 1494 1495 return true; 1496 } 1497 1498 static bool felix_rxtstamp(struct dsa_switch *ds, int port, 1499 struct sk_buff *skb, unsigned int type) 1500 { 1501 u32 tstamp_lo = OCELOT_SKB_CB(skb)->tstamp_lo; 1502 struct skb_shared_hwtstamps *shhwtstamps; 1503 struct ocelot *ocelot = ds->priv; 1504 struct timespec64 ts; 1505 u32 tstamp_hi; 1506 u64 tstamp; 1507 1508 /* If the "no XTR IRQ" workaround is in use, tell DSA to defer this skb 1509 * for RX timestamping. Then free it, and poll for its copy through 1510 * MMIO in the CPU port module, and inject that into the stack from 1511 * ocelot_xtr_poll(). 1512 */ 1513 if (felix_check_xtr_pkt(ocelot)) { 1514 kfree_skb(skb); 1515 return true; 1516 } 1517 1518 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1519 tstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 1520 1521 tstamp_hi = tstamp >> 32; 1522 if ((tstamp & 0xffffffff) < tstamp_lo) 1523 tstamp_hi--; 1524 1525 tstamp = ((u64)tstamp_hi << 32) | tstamp_lo; 1526 1527 shhwtstamps = skb_hwtstamps(skb); 1528 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1529 shhwtstamps->hwtstamp = tstamp; 1530 return false; 1531 } 1532 1533 static void felix_txtstamp(struct dsa_switch *ds, int port, 1534 struct sk_buff *skb) 1535 { 1536 struct ocelot *ocelot = ds->priv; 1537 struct sk_buff *clone = NULL; 1538 1539 if (!ocelot->ptp) 1540 return; 1541 1542 if (ocelot_port_txtstamp_request(ocelot, port, skb, &clone)) { 1543 dev_err_ratelimited(ds->dev, 1544 "port %d delivering skb without TX timestamp\n", 1545 port); 1546 return; 1547 } 1548 1549 if (clone) 1550 OCELOT_SKB_CB(skb)->clone = clone; 1551 } 1552 1553 static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1554 { 1555 struct ocelot *ocelot = ds->priv; 1556 1557 ocelot_port_set_maxlen(ocelot, port, new_mtu); 1558 1559 return 0; 1560 } 1561 1562 static int felix_get_max_mtu(struct dsa_switch *ds, int port) 1563 { 1564 struct ocelot *ocelot = ds->priv; 1565 1566 return ocelot_get_max_mtu(ocelot, port); 1567 } 1568 1569 static int felix_cls_flower_add(struct dsa_switch *ds, int port, 1570 struct flow_cls_offload *cls, bool ingress) 1571 { 1572 struct ocelot *ocelot = ds->priv; 1573 struct felix *felix = ocelot_to_felix(ocelot); 1574 bool using_tag_8021q; 1575 int err; 1576 1577 err = ocelot_cls_flower_replace(ocelot, port, cls, ingress); 1578 if (err) 1579 return err; 1580 1581 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q; 1582 1583 return felix_update_trapping_destinations(ds, using_tag_8021q); 1584 } 1585 1586 static int felix_cls_flower_del(struct dsa_switch *ds, int port, 1587 struct flow_cls_offload *cls, bool ingress) 1588 { 1589 struct ocelot *ocelot = ds->priv; 1590 1591 return ocelot_cls_flower_destroy(ocelot, port, cls, ingress); 1592 } 1593 1594 static int felix_cls_flower_stats(struct dsa_switch *ds, int port, 1595 struct flow_cls_offload *cls, bool ingress) 1596 { 1597 struct ocelot *ocelot = ds->priv; 1598 1599 return ocelot_cls_flower_stats(ocelot, port, cls, ingress); 1600 } 1601 1602 static int felix_port_policer_add(struct dsa_switch *ds, int port, 1603 struct dsa_mall_policer_tc_entry *policer) 1604 { 1605 struct ocelot *ocelot = ds->priv; 1606 struct ocelot_policer pol = { 1607 .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8, 1608 .burst = policer->burst, 1609 }; 1610 1611 return ocelot_port_policer_add(ocelot, port, &pol); 1612 } 1613 1614 static void felix_port_policer_del(struct dsa_switch *ds, int port) 1615 { 1616 struct ocelot *ocelot = ds->priv; 1617 1618 ocelot_port_policer_del(ocelot, port); 1619 } 1620 1621 static int felix_port_mirror_add(struct dsa_switch *ds, int port, 1622 struct dsa_mall_mirror_tc_entry *mirror, 1623 bool ingress, struct netlink_ext_ack *extack) 1624 { 1625 struct ocelot *ocelot = ds->priv; 1626 1627 return ocelot_port_mirror_add(ocelot, port, mirror->to_local_port, 1628 ingress, extack); 1629 } 1630 1631 static void felix_port_mirror_del(struct dsa_switch *ds, int port, 1632 struct dsa_mall_mirror_tc_entry *mirror) 1633 { 1634 struct ocelot *ocelot = ds->priv; 1635 1636 ocelot_port_mirror_del(ocelot, port, mirror->ingress); 1637 } 1638 1639 static int felix_port_setup_tc(struct dsa_switch *ds, int port, 1640 enum tc_setup_type type, 1641 void *type_data) 1642 { 1643 struct ocelot *ocelot = ds->priv; 1644 struct felix *felix = ocelot_to_felix(ocelot); 1645 1646 if (felix->info->port_setup_tc) 1647 return felix->info->port_setup_tc(ds, port, type, type_data); 1648 else 1649 return -EOPNOTSUPP; 1650 } 1651 1652 static int felix_sb_pool_get(struct dsa_switch *ds, unsigned int sb_index, 1653 u16 pool_index, 1654 struct devlink_sb_pool_info *pool_info) 1655 { 1656 struct ocelot *ocelot = ds->priv; 1657 1658 return ocelot_sb_pool_get(ocelot, sb_index, pool_index, pool_info); 1659 } 1660 1661 static int felix_sb_pool_set(struct dsa_switch *ds, unsigned int sb_index, 1662 u16 pool_index, u32 size, 1663 enum devlink_sb_threshold_type threshold_type, 1664 struct netlink_ext_ack *extack) 1665 { 1666 struct ocelot *ocelot = ds->priv; 1667 1668 return ocelot_sb_pool_set(ocelot, sb_index, pool_index, size, 1669 threshold_type, extack); 1670 } 1671 1672 static int felix_sb_port_pool_get(struct dsa_switch *ds, int port, 1673 unsigned int sb_index, u16 pool_index, 1674 u32 *p_threshold) 1675 { 1676 struct ocelot *ocelot = ds->priv; 1677 1678 return ocelot_sb_port_pool_get(ocelot, port, sb_index, pool_index, 1679 p_threshold); 1680 } 1681 1682 static int felix_sb_port_pool_set(struct dsa_switch *ds, int port, 1683 unsigned int sb_index, u16 pool_index, 1684 u32 threshold, struct netlink_ext_ack *extack) 1685 { 1686 struct ocelot *ocelot = ds->priv; 1687 1688 return ocelot_sb_port_pool_set(ocelot, port, sb_index, pool_index, 1689 threshold, extack); 1690 } 1691 1692 static int felix_sb_tc_pool_bind_get(struct dsa_switch *ds, int port, 1693 unsigned int sb_index, u16 tc_index, 1694 enum devlink_sb_pool_type pool_type, 1695 u16 *p_pool_index, u32 *p_threshold) 1696 { 1697 struct ocelot *ocelot = ds->priv; 1698 1699 return ocelot_sb_tc_pool_bind_get(ocelot, port, sb_index, tc_index, 1700 pool_type, p_pool_index, 1701 p_threshold); 1702 } 1703 1704 static int felix_sb_tc_pool_bind_set(struct dsa_switch *ds, int port, 1705 unsigned int sb_index, u16 tc_index, 1706 enum devlink_sb_pool_type pool_type, 1707 u16 pool_index, u32 threshold, 1708 struct netlink_ext_ack *extack) 1709 { 1710 struct ocelot *ocelot = ds->priv; 1711 1712 return ocelot_sb_tc_pool_bind_set(ocelot, port, sb_index, tc_index, 1713 pool_type, pool_index, threshold, 1714 extack); 1715 } 1716 1717 static int felix_sb_occ_snapshot(struct dsa_switch *ds, 1718 unsigned int sb_index) 1719 { 1720 struct ocelot *ocelot = ds->priv; 1721 1722 return ocelot_sb_occ_snapshot(ocelot, sb_index); 1723 } 1724 1725 static int felix_sb_occ_max_clear(struct dsa_switch *ds, 1726 unsigned int sb_index) 1727 { 1728 struct ocelot *ocelot = ds->priv; 1729 1730 return ocelot_sb_occ_max_clear(ocelot, sb_index); 1731 } 1732 1733 static int felix_sb_occ_port_pool_get(struct dsa_switch *ds, int port, 1734 unsigned int sb_index, u16 pool_index, 1735 u32 *p_cur, u32 *p_max) 1736 { 1737 struct ocelot *ocelot = ds->priv; 1738 1739 return ocelot_sb_occ_port_pool_get(ocelot, port, sb_index, pool_index, 1740 p_cur, p_max); 1741 } 1742 1743 static int felix_sb_occ_tc_port_bind_get(struct dsa_switch *ds, int port, 1744 unsigned int sb_index, u16 tc_index, 1745 enum devlink_sb_pool_type pool_type, 1746 u32 *p_cur, u32 *p_max) 1747 { 1748 struct ocelot *ocelot = ds->priv; 1749 1750 return ocelot_sb_occ_tc_port_bind_get(ocelot, port, sb_index, tc_index, 1751 pool_type, p_cur, p_max); 1752 } 1753 1754 static int felix_mrp_add(struct dsa_switch *ds, int port, 1755 const struct switchdev_obj_mrp *mrp) 1756 { 1757 struct ocelot *ocelot = ds->priv; 1758 1759 return ocelot_mrp_add(ocelot, port, mrp); 1760 } 1761 1762 static int felix_mrp_del(struct dsa_switch *ds, int port, 1763 const struct switchdev_obj_mrp *mrp) 1764 { 1765 struct ocelot *ocelot = ds->priv; 1766 1767 return ocelot_mrp_add(ocelot, port, mrp); 1768 } 1769 1770 static int 1771 felix_mrp_add_ring_role(struct dsa_switch *ds, int port, 1772 const struct switchdev_obj_ring_role_mrp *mrp) 1773 { 1774 struct ocelot *ocelot = ds->priv; 1775 1776 return ocelot_mrp_add_ring_role(ocelot, port, mrp); 1777 } 1778 1779 static int 1780 felix_mrp_del_ring_role(struct dsa_switch *ds, int port, 1781 const struct switchdev_obj_ring_role_mrp *mrp) 1782 { 1783 struct ocelot *ocelot = ds->priv; 1784 1785 return ocelot_mrp_del_ring_role(ocelot, port, mrp); 1786 } 1787 1788 static int felix_port_get_default_prio(struct dsa_switch *ds, int port) 1789 { 1790 struct ocelot *ocelot = ds->priv; 1791 1792 return ocelot_port_get_default_prio(ocelot, port); 1793 } 1794 1795 static int felix_port_set_default_prio(struct dsa_switch *ds, int port, 1796 u8 prio) 1797 { 1798 struct ocelot *ocelot = ds->priv; 1799 1800 return ocelot_port_set_default_prio(ocelot, port, prio); 1801 } 1802 1803 static int felix_port_get_dscp_prio(struct dsa_switch *ds, int port, u8 dscp) 1804 { 1805 struct ocelot *ocelot = ds->priv; 1806 1807 return ocelot_port_get_dscp_prio(ocelot, port, dscp); 1808 } 1809 1810 static int felix_port_add_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, 1811 u8 prio) 1812 { 1813 struct ocelot *ocelot = ds->priv; 1814 1815 return ocelot_port_add_dscp_prio(ocelot, port, dscp, prio); 1816 } 1817 1818 static int felix_port_del_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, 1819 u8 prio) 1820 { 1821 struct ocelot *ocelot = ds->priv; 1822 1823 return ocelot_port_del_dscp_prio(ocelot, port, dscp, prio); 1824 } 1825 1826 const struct dsa_switch_ops felix_switch_ops = { 1827 .get_tag_protocol = felix_get_tag_protocol, 1828 .change_tag_protocol = felix_change_tag_protocol, 1829 .connect_tag_protocol = felix_connect_tag_protocol, 1830 .setup = felix_setup, 1831 .teardown = felix_teardown, 1832 .set_ageing_time = felix_set_ageing_time, 1833 .get_strings = felix_get_strings, 1834 .get_ethtool_stats = felix_get_ethtool_stats, 1835 .get_sset_count = felix_get_sset_count, 1836 .get_ts_info = felix_get_ts_info, 1837 .phylink_get_caps = felix_phylink_get_caps, 1838 .phylink_validate = felix_phylink_validate, 1839 .phylink_mac_select_pcs = felix_phylink_mac_select_pcs, 1840 .phylink_mac_link_down = felix_phylink_mac_link_down, 1841 .phylink_mac_link_up = felix_phylink_mac_link_up, 1842 .port_fast_age = felix_port_fast_age, 1843 .port_fdb_dump = felix_fdb_dump, 1844 .port_fdb_add = felix_fdb_add, 1845 .port_fdb_del = felix_fdb_del, 1846 .lag_fdb_add = felix_lag_fdb_add, 1847 .lag_fdb_del = felix_lag_fdb_del, 1848 .port_mdb_add = felix_mdb_add, 1849 .port_mdb_del = felix_mdb_del, 1850 .port_pre_bridge_flags = felix_pre_bridge_flags, 1851 .port_bridge_flags = felix_bridge_flags, 1852 .port_bridge_join = felix_bridge_join, 1853 .port_bridge_leave = felix_bridge_leave, 1854 .port_lag_join = felix_lag_join, 1855 .port_lag_leave = felix_lag_leave, 1856 .port_lag_change = felix_lag_change, 1857 .port_stp_state_set = felix_bridge_stp_state_set, 1858 .port_vlan_filtering = felix_vlan_filtering, 1859 .port_vlan_add = felix_vlan_add, 1860 .port_vlan_del = felix_vlan_del, 1861 .port_hwtstamp_get = felix_hwtstamp_get, 1862 .port_hwtstamp_set = felix_hwtstamp_set, 1863 .port_rxtstamp = felix_rxtstamp, 1864 .port_txtstamp = felix_txtstamp, 1865 .port_change_mtu = felix_change_mtu, 1866 .port_max_mtu = felix_get_max_mtu, 1867 .port_policer_add = felix_port_policer_add, 1868 .port_policer_del = felix_port_policer_del, 1869 .port_mirror_add = felix_port_mirror_add, 1870 .port_mirror_del = felix_port_mirror_del, 1871 .cls_flower_add = felix_cls_flower_add, 1872 .cls_flower_del = felix_cls_flower_del, 1873 .cls_flower_stats = felix_cls_flower_stats, 1874 .port_setup_tc = felix_port_setup_tc, 1875 .devlink_sb_pool_get = felix_sb_pool_get, 1876 .devlink_sb_pool_set = felix_sb_pool_set, 1877 .devlink_sb_port_pool_get = felix_sb_port_pool_get, 1878 .devlink_sb_port_pool_set = felix_sb_port_pool_set, 1879 .devlink_sb_tc_pool_bind_get = felix_sb_tc_pool_bind_get, 1880 .devlink_sb_tc_pool_bind_set = felix_sb_tc_pool_bind_set, 1881 .devlink_sb_occ_snapshot = felix_sb_occ_snapshot, 1882 .devlink_sb_occ_max_clear = felix_sb_occ_max_clear, 1883 .devlink_sb_occ_port_pool_get = felix_sb_occ_port_pool_get, 1884 .devlink_sb_occ_tc_port_bind_get= felix_sb_occ_tc_port_bind_get, 1885 .port_mrp_add = felix_mrp_add, 1886 .port_mrp_del = felix_mrp_del, 1887 .port_mrp_add_ring_role = felix_mrp_add_ring_role, 1888 .port_mrp_del_ring_role = felix_mrp_del_ring_role, 1889 .tag_8021q_vlan_add = felix_tag_8021q_vlan_add, 1890 .tag_8021q_vlan_del = felix_tag_8021q_vlan_del, 1891 .port_get_default_prio = felix_port_get_default_prio, 1892 .port_set_default_prio = felix_port_set_default_prio, 1893 .port_get_dscp_prio = felix_port_get_dscp_prio, 1894 .port_add_dscp_prio = felix_port_add_dscp_prio, 1895 .port_del_dscp_prio = felix_port_del_dscp_prio, 1896 .port_set_host_flood = felix_port_set_host_flood, 1897 }; 1898 1899 struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port) 1900 { 1901 struct felix *felix = ocelot_to_felix(ocelot); 1902 struct dsa_switch *ds = felix->ds; 1903 1904 if (!dsa_is_user_port(ds, port)) 1905 return NULL; 1906 1907 return dsa_to_port(ds, port)->slave; 1908 } 1909 1910 int felix_netdev_to_port(struct net_device *dev) 1911 { 1912 struct dsa_port *dp; 1913 1914 dp = dsa_port_from_netdev(dev); 1915 if (IS_ERR(dp)) 1916 return -EINVAL; 1917 1918 return dp->index; 1919 } 1920