1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2019 NXP Semiconductors 3 * 4 * This is an umbrella module for all network switches that are 5 * register-compatible with Ocelot and that perform I/O to their host CPU 6 * through an NPI (Node Processor Interface) Ethernet port. 7 */ 8 #include <uapi/linux/if_bridge.h> 9 #include <soc/mscc/ocelot_vcap.h> 10 #include <soc/mscc/ocelot_qsys.h> 11 #include <soc/mscc/ocelot_sys.h> 12 #include <soc/mscc/ocelot_dev.h> 13 #include <soc/mscc/ocelot_ana.h> 14 #include <soc/mscc/ocelot_ptp.h> 15 #include <soc/mscc/ocelot.h> 16 #include <linux/platform_device.h> 17 #include <linux/packing.h> 18 #include <linux/module.h> 19 #include <linux/of_net.h> 20 #include <linux/pci.h> 21 #include <linux/of.h> 22 #include <linux/pcs-lynx.h> 23 #include <net/pkt_sched.h> 24 #include <net/dsa.h> 25 #include "felix.h" 26 27 static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds, 28 int port, 29 enum dsa_tag_protocol mp) 30 { 31 return DSA_TAG_PROTO_OCELOT; 32 } 33 34 static int felix_set_ageing_time(struct dsa_switch *ds, 35 unsigned int ageing_time) 36 { 37 struct ocelot *ocelot = ds->priv; 38 39 ocelot_set_ageing_time(ocelot, ageing_time); 40 41 return 0; 42 } 43 44 static int felix_fdb_dump(struct dsa_switch *ds, int port, 45 dsa_fdb_dump_cb_t *cb, void *data) 46 { 47 struct ocelot *ocelot = ds->priv; 48 49 return ocelot_fdb_dump(ocelot, port, cb, data); 50 } 51 52 static int felix_fdb_add(struct dsa_switch *ds, int port, 53 const unsigned char *addr, u16 vid) 54 { 55 struct ocelot *ocelot = ds->priv; 56 57 return ocelot_fdb_add(ocelot, port, addr, vid); 58 } 59 60 static int felix_fdb_del(struct dsa_switch *ds, int port, 61 const unsigned char *addr, u16 vid) 62 { 63 struct ocelot *ocelot = ds->priv; 64 65 return ocelot_fdb_del(ocelot, port, addr, vid); 66 } 67 68 /* This callback needs to be present */ 69 static int felix_mdb_prepare(struct dsa_switch *ds, int port, 70 const struct switchdev_obj_port_mdb *mdb) 71 { 72 return 0; 73 } 74 75 static void felix_mdb_add(struct dsa_switch *ds, int port, 76 const struct switchdev_obj_port_mdb *mdb) 77 { 78 struct ocelot *ocelot = ds->priv; 79 80 ocelot_port_mdb_add(ocelot, port, mdb); 81 } 82 83 static int felix_mdb_del(struct dsa_switch *ds, int port, 84 const struct switchdev_obj_port_mdb *mdb) 85 { 86 struct ocelot *ocelot = ds->priv; 87 88 return ocelot_port_mdb_del(ocelot, port, mdb); 89 } 90 91 static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port, 92 u8 state) 93 { 94 struct ocelot *ocelot = ds->priv; 95 96 return ocelot_bridge_stp_state_set(ocelot, port, state); 97 } 98 99 static int felix_bridge_join(struct dsa_switch *ds, int port, 100 struct net_device *br) 101 { 102 struct ocelot *ocelot = ds->priv; 103 104 return ocelot_port_bridge_join(ocelot, port, br); 105 } 106 107 static void felix_bridge_leave(struct dsa_switch *ds, int port, 108 struct net_device *br) 109 { 110 struct ocelot *ocelot = ds->priv; 111 112 ocelot_port_bridge_leave(ocelot, port, br); 113 } 114 115 static int felix_vlan_prepare(struct dsa_switch *ds, int port, 116 const struct switchdev_obj_port_vlan *vlan) 117 { 118 struct ocelot *ocelot = ds->priv; 119 u16 vid, flags = vlan->flags; 120 int err; 121 122 /* Ocelot switches copy frames as-is to the CPU, so the flags: 123 * egress-untagged or not, pvid or not, make no difference. This 124 * behavior is already better than what DSA just tries to approximate 125 * when it installs the VLAN with the same flags on the CPU port. 126 * Just accept any configuration, and don't let ocelot deny installing 127 * multiple native VLANs on the NPI port, because the switch doesn't 128 * look at the port tag settings towards the NPI interface anyway. 129 */ 130 if (port == ocelot->npi) 131 return 0; 132 133 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 134 err = ocelot_vlan_prepare(ocelot, port, vid, 135 flags & BRIDGE_VLAN_INFO_PVID, 136 flags & BRIDGE_VLAN_INFO_UNTAGGED); 137 if (err) 138 return err; 139 } 140 141 return 0; 142 } 143 144 static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 145 struct switchdev_trans *trans) 146 { 147 struct ocelot *ocelot = ds->priv; 148 149 return ocelot_port_vlan_filtering(ocelot, port, enabled, trans); 150 } 151 152 static void felix_vlan_add(struct dsa_switch *ds, int port, 153 const struct switchdev_obj_port_vlan *vlan) 154 { 155 struct ocelot *ocelot = ds->priv; 156 u16 flags = vlan->flags; 157 u16 vid; 158 int err; 159 160 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 161 err = ocelot_vlan_add(ocelot, port, vid, 162 flags & BRIDGE_VLAN_INFO_PVID, 163 flags & BRIDGE_VLAN_INFO_UNTAGGED); 164 if (err) { 165 dev_err(ds->dev, "Failed to add VLAN %d to port %d: %d\n", 166 vid, port, err); 167 return; 168 } 169 } 170 } 171 172 static int felix_vlan_del(struct dsa_switch *ds, int port, 173 const struct switchdev_obj_port_vlan *vlan) 174 { 175 struct ocelot *ocelot = ds->priv; 176 u16 vid; 177 int err; 178 179 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 180 err = ocelot_vlan_del(ocelot, port, vid); 181 if (err) { 182 dev_err(ds->dev, "Failed to remove VLAN %d from port %d: %d\n", 183 vid, port, err); 184 return err; 185 } 186 } 187 return 0; 188 } 189 190 static int felix_port_enable(struct dsa_switch *ds, int port, 191 struct phy_device *phy) 192 { 193 struct ocelot *ocelot = ds->priv; 194 195 ocelot_port_enable(ocelot, port, phy); 196 197 return 0; 198 } 199 200 static void felix_port_disable(struct dsa_switch *ds, int port) 201 { 202 struct ocelot *ocelot = ds->priv; 203 204 return ocelot_port_disable(ocelot, port); 205 } 206 207 static void felix_phylink_validate(struct dsa_switch *ds, int port, 208 unsigned long *supported, 209 struct phylink_link_state *state) 210 { 211 struct ocelot *ocelot = ds->priv; 212 struct felix *felix = ocelot_to_felix(ocelot); 213 214 if (felix->info->phylink_validate) 215 felix->info->phylink_validate(ocelot, port, supported, state); 216 } 217 218 static void felix_phylink_mac_config(struct dsa_switch *ds, int port, 219 unsigned int link_an_mode, 220 const struct phylink_link_state *state) 221 { 222 struct ocelot *ocelot = ds->priv; 223 struct felix *felix = ocelot_to_felix(ocelot); 224 struct dsa_port *dp = dsa_to_port(ds, port); 225 226 if (felix->pcs[port]) 227 phylink_set_pcs(dp->pl, &felix->pcs[port]->pcs); 228 } 229 230 static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, 231 unsigned int link_an_mode, 232 phy_interface_t interface) 233 { 234 struct ocelot *ocelot = ds->priv; 235 struct ocelot_port *ocelot_port = ocelot->ports[port]; 236 237 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 238 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 239 } 240 241 static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, 242 unsigned int link_an_mode, 243 phy_interface_t interface, 244 struct phy_device *phydev, 245 int speed, int duplex, 246 bool tx_pause, bool rx_pause) 247 { 248 struct ocelot *ocelot = ds->priv; 249 struct ocelot_port *ocelot_port = ocelot->ports[port]; 250 struct felix *felix = ocelot_to_felix(ocelot); 251 u32 mac_fc_cfg; 252 253 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 254 * PORT_RST bits in DEV_CLOCK_CFG. Note that the way this system is 255 * integrated is that the MAC speed is fixed and it's the PCS who is 256 * performing the rate adaptation, so we have to write "1000Mbps" into 257 * the LINK_SPEED field of DEV_CLOCK_CFG (which is also its default 258 * value). 259 */ 260 ocelot_port_writel(ocelot_port, 261 DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000), 262 DEV_CLOCK_CFG); 263 264 switch (speed) { 265 case SPEED_10: 266 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(3); 267 break; 268 case SPEED_100: 269 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(2); 270 break; 271 case SPEED_1000: 272 case SPEED_2500: 273 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(1); 274 break; 275 default: 276 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 277 port, speed); 278 return; 279 } 280 281 /* handle Rx pause in all cases, with 2500base-X this is used for rate 282 * adaptation. 283 */ 284 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 285 286 if (tx_pause) 287 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 288 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 289 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 290 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 291 292 /* Flow control. Link speed is only used here to evaluate the time 293 * specification in incoming pause frames. 294 */ 295 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 296 297 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 298 299 /* Undo the effects of felix_phylink_mac_link_down: 300 * enable MAC module 301 */ 302 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 303 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 304 305 /* Enable receiving frames on the port, and activate auto-learning of 306 * MAC addresses. 307 */ 308 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 309 ANA_PORT_PORT_CFG_RECV_ENA | 310 ANA_PORT_PORT_CFG_PORTID_VAL(port), 311 ANA_PORT_PORT_CFG, port); 312 313 /* Core: Enable port for frame transfer */ 314 ocelot_fields_write(ocelot, port, 315 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 316 317 if (felix->info->port_sched_speed_set) 318 felix->info->port_sched_speed_set(ocelot, port, speed); 319 } 320 321 static void felix_port_qos_map_init(struct ocelot *ocelot, int port) 322 { 323 int i; 324 325 ocelot_rmw_gix(ocelot, 326 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 327 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 328 ANA_PORT_QOS_CFG, 329 port); 330 331 for (i = 0; i < FELIX_NUM_TC * 2; i++) { 332 ocelot_rmw_ix(ocelot, 333 (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) | 334 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i), 335 ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL | 336 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M, 337 ANA_PORT_PCP_DEI_MAP, 338 port, i); 339 } 340 } 341 342 static void felix_get_strings(struct dsa_switch *ds, int port, 343 u32 stringset, u8 *data) 344 { 345 struct ocelot *ocelot = ds->priv; 346 347 return ocelot_get_strings(ocelot, port, stringset, data); 348 } 349 350 static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 351 { 352 struct ocelot *ocelot = ds->priv; 353 354 ocelot_get_ethtool_stats(ocelot, port, data); 355 } 356 357 static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset) 358 { 359 struct ocelot *ocelot = ds->priv; 360 361 return ocelot_get_sset_count(ocelot, port, sset); 362 } 363 364 static int felix_get_ts_info(struct dsa_switch *ds, int port, 365 struct ethtool_ts_info *info) 366 { 367 struct ocelot *ocelot = ds->priv; 368 369 return ocelot_get_ts_info(ocelot, port, info); 370 } 371 372 static int felix_parse_ports_node(struct felix *felix, 373 struct device_node *ports_node, 374 phy_interface_t *port_phy_modes) 375 { 376 struct ocelot *ocelot = &felix->ocelot; 377 struct device *dev = felix->ocelot.dev; 378 struct device_node *child; 379 380 for_each_available_child_of_node(ports_node, child) { 381 phy_interface_t phy_mode; 382 u32 port; 383 int err; 384 385 /* Get switch port number from DT */ 386 if (of_property_read_u32(child, "reg", &port) < 0) { 387 dev_err(dev, "Port number not defined in device tree " 388 "(property \"reg\")\n"); 389 of_node_put(child); 390 return -ENODEV; 391 } 392 393 /* Get PHY mode from DT */ 394 err = of_get_phy_mode(child, &phy_mode); 395 if (err) { 396 dev_err(dev, "Failed to read phy-mode or " 397 "phy-interface-type property for port %d\n", 398 port); 399 of_node_put(child); 400 return -ENODEV; 401 } 402 403 err = felix->info->prevalidate_phy_mode(ocelot, port, phy_mode); 404 if (err < 0) { 405 dev_err(dev, "Unsupported PHY mode %s on port %d\n", 406 phy_modes(phy_mode), port); 407 of_node_put(child); 408 return err; 409 } 410 411 port_phy_modes[port] = phy_mode; 412 } 413 414 return 0; 415 } 416 417 static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes) 418 { 419 struct device *dev = felix->ocelot.dev; 420 struct device_node *switch_node; 421 struct device_node *ports_node; 422 int err; 423 424 switch_node = dev->of_node; 425 426 ports_node = of_get_child_by_name(switch_node, "ports"); 427 if (!ports_node) { 428 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n"); 429 return -ENODEV; 430 } 431 432 err = felix_parse_ports_node(felix, ports_node, port_phy_modes); 433 of_node_put(ports_node); 434 435 return err; 436 } 437 438 static int felix_init_structs(struct felix *felix, int num_phys_ports) 439 { 440 struct ocelot *ocelot = &felix->ocelot; 441 phy_interface_t *port_phy_modes; 442 struct resource res; 443 int port, i, err; 444 445 ocelot->num_phys_ports = num_phys_ports; 446 ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports, 447 sizeof(struct ocelot_port *), GFP_KERNEL); 448 if (!ocelot->ports) 449 return -ENOMEM; 450 451 ocelot->map = felix->info->map; 452 ocelot->stats_layout = felix->info->stats_layout; 453 ocelot->num_stats = felix->info->num_stats; 454 ocelot->shared_queue_sz = felix->info->shared_queue_sz; 455 ocelot->num_mact_rows = felix->info->num_mact_rows; 456 ocelot->vcap = felix->info->vcap; 457 ocelot->ops = felix->info->ops; 458 ocelot->inj_prefix = OCELOT_TAG_PREFIX_SHORT; 459 ocelot->xtr_prefix = OCELOT_TAG_PREFIX_SHORT; 460 461 port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t), 462 GFP_KERNEL); 463 if (!port_phy_modes) 464 return -ENOMEM; 465 466 err = felix_parse_dt(felix, port_phy_modes); 467 if (err) { 468 kfree(port_phy_modes); 469 return err; 470 } 471 472 for (i = 0; i < TARGET_MAX; i++) { 473 struct regmap *target; 474 475 if (!felix->info->target_io_res[i].name) 476 continue; 477 478 memcpy(&res, &felix->info->target_io_res[i], sizeof(res)); 479 res.flags = IORESOURCE_MEM; 480 res.start += felix->switch_base; 481 res.end += felix->switch_base; 482 483 target = ocelot_regmap_init(ocelot, &res); 484 if (IS_ERR(target)) { 485 dev_err(ocelot->dev, 486 "Failed to map device memory space\n"); 487 kfree(port_phy_modes); 488 return PTR_ERR(target); 489 } 490 491 ocelot->targets[i] = target; 492 } 493 494 err = ocelot_regfields_init(ocelot, felix->info->regfields); 495 if (err) { 496 dev_err(ocelot->dev, "failed to init reg fields map\n"); 497 kfree(port_phy_modes); 498 return err; 499 } 500 501 for (port = 0; port < num_phys_ports; port++) { 502 struct ocelot_port *ocelot_port; 503 struct regmap *target; 504 u8 *template; 505 506 ocelot_port = devm_kzalloc(ocelot->dev, 507 sizeof(struct ocelot_port), 508 GFP_KERNEL); 509 if (!ocelot_port) { 510 dev_err(ocelot->dev, 511 "failed to allocate port memory\n"); 512 kfree(port_phy_modes); 513 return -ENOMEM; 514 } 515 516 memcpy(&res, &felix->info->port_io_res[port], sizeof(res)); 517 res.flags = IORESOURCE_MEM; 518 res.start += felix->switch_base; 519 res.end += felix->switch_base; 520 521 target = ocelot_regmap_init(ocelot, &res); 522 if (IS_ERR(target)) { 523 dev_err(ocelot->dev, 524 "Failed to map memory space for port %d\n", 525 port); 526 kfree(port_phy_modes); 527 return PTR_ERR(target); 528 } 529 530 template = devm_kzalloc(ocelot->dev, OCELOT_TOTAL_TAG_LEN, 531 GFP_KERNEL); 532 if (!template) { 533 dev_err(ocelot->dev, 534 "Failed to allocate memory for DSA tag\n"); 535 kfree(port_phy_modes); 536 return -ENOMEM; 537 } 538 539 ocelot_port->phy_mode = port_phy_modes[port]; 540 ocelot_port->ocelot = ocelot; 541 ocelot_port->target = target; 542 ocelot_port->xmit_template = template; 543 ocelot->ports[port] = ocelot_port; 544 545 felix->info->xmit_template_populate(ocelot, port); 546 } 547 548 kfree(port_phy_modes); 549 550 if (felix->info->mdio_bus_alloc) { 551 err = felix->info->mdio_bus_alloc(ocelot); 552 if (err < 0) 553 return err; 554 } 555 556 return 0; 557 } 558 559 /* The CPU port module is connected to the Node Processor Interface (NPI). This 560 * is the mode through which frames can be injected from and extracted to an 561 * external CPU, over Ethernet. 562 */ 563 static void felix_npi_port_init(struct ocelot *ocelot, int port) 564 { 565 ocelot->npi = port; 566 567 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 568 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(port), 569 QSYS_EXT_CPU_CFG); 570 571 /* NPI port Injection/Extraction configuration */ 572 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 573 ocelot->xtr_prefix); 574 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 575 ocelot->inj_prefix); 576 577 /* Disable transmission of pause frames */ 578 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 579 } 580 581 /* Hardware initialization done here so that we can allocate structures with 582 * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing 583 * us to allocate structures twice (leak memory) and map PCI memory twice 584 * (which will not work). 585 */ 586 static int felix_setup(struct dsa_switch *ds) 587 { 588 struct ocelot *ocelot = ds->priv; 589 struct felix *felix = ocelot_to_felix(ocelot); 590 int port, err; 591 592 err = felix_init_structs(felix, ds->num_ports); 593 if (err) 594 return err; 595 596 err = ocelot_init(ocelot); 597 if (err) 598 return err; 599 600 if (ocelot->ptp) { 601 err = ocelot_init_timestamp(ocelot, felix->info->ptp_caps); 602 if (err) { 603 dev_err(ocelot->dev, 604 "Timestamp initialization failed\n"); 605 ocelot->ptp = 0; 606 } 607 } 608 609 for (port = 0; port < ds->num_ports; port++) { 610 ocelot_init_port(ocelot, port); 611 612 if (dsa_is_cpu_port(ds, port)) 613 felix_npi_port_init(ocelot, port); 614 615 /* Set the default QoS Classification based on PCP and DEI 616 * bits of vlan tag. 617 */ 618 felix_port_qos_map_init(ocelot, port); 619 } 620 621 /* Include the CPU port module in the forwarding mask for unknown 622 * unicast - the hardware default value for ANA_FLOODING_FLD_UNICAST 623 * excludes BIT(ocelot->num_phys_ports), and so does ocelot_init, since 624 * Ocelot relies on whitelisting MAC addresses towards PGID_CPU. 625 */ 626 ocelot_write_rix(ocelot, 627 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 628 ANA_PGID_PGID, PGID_UC); 629 630 ds->mtu_enforcement_ingress = true; 631 ds->configure_vlan_while_not_filtering = true; 632 633 return 0; 634 } 635 636 static void felix_teardown(struct dsa_switch *ds) 637 { 638 struct ocelot *ocelot = ds->priv; 639 struct felix *felix = ocelot_to_felix(ocelot); 640 int port; 641 642 if (felix->info->mdio_bus_free) 643 felix->info->mdio_bus_free(ocelot); 644 645 for (port = 0; port < ocelot->num_phys_ports; port++) 646 ocelot_deinit_port(ocelot, port); 647 ocelot_deinit_timestamp(ocelot); 648 /* stop workqueue thread */ 649 ocelot_deinit(ocelot); 650 } 651 652 static int felix_hwtstamp_get(struct dsa_switch *ds, int port, 653 struct ifreq *ifr) 654 { 655 struct ocelot *ocelot = ds->priv; 656 657 return ocelot_hwstamp_get(ocelot, port, ifr); 658 } 659 660 static int felix_hwtstamp_set(struct dsa_switch *ds, int port, 661 struct ifreq *ifr) 662 { 663 struct ocelot *ocelot = ds->priv; 664 665 return ocelot_hwstamp_set(ocelot, port, ifr); 666 } 667 668 static bool felix_rxtstamp(struct dsa_switch *ds, int port, 669 struct sk_buff *skb, unsigned int type) 670 { 671 struct skb_shared_hwtstamps *shhwtstamps; 672 struct ocelot *ocelot = ds->priv; 673 u8 *extraction = skb->data - ETH_HLEN - OCELOT_TAG_LEN; 674 u32 tstamp_lo, tstamp_hi; 675 struct timespec64 ts; 676 u64 tstamp, val; 677 678 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 679 tstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 680 681 packing(extraction, &val, 116, 85, OCELOT_TAG_LEN, UNPACK, 0); 682 tstamp_lo = (u32)val; 683 684 tstamp_hi = tstamp >> 32; 685 if ((tstamp & 0xffffffff) < tstamp_lo) 686 tstamp_hi--; 687 688 tstamp = ((u64)tstamp_hi << 32) | tstamp_lo; 689 690 shhwtstamps = skb_hwtstamps(skb); 691 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 692 shhwtstamps->hwtstamp = tstamp; 693 return false; 694 } 695 696 static bool felix_txtstamp(struct dsa_switch *ds, int port, 697 struct sk_buff *clone, unsigned int type) 698 { 699 struct ocelot *ocelot = ds->priv; 700 struct ocelot_port *ocelot_port = ocelot->ports[port]; 701 702 if (ocelot->ptp && (skb_shinfo(clone)->tx_flags & SKBTX_HW_TSTAMP) && 703 ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 704 ocelot_port_add_txtstamp_skb(ocelot, port, clone); 705 return true; 706 } 707 708 return false; 709 } 710 711 static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 712 { 713 struct ocelot *ocelot = ds->priv; 714 715 ocelot_port_set_maxlen(ocelot, port, new_mtu); 716 717 return 0; 718 } 719 720 static int felix_get_max_mtu(struct dsa_switch *ds, int port) 721 { 722 struct ocelot *ocelot = ds->priv; 723 724 return ocelot_get_max_mtu(ocelot, port); 725 } 726 727 static int felix_cls_flower_add(struct dsa_switch *ds, int port, 728 struct flow_cls_offload *cls, bool ingress) 729 { 730 struct ocelot *ocelot = ds->priv; 731 732 return ocelot_cls_flower_replace(ocelot, port, cls, ingress); 733 } 734 735 static int felix_cls_flower_del(struct dsa_switch *ds, int port, 736 struct flow_cls_offload *cls, bool ingress) 737 { 738 struct ocelot *ocelot = ds->priv; 739 740 return ocelot_cls_flower_destroy(ocelot, port, cls, ingress); 741 } 742 743 static int felix_cls_flower_stats(struct dsa_switch *ds, int port, 744 struct flow_cls_offload *cls, bool ingress) 745 { 746 struct ocelot *ocelot = ds->priv; 747 748 return ocelot_cls_flower_stats(ocelot, port, cls, ingress); 749 } 750 751 static int felix_port_policer_add(struct dsa_switch *ds, int port, 752 struct dsa_mall_policer_tc_entry *policer) 753 { 754 struct ocelot *ocelot = ds->priv; 755 struct ocelot_policer pol = { 756 .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8, 757 .burst = policer->burst, 758 }; 759 760 return ocelot_port_policer_add(ocelot, port, &pol); 761 } 762 763 static void felix_port_policer_del(struct dsa_switch *ds, int port) 764 { 765 struct ocelot *ocelot = ds->priv; 766 767 ocelot_port_policer_del(ocelot, port); 768 } 769 770 static int felix_port_setup_tc(struct dsa_switch *ds, int port, 771 enum tc_setup_type type, 772 void *type_data) 773 { 774 struct ocelot *ocelot = ds->priv; 775 struct felix *felix = ocelot_to_felix(ocelot); 776 777 if (felix->info->port_setup_tc) 778 return felix->info->port_setup_tc(ds, port, type, type_data); 779 else 780 return -EOPNOTSUPP; 781 } 782 783 const struct dsa_switch_ops felix_switch_ops = { 784 .get_tag_protocol = felix_get_tag_protocol, 785 .setup = felix_setup, 786 .teardown = felix_teardown, 787 .set_ageing_time = felix_set_ageing_time, 788 .get_strings = felix_get_strings, 789 .get_ethtool_stats = felix_get_ethtool_stats, 790 .get_sset_count = felix_get_sset_count, 791 .get_ts_info = felix_get_ts_info, 792 .phylink_validate = felix_phylink_validate, 793 .phylink_mac_config = felix_phylink_mac_config, 794 .phylink_mac_link_down = felix_phylink_mac_link_down, 795 .phylink_mac_link_up = felix_phylink_mac_link_up, 796 .port_enable = felix_port_enable, 797 .port_disable = felix_port_disable, 798 .port_fdb_dump = felix_fdb_dump, 799 .port_fdb_add = felix_fdb_add, 800 .port_fdb_del = felix_fdb_del, 801 .port_mdb_prepare = felix_mdb_prepare, 802 .port_mdb_add = felix_mdb_add, 803 .port_mdb_del = felix_mdb_del, 804 .port_bridge_join = felix_bridge_join, 805 .port_bridge_leave = felix_bridge_leave, 806 .port_stp_state_set = felix_bridge_stp_state_set, 807 .port_vlan_prepare = felix_vlan_prepare, 808 .port_vlan_filtering = felix_vlan_filtering, 809 .port_vlan_add = felix_vlan_add, 810 .port_vlan_del = felix_vlan_del, 811 .port_hwtstamp_get = felix_hwtstamp_get, 812 .port_hwtstamp_set = felix_hwtstamp_set, 813 .port_rxtstamp = felix_rxtstamp, 814 .port_txtstamp = felix_txtstamp, 815 .port_change_mtu = felix_change_mtu, 816 .port_max_mtu = felix_get_max_mtu, 817 .port_policer_add = felix_port_policer_add, 818 .port_policer_del = felix_port_policer_del, 819 .cls_flower_add = felix_cls_flower_add, 820 .cls_flower_del = felix_cls_flower_del, 821 .cls_flower_stats = felix_cls_flower_stats, 822 .port_setup_tc = felix_port_setup_tc, 823 }; 824 825 struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port) 826 { 827 struct felix *felix = ocelot_to_felix(ocelot); 828 struct dsa_switch *ds = felix->ds; 829 830 if (!dsa_is_user_port(ds, port)) 831 return NULL; 832 833 return dsa_to_port(ds, port)->slave; 834 } 835 836 int felix_netdev_to_port(struct net_device *dev) 837 { 838 struct dsa_port *dp; 839 840 dp = dsa_port_from_netdev(dev); 841 if (IS_ERR(dp)) 842 return -EINVAL; 843 844 return dp->index; 845 } 846