1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2019-2021 NXP 3 * 4 * This is an umbrella module for all network switches that are 5 * register-compatible with Ocelot and that perform I/O to their host CPU 6 * through an NPI (Node Processor Interface) Ethernet port. 7 */ 8 #include <uapi/linux/if_bridge.h> 9 #include <soc/mscc/ocelot_vcap.h> 10 #include <soc/mscc/ocelot_qsys.h> 11 #include <soc/mscc/ocelot_sys.h> 12 #include <soc/mscc/ocelot_dev.h> 13 #include <soc/mscc/ocelot_ana.h> 14 #include <soc/mscc/ocelot_ptp.h> 15 #include <soc/mscc/ocelot.h> 16 #include <linux/dsa/8021q.h> 17 #include <linux/dsa/ocelot.h> 18 #include <linux/platform_device.h> 19 #include <linux/ptp_classify.h> 20 #include <linux/module.h> 21 #include <linux/of_net.h> 22 #include <linux/pci.h> 23 #include <linux/of.h> 24 #include <net/pkt_sched.h> 25 #include <net/dsa.h> 26 #include "felix.h" 27 28 /* Translate the DSA database API into the ocelot switch library API, 29 * which uses VID 0 for all ports that aren't part of a bridge, 30 * and expects the bridge_dev to be NULL in that case. 31 */ 32 static struct net_device *felix_classify_db(struct dsa_db db) 33 { 34 switch (db.type) { 35 case DSA_DB_PORT: 36 case DSA_DB_LAG: 37 return NULL; 38 case DSA_DB_BRIDGE: 39 return db.bridge.dev; 40 default: 41 return ERR_PTR(-EOPNOTSUPP); 42 } 43 } 44 45 /* We are called before felix_npi_port_init(), so ocelot->npi is -1. */ 46 static int felix_migrate_fdbs_to_npi_port(struct dsa_switch *ds, int port, 47 const unsigned char *addr, u16 vid, 48 struct dsa_db db) 49 { 50 struct net_device *bridge_dev = felix_classify_db(db); 51 struct ocelot *ocelot = ds->priv; 52 int cpu = ocelot->num_phys_ports; 53 int err; 54 55 err = ocelot_fdb_del(ocelot, port, addr, vid, bridge_dev); 56 if (err) 57 return err; 58 59 return ocelot_fdb_add(ocelot, cpu, addr, vid, bridge_dev); 60 } 61 62 static int felix_migrate_mdbs_to_npi_port(struct dsa_switch *ds, int port, 63 const unsigned char *addr, u16 vid, 64 struct dsa_db db) 65 { 66 struct net_device *bridge_dev = felix_classify_db(db); 67 struct switchdev_obj_port_mdb mdb; 68 struct ocelot *ocelot = ds->priv; 69 int cpu = ocelot->num_phys_ports; 70 int err; 71 72 memset(&mdb, 0, sizeof(mdb)); 73 ether_addr_copy(mdb.addr, addr); 74 mdb.vid = vid; 75 76 err = ocelot_port_mdb_del(ocelot, port, &mdb, bridge_dev); 77 if (err) 78 return err; 79 80 return ocelot_port_mdb_add(ocelot, cpu, &mdb, bridge_dev); 81 } 82 83 static void felix_migrate_pgid_bit(struct dsa_switch *ds, int from, int to, 84 int pgid) 85 { 86 struct ocelot *ocelot = ds->priv; 87 bool on; 88 u32 val; 89 90 val = ocelot_read_rix(ocelot, ANA_PGID_PGID, pgid); 91 on = !!(val & BIT(from)); 92 val &= ~BIT(from); 93 if (on) 94 val |= BIT(to); 95 else 96 val &= ~BIT(to); 97 98 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, pgid); 99 } 100 101 static void felix_migrate_flood_to_npi_port(struct dsa_switch *ds, int port) 102 { 103 struct ocelot *ocelot = ds->priv; 104 105 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_UC); 106 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_MC); 107 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_BC); 108 } 109 110 static void 111 felix_migrate_flood_to_tag_8021q_port(struct dsa_switch *ds, int port) 112 { 113 struct ocelot *ocelot = ds->priv; 114 115 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_UC); 116 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_MC); 117 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_BC); 118 } 119 120 /* ocelot->npi was already set to -1 by felix_npi_port_deinit, so 121 * ocelot_fdb_add() will not redirect FDB entries towards the 122 * CPU port module here, which is what we want. 123 */ 124 static int 125 felix_migrate_fdbs_to_tag_8021q_port(struct dsa_switch *ds, int port, 126 const unsigned char *addr, u16 vid, 127 struct dsa_db db) 128 { 129 struct net_device *bridge_dev = felix_classify_db(db); 130 struct ocelot *ocelot = ds->priv; 131 int cpu = ocelot->num_phys_ports; 132 int err; 133 134 err = ocelot_fdb_del(ocelot, cpu, addr, vid, bridge_dev); 135 if (err) 136 return err; 137 138 return ocelot_fdb_add(ocelot, port, addr, vid, bridge_dev); 139 } 140 141 static int 142 felix_migrate_mdbs_to_tag_8021q_port(struct dsa_switch *ds, int port, 143 const unsigned char *addr, u16 vid, 144 struct dsa_db db) 145 { 146 struct net_device *bridge_dev = felix_classify_db(db); 147 struct switchdev_obj_port_mdb mdb; 148 struct ocelot *ocelot = ds->priv; 149 int cpu = ocelot->num_phys_ports; 150 int err; 151 152 memset(&mdb, 0, sizeof(mdb)); 153 ether_addr_copy(mdb.addr, addr); 154 mdb.vid = vid; 155 156 err = ocelot_port_mdb_del(ocelot, cpu, &mdb, bridge_dev); 157 if (err) 158 return err; 159 160 return ocelot_port_mdb_add(ocelot, port, &mdb, bridge_dev); 161 } 162 163 /* Set up VCAP ES0 rules for pushing a tag_8021q VLAN towards the CPU such that 164 * the tagger can perform RX source port identification. 165 */ 166 static int felix_tag_8021q_vlan_add_rx(struct felix *felix, int port, u16 vid) 167 { 168 struct ocelot_vcap_filter *outer_tagging_rule; 169 struct ocelot *ocelot = &felix->ocelot; 170 struct dsa_switch *ds = felix->ds; 171 int key_length, upstream, err; 172 173 key_length = ocelot->vcap[VCAP_ES0].keys[VCAP_ES0_IGR_PORT].length; 174 upstream = dsa_upstream_port(ds, port); 175 176 outer_tagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), 177 GFP_KERNEL); 178 if (!outer_tagging_rule) 179 return -ENOMEM; 180 181 outer_tagging_rule->key_type = OCELOT_VCAP_KEY_ANY; 182 outer_tagging_rule->prio = 1; 183 outer_tagging_rule->id.cookie = OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port); 184 outer_tagging_rule->id.tc_offload = false; 185 outer_tagging_rule->block_id = VCAP_ES0; 186 outer_tagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 187 outer_tagging_rule->lookup = 0; 188 outer_tagging_rule->ingress_port.value = port; 189 outer_tagging_rule->ingress_port.mask = GENMASK(key_length - 1, 0); 190 outer_tagging_rule->egress_port.value = upstream; 191 outer_tagging_rule->egress_port.mask = GENMASK(key_length - 1, 0); 192 outer_tagging_rule->action.push_outer_tag = OCELOT_ES0_TAG; 193 outer_tagging_rule->action.tag_a_tpid_sel = OCELOT_TAG_TPID_SEL_8021AD; 194 outer_tagging_rule->action.tag_a_vid_sel = 1; 195 outer_tagging_rule->action.vid_a_val = vid; 196 197 err = ocelot_vcap_filter_add(ocelot, outer_tagging_rule, NULL); 198 if (err) 199 kfree(outer_tagging_rule); 200 201 return err; 202 } 203 204 static int felix_tag_8021q_vlan_del_rx(struct felix *felix, int port, u16 vid) 205 { 206 struct ocelot_vcap_filter *outer_tagging_rule; 207 struct ocelot_vcap_block *block_vcap_es0; 208 struct ocelot *ocelot = &felix->ocelot; 209 210 block_vcap_es0 = &ocelot->block[VCAP_ES0]; 211 212 outer_tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_es0, 213 port, false); 214 if (!outer_tagging_rule) 215 return -ENOENT; 216 217 return ocelot_vcap_filter_del(ocelot, outer_tagging_rule); 218 } 219 220 /* Set up VCAP IS1 rules for stripping the tag_8021q VLAN on TX and VCAP IS2 221 * rules for steering those tagged packets towards the correct destination port 222 */ 223 static int felix_tag_8021q_vlan_add_tx(struct felix *felix, int port, u16 vid) 224 { 225 struct ocelot_vcap_filter *untagging_rule, *redirect_rule; 226 struct ocelot *ocelot = &felix->ocelot; 227 struct dsa_switch *ds = felix->ds; 228 int upstream, err; 229 230 untagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); 231 if (!untagging_rule) 232 return -ENOMEM; 233 234 redirect_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); 235 if (!redirect_rule) { 236 kfree(untagging_rule); 237 return -ENOMEM; 238 } 239 240 upstream = dsa_upstream_port(ds, port); 241 242 untagging_rule->key_type = OCELOT_VCAP_KEY_ANY; 243 untagging_rule->ingress_port_mask = BIT(upstream); 244 untagging_rule->vlan.vid.value = vid; 245 untagging_rule->vlan.vid.mask = VLAN_VID_MASK; 246 untagging_rule->prio = 1; 247 untagging_rule->id.cookie = OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port); 248 untagging_rule->id.tc_offload = false; 249 untagging_rule->block_id = VCAP_IS1; 250 untagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 251 untagging_rule->lookup = 0; 252 untagging_rule->action.vlan_pop_cnt_ena = true; 253 untagging_rule->action.vlan_pop_cnt = 1; 254 untagging_rule->action.pag_override_mask = 0xff; 255 untagging_rule->action.pag_val = port; 256 257 err = ocelot_vcap_filter_add(ocelot, untagging_rule, NULL); 258 if (err) { 259 kfree(untagging_rule); 260 kfree(redirect_rule); 261 return err; 262 } 263 264 redirect_rule->key_type = OCELOT_VCAP_KEY_ANY; 265 redirect_rule->ingress_port_mask = BIT(upstream); 266 redirect_rule->pag = port; 267 redirect_rule->prio = 1; 268 redirect_rule->id.cookie = OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port); 269 redirect_rule->id.tc_offload = false; 270 redirect_rule->block_id = VCAP_IS2; 271 redirect_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 272 redirect_rule->lookup = 0; 273 redirect_rule->action.mask_mode = OCELOT_MASK_MODE_REDIRECT; 274 redirect_rule->action.port_mask = BIT(port); 275 276 err = ocelot_vcap_filter_add(ocelot, redirect_rule, NULL); 277 if (err) { 278 ocelot_vcap_filter_del(ocelot, untagging_rule); 279 kfree(redirect_rule); 280 return err; 281 } 282 283 return 0; 284 } 285 286 static int felix_tag_8021q_vlan_del_tx(struct felix *felix, int port, u16 vid) 287 { 288 struct ocelot_vcap_filter *untagging_rule, *redirect_rule; 289 struct ocelot_vcap_block *block_vcap_is1; 290 struct ocelot_vcap_block *block_vcap_is2; 291 struct ocelot *ocelot = &felix->ocelot; 292 int err; 293 294 block_vcap_is1 = &ocelot->block[VCAP_IS1]; 295 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 296 297 untagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is1, 298 port, false); 299 if (!untagging_rule) 300 return -ENOENT; 301 302 err = ocelot_vcap_filter_del(ocelot, untagging_rule); 303 if (err) 304 return err; 305 306 redirect_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, 307 port, false); 308 if (!redirect_rule) 309 return -ENOENT; 310 311 return ocelot_vcap_filter_del(ocelot, redirect_rule); 312 } 313 314 static int felix_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 315 u16 flags) 316 { 317 struct ocelot *ocelot = ds->priv; 318 int err; 319 320 /* tag_8021q.c assumes we are implementing this via port VLAN 321 * membership, which we aren't. So we don't need to add any VCAP filter 322 * for the CPU port. 323 */ 324 if (!dsa_is_user_port(ds, port)) 325 return 0; 326 327 err = felix_tag_8021q_vlan_add_rx(ocelot_to_felix(ocelot), port, vid); 328 if (err) 329 return err; 330 331 err = felix_tag_8021q_vlan_add_tx(ocelot_to_felix(ocelot), port, vid); 332 if (err) { 333 felix_tag_8021q_vlan_del_rx(ocelot_to_felix(ocelot), port, vid); 334 return err; 335 } 336 337 return 0; 338 } 339 340 static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 341 { 342 struct ocelot *ocelot = ds->priv; 343 int err; 344 345 if (!dsa_is_user_port(ds, port)) 346 return 0; 347 348 err = felix_tag_8021q_vlan_del_rx(ocelot_to_felix(ocelot), port, vid); 349 if (err) 350 return err; 351 352 err = felix_tag_8021q_vlan_del_tx(ocelot_to_felix(ocelot), port, vid); 353 if (err) { 354 felix_tag_8021q_vlan_add_rx(ocelot_to_felix(ocelot), port, vid); 355 return err; 356 } 357 358 return 0; 359 } 360 361 /* Alternatively to using the NPI functionality, that same hardware MAC 362 * connected internally to the enetc or fman DSA master can be configured to 363 * use the software-defined tag_8021q frame format. As far as the hardware is 364 * concerned, it thinks it is a "dumb switch" - the queues of the CPU port 365 * module are now disconnected from it, but can still be accessed through 366 * register-based MMIO. 367 */ 368 static void felix_8021q_cpu_port_init(struct ocelot *ocelot, int port) 369 { 370 mutex_lock(&ocelot->fwd_domain_lock); 371 372 ocelot_port_set_dsa_8021q_cpu(ocelot, port); 373 374 /* Overwrite PGID_CPU with the non-tagging port */ 375 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, PGID_CPU); 376 377 ocelot_apply_bridge_fwd_mask(ocelot, true); 378 379 mutex_unlock(&ocelot->fwd_domain_lock); 380 } 381 382 static void felix_8021q_cpu_port_deinit(struct ocelot *ocelot, int port) 383 { 384 mutex_lock(&ocelot->fwd_domain_lock); 385 386 ocelot_port_unset_dsa_8021q_cpu(ocelot, port); 387 388 /* Restore PGID_CPU */ 389 ocelot_write_rix(ocelot, BIT(ocelot->num_phys_ports), ANA_PGID_PGID, 390 PGID_CPU); 391 392 ocelot_apply_bridge_fwd_mask(ocelot, true); 393 394 mutex_unlock(&ocelot->fwd_domain_lock); 395 } 396 397 /* On switches with no extraction IRQ wired, trapped packets need to be 398 * replicated over Ethernet as well, otherwise we'd get no notification of 399 * their arrival when using the ocelot-8021q tagging protocol. 400 */ 401 static int felix_update_trapping_destinations(struct dsa_switch *ds, 402 bool using_tag_8021q) 403 { 404 struct ocelot *ocelot = ds->priv; 405 struct felix *felix = ocelot_to_felix(ocelot); 406 struct ocelot_vcap_filter *trap; 407 enum ocelot_mask_mode mask_mode; 408 unsigned long port_mask; 409 struct dsa_port *dp; 410 bool cpu_copy_ena; 411 int cpu = -1, err; 412 413 if (!felix->info->quirk_no_xtr_irq) 414 return 0; 415 416 /* Figure out the current CPU port */ 417 dsa_switch_for_each_cpu_port(dp, ds) { 418 cpu = dp->index; 419 break; 420 } 421 422 /* We are sure that "cpu" was found, otherwise 423 * dsa_tree_setup_default_cpu() would have failed earlier. 424 */ 425 426 /* Make sure all traps are set up for that destination */ 427 list_for_each_entry(trap, &ocelot->traps, trap_list) { 428 /* Figure out the current trapping destination */ 429 if (using_tag_8021q) { 430 /* Redirect to the tag_8021q CPU port. If timestamps 431 * are necessary, also copy trapped packets to the CPU 432 * port module. 433 */ 434 mask_mode = OCELOT_MASK_MODE_REDIRECT; 435 port_mask = BIT(cpu); 436 cpu_copy_ena = !!trap->take_ts; 437 } else { 438 /* Trap packets only to the CPU port module, which is 439 * redirected to the NPI port (the DSA CPU port) 440 */ 441 mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 442 port_mask = 0; 443 cpu_copy_ena = true; 444 } 445 446 if (trap->action.mask_mode == mask_mode && 447 trap->action.port_mask == port_mask && 448 trap->action.cpu_copy_ena == cpu_copy_ena) 449 continue; 450 451 trap->action.mask_mode = mask_mode; 452 trap->action.port_mask = port_mask; 453 trap->action.cpu_copy_ena = cpu_copy_ena; 454 455 err = ocelot_vcap_filter_replace(ocelot, trap); 456 if (err) 457 return err; 458 } 459 460 return 0; 461 } 462 463 static int felix_setup_tag_8021q(struct dsa_switch *ds, int cpu) 464 { 465 struct ocelot *ocelot = ds->priv; 466 struct dsa_port *dp; 467 int err; 468 469 felix_8021q_cpu_port_init(ocelot, cpu); 470 471 dsa_switch_for_each_available_port(dp, ds) { 472 /* This overwrites ocelot_init(): 473 * Do not forward BPDU frames to the CPU port module, 474 * for 2 reasons: 475 * - When these packets are injected from the tag_8021q 476 * CPU port, we want them to go out, not loop back 477 * into the system. 478 * - STP traffic ingressing on a user port should go to 479 * the tag_8021q CPU port, not to the hardware CPU 480 * port module. 481 */ 482 ocelot_write_gix(ocelot, 483 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0), 484 ANA_PORT_CPU_FWD_BPDU_CFG, dp->index); 485 } 486 487 err = dsa_tag_8021q_register(ds, htons(ETH_P_8021AD)); 488 if (err) 489 return err; 490 491 err = dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_tag_8021q_port); 492 if (err) 493 goto out_tag_8021q_unregister; 494 495 err = dsa_port_walk_mdbs(ds, cpu, felix_migrate_mdbs_to_tag_8021q_port); 496 if (err) 497 goto out_migrate_fdbs; 498 499 felix_migrate_flood_to_tag_8021q_port(ds, cpu); 500 501 err = felix_update_trapping_destinations(ds, true); 502 if (err) 503 goto out_migrate_flood; 504 505 /* The ownership of the CPU port module's queues might have just been 506 * transferred to the tag_8021q tagger from the NPI-based tagger. 507 * So there might still be all sorts of crap in the queues. On the 508 * other hand, the MMIO-based matching of PTP frames is very brittle, 509 * so we need to be careful that there are no extra frames to be 510 * dequeued over MMIO, since we would never know to discard them. 511 */ 512 ocelot_drain_cpu_queue(ocelot, 0); 513 514 return 0; 515 516 out_migrate_flood: 517 felix_migrate_flood_to_npi_port(ds, cpu); 518 dsa_port_walk_mdbs(ds, cpu, felix_migrate_mdbs_to_npi_port); 519 out_migrate_fdbs: 520 dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_npi_port); 521 out_tag_8021q_unregister: 522 dsa_tag_8021q_unregister(ds); 523 return err; 524 } 525 526 static void felix_teardown_tag_8021q(struct dsa_switch *ds, int cpu) 527 { 528 struct ocelot *ocelot = ds->priv; 529 struct dsa_port *dp; 530 int err; 531 532 err = felix_update_trapping_destinations(ds, false); 533 if (err) 534 dev_err(ds->dev, "felix_teardown_mmio_filtering returned %d", 535 err); 536 537 dsa_tag_8021q_unregister(ds); 538 539 dsa_switch_for_each_available_port(dp, ds) { 540 /* Restore the logic from ocelot_init: 541 * do not forward BPDU frames to the front ports. 542 */ 543 ocelot_write_gix(ocelot, 544 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 545 ANA_PORT_CPU_FWD_BPDU_CFG, 546 dp->index); 547 } 548 549 felix_8021q_cpu_port_deinit(ocelot, cpu); 550 } 551 552 /* The CPU port module is connected to the Node Processor Interface (NPI). This 553 * is the mode through which frames can be injected from and extracted to an 554 * external CPU, over Ethernet. In NXP SoCs, the "external CPU" is the ARM CPU 555 * running Linux, and this forms a DSA setup together with the enetc or fman 556 * DSA master. 557 */ 558 static void felix_npi_port_init(struct ocelot *ocelot, int port) 559 { 560 ocelot->npi = port; 561 562 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 563 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(port), 564 QSYS_EXT_CPU_CFG); 565 566 /* NPI port Injection/Extraction configuration */ 567 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 568 ocelot->npi_xtr_prefix); 569 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 570 ocelot->npi_inj_prefix); 571 572 /* Disable transmission of pause frames */ 573 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 574 } 575 576 static void felix_npi_port_deinit(struct ocelot *ocelot, int port) 577 { 578 /* Restore hardware defaults */ 579 int unused_port = ocelot->num_phys_ports + 2; 580 581 ocelot->npi = -1; 582 583 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPU_PORT(unused_port), 584 QSYS_EXT_CPU_CFG); 585 586 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 587 OCELOT_TAG_PREFIX_DISABLED); 588 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 589 OCELOT_TAG_PREFIX_DISABLED); 590 591 /* Enable transmission of pause frames */ 592 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 593 } 594 595 static int felix_setup_tag_npi(struct dsa_switch *ds, int cpu) 596 { 597 struct ocelot *ocelot = ds->priv; 598 int err; 599 600 err = dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_npi_port); 601 if (err) 602 return err; 603 604 err = dsa_port_walk_mdbs(ds, cpu, felix_migrate_mdbs_to_npi_port); 605 if (err) 606 goto out_migrate_fdbs; 607 608 felix_migrate_flood_to_npi_port(ds, cpu); 609 610 felix_npi_port_init(ocelot, cpu); 611 612 return 0; 613 614 out_migrate_fdbs: 615 dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_tag_8021q_port); 616 617 return err; 618 } 619 620 static void felix_teardown_tag_npi(struct dsa_switch *ds, int cpu) 621 { 622 struct ocelot *ocelot = ds->priv; 623 624 felix_npi_port_deinit(ocelot, cpu); 625 } 626 627 static int felix_set_tag_protocol(struct dsa_switch *ds, int cpu, 628 enum dsa_tag_protocol proto) 629 { 630 int err; 631 632 switch (proto) { 633 case DSA_TAG_PROTO_SEVILLE: 634 case DSA_TAG_PROTO_OCELOT: 635 err = felix_setup_tag_npi(ds, cpu); 636 break; 637 case DSA_TAG_PROTO_OCELOT_8021Q: 638 err = felix_setup_tag_8021q(ds, cpu); 639 break; 640 default: 641 err = -EPROTONOSUPPORT; 642 } 643 644 return err; 645 } 646 647 static void felix_del_tag_protocol(struct dsa_switch *ds, int cpu, 648 enum dsa_tag_protocol proto) 649 { 650 switch (proto) { 651 case DSA_TAG_PROTO_SEVILLE: 652 case DSA_TAG_PROTO_OCELOT: 653 felix_teardown_tag_npi(ds, cpu); 654 break; 655 case DSA_TAG_PROTO_OCELOT_8021Q: 656 felix_teardown_tag_8021q(ds, cpu); 657 break; 658 default: 659 break; 660 } 661 } 662 663 /* This always leaves the switch in a consistent state, because although the 664 * tag_8021q setup can fail, the NPI setup can't. So either the change is made, 665 * or the restoration is guaranteed to work. 666 */ 667 static int felix_change_tag_protocol(struct dsa_switch *ds, int cpu, 668 enum dsa_tag_protocol proto) 669 { 670 struct ocelot *ocelot = ds->priv; 671 struct felix *felix = ocelot_to_felix(ocelot); 672 enum dsa_tag_protocol old_proto = felix->tag_proto; 673 bool cpu_port_active = false; 674 struct dsa_port *dp; 675 int err; 676 677 if (proto != DSA_TAG_PROTO_SEVILLE && 678 proto != DSA_TAG_PROTO_OCELOT && 679 proto != DSA_TAG_PROTO_OCELOT_8021Q) 680 return -EPROTONOSUPPORT; 681 682 /* We don't support multiple CPU ports, yet the DT blob may have 683 * multiple CPU ports defined. The first CPU port is the active one, 684 * the others are inactive. In this case, DSA will call 685 * ->change_tag_protocol() multiple times, once per CPU port. 686 * Since we implement the tagging protocol change towards "ocelot" or 687 * "seville" as effectively initializing the NPI port, what we are 688 * doing is effectively changing who the NPI port is to the last @cpu 689 * argument passed, which is an unused DSA CPU port and not the one 690 * that should actively pass traffic. 691 * Suppress DSA's calls on CPU ports that are inactive. 692 */ 693 dsa_switch_for_each_user_port(dp, ds) { 694 if (dp->cpu_dp->index == cpu) { 695 cpu_port_active = true; 696 break; 697 } 698 } 699 700 if (!cpu_port_active) 701 return 0; 702 703 felix_del_tag_protocol(ds, cpu, old_proto); 704 705 err = felix_set_tag_protocol(ds, cpu, proto); 706 if (err) { 707 felix_set_tag_protocol(ds, cpu, old_proto); 708 return err; 709 } 710 711 felix->tag_proto = proto; 712 713 return 0; 714 } 715 716 static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds, 717 int port, 718 enum dsa_tag_protocol mp) 719 { 720 struct ocelot *ocelot = ds->priv; 721 struct felix *felix = ocelot_to_felix(ocelot); 722 723 return felix->tag_proto; 724 } 725 726 static int felix_set_ageing_time(struct dsa_switch *ds, 727 unsigned int ageing_time) 728 { 729 struct ocelot *ocelot = ds->priv; 730 731 ocelot_set_ageing_time(ocelot, ageing_time); 732 733 return 0; 734 } 735 736 static void felix_port_fast_age(struct dsa_switch *ds, int port) 737 { 738 struct ocelot *ocelot = ds->priv; 739 int err; 740 741 err = ocelot_mact_flush(ocelot, port); 742 if (err) 743 dev_err(ds->dev, "Flushing MAC table on port %d returned %pe\n", 744 port, ERR_PTR(err)); 745 } 746 747 static int felix_fdb_dump(struct dsa_switch *ds, int port, 748 dsa_fdb_dump_cb_t *cb, void *data) 749 { 750 struct ocelot *ocelot = ds->priv; 751 752 return ocelot_fdb_dump(ocelot, port, cb, data); 753 } 754 755 static int felix_fdb_add(struct dsa_switch *ds, int port, 756 const unsigned char *addr, u16 vid, 757 struct dsa_db db) 758 { 759 struct net_device *bridge_dev = felix_classify_db(db); 760 struct ocelot *ocelot = ds->priv; 761 762 if (IS_ERR(bridge_dev)) 763 return PTR_ERR(bridge_dev); 764 765 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 766 dsa_fdb_present_in_other_db(ds, port, addr, vid, db)) 767 return 0; 768 769 return ocelot_fdb_add(ocelot, port, addr, vid, bridge_dev); 770 } 771 772 static int felix_fdb_del(struct dsa_switch *ds, int port, 773 const unsigned char *addr, u16 vid, 774 struct dsa_db db) 775 { 776 struct net_device *bridge_dev = felix_classify_db(db); 777 struct ocelot *ocelot = ds->priv; 778 779 if (IS_ERR(bridge_dev)) 780 return PTR_ERR(bridge_dev); 781 782 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 783 dsa_fdb_present_in_other_db(ds, port, addr, vid, db)) 784 return 0; 785 786 return ocelot_fdb_del(ocelot, port, addr, vid, bridge_dev); 787 } 788 789 static int felix_lag_fdb_add(struct dsa_switch *ds, struct dsa_lag lag, 790 const unsigned char *addr, u16 vid, 791 struct dsa_db db) 792 { 793 struct net_device *bridge_dev = felix_classify_db(db); 794 struct ocelot *ocelot = ds->priv; 795 796 if (IS_ERR(bridge_dev)) 797 return PTR_ERR(bridge_dev); 798 799 return ocelot_lag_fdb_add(ocelot, lag.dev, addr, vid, bridge_dev); 800 } 801 802 static int felix_lag_fdb_del(struct dsa_switch *ds, struct dsa_lag lag, 803 const unsigned char *addr, u16 vid, 804 struct dsa_db db) 805 { 806 struct net_device *bridge_dev = felix_classify_db(db); 807 struct ocelot *ocelot = ds->priv; 808 809 if (IS_ERR(bridge_dev)) 810 return PTR_ERR(bridge_dev); 811 812 return ocelot_lag_fdb_del(ocelot, lag.dev, addr, vid, bridge_dev); 813 } 814 815 static int felix_mdb_add(struct dsa_switch *ds, int port, 816 const struct switchdev_obj_port_mdb *mdb, 817 struct dsa_db db) 818 { 819 struct net_device *bridge_dev = felix_classify_db(db); 820 struct ocelot *ocelot = ds->priv; 821 822 if (IS_ERR(bridge_dev)) 823 return PTR_ERR(bridge_dev); 824 825 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 826 dsa_mdb_present_in_other_db(ds, port, mdb, db)) 827 return 0; 828 829 return ocelot_port_mdb_add(ocelot, port, mdb, bridge_dev); 830 } 831 832 static int felix_mdb_del(struct dsa_switch *ds, int port, 833 const struct switchdev_obj_port_mdb *mdb, 834 struct dsa_db db) 835 { 836 struct net_device *bridge_dev = felix_classify_db(db); 837 struct ocelot *ocelot = ds->priv; 838 839 if (IS_ERR(bridge_dev)) 840 return PTR_ERR(bridge_dev); 841 842 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 843 dsa_mdb_present_in_other_db(ds, port, mdb, db)) 844 return 0; 845 846 return ocelot_port_mdb_del(ocelot, port, mdb, bridge_dev); 847 } 848 849 static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port, 850 u8 state) 851 { 852 struct ocelot *ocelot = ds->priv; 853 854 return ocelot_bridge_stp_state_set(ocelot, port, state); 855 } 856 857 static int felix_pre_bridge_flags(struct dsa_switch *ds, int port, 858 struct switchdev_brport_flags val, 859 struct netlink_ext_ack *extack) 860 { 861 struct ocelot *ocelot = ds->priv; 862 863 return ocelot_port_pre_bridge_flags(ocelot, port, val); 864 } 865 866 static int felix_bridge_flags(struct dsa_switch *ds, int port, 867 struct switchdev_brport_flags val, 868 struct netlink_ext_ack *extack) 869 { 870 struct ocelot *ocelot = ds->priv; 871 872 ocelot_port_bridge_flags(ocelot, port, val); 873 874 return 0; 875 } 876 877 static int felix_bridge_join(struct dsa_switch *ds, int port, 878 struct dsa_bridge bridge, bool *tx_fwd_offload, 879 struct netlink_ext_ack *extack) 880 { 881 struct ocelot *ocelot = ds->priv; 882 883 return ocelot_port_bridge_join(ocelot, port, bridge.dev, bridge.num, 884 extack); 885 } 886 887 static void felix_bridge_leave(struct dsa_switch *ds, int port, 888 struct dsa_bridge bridge) 889 { 890 struct ocelot *ocelot = ds->priv; 891 892 ocelot_port_bridge_leave(ocelot, port, bridge.dev); 893 } 894 895 static int felix_lag_join(struct dsa_switch *ds, int port, 896 struct dsa_lag lag, 897 struct netdev_lag_upper_info *info) 898 { 899 struct ocelot *ocelot = ds->priv; 900 901 return ocelot_port_lag_join(ocelot, port, lag.dev, info); 902 } 903 904 static int felix_lag_leave(struct dsa_switch *ds, int port, 905 struct dsa_lag lag) 906 { 907 struct ocelot *ocelot = ds->priv; 908 909 ocelot_port_lag_leave(ocelot, port, lag.dev); 910 911 return 0; 912 } 913 914 static int felix_lag_change(struct dsa_switch *ds, int port) 915 { 916 struct dsa_port *dp = dsa_to_port(ds, port); 917 struct ocelot *ocelot = ds->priv; 918 919 ocelot_port_lag_change(ocelot, port, dp->lag_tx_enabled); 920 921 return 0; 922 } 923 924 static int felix_vlan_prepare(struct dsa_switch *ds, int port, 925 const struct switchdev_obj_port_vlan *vlan, 926 struct netlink_ext_ack *extack) 927 { 928 struct ocelot *ocelot = ds->priv; 929 u16 flags = vlan->flags; 930 931 /* Ocelot switches copy frames as-is to the CPU, so the flags: 932 * egress-untagged or not, pvid or not, make no difference. This 933 * behavior is already better than what DSA just tries to approximate 934 * when it installs the VLAN with the same flags on the CPU port. 935 * Just accept any configuration, and don't let ocelot deny installing 936 * multiple native VLANs on the NPI port, because the switch doesn't 937 * look at the port tag settings towards the NPI interface anyway. 938 */ 939 if (port == ocelot->npi) 940 return 0; 941 942 return ocelot_vlan_prepare(ocelot, port, vlan->vid, 943 flags & BRIDGE_VLAN_INFO_PVID, 944 flags & BRIDGE_VLAN_INFO_UNTAGGED, 945 extack); 946 } 947 948 static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 949 struct netlink_ext_ack *extack) 950 { 951 struct ocelot *ocelot = ds->priv; 952 953 return ocelot_port_vlan_filtering(ocelot, port, enabled, extack); 954 } 955 956 static int felix_vlan_add(struct dsa_switch *ds, int port, 957 const struct switchdev_obj_port_vlan *vlan, 958 struct netlink_ext_ack *extack) 959 { 960 struct ocelot *ocelot = ds->priv; 961 u16 flags = vlan->flags; 962 int err; 963 964 err = felix_vlan_prepare(ds, port, vlan, extack); 965 if (err) 966 return err; 967 968 return ocelot_vlan_add(ocelot, port, vlan->vid, 969 flags & BRIDGE_VLAN_INFO_PVID, 970 flags & BRIDGE_VLAN_INFO_UNTAGGED); 971 } 972 973 static int felix_vlan_del(struct dsa_switch *ds, int port, 974 const struct switchdev_obj_port_vlan *vlan) 975 { 976 struct ocelot *ocelot = ds->priv; 977 978 return ocelot_vlan_del(ocelot, port, vlan->vid); 979 } 980 981 static void felix_phylink_get_caps(struct dsa_switch *ds, int port, 982 struct phylink_config *config) 983 { 984 struct ocelot *ocelot = ds->priv; 985 986 /* This driver does not make use of the speed, duplex, pause or the 987 * advertisement in its mac_config, so it is safe to mark this driver 988 * as non-legacy. 989 */ 990 config->legacy_pre_march2020 = false; 991 992 __set_bit(ocelot->ports[port]->phy_mode, 993 config->supported_interfaces); 994 } 995 996 static void felix_phylink_validate(struct dsa_switch *ds, int port, 997 unsigned long *supported, 998 struct phylink_link_state *state) 999 { 1000 struct ocelot *ocelot = ds->priv; 1001 struct felix *felix = ocelot_to_felix(ocelot); 1002 1003 if (felix->info->phylink_validate) 1004 felix->info->phylink_validate(ocelot, port, supported, state); 1005 } 1006 1007 static struct phylink_pcs *felix_phylink_mac_select_pcs(struct dsa_switch *ds, 1008 int port, 1009 phy_interface_t iface) 1010 { 1011 struct ocelot *ocelot = ds->priv; 1012 struct felix *felix = ocelot_to_felix(ocelot); 1013 struct phylink_pcs *pcs = NULL; 1014 1015 if (felix->pcs && felix->pcs[port]) 1016 pcs = felix->pcs[port]; 1017 1018 return pcs; 1019 } 1020 1021 static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, 1022 unsigned int link_an_mode, 1023 phy_interface_t interface) 1024 { 1025 struct ocelot *ocelot = ds->priv; 1026 1027 ocelot_phylink_mac_link_down(ocelot, port, link_an_mode, interface, 1028 FELIX_MAC_QUIRKS); 1029 } 1030 1031 static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, 1032 unsigned int link_an_mode, 1033 phy_interface_t interface, 1034 struct phy_device *phydev, 1035 int speed, int duplex, 1036 bool tx_pause, bool rx_pause) 1037 { 1038 struct ocelot *ocelot = ds->priv; 1039 struct felix *felix = ocelot_to_felix(ocelot); 1040 1041 ocelot_phylink_mac_link_up(ocelot, port, phydev, link_an_mode, 1042 interface, speed, duplex, tx_pause, rx_pause, 1043 FELIX_MAC_QUIRKS); 1044 1045 if (felix->info->port_sched_speed_set) 1046 felix->info->port_sched_speed_set(ocelot, port, speed); 1047 } 1048 1049 static void felix_port_qos_map_init(struct ocelot *ocelot, int port) 1050 { 1051 int i; 1052 1053 ocelot_rmw_gix(ocelot, 1054 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 1055 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 1056 ANA_PORT_QOS_CFG, 1057 port); 1058 1059 for (i = 0; i < OCELOT_NUM_TC * 2; i++) { 1060 ocelot_rmw_ix(ocelot, 1061 (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) | 1062 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i), 1063 ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL | 1064 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M, 1065 ANA_PORT_PCP_DEI_MAP, 1066 port, i); 1067 } 1068 } 1069 1070 static void felix_get_strings(struct dsa_switch *ds, int port, 1071 u32 stringset, u8 *data) 1072 { 1073 struct ocelot *ocelot = ds->priv; 1074 1075 return ocelot_get_strings(ocelot, port, stringset, data); 1076 } 1077 1078 static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 1079 { 1080 struct ocelot *ocelot = ds->priv; 1081 1082 ocelot_get_ethtool_stats(ocelot, port, data); 1083 } 1084 1085 static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset) 1086 { 1087 struct ocelot *ocelot = ds->priv; 1088 1089 return ocelot_get_sset_count(ocelot, port, sset); 1090 } 1091 1092 static int felix_get_ts_info(struct dsa_switch *ds, int port, 1093 struct ethtool_ts_info *info) 1094 { 1095 struct ocelot *ocelot = ds->priv; 1096 1097 return ocelot_get_ts_info(ocelot, port, info); 1098 } 1099 1100 static const u32 felix_phy_match_table[PHY_INTERFACE_MODE_MAX] = { 1101 [PHY_INTERFACE_MODE_INTERNAL] = OCELOT_PORT_MODE_INTERNAL, 1102 [PHY_INTERFACE_MODE_SGMII] = OCELOT_PORT_MODE_SGMII, 1103 [PHY_INTERFACE_MODE_QSGMII] = OCELOT_PORT_MODE_QSGMII, 1104 [PHY_INTERFACE_MODE_USXGMII] = OCELOT_PORT_MODE_USXGMII, 1105 [PHY_INTERFACE_MODE_2500BASEX] = OCELOT_PORT_MODE_2500BASEX, 1106 }; 1107 1108 static int felix_validate_phy_mode(struct felix *felix, int port, 1109 phy_interface_t phy_mode) 1110 { 1111 u32 modes = felix->info->port_modes[port]; 1112 1113 if (felix_phy_match_table[phy_mode] & modes) 1114 return 0; 1115 return -EOPNOTSUPP; 1116 } 1117 1118 static int felix_parse_ports_node(struct felix *felix, 1119 struct device_node *ports_node, 1120 phy_interface_t *port_phy_modes) 1121 { 1122 struct device *dev = felix->ocelot.dev; 1123 struct device_node *child; 1124 1125 for_each_available_child_of_node(ports_node, child) { 1126 phy_interface_t phy_mode; 1127 u32 port; 1128 int err; 1129 1130 /* Get switch port number from DT */ 1131 if (of_property_read_u32(child, "reg", &port) < 0) { 1132 dev_err(dev, "Port number not defined in device tree " 1133 "(property \"reg\")\n"); 1134 of_node_put(child); 1135 return -ENODEV; 1136 } 1137 1138 /* Get PHY mode from DT */ 1139 err = of_get_phy_mode(child, &phy_mode); 1140 if (err) { 1141 dev_err(dev, "Failed to read phy-mode or " 1142 "phy-interface-type property for port %d\n", 1143 port); 1144 of_node_put(child); 1145 return -ENODEV; 1146 } 1147 1148 err = felix_validate_phy_mode(felix, port, phy_mode); 1149 if (err < 0) { 1150 dev_err(dev, "Unsupported PHY mode %s on port %d\n", 1151 phy_modes(phy_mode), port); 1152 of_node_put(child); 1153 return err; 1154 } 1155 1156 port_phy_modes[port] = phy_mode; 1157 } 1158 1159 return 0; 1160 } 1161 1162 static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes) 1163 { 1164 struct device *dev = felix->ocelot.dev; 1165 struct device_node *switch_node; 1166 struct device_node *ports_node; 1167 int err; 1168 1169 switch_node = dev->of_node; 1170 1171 ports_node = of_get_child_by_name(switch_node, "ports"); 1172 if (!ports_node) 1173 ports_node = of_get_child_by_name(switch_node, "ethernet-ports"); 1174 if (!ports_node) { 1175 dev_err(dev, "Incorrect bindings: absent \"ports\" or \"ethernet-ports\" node\n"); 1176 return -ENODEV; 1177 } 1178 1179 err = felix_parse_ports_node(felix, ports_node, port_phy_modes); 1180 of_node_put(ports_node); 1181 1182 return err; 1183 } 1184 1185 static int felix_init_structs(struct felix *felix, int num_phys_ports) 1186 { 1187 struct ocelot *ocelot = &felix->ocelot; 1188 phy_interface_t *port_phy_modes; 1189 struct resource res; 1190 int port, i, err; 1191 1192 ocelot->num_phys_ports = num_phys_ports; 1193 ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports, 1194 sizeof(struct ocelot_port *), GFP_KERNEL); 1195 if (!ocelot->ports) 1196 return -ENOMEM; 1197 1198 ocelot->map = felix->info->map; 1199 ocelot->stats_layout = felix->info->stats_layout; 1200 ocelot->num_stats = felix->info->num_stats; 1201 ocelot->num_mact_rows = felix->info->num_mact_rows; 1202 ocelot->vcap = felix->info->vcap; 1203 ocelot->vcap_pol.base = felix->info->vcap_pol_base; 1204 ocelot->vcap_pol.max = felix->info->vcap_pol_max; 1205 ocelot->vcap_pol.base2 = felix->info->vcap_pol_base2; 1206 ocelot->vcap_pol.max2 = felix->info->vcap_pol_max2; 1207 ocelot->ops = felix->info->ops; 1208 ocelot->npi_inj_prefix = OCELOT_TAG_PREFIX_SHORT; 1209 ocelot->npi_xtr_prefix = OCELOT_TAG_PREFIX_SHORT; 1210 ocelot->devlink = felix->ds->devlink; 1211 1212 port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t), 1213 GFP_KERNEL); 1214 if (!port_phy_modes) 1215 return -ENOMEM; 1216 1217 err = felix_parse_dt(felix, port_phy_modes); 1218 if (err) { 1219 kfree(port_phy_modes); 1220 return err; 1221 } 1222 1223 for (i = 0; i < TARGET_MAX; i++) { 1224 struct regmap *target; 1225 1226 if (!felix->info->target_io_res[i].name) 1227 continue; 1228 1229 memcpy(&res, &felix->info->target_io_res[i], sizeof(res)); 1230 res.flags = IORESOURCE_MEM; 1231 res.start += felix->switch_base; 1232 res.end += felix->switch_base; 1233 1234 target = felix->info->init_regmap(ocelot, &res); 1235 if (IS_ERR(target)) { 1236 dev_err(ocelot->dev, 1237 "Failed to map device memory space\n"); 1238 kfree(port_phy_modes); 1239 return PTR_ERR(target); 1240 } 1241 1242 ocelot->targets[i] = target; 1243 } 1244 1245 err = ocelot_regfields_init(ocelot, felix->info->regfields); 1246 if (err) { 1247 dev_err(ocelot->dev, "failed to init reg fields map\n"); 1248 kfree(port_phy_modes); 1249 return err; 1250 } 1251 1252 for (port = 0; port < num_phys_ports; port++) { 1253 struct ocelot_port *ocelot_port; 1254 struct regmap *target; 1255 1256 ocelot_port = devm_kzalloc(ocelot->dev, 1257 sizeof(struct ocelot_port), 1258 GFP_KERNEL); 1259 if (!ocelot_port) { 1260 dev_err(ocelot->dev, 1261 "failed to allocate port memory\n"); 1262 kfree(port_phy_modes); 1263 return -ENOMEM; 1264 } 1265 1266 memcpy(&res, &felix->info->port_io_res[port], sizeof(res)); 1267 res.flags = IORESOURCE_MEM; 1268 res.start += felix->switch_base; 1269 res.end += felix->switch_base; 1270 1271 target = felix->info->init_regmap(ocelot, &res); 1272 if (IS_ERR(target)) { 1273 dev_err(ocelot->dev, 1274 "Failed to map memory space for port %d\n", 1275 port); 1276 kfree(port_phy_modes); 1277 return PTR_ERR(target); 1278 } 1279 1280 ocelot_port->phy_mode = port_phy_modes[port]; 1281 ocelot_port->ocelot = ocelot; 1282 ocelot_port->target = target; 1283 ocelot->ports[port] = ocelot_port; 1284 } 1285 1286 kfree(port_phy_modes); 1287 1288 if (felix->info->mdio_bus_alloc) { 1289 err = felix->info->mdio_bus_alloc(ocelot); 1290 if (err < 0) 1291 return err; 1292 } 1293 1294 return 0; 1295 } 1296 1297 static void ocelot_port_purge_txtstamp_skb(struct ocelot *ocelot, int port, 1298 struct sk_buff *skb) 1299 { 1300 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1301 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone; 1302 struct sk_buff *skb_match = NULL, *skb_tmp; 1303 unsigned long flags; 1304 1305 if (!clone) 1306 return; 1307 1308 spin_lock_irqsave(&ocelot_port->tx_skbs.lock, flags); 1309 1310 skb_queue_walk_safe(&ocelot_port->tx_skbs, skb, skb_tmp) { 1311 if (skb != clone) 1312 continue; 1313 __skb_unlink(skb, &ocelot_port->tx_skbs); 1314 skb_match = skb; 1315 break; 1316 } 1317 1318 spin_unlock_irqrestore(&ocelot_port->tx_skbs.lock, flags); 1319 1320 WARN_ONCE(!skb_match, 1321 "Could not find skb clone in TX timestamping list\n"); 1322 } 1323 1324 #define work_to_xmit_work(w) \ 1325 container_of((w), struct felix_deferred_xmit_work, work) 1326 1327 static void felix_port_deferred_xmit(struct kthread_work *work) 1328 { 1329 struct felix_deferred_xmit_work *xmit_work = work_to_xmit_work(work); 1330 struct dsa_switch *ds = xmit_work->dp->ds; 1331 struct sk_buff *skb = xmit_work->skb; 1332 u32 rew_op = ocelot_ptp_rew_op(skb); 1333 struct ocelot *ocelot = ds->priv; 1334 int port = xmit_work->dp->index; 1335 int retries = 10; 1336 1337 do { 1338 if (ocelot_can_inject(ocelot, 0)) 1339 break; 1340 1341 cpu_relax(); 1342 } while (--retries); 1343 1344 if (!retries) { 1345 dev_err(ocelot->dev, "port %d failed to inject skb\n", 1346 port); 1347 ocelot_port_purge_txtstamp_skb(ocelot, port, skb); 1348 kfree_skb(skb); 1349 return; 1350 } 1351 1352 ocelot_port_inject_frame(ocelot, port, 0, rew_op, skb); 1353 1354 consume_skb(skb); 1355 kfree(xmit_work); 1356 } 1357 1358 static int felix_connect_tag_protocol(struct dsa_switch *ds, 1359 enum dsa_tag_protocol proto) 1360 { 1361 struct ocelot_8021q_tagger_data *tagger_data; 1362 1363 switch (proto) { 1364 case DSA_TAG_PROTO_OCELOT_8021Q: 1365 tagger_data = ocelot_8021q_tagger_data(ds); 1366 tagger_data->xmit_work_fn = felix_port_deferred_xmit; 1367 return 0; 1368 case DSA_TAG_PROTO_OCELOT: 1369 case DSA_TAG_PROTO_SEVILLE: 1370 return 0; 1371 default: 1372 return -EPROTONOSUPPORT; 1373 } 1374 } 1375 1376 /* Hardware initialization done here so that we can allocate structures with 1377 * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing 1378 * us to allocate structures twice (leak memory) and map PCI memory twice 1379 * (which will not work). 1380 */ 1381 static int felix_setup(struct dsa_switch *ds) 1382 { 1383 struct ocelot *ocelot = ds->priv; 1384 struct felix *felix = ocelot_to_felix(ocelot); 1385 unsigned long cpu_flood; 1386 struct dsa_port *dp; 1387 int err; 1388 1389 err = felix_init_structs(felix, ds->num_ports); 1390 if (err) 1391 return err; 1392 1393 err = ocelot_init(ocelot); 1394 if (err) 1395 goto out_mdiobus_free; 1396 1397 if (ocelot->ptp) { 1398 err = ocelot_init_timestamp(ocelot, felix->info->ptp_caps); 1399 if (err) { 1400 dev_err(ocelot->dev, 1401 "Timestamp initialization failed\n"); 1402 ocelot->ptp = 0; 1403 } 1404 } 1405 1406 dsa_switch_for_each_available_port(dp, ds) { 1407 ocelot_init_port(ocelot, dp->index); 1408 1409 /* Set the default QoS Classification based on PCP and DEI 1410 * bits of vlan tag. 1411 */ 1412 felix_port_qos_map_init(ocelot, dp->index); 1413 } 1414 1415 err = ocelot_devlink_sb_register(ocelot); 1416 if (err) 1417 goto out_deinit_ports; 1418 1419 dsa_switch_for_each_cpu_port(dp, ds) { 1420 /* The initial tag protocol is NPI which always returns 0, so 1421 * there's no real point in checking for errors. 1422 */ 1423 felix_set_tag_protocol(ds, dp->index, felix->tag_proto); 1424 1425 /* Start off with flooding disabled towards the NPI port 1426 * (actually CPU port module). 1427 */ 1428 cpu_flood = ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)); 1429 ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_UC); 1430 ocelot_rmw_rix(ocelot, 0, cpu_flood, ANA_PGID_PGID, PGID_MC); 1431 1432 break; 1433 } 1434 1435 ds->mtu_enforcement_ingress = true; 1436 ds->assisted_learning_on_cpu_port = true; 1437 ds->fdb_isolation = true; 1438 ds->max_num_bridges = ds->num_ports; 1439 1440 return 0; 1441 1442 out_deinit_ports: 1443 dsa_switch_for_each_available_port(dp, ds) 1444 ocelot_deinit_port(ocelot, dp->index); 1445 1446 ocelot_deinit_timestamp(ocelot); 1447 ocelot_deinit(ocelot); 1448 1449 out_mdiobus_free: 1450 if (felix->info->mdio_bus_free) 1451 felix->info->mdio_bus_free(ocelot); 1452 1453 return err; 1454 } 1455 1456 static void felix_teardown(struct dsa_switch *ds) 1457 { 1458 struct ocelot *ocelot = ds->priv; 1459 struct felix *felix = ocelot_to_felix(ocelot); 1460 struct dsa_port *dp; 1461 1462 dsa_switch_for_each_cpu_port(dp, ds) { 1463 felix_del_tag_protocol(ds, dp->index, felix->tag_proto); 1464 break; 1465 } 1466 1467 dsa_switch_for_each_available_port(dp, ds) 1468 ocelot_deinit_port(ocelot, dp->index); 1469 1470 ocelot_devlink_sb_unregister(ocelot); 1471 ocelot_deinit_timestamp(ocelot); 1472 ocelot_deinit(ocelot); 1473 1474 if (felix->info->mdio_bus_free) 1475 felix->info->mdio_bus_free(ocelot); 1476 } 1477 1478 static int felix_hwtstamp_get(struct dsa_switch *ds, int port, 1479 struct ifreq *ifr) 1480 { 1481 struct ocelot *ocelot = ds->priv; 1482 1483 return ocelot_hwstamp_get(ocelot, port, ifr); 1484 } 1485 1486 static int felix_hwtstamp_set(struct dsa_switch *ds, int port, 1487 struct ifreq *ifr) 1488 { 1489 struct ocelot *ocelot = ds->priv; 1490 struct felix *felix = ocelot_to_felix(ocelot); 1491 bool using_tag_8021q; 1492 int err; 1493 1494 err = ocelot_hwstamp_set(ocelot, port, ifr); 1495 if (err) 1496 return err; 1497 1498 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q; 1499 1500 return felix_update_trapping_destinations(ds, using_tag_8021q); 1501 } 1502 1503 static bool felix_check_xtr_pkt(struct ocelot *ocelot) 1504 { 1505 struct felix *felix = ocelot_to_felix(ocelot); 1506 int err = 0, grp = 0; 1507 1508 if (felix->tag_proto != DSA_TAG_PROTO_OCELOT_8021Q) 1509 return false; 1510 1511 if (!felix->info->quirk_no_xtr_irq) 1512 return false; 1513 1514 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) { 1515 struct sk_buff *skb; 1516 unsigned int type; 1517 1518 err = ocelot_xtr_poll_frame(ocelot, grp, &skb); 1519 if (err) 1520 goto out; 1521 1522 /* We trap to the CPU port module all PTP frames, but 1523 * felix_rxtstamp() only gets called for event frames. 1524 * So we need to avoid sending duplicate general 1525 * message frames by running a second BPF classifier 1526 * here and dropping those. 1527 */ 1528 __skb_push(skb, ETH_HLEN); 1529 1530 type = ptp_classify_raw(skb); 1531 1532 __skb_pull(skb, ETH_HLEN); 1533 1534 if (type == PTP_CLASS_NONE) { 1535 kfree_skb(skb); 1536 continue; 1537 } 1538 1539 netif_rx(skb); 1540 } 1541 1542 out: 1543 if (err < 0) { 1544 dev_err_ratelimited(ocelot->dev, 1545 "Error during packet extraction: %pe\n", 1546 ERR_PTR(err)); 1547 ocelot_drain_cpu_queue(ocelot, 0); 1548 } 1549 1550 return true; 1551 } 1552 1553 static bool felix_rxtstamp(struct dsa_switch *ds, int port, 1554 struct sk_buff *skb, unsigned int type) 1555 { 1556 u32 tstamp_lo = OCELOT_SKB_CB(skb)->tstamp_lo; 1557 struct skb_shared_hwtstamps *shhwtstamps; 1558 struct ocelot *ocelot = ds->priv; 1559 struct timespec64 ts; 1560 u32 tstamp_hi; 1561 u64 tstamp; 1562 1563 /* If the "no XTR IRQ" workaround is in use, tell DSA to defer this skb 1564 * for RX timestamping. Then free it, and poll for its copy through 1565 * MMIO in the CPU port module, and inject that into the stack from 1566 * ocelot_xtr_poll(). 1567 */ 1568 if (felix_check_xtr_pkt(ocelot)) { 1569 kfree_skb(skb); 1570 return true; 1571 } 1572 1573 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1574 tstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 1575 1576 tstamp_hi = tstamp >> 32; 1577 if ((tstamp & 0xffffffff) < tstamp_lo) 1578 tstamp_hi--; 1579 1580 tstamp = ((u64)tstamp_hi << 32) | tstamp_lo; 1581 1582 shhwtstamps = skb_hwtstamps(skb); 1583 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1584 shhwtstamps->hwtstamp = tstamp; 1585 return false; 1586 } 1587 1588 static void felix_txtstamp(struct dsa_switch *ds, int port, 1589 struct sk_buff *skb) 1590 { 1591 struct ocelot *ocelot = ds->priv; 1592 struct sk_buff *clone = NULL; 1593 1594 if (!ocelot->ptp) 1595 return; 1596 1597 if (ocelot_port_txtstamp_request(ocelot, port, skb, &clone)) { 1598 dev_err_ratelimited(ds->dev, 1599 "port %d delivering skb without TX timestamp\n", 1600 port); 1601 return; 1602 } 1603 1604 if (clone) 1605 OCELOT_SKB_CB(skb)->clone = clone; 1606 } 1607 1608 static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1609 { 1610 struct ocelot *ocelot = ds->priv; 1611 1612 ocelot_port_set_maxlen(ocelot, port, new_mtu); 1613 1614 return 0; 1615 } 1616 1617 static int felix_get_max_mtu(struct dsa_switch *ds, int port) 1618 { 1619 struct ocelot *ocelot = ds->priv; 1620 1621 return ocelot_get_max_mtu(ocelot, port); 1622 } 1623 1624 static int felix_cls_flower_add(struct dsa_switch *ds, int port, 1625 struct flow_cls_offload *cls, bool ingress) 1626 { 1627 struct ocelot *ocelot = ds->priv; 1628 struct felix *felix = ocelot_to_felix(ocelot); 1629 bool using_tag_8021q; 1630 int err; 1631 1632 err = ocelot_cls_flower_replace(ocelot, port, cls, ingress); 1633 if (err) 1634 return err; 1635 1636 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q; 1637 1638 return felix_update_trapping_destinations(ds, using_tag_8021q); 1639 } 1640 1641 static int felix_cls_flower_del(struct dsa_switch *ds, int port, 1642 struct flow_cls_offload *cls, bool ingress) 1643 { 1644 struct ocelot *ocelot = ds->priv; 1645 1646 return ocelot_cls_flower_destroy(ocelot, port, cls, ingress); 1647 } 1648 1649 static int felix_cls_flower_stats(struct dsa_switch *ds, int port, 1650 struct flow_cls_offload *cls, bool ingress) 1651 { 1652 struct ocelot *ocelot = ds->priv; 1653 1654 return ocelot_cls_flower_stats(ocelot, port, cls, ingress); 1655 } 1656 1657 static int felix_port_policer_add(struct dsa_switch *ds, int port, 1658 struct dsa_mall_policer_tc_entry *policer) 1659 { 1660 struct ocelot *ocelot = ds->priv; 1661 struct ocelot_policer pol = { 1662 .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8, 1663 .burst = policer->burst, 1664 }; 1665 1666 return ocelot_port_policer_add(ocelot, port, &pol); 1667 } 1668 1669 static void felix_port_policer_del(struct dsa_switch *ds, int port) 1670 { 1671 struct ocelot *ocelot = ds->priv; 1672 1673 ocelot_port_policer_del(ocelot, port); 1674 } 1675 1676 static int felix_port_mirror_add(struct dsa_switch *ds, int port, 1677 struct dsa_mall_mirror_tc_entry *mirror, 1678 bool ingress, struct netlink_ext_ack *extack) 1679 { 1680 struct ocelot *ocelot = ds->priv; 1681 1682 return ocelot_port_mirror_add(ocelot, port, mirror->to_local_port, 1683 ingress, extack); 1684 } 1685 1686 static void felix_port_mirror_del(struct dsa_switch *ds, int port, 1687 struct dsa_mall_mirror_tc_entry *mirror) 1688 { 1689 struct ocelot *ocelot = ds->priv; 1690 1691 ocelot_port_mirror_del(ocelot, port, mirror->ingress); 1692 } 1693 1694 static int felix_port_setup_tc(struct dsa_switch *ds, int port, 1695 enum tc_setup_type type, 1696 void *type_data) 1697 { 1698 struct ocelot *ocelot = ds->priv; 1699 struct felix *felix = ocelot_to_felix(ocelot); 1700 1701 if (felix->info->port_setup_tc) 1702 return felix->info->port_setup_tc(ds, port, type, type_data); 1703 else 1704 return -EOPNOTSUPP; 1705 } 1706 1707 static int felix_sb_pool_get(struct dsa_switch *ds, unsigned int sb_index, 1708 u16 pool_index, 1709 struct devlink_sb_pool_info *pool_info) 1710 { 1711 struct ocelot *ocelot = ds->priv; 1712 1713 return ocelot_sb_pool_get(ocelot, sb_index, pool_index, pool_info); 1714 } 1715 1716 static int felix_sb_pool_set(struct dsa_switch *ds, unsigned int sb_index, 1717 u16 pool_index, u32 size, 1718 enum devlink_sb_threshold_type threshold_type, 1719 struct netlink_ext_ack *extack) 1720 { 1721 struct ocelot *ocelot = ds->priv; 1722 1723 return ocelot_sb_pool_set(ocelot, sb_index, pool_index, size, 1724 threshold_type, extack); 1725 } 1726 1727 static int felix_sb_port_pool_get(struct dsa_switch *ds, int port, 1728 unsigned int sb_index, u16 pool_index, 1729 u32 *p_threshold) 1730 { 1731 struct ocelot *ocelot = ds->priv; 1732 1733 return ocelot_sb_port_pool_get(ocelot, port, sb_index, pool_index, 1734 p_threshold); 1735 } 1736 1737 static int felix_sb_port_pool_set(struct dsa_switch *ds, int port, 1738 unsigned int sb_index, u16 pool_index, 1739 u32 threshold, struct netlink_ext_ack *extack) 1740 { 1741 struct ocelot *ocelot = ds->priv; 1742 1743 return ocelot_sb_port_pool_set(ocelot, port, sb_index, pool_index, 1744 threshold, extack); 1745 } 1746 1747 static int felix_sb_tc_pool_bind_get(struct dsa_switch *ds, int port, 1748 unsigned int sb_index, u16 tc_index, 1749 enum devlink_sb_pool_type pool_type, 1750 u16 *p_pool_index, u32 *p_threshold) 1751 { 1752 struct ocelot *ocelot = ds->priv; 1753 1754 return ocelot_sb_tc_pool_bind_get(ocelot, port, sb_index, tc_index, 1755 pool_type, p_pool_index, 1756 p_threshold); 1757 } 1758 1759 static int felix_sb_tc_pool_bind_set(struct dsa_switch *ds, int port, 1760 unsigned int sb_index, u16 tc_index, 1761 enum devlink_sb_pool_type pool_type, 1762 u16 pool_index, u32 threshold, 1763 struct netlink_ext_ack *extack) 1764 { 1765 struct ocelot *ocelot = ds->priv; 1766 1767 return ocelot_sb_tc_pool_bind_set(ocelot, port, sb_index, tc_index, 1768 pool_type, pool_index, threshold, 1769 extack); 1770 } 1771 1772 static int felix_sb_occ_snapshot(struct dsa_switch *ds, 1773 unsigned int sb_index) 1774 { 1775 struct ocelot *ocelot = ds->priv; 1776 1777 return ocelot_sb_occ_snapshot(ocelot, sb_index); 1778 } 1779 1780 static int felix_sb_occ_max_clear(struct dsa_switch *ds, 1781 unsigned int sb_index) 1782 { 1783 struct ocelot *ocelot = ds->priv; 1784 1785 return ocelot_sb_occ_max_clear(ocelot, sb_index); 1786 } 1787 1788 static int felix_sb_occ_port_pool_get(struct dsa_switch *ds, int port, 1789 unsigned int sb_index, u16 pool_index, 1790 u32 *p_cur, u32 *p_max) 1791 { 1792 struct ocelot *ocelot = ds->priv; 1793 1794 return ocelot_sb_occ_port_pool_get(ocelot, port, sb_index, pool_index, 1795 p_cur, p_max); 1796 } 1797 1798 static int felix_sb_occ_tc_port_bind_get(struct dsa_switch *ds, int port, 1799 unsigned int sb_index, u16 tc_index, 1800 enum devlink_sb_pool_type pool_type, 1801 u32 *p_cur, u32 *p_max) 1802 { 1803 struct ocelot *ocelot = ds->priv; 1804 1805 return ocelot_sb_occ_tc_port_bind_get(ocelot, port, sb_index, tc_index, 1806 pool_type, p_cur, p_max); 1807 } 1808 1809 static int felix_mrp_add(struct dsa_switch *ds, int port, 1810 const struct switchdev_obj_mrp *mrp) 1811 { 1812 struct ocelot *ocelot = ds->priv; 1813 1814 return ocelot_mrp_add(ocelot, port, mrp); 1815 } 1816 1817 static int felix_mrp_del(struct dsa_switch *ds, int port, 1818 const struct switchdev_obj_mrp *mrp) 1819 { 1820 struct ocelot *ocelot = ds->priv; 1821 1822 return ocelot_mrp_add(ocelot, port, mrp); 1823 } 1824 1825 static int 1826 felix_mrp_add_ring_role(struct dsa_switch *ds, int port, 1827 const struct switchdev_obj_ring_role_mrp *mrp) 1828 { 1829 struct ocelot *ocelot = ds->priv; 1830 1831 return ocelot_mrp_add_ring_role(ocelot, port, mrp); 1832 } 1833 1834 static int 1835 felix_mrp_del_ring_role(struct dsa_switch *ds, int port, 1836 const struct switchdev_obj_ring_role_mrp *mrp) 1837 { 1838 struct ocelot *ocelot = ds->priv; 1839 1840 return ocelot_mrp_del_ring_role(ocelot, port, mrp); 1841 } 1842 1843 static int felix_port_get_default_prio(struct dsa_switch *ds, int port) 1844 { 1845 struct ocelot *ocelot = ds->priv; 1846 1847 return ocelot_port_get_default_prio(ocelot, port); 1848 } 1849 1850 static int felix_port_set_default_prio(struct dsa_switch *ds, int port, 1851 u8 prio) 1852 { 1853 struct ocelot *ocelot = ds->priv; 1854 1855 return ocelot_port_set_default_prio(ocelot, port, prio); 1856 } 1857 1858 static int felix_port_get_dscp_prio(struct dsa_switch *ds, int port, u8 dscp) 1859 { 1860 struct ocelot *ocelot = ds->priv; 1861 1862 return ocelot_port_get_dscp_prio(ocelot, port, dscp); 1863 } 1864 1865 static int felix_port_add_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, 1866 u8 prio) 1867 { 1868 struct ocelot *ocelot = ds->priv; 1869 1870 return ocelot_port_add_dscp_prio(ocelot, port, dscp, prio); 1871 } 1872 1873 static int felix_port_del_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, 1874 u8 prio) 1875 { 1876 struct ocelot *ocelot = ds->priv; 1877 1878 return ocelot_port_del_dscp_prio(ocelot, port, dscp, prio); 1879 } 1880 1881 const struct dsa_switch_ops felix_switch_ops = { 1882 .get_tag_protocol = felix_get_tag_protocol, 1883 .change_tag_protocol = felix_change_tag_protocol, 1884 .connect_tag_protocol = felix_connect_tag_protocol, 1885 .setup = felix_setup, 1886 .teardown = felix_teardown, 1887 .set_ageing_time = felix_set_ageing_time, 1888 .get_strings = felix_get_strings, 1889 .get_ethtool_stats = felix_get_ethtool_stats, 1890 .get_sset_count = felix_get_sset_count, 1891 .get_ts_info = felix_get_ts_info, 1892 .phylink_get_caps = felix_phylink_get_caps, 1893 .phylink_validate = felix_phylink_validate, 1894 .phylink_mac_select_pcs = felix_phylink_mac_select_pcs, 1895 .phylink_mac_link_down = felix_phylink_mac_link_down, 1896 .phylink_mac_link_up = felix_phylink_mac_link_up, 1897 .port_fast_age = felix_port_fast_age, 1898 .port_fdb_dump = felix_fdb_dump, 1899 .port_fdb_add = felix_fdb_add, 1900 .port_fdb_del = felix_fdb_del, 1901 .lag_fdb_add = felix_lag_fdb_add, 1902 .lag_fdb_del = felix_lag_fdb_del, 1903 .port_mdb_add = felix_mdb_add, 1904 .port_mdb_del = felix_mdb_del, 1905 .port_pre_bridge_flags = felix_pre_bridge_flags, 1906 .port_bridge_flags = felix_bridge_flags, 1907 .port_bridge_join = felix_bridge_join, 1908 .port_bridge_leave = felix_bridge_leave, 1909 .port_lag_join = felix_lag_join, 1910 .port_lag_leave = felix_lag_leave, 1911 .port_lag_change = felix_lag_change, 1912 .port_stp_state_set = felix_bridge_stp_state_set, 1913 .port_vlan_filtering = felix_vlan_filtering, 1914 .port_vlan_add = felix_vlan_add, 1915 .port_vlan_del = felix_vlan_del, 1916 .port_hwtstamp_get = felix_hwtstamp_get, 1917 .port_hwtstamp_set = felix_hwtstamp_set, 1918 .port_rxtstamp = felix_rxtstamp, 1919 .port_txtstamp = felix_txtstamp, 1920 .port_change_mtu = felix_change_mtu, 1921 .port_max_mtu = felix_get_max_mtu, 1922 .port_policer_add = felix_port_policer_add, 1923 .port_policer_del = felix_port_policer_del, 1924 .port_mirror_add = felix_port_mirror_add, 1925 .port_mirror_del = felix_port_mirror_del, 1926 .cls_flower_add = felix_cls_flower_add, 1927 .cls_flower_del = felix_cls_flower_del, 1928 .cls_flower_stats = felix_cls_flower_stats, 1929 .port_setup_tc = felix_port_setup_tc, 1930 .devlink_sb_pool_get = felix_sb_pool_get, 1931 .devlink_sb_pool_set = felix_sb_pool_set, 1932 .devlink_sb_port_pool_get = felix_sb_port_pool_get, 1933 .devlink_sb_port_pool_set = felix_sb_port_pool_set, 1934 .devlink_sb_tc_pool_bind_get = felix_sb_tc_pool_bind_get, 1935 .devlink_sb_tc_pool_bind_set = felix_sb_tc_pool_bind_set, 1936 .devlink_sb_occ_snapshot = felix_sb_occ_snapshot, 1937 .devlink_sb_occ_max_clear = felix_sb_occ_max_clear, 1938 .devlink_sb_occ_port_pool_get = felix_sb_occ_port_pool_get, 1939 .devlink_sb_occ_tc_port_bind_get= felix_sb_occ_tc_port_bind_get, 1940 .port_mrp_add = felix_mrp_add, 1941 .port_mrp_del = felix_mrp_del, 1942 .port_mrp_add_ring_role = felix_mrp_add_ring_role, 1943 .port_mrp_del_ring_role = felix_mrp_del_ring_role, 1944 .tag_8021q_vlan_add = felix_tag_8021q_vlan_add, 1945 .tag_8021q_vlan_del = felix_tag_8021q_vlan_del, 1946 .port_get_default_prio = felix_port_get_default_prio, 1947 .port_set_default_prio = felix_port_set_default_prio, 1948 .port_get_dscp_prio = felix_port_get_dscp_prio, 1949 .port_add_dscp_prio = felix_port_add_dscp_prio, 1950 .port_del_dscp_prio = felix_port_del_dscp_prio, 1951 }; 1952 1953 struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port) 1954 { 1955 struct felix *felix = ocelot_to_felix(ocelot); 1956 struct dsa_switch *ds = felix->ds; 1957 1958 if (!dsa_is_user_port(ds, port)) 1959 return NULL; 1960 1961 return dsa_to_port(ds, port)->slave; 1962 } 1963 1964 int felix_netdev_to_port(struct net_device *dev) 1965 { 1966 struct dsa_port *dp; 1967 1968 dp = dsa_port_from_netdev(dev); 1969 if (IS_ERR(dp)) 1970 return -EINVAL; 1971 1972 return dp->index; 1973 } 1974