1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx SERDES manipulation, via SMI bus 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 */ 9 10 #ifndef _MV88E6XXX_SERDES_H 11 #define _MV88E6XXX_SERDES_H 12 13 #include "chip.h" 14 15 #define MV88E6352_ADDR_SERDES 0x0f 16 #define MV88E6352_SERDES_PAGE_FIBER 0x01 17 #define MV88E6352_SERDES_IRQ 0x0b 18 #define MV88E6352_SERDES_INT_ENABLE 0x12 19 #define MV88E6352_SERDES_INT_SPEED_CHANGE BIT(14) 20 #define MV88E6352_SERDES_INT_DUPLEX_CHANGE BIT(13) 21 #define MV88E6352_SERDES_INT_PAGE_RX BIT(12) 22 #define MV88E6352_SERDES_INT_AN_COMPLETE BIT(11) 23 #define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10) 24 #define MV88E6352_SERDES_INT_SYMBOL_ERROR BIT(9) 25 #define MV88E6352_SERDES_INT_FALSE_CARRIER BIT(8) 26 #define MV88E6352_SERDES_INT_FIFO_OVER_UNDER BIT(7) 27 #define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4) 28 #define MV88E6352_SERDES_INT_STATUS 0x13 29 30 31 #define MV88E6341_PORT5_LANE 0x15 32 33 #define MV88E6390_PORT9_LANE0 0x09 34 #define MV88E6390_PORT9_LANE1 0x12 35 #define MV88E6390_PORT9_LANE2 0x13 36 #define MV88E6390_PORT9_LANE3 0x14 37 #define MV88E6390_PORT10_LANE0 0x0a 38 #define MV88E6390_PORT10_LANE1 0x15 39 #define MV88E6390_PORT10_LANE2 0x16 40 #define MV88E6390_PORT10_LANE3 0x17 41 42 /* 10GBASE-R and 10GBASE-X4/X2 */ 43 #define MV88E6390_PCS_CONTROL_1 0x1000 44 #define MV88E6390_PCS_CONTROL_1_RESET BIT(15) 45 #define MV88E6390_PCS_CONTROL_1_LOOPBACK BIT(14) 46 #define MV88E6390_PCS_CONTROL_1_SPEED BIT(13) 47 #define MV88E6390_PCS_CONTROL_1_PDOWN BIT(11) 48 49 /* 1000BASE-X and SGMII */ 50 #define MV88E6390_SGMII_BMCR (0x2000 + MII_BMCR) 51 #define MV88E6390_SGMII_BMSR (0x2000 + MII_BMSR) 52 #define MV88E6390_SGMII_ADVERTISE (0x2000 + MII_ADVERTISE) 53 #define MV88E6390_SGMII_LPA (0x2000 + MII_LPA) 54 #define MV88E6390_SGMII_INT_ENABLE 0xa001 55 #define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14) 56 #define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13) 57 #define MV88E6390_SGMII_INT_PAGE_RX BIT(12) 58 #define MV88E6390_SGMII_INT_AN_COMPLETE BIT(11) 59 #define MV88E6390_SGMII_INT_LINK_DOWN BIT(10) 60 #define MV88E6390_SGMII_INT_LINK_UP BIT(9) 61 #define MV88E6390_SGMII_INT_SYMBOL_ERROR BIT(8) 62 #define MV88E6390_SGMII_INT_FALSE_CARRIER BIT(7) 63 #define MV88E6390_SGMII_INT_STATUS 0xa002 64 #define MV88E6390_SGMII_PHY_STATUS 0xa003 65 #define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK GENMASK(15, 14) 66 #define MV88E6390_SGMII_PHY_STATUS_SPEED_1000 0x8000 67 #define MV88E6390_SGMII_PHY_STATUS_SPEED_100 0x4000 68 #define MV88E6390_SGMII_PHY_STATUS_SPEED_10 0x0000 69 #define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL BIT(13) 70 #define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11) 71 #define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10) 72 #define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE BIT(3) 73 #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE BIT(2) 74 75 /* Packet generator pad packet checker */ 76 #define MV88E6390_PG_CONTROL 0xf010 77 #define MV88E6390_PG_CONTROL_ENABLE_PC BIT(0) 78 79 u8 mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 80 u8 mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 81 u8 mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 82 u8 mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 83 int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 84 u8 lane, unsigned int mode, 85 phy_interface_t interface, 86 const unsigned long *advertise); 87 int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 88 u8 lane, unsigned int mode, 89 phy_interface_t interface, 90 const unsigned long *advertise); 91 int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 92 u8 lane, struct phylink_link_state *state); 93 int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 94 u8 lane, struct phylink_link_state *state); 95 int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, 96 u8 lane); 97 int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, 98 u8 lane); 99 int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 100 u8 lane, int speed, int duplex); 101 int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 102 u8 lane, int speed, int duplex); 103 unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip, 104 int port); 105 unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip, 106 int port); 107 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, 108 bool on); 109 int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, 110 bool on); 111 int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, 112 bool enable); 113 int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, 114 bool enable); 115 irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 116 u8 lane); 117 irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 118 u8 lane); 119 int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port); 120 int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip, 121 int port, uint8_t *data); 122 int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, 123 uint64_t *data); 124 int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port); 125 int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip, 126 int port, uint8_t *data); 127 int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, 128 uint64_t *data); 129 130 int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port); 131 void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p); 132 int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port); 133 void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p); 134 135 /* Return the (first) SERDES lane address a port is using, 0 otherwise. */ 136 static inline u8 mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip, 137 int port) 138 { 139 if (!chip->info->ops->serdes_get_lane) 140 return 0; 141 142 return chip->info->ops->serdes_get_lane(chip, port); 143 } 144 145 static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip, 146 int port, u8 lane) 147 { 148 if (!chip->info->ops->serdes_power) 149 return -EOPNOTSUPP; 150 151 return chip->info->ops->serdes_power(chip, port, lane, true); 152 } 153 154 static inline int mv88e6xxx_serdes_power_down(struct mv88e6xxx_chip *chip, 155 int port, u8 lane) 156 { 157 if (!chip->info->ops->serdes_power) 158 return -EOPNOTSUPP; 159 160 return chip->info->ops->serdes_power(chip, port, lane, false); 161 } 162 163 static inline unsigned int 164 mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port) 165 { 166 if (!chip->info->ops->serdes_irq_mapping) 167 return 0; 168 169 return chip->info->ops->serdes_irq_mapping(chip, port); 170 } 171 172 static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip, 173 int port, u8 lane) 174 { 175 if (!chip->info->ops->serdes_irq_enable) 176 return -EOPNOTSUPP; 177 178 return chip->info->ops->serdes_irq_enable(chip, port, lane, true); 179 } 180 181 static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip, 182 int port, u8 lane) 183 { 184 if (!chip->info->ops->serdes_irq_enable) 185 return -EOPNOTSUPP; 186 187 return chip->info->ops->serdes_irq_enable(chip, port, lane, false); 188 } 189 190 static inline irqreturn_t 191 mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, u8 lane) 192 { 193 if (!chip->info->ops->serdes_irq_status) 194 return IRQ_NONE; 195 196 return chip->info->ops->serdes_irq_status(chip, port, lane); 197 } 198 199 #endif 200