1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx SERDES manipulation, via SMI bus 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 */ 9 10 #ifndef _MV88E6XXX_SERDES_H 11 #define _MV88E6XXX_SERDES_H 12 13 #include "chip.h" 14 15 #define MV88E6352_ADDR_SERDES 0x0f 16 #define MV88E6352_SERDES_PAGE_FIBER 0x01 17 #define MV88E6352_SERDES_IRQ 0x0b 18 #define MV88E6352_SERDES_INT_ENABLE 0x12 19 #define MV88E6352_SERDES_INT_SPEED_CHANGE BIT(14) 20 #define MV88E6352_SERDES_INT_DUPLEX_CHANGE BIT(13) 21 #define MV88E6352_SERDES_INT_PAGE_RX BIT(12) 22 #define MV88E6352_SERDES_INT_AN_COMPLETE BIT(11) 23 #define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10) 24 #define MV88E6352_SERDES_INT_SYMBOL_ERROR BIT(9) 25 #define MV88E6352_SERDES_INT_FALSE_CARRIER BIT(8) 26 #define MV88E6352_SERDES_INT_FIFO_OVER_UNDER BIT(7) 27 #define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4) 28 #define MV88E6352_SERDES_INT_STATUS 0x13 29 30 31 #define MV88E6341_PORT5_LANE 0x15 32 33 #define MV88E6390_PORT9_LANE0 0x09 34 #define MV88E6390_PORT9_LANE1 0x12 35 #define MV88E6390_PORT9_LANE2 0x13 36 #define MV88E6390_PORT9_LANE3 0x14 37 #define MV88E6390_PORT10_LANE0 0x0a 38 #define MV88E6390_PORT10_LANE1 0x15 39 #define MV88E6390_PORT10_LANE2 0x16 40 #define MV88E6390_PORT10_LANE3 0x17 41 42 /* 10GBASE-R and 10GBASE-X4/X2 */ 43 #define MV88E6390_PCS_CONTROL_1 0x1000 44 #define MV88E6390_PCS_CONTROL_1_RESET BIT(15) 45 #define MV88E6390_PCS_CONTROL_1_LOOPBACK BIT(14) 46 #define MV88E6390_PCS_CONTROL_1_SPEED BIT(13) 47 #define MV88E6390_PCS_CONTROL_1_PDOWN BIT(11) 48 49 /* 1000BASE-X and SGMII */ 50 #define MV88E6390_SGMII_BMCR (0x2000 + MII_BMCR) 51 #define MV88E6390_SGMII_ADVERTISE (0x2000 + MII_ADVERTISE) 52 #define MV88E6390_SGMII_LPA (0x2000 + MII_LPA) 53 #define MV88E6390_SGMII_INT_ENABLE 0xa001 54 #define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14) 55 #define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13) 56 #define MV88E6390_SGMII_INT_PAGE_RX BIT(12) 57 #define MV88E6390_SGMII_INT_AN_COMPLETE BIT(11) 58 #define MV88E6390_SGMII_INT_LINK_DOWN BIT(10) 59 #define MV88E6390_SGMII_INT_LINK_UP BIT(9) 60 #define MV88E6390_SGMII_INT_SYMBOL_ERROR BIT(8) 61 #define MV88E6390_SGMII_INT_FALSE_CARRIER BIT(7) 62 #define MV88E6390_SGMII_INT_STATUS 0xa002 63 #define MV88E6390_SGMII_PHY_STATUS 0xa003 64 #define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK GENMASK(15, 14) 65 #define MV88E6390_SGMII_PHY_STATUS_SPEED_1000 0x8000 66 #define MV88E6390_SGMII_PHY_STATUS_SPEED_100 0x4000 67 #define MV88E6390_SGMII_PHY_STATUS_SPEED_10 0x0000 68 #define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL BIT(13) 69 #define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11) 70 #define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10) 71 #define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE BIT(3) 72 #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE BIT(2) 73 74 /* Packet generator pad packet checker */ 75 #define MV88E6390_PG_CONTROL 0xf010 76 #define MV88E6390_PG_CONTROL_ENABLE_PC BIT(0) 77 78 u8 mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 79 u8 mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 80 u8 mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 81 u8 mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port); 82 int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 83 u8 lane, unsigned int mode, 84 phy_interface_t interface, 85 const unsigned long *advertise); 86 int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 87 u8 lane, unsigned int mode, 88 phy_interface_t interface, 89 const unsigned long *advertise); 90 int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 91 u8 lane, struct phylink_link_state *state); 92 int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 93 u8 lane, struct phylink_link_state *state); 94 int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, 95 u8 lane); 96 int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, 97 u8 lane); 98 int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 99 u8 lane, int speed, int duplex); 100 int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 101 u8 lane, int speed, int duplex); 102 unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip, 103 int port); 104 unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip, 105 int port); 106 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, 107 bool on); 108 int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, 109 bool on); 110 int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, 111 bool enable); 112 int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, 113 bool enable); 114 irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 115 u8 lane); 116 irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 117 u8 lane); 118 int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port); 119 int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip, 120 int port, uint8_t *data); 121 int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, 122 uint64_t *data); 123 int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port); 124 int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip, 125 int port, uint8_t *data); 126 int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, 127 uint64_t *data); 128 129 int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port); 130 void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p); 131 int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port); 132 void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p); 133 134 /* Return the (first) SERDES lane address a port is using, 0 otherwise. */ 135 static inline u8 mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip, 136 int port) 137 { 138 if (!chip->info->ops->serdes_get_lane) 139 return 0; 140 141 return chip->info->ops->serdes_get_lane(chip, port); 142 } 143 144 static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip, 145 int port, u8 lane) 146 { 147 if (!chip->info->ops->serdes_power) 148 return -EOPNOTSUPP; 149 150 return chip->info->ops->serdes_power(chip, port, lane, true); 151 } 152 153 static inline int mv88e6xxx_serdes_power_down(struct mv88e6xxx_chip *chip, 154 int port, u8 lane) 155 { 156 if (!chip->info->ops->serdes_power) 157 return -EOPNOTSUPP; 158 159 return chip->info->ops->serdes_power(chip, port, lane, false); 160 } 161 162 static inline unsigned int 163 mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port) 164 { 165 if (!chip->info->ops->serdes_irq_mapping) 166 return 0; 167 168 return chip->info->ops->serdes_irq_mapping(chip, port); 169 } 170 171 static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip, 172 int port, u8 lane) 173 { 174 if (!chip->info->ops->serdes_irq_enable) 175 return -EOPNOTSUPP; 176 177 return chip->info->ops->serdes_irq_enable(chip, port, lane, true); 178 } 179 180 static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip, 181 int port, u8 lane) 182 { 183 if (!chip->info->ops->serdes_irq_enable) 184 return -EOPNOTSUPP; 185 186 return chip->info->ops->serdes_irq_enable(chip, port, lane, false); 187 } 188 189 static inline irqreturn_t 190 mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, u8 lane) 191 { 192 if (!chip->info->ops->serdes_irq_status) 193 return IRQ_NONE; 194 195 return chip->info->ops->serdes_irq_status(chip, port, lane); 196 } 197 198 #endif 199