1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx SERDES manipulation, via SMI bus 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch> 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/irqdomain.h> 12 #include <linux/mii.h> 13 14 #include "chip.h" 15 #include "global2.h" 16 #include "phy.h" 17 #include "port.h" 18 #include "serdes.h" 19 20 static int mv88e6352_serdes_read(struct mv88e6xxx_chip *chip, int reg, 21 u16 *val) 22 { 23 return mv88e6xxx_phy_page_read(chip, MV88E6352_ADDR_SERDES, 24 MV88E6352_SERDES_PAGE_FIBER, 25 reg, val); 26 } 27 28 static int mv88e6352_serdes_write(struct mv88e6xxx_chip *chip, int reg, 29 u16 val) 30 { 31 return mv88e6xxx_phy_page_write(chip, MV88E6352_ADDR_SERDES, 32 MV88E6352_SERDES_PAGE_FIBER, 33 reg, val); 34 } 35 36 static int mv88e6390_serdes_read(struct mv88e6xxx_chip *chip, 37 int lane, int device, int reg, u16 *val) 38 { 39 int reg_c45 = MII_ADDR_C45 | device << 16 | reg; 40 41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); 42 } 43 44 static int mv88e6390_serdes_write(struct mv88e6xxx_chip *chip, 45 int lane, int device, int reg, u16 val) 46 { 47 int reg_c45 = MII_ADDR_C45 | device << 16 | reg; 48 49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); 50 } 51 52 static int mv88e6xxx_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, 53 u16 ctrl, u16 status, u16 lpa, 54 struct phylink_link_state *state) 55 { 56 state->link = !!(status & MV88E6390_SGMII_PHY_STATUS_LINK); 57 58 if (status & MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID) { 59 /* The Spped and Duplex Resolved register is 1 if AN is enabled 60 * and complete, or if AN is disabled. So with disabled AN we 61 * still get here on link up. But we want to set an_complete 62 * only if AN was enabled, thus we look at BMCR_ANENABLE. 63 * (According to 802.3-2008 section 22.2.4.2.10, we should be 64 * able to get this same value from BMSR_ANEGCAPABLE, but tests 65 * show that these Marvell PHYs don't conform to this part of 66 * the specificaion - BMSR_ANEGCAPABLE is simply always 1.) 67 */ 68 state->an_complete = !!(ctrl & BMCR_ANENABLE); 69 state->duplex = status & 70 MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL ? 71 DUPLEX_FULL : DUPLEX_HALF; 72 73 if (status & MV88E6390_SGMII_PHY_STATUS_TX_PAUSE) 74 state->pause |= MLO_PAUSE_TX; 75 if (status & MV88E6390_SGMII_PHY_STATUS_RX_PAUSE) 76 state->pause |= MLO_PAUSE_RX; 77 78 switch (status & MV88E6390_SGMII_PHY_STATUS_SPEED_MASK) { 79 case MV88E6390_SGMII_PHY_STATUS_SPEED_1000: 80 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 81 state->speed = SPEED_2500; 82 else 83 state->speed = SPEED_1000; 84 break; 85 case MV88E6390_SGMII_PHY_STATUS_SPEED_100: 86 state->speed = SPEED_100; 87 break; 88 case MV88E6390_SGMII_PHY_STATUS_SPEED_10: 89 state->speed = SPEED_10; 90 break; 91 default: 92 dev_err(chip->dev, "invalid PHY speed\n"); 93 return -EINVAL; 94 } 95 } else if (state->link && 96 state->interface != PHY_INTERFACE_MODE_SGMII) { 97 /* If Speed and Duplex Resolved register is 0 and link is up, it 98 * means that AN was enabled, but link partner had it disabled 99 * and the PHY invoked the Auto-Negotiation Bypass feature and 100 * linked anyway. 101 */ 102 state->duplex = DUPLEX_FULL; 103 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 104 state->speed = SPEED_2500; 105 else 106 state->speed = SPEED_1000; 107 } else { 108 state->link = false; 109 } 110 111 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 112 mii_lpa_mod_linkmode_x(state->lp_advertising, lpa, 113 ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 114 else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) 115 mii_lpa_mod_linkmode_x(state->lp_advertising, lpa, 116 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 117 118 return 0; 119 } 120 121 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, 122 bool up) 123 { 124 u16 val, new_val; 125 int err; 126 127 err = mv88e6352_serdes_read(chip, MII_BMCR, &val); 128 if (err) 129 return err; 130 131 if (up) 132 new_val = val & ~BMCR_PDOWN; 133 else 134 new_val = val | BMCR_PDOWN; 135 136 if (val != new_val) 137 err = mv88e6352_serdes_write(chip, MII_BMCR, new_val); 138 139 return err; 140 } 141 142 int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 143 int lane, unsigned int mode, 144 phy_interface_t interface, 145 const unsigned long *advertise) 146 { 147 u16 adv, bmcr, val; 148 bool changed; 149 int err; 150 151 switch (interface) { 152 case PHY_INTERFACE_MODE_SGMII: 153 adv = 0x0001; 154 break; 155 156 case PHY_INTERFACE_MODE_1000BASEX: 157 adv = linkmode_adv_to_mii_adv_x(advertise, 158 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 159 break; 160 161 default: 162 return 0; 163 } 164 165 err = mv88e6352_serdes_read(chip, MII_ADVERTISE, &val); 166 if (err) 167 return err; 168 169 changed = val != adv; 170 if (changed) { 171 err = mv88e6352_serdes_write(chip, MII_ADVERTISE, adv); 172 if (err) 173 return err; 174 } 175 176 err = mv88e6352_serdes_read(chip, MII_BMCR, &val); 177 if (err) 178 return err; 179 180 if (phylink_autoneg_inband(mode)) 181 bmcr = val | BMCR_ANENABLE; 182 else 183 bmcr = val & ~BMCR_ANENABLE; 184 185 if (bmcr == val) 186 return changed; 187 188 return mv88e6352_serdes_write(chip, MII_BMCR, bmcr); 189 } 190 191 int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 192 int lane, struct phylink_link_state *state) 193 { 194 u16 lpa, status, ctrl; 195 int err; 196 197 err = mv88e6352_serdes_read(chip, MII_BMCR, &ctrl); 198 if (err) { 199 dev_err(chip->dev, "can't read Serdes PHY control: %d\n", err); 200 return err; 201 } 202 203 err = mv88e6352_serdes_read(chip, 0x11, &status); 204 if (err) { 205 dev_err(chip->dev, "can't read Serdes PHY status: %d\n", err); 206 return err; 207 } 208 209 err = mv88e6352_serdes_read(chip, MII_LPA, &lpa); 210 if (err) { 211 dev_err(chip->dev, "can't read Serdes PHY LPA: %d\n", err); 212 return err; 213 } 214 215 return mv88e6xxx_serdes_pcs_get_state(chip, ctrl, status, lpa, state); 216 } 217 218 int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, 219 int lane) 220 { 221 u16 bmcr; 222 int err; 223 224 err = mv88e6352_serdes_read(chip, MII_BMCR, &bmcr); 225 if (err) 226 return err; 227 228 return mv88e6352_serdes_write(chip, MII_BMCR, bmcr | BMCR_ANRESTART); 229 } 230 231 int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 232 int lane, int speed, int duplex) 233 { 234 u16 val, bmcr; 235 int err; 236 237 err = mv88e6352_serdes_read(chip, MII_BMCR, &val); 238 if (err) 239 return err; 240 241 bmcr = val & ~(BMCR_SPEED100 | BMCR_FULLDPLX | BMCR_SPEED1000); 242 switch (speed) { 243 case SPEED_1000: 244 bmcr |= BMCR_SPEED1000; 245 break; 246 case SPEED_100: 247 bmcr |= BMCR_SPEED100; 248 break; 249 case SPEED_10: 250 break; 251 } 252 253 if (duplex == DUPLEX_FULL) 254 bmcr |= BMCR_FULLDPLX; 255 256 if (bmcr == val) 257 return 0; 258 259 return mv88e6352_serdes_write(chip, MII_BMCR, bmcr); 260 } 261 262 int mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) 263 { 264 u8 cmode = chip->ports[port].cmode; 265 int lane = -ENODEV; 266 267 if ((cmode == MV88E6XXX_PORT_STS_CMODE_100BASEX) || 268 (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX) || 269 (cmode == MV88E6XXX_PORT_STS_CMODE_SGMII)) 270 lane = 0xff; /* Unused */ 271 272 return lane; 273 } 274 275 static bool mv88e6352_port_has_serdes(struct mv88e6xxx_chip *chip, int port) 276 { 277 if (mv88e6xxx_serdes_get_lane(chip, port) >= 0) 278 return true; 279 280 return false; 281 } 282 283 struct mv88e6352_serdes_hw_stat { 284 char string[ETH_GSTRING_LEN]; 285 int sizeof_stat; 286 int reg; 287 }; 288 289 static struct mv88e6352_serdes_hw_stat mv88e6352_serdes_hw_stats[] = { 290 { "serdes_fibre_rx_error", 16, 21 }, 291 { "serdes_PRBS_error", 32, 24 }, 292 }; 293 294 int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port) 295 { 296 if (mv88e6352_port_has_serdes(chip, port)) 297 return ARRAY_SIZE(mv88e6352_serdes_hw_stats); 298 299 return 0; 300 } 301 302 int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip, 303 int port, uint8_t *data) 304 { 305 struct mv88e6352_serdes_hw_stat *stat; 306 int i; 307 308 if (!mv88e6352_port_has_serdes(chip, port)) 309 return 0; 310 311 for (i = 0; i < ARRAY_SIZE(mv88e6352_serdes_hw_stats); i++) { 312 stat = &mv88e6352_serdes_hw_stats[i]; 313 memcpy(data + i * ETH_GSTRING_LEN, stat->string, 314 ETH_GSTRING_LEN); 315 } 316 return ARRAY_SIZE(mv88e6352_serdes_hw_stats); 317 } 318 319 static uint64_t mv88e6352_serdes_get_stat(struct mv88e6xxx_chip *chip, 320 struct mv88e6352_serdes_hw_stat *stat) 321 { 322 u64 val = 0; 323 u16 reg; 324 int err; 325 326 err = mv88e6352_serdes_read(chip, stat->reg, ®); 327 if (err) { 328 dev_err(chip->dev, "failed to read statistic\n"); 329 return 0; 330 } 331 332 val = reg; 333 334 if (stat->sizeof_stat == 32) { 335 err = mv88e6352_serdes_read(chip, stat->reg + 1, ®); 336 if (err) { 337 dev_err(chip->dev, "failed to read statistic\n"); 338 return 0; 339 } 340 val = val << 16 | reg; 341 } 342 343 return val; 344 } 345 346 int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, 347 uint64_t *data) 348 { 349 struct mv88e6xxx_port *mv88e6xxx_port = &chip->ports[port]; 350 struct mv88e6352_serdes_hw_stat *stat; 351 u64 value; 352 int i; 353 354 if (!mv88e6352_port_has_serdes(chip, port)) 355 return 0; 356 357 BUILD_BUG_ON(ARRAY_SIZE(mv88e6352_serdes_hw_stats) > 358 ARRAY_SIZE(mv88e6xxx_port->serdes_stats)); 359 360 for (i = 0; i < ARRAY_SIZE(mv88e6352_serdes_hw_stats); i++) { 361 stat = &mv88e6352_serdes_hw_stats[i]; 362 value = mv88e6352_serdes_get_stat(chip, stat); 363 mv88e6xxx_port->serdes_stats[i] += value; 364 data[i] = mv88e6xxx_port->serdes_stats[i]; 365 } 366 367 return ARRAY_SIZE(mv88e6352_serdes_hw_stats); 368 } 369 370 static void mv88e6352_serdes_irq_link(struct mv88e6xxx_chip *chip, int port) 371 { 372 u16 bmsr; 373 int err; 374 375 /* If the link has dropped, we want to know about it. */ 376 err = mv88e6352_serdes_read(chip, MII_BMSR, &bmsr); 377 if (err) { 378 dev_err(chip->dev, "can't read Serdes BMSR: %d\n", err); 379 return; 380 } 381 382 dsa_port_phylink_mac_change(chip->ds, port, !!(bmsr & BMSR_LSTATUS)); 383 } 384 385 irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 386 int lane) 387 { 388 irqreturn_t ret = IRQ_NONE; 389 u16 status; 390 int err; 391 392 err = mv88e6352_serdes_read(chip, MV88E6352_SERDES_INT_STATUS, &status); 393 if (err) 394 return ret; 395 396 if (status & MV88E6352_SERDES_INT_LINK_CHANGE) { 397 ret = IRQ_HANDLED; 398 mv88e6352_serdes_irq_link(chip, port); 399 } 400 401 return ret; 402 } 403 404 int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, 405 bool enable) 406 { 407 u16 val = 0; 408 409 if (enable) 410 val |= MV88E6352_SERDES_INT_LINK_CHANGE; 411 412 return mv88e6352_serdes_write(chip, MV88E6352_SERDES_INT_ENABLE, val); 413 } 414 415 unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port) 416 { 417 return irq_find_mapping(chip->g2_irq.domain, MV88E6352_SERDES_IRQ); 418 } 419 420 int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port) 421 { 422 if (!mv88e6352_port_has_serdes(chip, port)) 423 return 0; 424 425 return 32 * sizeof(u16); 426 } 427 428 void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p) 429 { 430 u16 *p = _p; 431 u16 reg; 432 int err; 433 int i; 434 435 if (!mv88e6352_port_has_serdes(chip, port)) 436 return; 437 438 for (i = 0 ; i < 32; i++) { 439 err = mv88e6352_serdes_read(chip, i, ®); 440 if (!err) 441 p[i] = reg; 442 } 443 } 444 445 int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) 446 { 447 u8 cmode = chip->ports[port].cmode; 448 int lane = -ENODEV; 449 450 switch (port) { 451 case 5: 452 if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 453 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII || 454 cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX) 455 lane = MV88E6341_PORT5_LANE; 456 break; 457 } 458 459 return lane; 460 } 461 462 int mv88e6185_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, 463 bool up) 464 { 465 /* The serdes power can't be controlled on this switch chip but we need 466 * to supply this function to avoid returning -EOPNOTSUPP in 467 * mv88e6xxx_serdes_power_up/mv88e6xxx_serdes_power_down 468 */ 469 return 0; 470 } 471 472 int mv88e6185_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) 473 { 474 /* There are no configurable serdes lanes on this switch chip but we 475 * need to return a non-negative lane number so that callers of 476 * mv88e6xxx_serdes_get_lane() know this is a serdes port. 477 */ 478 switch (chip->ports[port].cmode) { 479 case MV88E6185_PORT_STS_CMODE_SERDES: 480 case MV88E6185_PORT_STS_CMODE_1000BASE_X: 481 return 0; 482 default: 483 return -ENODEV; 484 } 485 } 486 487 int mv88e6185_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 488 int lane, struct phylink_link_state *state) 489 { 490 int err; 491 u16 status; 492 493 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &status); 494 if (err) 495 return err; 496 497 state->link = !!(status & MV88E6XXX_PORT_STS_LINK); 498 499 if (state->link) { 500 state->duplex = status & MV88E6XXX_PORT_STS_DUPLEX ? DUPLEX_FULL : DUPLEX_HALF; 501 502 switch (status & MV88E6XXX_PORT_STS_SPEED_MASK) { 503 case MV88E6XXX_PORT_STS_SPEED_1000: 504 state->speed = SPEED_1000; 505 break; 506 case MV88E6XXX_PORT_STS_SPEED_100: 507 state->speed = SPEED_100; 508 break; 509 case MV88E6XXX_PORT_STS_SPEED_10: 510 state->speed = SPEED_10; 511 break; 512 default: 513 dev_err(chip->dev, "invalid PHY speed\n"); 514 return -EINVAL; 515 } 516 } else { 517 state->duplex = DUPLEX_UNKNOWN; 518 state->speed = SPEED_UNKNOWN; 519 } 520 521 return 0; 522 } 523 524 int mv88e6097_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, 525 bool enable) 526 { 527 u8 cmode = chip->ports[port].cmode; 528 529 /* The serdes interrupts are enabled in the G2_INT_MASK register. We 530 * need to return 0 to avoid returning -EOPNOTSUPP in 531 * mv88e6xxx_serdes_irq_enable/mv88e6xxx_serdes_irq_disable 532 */ 533 switch (cmode) { 534 case MV88E6185_PORT_STS_CMODE_SERDES: 535 case MV88E6185_PORT_STS_CMODE_1000BASE_X: 536 return 0; 537 } 538 539 return -EOPNOTSUPP; 540 } 541 542 static void mv88e6097_serdes_irq_link(struct mv88e6xxx_chip *chip, int port) 543 { 544 u16 status; 545 int err; 546 547 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &status); 548 if (err) { 549 dev_err(chip->dev, "can't read port status: %d\n", err); 550 return; 551 } 552 553 dsa_port_phylink_mac_change(chip->ds, port, !!(status & MV88E6XXX_PORT_STS_LINK)); 554 } 555 556 irqreturn_t mv88e6097_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 557 int lane) 558 { 559 u8 cmode = chip->ports[port].cmode; 560 561 switch (cmode) { 562 case MV88E6185_PORT_STS_CMODE_SERDES: 563 case MV88E6185_PORT_STS_CMODE_1000BASE_X: 564 mv88e6097_serdes_irq_link(chip, port); 565 return IRQ_HANDLED; 566 } 567 568 return IRQ_NONE; 569 } 570 571 int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) 572 { 573 u8 cmode = chip->ports[port].cmode; 574 int lane = -ENODEV; 575 576 switch (port) { 577 case 9: 578 if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 579 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII || 580 cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX) 581 lane = MV88E6390_PORT9_LANE0; 582 break; 583 case 10: 584 if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 585 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII || 586 cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX) 587 lane = MV88E6390_PORT10_LANE0; 588 break; 589 } 590 591 return lane; 592 } 593 594 int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) 595 { 596 u8 cmode_port = chip->ports[port].cmode; 597 u8 cmode_port10 = chip->ports[10].cmode; 598 u8 cmode_port9 = chip->ports[9].cmode; 599 int lane = -ENODEV; 600 601 switch (port) { 602 case 2: 603 if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 604 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII || 605 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX) 606 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX) 607 lane = MV88E6390_PORT9_LANE1; 608 break; 609 case 3: 610 if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 611 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII || 612 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX || 613 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_RXAUI) 614 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX) 615 lane = MV88E6390_PORT9_LANE2; 616 break; 617 case 4: 618 if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 619 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII || 620 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX || 621 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_RXAUI) 622 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX) 623 lane = MV88E6390_PORT9_LANE3; 624 break; 625 case 5: 626 if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 627 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII || 628 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX) 629 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX) 630 lane = MV88E6390_PORT10_LANE1; 631 break; 632 case 6: 633 if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 634 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII || 635 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX || 636 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_RXAUI) 637 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX) 638 lane = MV88E6390_PORT10_LANE2; 639 break; 640 case 7: 641 if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 642 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII || 643 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX || 644 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_RXAUI) 645 if (cmode_port == MV88E6XXX_PORT_STS_CMODE_1000BASEX) 646 lane = MV88E6390_PORT10_LANE3; 647 break; 648 case 9: 649 if (cmode_port9 == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 650 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_SGMII || 651 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_2500BASEX || 652 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_XAUI || 653 cmode_port9 == MV88E6XXX_PORT_STS_CMODE_RXAUI) 654 lane = MV88E6390_PORT9_LANE0; 655 break; 656 case 10: 657 if (cmode_port10 == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 658 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_SGMII || 659 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_2500BASEX || 660 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_XAUI || 661 cmode_port10 == MV88E6XXX_PORT_STS_CMODE_RXAUI) 662 lane = MV88E6390_PORT10_LANE0; 663 break; 664 } 665 666 return lane; 667 } 668 669 /* Only Ports 0, 9 and 10 have SERDES lanes. Return the SERDES lane address 670 * a port is using else Returns -ENODEV. 671 */ 672 int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port) 673 { 674 u8 cmode = chip->ports[port].cmode; 675 int lane = -ENODEV; 676 677 if (port != 0 && port != 9 && port != 10) 678 return -EOPNOTSUPP; 679 680 if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX || 681 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII || 682 cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX || 683 cmode == MV88E6393X_PORT_STS_CMODE_5GBASER || 684 cmode == MV88E6393X_PORT_STS_CMODE_10GBASER) 685 lane = port; 686 687 return lane; 688 } 689 690 /* Set power up/down for 10GBASE-R and 10GBASE-X4/X2 */ 691 static int mv88e6390_serdes_power_10g(struct mv88e6xxx_chip *chip, int lane, 692 bool up) 693 { 694 u16 val, new_val; 695 int err; 696 697 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 698 MV88E6390_10G_CTRL1, &val); 699 700 if (err) 701 return err; 702 703 if (up) 704 new_val = val & ~(MDIO_CTRL1_RESET | 705 MDIO_PCS_CTRL1_LOOPBACK | 706 MDIO_CTRL1_LPOWER); 707 else 708 new_val = val | MDIO_CTRL1_LPOWER; 709 710 if (val != new_val) 711 err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 712 MV88E6390_10G_CTRL1, new_val); 713 714 return err; 715 } 716 717 /* Set power up/down for SGMII and 1000Base-X */ 718 static int mv88e6390_serdes_power_sgmii(struct mv88e6xxx_chip *chip, int lane, 719 bool up) 720 { 721 u16 val, new_val; 722 int err; 723 724 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 725 MV88E6390_SGMII_BMCR, &val); 726 if (err) 727 return err; 728 729 if (up) 730 new_val = val & ~(BMCR_RESET | BMCR_LOOPBACK | BMCR_PDOWN); 731 else 732 new_val = val | BMCR_PDOWN; 733 734 if (val != new_val) 735 err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 736 MV88E6390_SGMII_BMCR, new_val); 737 738 return err; 739 } 740 741 struct mv88e6390_serdes_hw_stat { 742 char string[ETH_GSTRING_LEN]; 743 int reg; 744 }; 745 746 static struct mv88e6390_serdes_hw_stat mv88e6390_serdes_hw_stats[] = { 747 { "serdes_rx_pkts", 0xf021 }, 748 { "serdes_rx_bytes", 0xf024 }, 749 { "serdes_rx_pkts_error", 0xf027 }, 750 }; 751 752 int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port) 753 { 754 if (mv88e6xxx_serdes_get_lane(chip, port) < 0) 755 return 0; 756 757 return ARRAY_SIZE(mv88e6390_serdes_hw_stats); 758 } 759 760 int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip, 761 int port, uint8_t *data) 762 { 763 struct mv88e6390_serdes_hw_stat *stat; 764 int i; 765 766 if (mv88e6xxx_serdes_get_lane(chip, port) < 0) 767 return 0; 768 769 for (i = 0; i < ARRAY_SIZE(mv88e6390_serdes_hw_stats); i++) { 770 stat = &mv88e6390_serdes_hw_stats[i]; 771 memcpy(data + i * ETH_GSTRING_LEN, stat->string, 772 ETH_GSTRING_LEN); 773 } 774 return ARRAY_SIZE(mv88e6390_serdes_hw_stats); 775 } 776 777 static uint64_t mv88e6390_serdes_get_stat(struct mv88e6xxx_chip *chip, int lane, 778 struct mv88e6390_serdes_hw_stat *stat) 779 { 780 u16 reg[3]; 781 int err, i; 782 783 for (i = 0; i < 3; i++) { 784 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 785 stat->reg + i, ®[i]); 786 if (err) { 787 dev_err(chip->dev, "failed to read statistic\n"); 788 return 0; 789 } 790 } 791 792 return reg[0] | ((u64)reg[1] << 16) | ((u64)reg[2] << 32); 793 } 794 795 int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port, 796 uint64_t *data) 797 { 798 struct mv88e6390_serdes_hw_stat *stat; 799 int lane; 800 int i; 801 802 lane = mv88e6xxx_serdes_get_lane(chip, port); 803 if (lane < 0) 804 return 0; 805 806 for (i = 0; i < ARRAY_SIZE(mv88e6390_serdes_hw_stats); i++) { 807 stat = &mv88e6390_serdes_hw_stats[i]; 808 data[i] = mv88e6390_serdes_get_stat(chip, lane, stat); 809 } 810 811 return ARRAY_SIZE(mv88e6390_serdes_hw_stats); 812 } 813 814 static int mv88e6390_serdes_enable_checker(struct mv88e6xxx_chip *chip, int lane) 815 { 816 u16 reg; 817 int err; 818 819 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 820 MV88E6390_PG_CONTROL, ®); 821 if (err) 822 return err; 823 824 reg |= MV88E6390_PG_CONTROL_ENABLE_PC; 825 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 826 MV88E6390_PG_CONTROL, reg); 827 } 828 829 int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, 830 bool up) 831 { 832 u8 cmode = chip->ports[port].cmode; 833 int err = 0; 834 835 switch (cmode) { 836 case MV88E6XXX_PORT_STS_CMODE_SGMII: 837 case MV88E6XXX_PORT_STS_CMODE_1000BASEX: 838 case MV88E6XXX_PORT_STS_CMODE_2500BASEX: 839 err = mv88e6390_serdes_power_sgmii(chip, lane, up); 840 break; 841 case MV88E6XXX_PORT_STS_CMODE_XAUI: 842 case MV88E6XXX_PORT_STS_CMODE_RXAUI: 843 err = mv88e6390_serdes_power_10g(chip, lane, up); 844 break; 845 } 846 847 if (!err && up) 848 err = mv88e6390_serdes_enable_checker(chip, lane); 849 850 return err; 851 } 852 853 int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 854 int lane, unsigned int mode, 855 phy_interface_t interface, 856 const unsigned long *advertise) 857 { 858 u16 val, bmcr, adv; 859 bool changed; 860 int err; 861 862 switch (interface) { 863 case PHY_INTERFACE_MODE_SGMII: 864 adv = 0x0001; 865 break; 866 867 case PHY_INTERFACE_MODE_1000BASEX: 868 adv = linkmode_adv_to_mii_adv_x(advertise, 869 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 870 break; 871 872 case PHY_INTERFACE_MODE_2500BASEX: 873 adv = linkmode_adv_to_mii_adv_x(advertise, 874 ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 875 break; 876 877 default: 878 return 0; 879 } 880 881 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 882 MV88E6390_SGMII_ADVERTISE, &val); 883 if (err) 884 return err; 885 886 changed = val != adv; 887 if (changed) { 888 err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 889 MV88E6390_SGMII_ADVERTISE, adv); 890 if (err) 891 return err; 892 } 893 894 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 895 MV88E6390_SGMII_BMCR, &val); 896 if (err) 897 return err; 898 899 if (phylink_autoneg_inband(mode)) 900 bmcr = val | BMCR_ANENABLE; 901 else 902 bmcr = val & ~BMCR_ANENABLE; 903 904 /* setting ANENABLE triggers a restart of negotiation */ 905 if (bmcr == val) 906 return changed; 907 908 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 909 MV88E6390_SGMII_BMCR, bmcr); 910 } 911 912 static int mv88e6390_serdes_pcs_get_state_sgmii(struct mv88e6xxx_chip *chip, 913 int port, int lane, struct phylink_link_state *state) 914 { 915 u16 lpa, status, ctrl; 916 int err; 917 918 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 919 MV88E6390_SGMII_BMCR, &ctrl); 920 if (err) { 921 dev_err(chip->dev, "can't read Serdes PHY control: %d\n", err); 922 return err; 923 } 924 925 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 926 MV88E6390_SGMII_PHY_STATUS, &status); 927 if (err) { 928 dev_err(chip->dev, "can't read Serdes PHY status: %d\n", err); 929 return err; 930 } 931 932 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 933 MV88E6390_SGMII_LPA, &lpa); 934 if (err) { 935 dev_err(chip->dev, "can't read Serdes PHY LPA: %d\n", err); 936 return err; 937 } 938 939 return mv88e6xxx_serdes_pcs_get_state(chip, ctrl, status, lpa, state); 940 } 941 942 static int mv88e6390_serdes_pcs_get_state_10g(struct mv88e6xxx_chip *chip, 943 int port, int lane, struct phylink_link_state *state) 944 { 945 u16 status; 946 int err; 947 948 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 949 MV88E6390_10G_STAT1, &status); 950 if (err) 951 return err; 952 953 state->link = !!(status & MDIO_STAT1_LSTATUS); 954 if (state->link) { 955 state->speed = SPEED_10000; 956 state->duplex = DUPLEX_FULL; 957 } 958 959 return 0; 960 } 961 962 static int mv88e6393x_serdes_pcs_get_state_10g(struct mv88e6xxx_chip *chip, 963 int port, int lane, 964 struct phylink_link_state *state) 965 { 966 u16 status; 967 int err; 968 969 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 970 MV88E6390_10G_STAT1, &status); 971 if (err) 972 return err; 973 974 state->link = !!(status & MDIO_STAT1_LSTATUS); 975 if (state->link) { 976 if (state->interface == PHY_INTERFACE_MODE_5GBASER) 977 state->speed = SPEED_5000; 978 else 979 state->speed = SPEED_10000; 980 state->duplex = DUPLEX_FULL; 981 } 982 983 return 0; 984 } 985 986 int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 987 int lane, struct phylink_link_state *state) 988 { 989 switch (state->interface) { 990 case PHY_INTERFACE_MODE_SGMII: 991 case PHY_INTERFACE_MODE_1000BASEX: 992 case PHY_INTERFACE_MODE_2500BASEX: 993 return mv88e6390_serdes_pcs_get_state_sgmii(chip, port, lane, 994 state); 995 case PHY_INTERFACE_MODE_XAUI: 996 case PHY_INTERFACE_MODE_RXAUI: 997 return mv88e6390_serdes_pcs_get_state_10g(chip, port, lane, 998 state); 999 1000 default: 1001 return -EOPNOTSUPP; 1002 } 1003 } 1004 1005 int mv88e6393x_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port, 1006 int lane, struct phylink_link_state *state) 1007 { 1008 switch (state->interface) { 1009 case PHY_INTERFACE_MODE_SGMII: 1010 case PHY_INTERFACE_MODE_1000BASEX: 1011 case PHY_INTERFACE_MODE_2500BASEX: 1012 return mv88e6390_serdes_pcs_get_state_sgmii(chip, port, lane, 1013 state); 1014 case PHY_INTERFACE_MODE_5GBASER: 1015 case PHY_INTERFACE_MODE_10GBASER: 1016 return mv88e6393x_serdes_pcs_get_state_10g(chip, port, lane, 1017 state); 1018 1019 default: 1020 return -EOPNOTSUPP; 1021 } 1022 } 1023 1024 int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port, 1025 int lane) 1026 { 1027 u16 bmcr; 1028 int err; 1029 1030 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1031 MV88E6390_SGMII_BMCR, &bmcr); 1032 if (err) 1033 return err; 1034 1035 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 1036 MV88E6390_SGMII_BMCR, 1037 bmcr | BMCR_ANRESTART); 1038 } 1039 1040 int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 1041 int lane, int speed, int duplex) 1042 { 1043 u16 val, bmcr; 1044 int err; 1045 1046 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1047 MV88E6390_SGMII_BMCR, &val); 1048 if (err) 1049 return err; 1050 1051 bmcr = val & ~(BMCR_SPEED100 | BMCR_FULLDPLX | BMCR_SPEED1000); 1052 switch (speed) { 1053 case SPEED_2500: 1054 case SPEED_1000: 1055 bmcr |= BMCR_SPEED1000; 1056 break; 1057 case SPEED_100: 1058 bmcr |= BMCR_SPEED100; 1059 break; 1060 case SPEED_10: 1061 break; 1062 } 1063 1064 if (duplex == DUPLEX_FULL) 1065 bmcr |= BMCR_FULLDPLX; 1066 1067 if (bmcr == val) 1068 return 0; 1069 1070 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 1071 MV88E6390_SGMII_BMCR, bmcr); 1072 } 1073 1074 static void mv88e6390_serdes_irq_link_sgmii(struct mv88e6xxx_chip *chip, 1075 int port, int lane) 1076 { 1077 u16 bmsr; 1078 int err; 1079 1080 /* If the link has dropped, we want to know about it. */ 1081 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1082 MV88E6390_SGMII_BMSR, &bmsr); 1083 if (err) { 1084 dev_err(chip->dev, "can't read Serdes BMSR: %d\n", err); 1085 return; 1086 } 1087 1088 dsa_port_phylink_mac_change(chip->ds, port, !!(bmsr & BMSR_LSTATUS)); 1089 } 1090 1091 static void mv88e6393x_serdes_irq_link_10g(struct mv88e6xxx_chip *chip, 1092 int port, u8 lane) 1093 { 1094 u16 status; 1095 int err; 1096 1097 /* If the link has dropped, we want to know about it. */ 1098 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1099 MV88E6390_10G_STAT1, &status); 1100 if (err) { 1101 dev_err(chip->dev, "can't read Serdes STAT1: %d\n", err); 1102 return; 1103 } 1104 1105 dsa_port_phylink_mac_change(chip->ds, port, !!(status & MDIO_STAT1_LSTATUS)); 1106 } 1107 1108 static int mv88e6390_serdes_irq_enable_sgmii(struct mv88e6xxx_chip *chip, 1109 int lane, bool enable) 1110 { 1111 u16 val = 0; 1112 1113 if (enable) 1114 val |= MV88E6390_SGMII_INT_LINK_DOWN | 1115 MV88E6390_SGMII_INT_LINK_UP; 1116 1117 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 1118 MV88E6390_SGMII_INT_ENABLE, val); 1119 } 1120 1121 int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane, 1122 bool enable) 1123 { 1124 u8 cmode = chip->ports[port].cmode; 1125 1126 switch (cmode) { 1127 case MV88E6XXX_PORT_STS_CMODE_SGMII: 1128 case MV88E6XXX_PORT_STS_CMODE_1000BASEX: 1129 case MV88E6XXX_PORT_STS_CMODE_2500BASEX: 1130 return mv88e6390_serdes_irq_enable_sgmii(chip, lane, enable); 1131 } 1132 1133 return 0; 1134 } 1135 1136 static int mv88e6390_serdes_irq_status_sgmii(struct mv88e6xxx_chip *chip, 1137 int lane, u16 *status) 1138 { 1139 int err; 1140 1141 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1142 MV88E6390_SGMII_INT_STATUS, status); 1143 1144 return err; 1145 } 1146 1147 static int mv88e6393x_serdes_irq_enable_10g(struct mv88e6xxx_chip *chip, 1148 u8 lane, bool enable) 1149 { 1150 u16 val = 0; 1151 1152 if (enable) 1153 val |= MV88E6393X_10G_INT_LINK_CHANGE; 1154 1155 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 1156 MV88E6393X_10G_INT_ENABLE, val); 1157 } 1158 1159 int mv88e6393x_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, 1160 int lane, bool enable) 1161 { 1162 u8 cmode = chip->ports[port].cmode; 1163 1164 switch (cmode) { 1165 case MV88E6XXX_PORT_STS_CMODE_SGMII: 1166 case MV88E6XXX_PORT_STS_CMODE_1000BASEX: 1167 case MV88E6XXX_PORT_STS_CMODE_2500BASEX: 1168 return mv88e6390_serdes_irq_enable_sgmii(chip, lane, enable); 1169 case MV88E6393X_PORT_STS_CMODE_5GBASER: 1170 case MV88E6393X_PORT_STS_CMODE_10GBASER: 1171 return mv88e6393x_serdes_irq_enable_10g(chip, lane, enable); 1172 } 1173 1174 return 0; 1175 } 1176 1177 static int mv88e6393x_serdes_irq_status_10g(struct mv88e6xxx_chip *chip, 1178 u8 lane, u16 *status) 1179 { 1180 int err; 1181 1182 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1183 MV88E6393X_10G_INT_STATUS, status); 1184 1185 return err; 1186 } 1187 1188 irqreturn_t mv88e6393x_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 1189 int lane) 1190 { 1191 u8 cmode = chip->ports[port].cmode; 1192 irqreturn_t ret = IRQ_NONE; 1193 u16 status; 1194 int err; 1195 1196 switch (cmode) { 1197 case MV88E6XXX_PORT_STS_CMODE_SGMII: 1198 case MV88E6XXX_PORT_STS_CMODE_1000BASEX: 1199 case MV88E6XXX_PORT_STS_CMODE_2500BASEX: 1200 err = mv88e6390_serdes_irq_status_sgmii(chip, lane, &status); 1201 if (err) 1202 return ret; 1203 if (status & (MV88E6390_SGMII_INT_LINK_DOWN | 1204 MV88E6390_SGMII_INT_LINK_UP)) { 1205 ret = IRQ_HANDLED; 1206 mv88e6390_serdes_irq_link_sgmii(chip, port, lane); 1207 } 1208 break; 1209 case MV88E6393X_PORT_STS_CMODE_5GBASER: 1210 case MV88E6393X_PORT_STS_CMODE_10GBASER: 1211 err = mv88e6393x_serdes_irq_status_10g(chip, lane, &status); 1212 if (err) 1213 return err; 1214 if (status & MV88E6393X_10G_INT_LINK_CHANGE) { 1215 ret = IRQ_HANDLED; 1216 mv88e6393x_serdes_irq_link_10g(chip, port, lane); 1217 } 1218 break; 1219 } 1220 1221 return ret; 1222 } 1223 1224 irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, 1225 int lane) 1226 { 1227 u8 cmode = chip->ports[port].cmode; 1228 irqreturn_t ret = IRQ_NONE; 1229 u16 status; 1230 int err; 1231 1232 switch (cmode) { 1233 case MV88E6XXX_PORT_STS_CMODE_SGMII: 1234 case MV88E6XXX_PORT_STS_CMODE_1000BASEX: 1235 case MV88E6XXX_PORT_STS_CMODE_2500BASEX: 1236 err = mv88e6390_serdes_irq_status_sgmii(chip, lane, &status); 1237 if (err) 1238 return ret; 1239 if (status & (MV88E6390_SGMII_INT_LINK_DOWN | 1240 MV88E6390_SGMII_INT_LINK_UP)) { 1241 ret = IRQ_HANDLED; 1242 mv88e6390_serdes_irq_link_sgmii(chip, port, lane); 1243 } 1244 } 1245 1246 return ret; 1247 } 1248 1249 unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port) 1250 { 1251 return irq_find_mapping(chip->g2_irq.domain, port); 1252 } 1253 1254 static const u16 mv88e6390_serdes_regs[] = { 1255 /* SERDES common registers */ 1256 0xf00a, 0xf00b, 0xf00c, 1257 0xf010, 0xf011, 0xf012, 0xf013, 1258 0xf016, 0xf017, 0xf018, 1259 0xf01b, 0xf01c, 0xf01d, 0xf01e, 0xf01f, 1260 0xf020, 0xf021, 0xf022, 0xf023, 0xf024, 0xf025, 0xf026, 0xf027, 1261 0xf028, 0xf029, 1262 0xf030, 0xf031, 0xf032, 0xf033, 0xf034, 0xf035, 0xf036, 0xf037, 1263 0xf038, 0xf039, 1264 /* SGMII */ 1265 0x2000, 0x2001, 0x2002, 0x2003, 0x2004, 0x2005, 0x2006, 0x2007, 1266 0x2008, 1267 0x200f, 1268 0xa000, 0xa001, 0xa002, 0xa003, 1269 /* 10Gbase-X */ 1270 0x1000, 0x1001, 0x1002, 0x1003, 0x1004, 0x1005, 0x1006, 0x1007, 1271 0x1008, 1272 0x100e, 0x100f, 1273 0x1018, 0x1019, 1274 0x9000, 0x9001, 0x9002, 0x9003, 0x9004, 1275 0x9006, 1276 0x9010, 0x9011, 0x9012, 0x9013, 0x9014, 0x9015, 0x9016, 1277 /* 10Gbase-R */ 1278 0x1020, 0x1021, 0x1022, 0x1023, 0x1024, 0x1025, 0x1026, 0x1027, 1279 0x1028, 0x1029, 0x102a, 0x102b, 1280 }; 1281 1282 int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port) 1283 { 1284 if (mv88e6xxx_serdes_get_lane(chip, port) < 0) 1285 return 0; 1286 1287 return ARRAY_SIZE(mv88e6390_serdes_regs) * sizeof(u16); 1288 } 1289 1290 void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p) 1291 { 1292 u16 *p = _p; 1293 int lane; 1294 u16 reg; 1295 int err; 1296 int i; 1297 1298 lane = mv88e6xxx_serdes_get_lane(chip, port); 1299 if (lane < 0) 1300 return; 1301 1302 for (i = 0 ; i < ARRAY_SIZE(mv88e6390_serdes_regs); i++) { 1303 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1304 mv88e6390_serdes_regs[i], ®); 1305 if (!err) 1306 p[i] = reg; 1307 } 1308 } 1309 1310 static int mv88e6393x_serdes_power_lane(struct mv88e6xxx_chip *chip, int lane, 1311 bool on) 1312 { 1313 u16 reg; 1314 int err; 1315 1316 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1317 MV88E6393X_SERDES_CTRL1, ®); 1318 if (err) 1319 return err; 1320 1321 if (on) 1322 reg &= ~(MV88E6393X_SERDES_CTRL1_TX_PDOWN | 1323 MV88E6393X_SERDES_CTRL1_RX_PDOWN); 1324 else 1325 reg |= MV88E6393X_SERDES_CTRL1_TX_PDOWN | 1326 MV88E6393X_SERDES_CTRL1_RX_PDOWN; 1327 1328 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 1329 MV88E6393X_SERDES_CTRL1, reg); 1330 } 1331 1332 static int mv88e6393x_serdes_erratum_4_6(struct mv88e6xxx_chip *chip, int lane) 1333 { 1334 u16 reg; 1335 int err; 1336 1337 /* mv88e6393x family errata 4.6: 1338 * Cannot clear PwrDn bit on SERDES if device is configured CPU_MGD 1339 * mode or P0_mode is configured for [x]MII. 1340 * Workaround: Set SERDES register 4.F002 bit 5=0 and bit 15=1. 1341 * 1342 * It seems that after this workaround the SERDES is automatically 1343 * powered up (the bit is cleared), so power it down. 1344 */ 1345 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1346 MV88E6393X_SERDES_POC, ®); 1347 if (err) 1348 return err; 1349 1350 reg &= ~MV88E6393X_SERDES_POC_PDOWN; 1351 reg |= MV88E6393X_SERDES_POC_RESET; 1352 1353 err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 1354 MV88E6393X_SERDES_POC, reg); 1355 if (err) 1356 return err; 1357 1358 err = mv88e6390_serdes_power_sgmii(chip, lane, false); 1359 if (err) 1360 return err; 1361 1362 return mv88e6393x_serdes_power_lane(chip, lane, false); 1363 } 1364 1365 int mv88e6393x_serdes_setup_errata(struct mv88e6xxx_chip *chip) 1366 { 1367 int err; 1368 1369 err = mv88e6393x_serdes_erratum_4_6(chip, MV88E6393X_PORT0_LANE); 1370 if (err) 1371 return err; 1372 1373 err = mv88e6393x_serdes_erratum_4_6(chip, MV88E6393X_PORT9_LANE); 1374 if (err) 1375 return err; 1376 1377 return mv88e6393x_serdes_erratum_4_6(chip, MV88E6393X_PORT10_LANE); 1378 } 1379 1380 static int mv88e6393x_serdes_erratum_4_8(struct mv88e6xxx_chip *chip, int lane) 1381 { 1382 u16 reg, pcs; 1383 int err; 1384 1385 /* mv88e6393x family errata 4.8: 1386 * When a SERDES port is operating in 1000BASE-X or SGMII mode link may 1387 * not come up after hardware reset or software reset of SERDES core. 1388 * Workaround is to write SERDES register 4.F074.14=1 for only those 1389 * modes and 0 in all other modes. 1390 */ 1391 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1392 MV88E6393X_SERDES_POC, &pcs); 1393 if (err) 1394 return err; 1395 1396 pcs &= MV88E6393X_SERDES_POC_PCS_MASK; 1397 1398 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1399 MV88E6393X_ERRATA_4_8_REG, ®); 1400 if (err) 1401 return err; 1402 1403 if (pcs == MV88E6393X_SERDES_POC_PCS_1000BASEX || 1404 pcs == MV88E6393X_SERDES_POC_PCS_SGMII_PHY || 1405 pcs == MV88E6393X_SERDES_POC_PCS_SGMII_MAC) 1406 reg |= MV88E6393X_ERRATA_4_8_BIT; 1407 else 1408 reg &= ~MV88E6393X_ERRATA_4_8_BIT; 1409 1410 return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 1411 MV88E6393X_ERRATA_4_8_REG, reg); 1412 } 1413 1414 static int mv88e6393x_serdes_erratum_5_2(struct mv88e6xxx_chip *chip, int lane, 1415 u8 cmode) 1416 { 1417 static const struct { 1418 u16 dev, reg, val, mask; 1419 } fixes[] = { 1420 { MDIO_MMD_VEND1, 0x8093, 0xcb5a, 0xffff }, 1421 { MDIO_MMD_VEND1, 0x8171, 0x7088, 0xffff }, 1422 { MDIO_MMD_VEND1, 0x80c9, 0x311a, 0xffff }, 1423 { MDIO_MMD_VEND1, 0x80a2, 0x8000, 0xff7f }, 1424 { MDIO_MMD_VEND1, 0x80a9, 0x0000, 0xfff0 }, 1425 { MDIO_MMD_VEND1, 0x80a3, 0x0000, 0xf8ff }, 1426 { MDIO_MMD_PHYXS, MV88E6393X_SERDES_POC, 1427 MV88E6393X_SERDES_POC_RESET, MV88E6393X_SERDES_POC_RESET }, 1428 }; 1429 int err, i; 1430 u16 reg; 1431 1432 /* mv88e6393x family errata 5.2: 1433 * For optimal signal integrity the following sequence should be applied 1434 * to SERDES operating in 10G mode. These registers only apply to 10G 1435 * operation and have no effect on other speeds. 1436 */ 1437 if (cmode != MV88E6393X_PORT_STS_CMODE_10GBASER) 1438 return 0; 1439 1440 for (i = 0; i < ARRAY_SIZE(fixes); ++i) { 1441 err = mv88e6390_serdes_read(chip, lane, fixes[i].dev, 1442 fixes[i].reg, ®); 1443 if (err) 1444 return err; 1445 1446 reg &= ~fixes[i].mask; 1447 reg |= fixes[i].val; 1448 1449 err = mv88e6390_serdes_write(chip, lane, fixes[i].dev, 1450 fixes[i].reg, reg); 1451 if (err) 1452 return err; 1453 } 1454 1455 return 0; 1456 } 1457 1458 static int mv88e6393x_serdes_fix_2500basex_an(struct mv88e6xxx_chip *chip, 1459 int lane, u8 cmode, bool on) 1460 { 1461 u16 reg; 1462 int err; 1463 1464 if (cmode != MV88E6XXX_PORT_STS_CMODE_2500BASEX) 1465 return 0; 1466 1467 /* Inband AN is broken on Amethyst in 2500base-x mode when set by 1468 * standard mechanism (via cmode). 1469 * We can get around this by configuring the PCS mode to 1000base-x 1470 * and then writing value 0x58 to register 1e.8000. (This must be done 1471 * while SerDes receiver and transmitter are disabled, which is, when 1472 * this function is called.) 1473 * It seem that when we do this configuration to 2500base-x mode (by 1474 * changing PCS mode to 1000base-x and frequency to 3.125 GHz from 1475 * 1.25 GHz) and then configure to sgmii or 1000base-x, the device 1476 * thinks that it already has SerDes at 1.25 GHz and does not change 1477 * the 1e.8000 register, leaving SerDes at 3.125 GHz. 1478 * To avoid this, change PCS mode back to 2500base-x when disabling 1479 * SerDes from 2500base-x mode. 1480 */ 1481 err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, 1482 MV88E6393X_SERDES_POC, ®); 1483 if (err) 1484 return err; 1485 1486 reg &= ~(MV88E6393X_SERDES_POC_PCS_MASK | MV88E6393X_SERDES_POC_AN); 1487 if (on) 1488 reg |= MV88E6393X_SERDES_POC_PCS_1000BASEX | 1489 MV88E6393X_SERDES_POC_AN; 1490 else 1491 reg |= MV88E6393X_SERDES_POC_PCS_2500BASEX; 1492 reg |= MV88E6393X_SERDES_POC_RESET; 1493 1494 err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, 1495 MV88E6393X_SERDES_POC, reg); 1496 if (err) 1497 return err; 1498 1499 err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_VEND1, 0x8000, 0x58); 1500 if (err) 1501 return err; 1502 1503 return 0; 1504 } 1505 1506 int mv88e6393x_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane, 1507 bool on) 1508 { 1509 u8 cmode = chip->ports[port].cmode; 1510 int err; 1511 1512 if (port != 0 && port != 9 && port != 10) 1513 return -EOPNOTSUPP; 1514 1515 if (on) { 1516 err = mv88e6393x_serdes_erratum_4_8(chip, lane); 1517 if (err) 1518 return err; 1519 1520 err = mv88e6393x_serdes_erratum_5_2(chip, lane, cmode); 1521 if (err) 1522 return err; 1523 1524 err = mv88e6393x_serdes_fix_2500basex_an(chip, lane, cmode, 1525 true); 1526 if (err) 1527 return err; 1528 1529 err = mv88e6393x_serdes_power_lane(chip, lane, true); 1530 if (err) 1531 return err; 1532 } 1533 1534 switch (cmode) { 1535 case MV88E6XXX_PORT_STS_CMODE_SGMII: 1536 case MV88E6XXX_PORT_STS_CMODE_1000BASEX: 1537 case MV88E6XXX_PORT_STS_CMODE_2500BASEX: 1538 err = mv88e6390_serdes_power_sgmii(chip, lane, on); 1539 break; 1540 case MV88E6393X_PORT_STS_CMODE_5GBASER: 1541 case MV88E6393X_PORT_STS_CMODE_10GBASER: 1542 err = mv88e6390_serdes_power_10g(chip, lane, on); 1543 break; 1544 } 1545 1546 if (err) 1547 return err; 1548 1549 if (!on) { 1550 err = mv88e6393x_serdes_power_lane(chip, lane, false); 1551 if (err) 1552 return err; 1553 1554 err = mv88e6393x_serdes_fix_2500basex_an(chip, lane, cmode, 1555 false); 1556 } 1557 1558 return err; 1559 } 1560