1 /* 2 * Marvell 88E6xxx Switch PTP support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2017 National Instruments 7 * Erik Hons <erik.hons@ni.com> 8 * Brandon Streiff <brandon.streiff@ni.com> 9 * Dane Wagner <dane.wagner@ni.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #ifndef _MV88E6XXX_PTP_H 18 #define _MV88E6XXX_PTP_H 19 20 #include "chip.h" 21 22 /* Offset 0x00: TAI Global Config */ 23 #define MV88E6XXX_TAI_CFG 0x00 24 #define MV88E6XXX_TAI_CFG_CAP_OVERWRITE 0x8000 25 #define MV88E6XXX_TAI_CFG_CAP_CTR_START 0x4000 26 #define MV88E6XXX_TAI_CFG_EVREQ_FALLING 0x2000 27 #define MV88E6XXX_TAI_CFG_TRIG_ACTIVE_LO 0x1000 28 #define MV88E6XXX_TAI_CFG_IRL_ENABLE 0x0400 29 #define MV88E6XXX_TAI_CFG_TRIG_IRQ_EN 0x0200 30 #define MV88E6XXX_TAI_CFG_EVREQ_IRQ_EN 0x0100 31 #define MV88E6XXX_TAI_CFG_TRIG_LOCK 0x0080 32 #define MV88E6XXX_TAI_CFG_BLOCK_UPDATE 0x0008 33 #define MV88E6XXX_TAI_CFG_MULTI_PTP 0x0004 34 #define MV88E6XXX_TAI_CFG_TRIG_MODE_ONESHOT 0x0002 35 #define MV88E6XXX_TAI_CFG_TRIG_ENABLE 0x0001 36 37 /* Offset 0x01: Timestamp Clock Period (ps) */ 38 #define MV88E6XXX_TAI_CLOCK_PERIOD 0x01 39 40 /* Offset 0x02/0x03: Trigger Generation Amount */ 41 #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO 0x02 42 #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI 0x03 43 44 /* Offset 0x04: Clock Compensation */ 45 #define MV88E6XXX_TAI_TRIG_CLOCK_COMP 0x04 46 47 /* Offset 0x05: Trigger Configuration */ 48 #define MV88E6XXX_TAI_TRIG_CFG 0x05 49 50 /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */ 51 #define MV88E6XXX_TAI_IRL_AMOUNT 0x06 52 53 /* Offset 0x07: Ingress Rate Limiter Compensation */ 54 #define MV88E6XXX_TAI_IRL_COMP 0x07 55 56 /* Offset 0x08: Ingress Rate Limiter Compensation */ 57 #define MV88E6XXX_TAI_IRL_COMP_PS 0x08 58 59 /* Offset 0x09: Event Status */ 60 #define MV88E6XXX_TAI_EVENT_STATUS 0x09 61 #define MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG 0x4000 62 #define MV88E6XXX_TAI_EVENT_STATUS_ERROR 0x0200 63 #define MV88E6XXX_TAI_EVENT_STATUS_VALID 0x0100 64 #define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK 0x00ff 65 66 /* Offset 0x0A/0x0B: Event Time */ 67 #define MV88E6XXX_TAI_EVENT_TIME_LO 0x0a 68 #define MV88E6XXX_TAI_EVENT_TYPE_HI 0x0b 69 70 /* Offset 0x0E/0x0F: PTP Global Time */ 71 #define MV88E6XXX_TAI_TIME_LO 0x0e 72 #define MV88E6XXX_TAI_TIME_HI 0x0f 73 74 /* Offset 0x10/0x11: Trig Generation Time */ 75 #define MV88E6XXX_TAI_TRIG_TIME_LO 0x10 76 #define MV88E6XXX_TAI_TRIG_TIME_HI 0x11 77 78 /* Offset 0x12: Lock Status */ 79 #define MV88E6XXX_TAI_LOCK_STATUS 0x12 80 81 /* Offset 0x00: Ether Type */ 82 #define MV88E6XXX_PTP_GC_ETYPE 0x00 83 84 /* 6165 Global Control Registers */ 85 /* Offset 0x00: Ether Type */ 86 #define MV88E6XXX_PTP_GC_ETYPE 0x00 87 88 /* Offset 0x01: Message ID */ 89 #define MV88E6XXX_PTP_GC_MESSAGE_ID 0x01 90 91 /* Offset 0x02: Time Stamp Arrive Time */ 92 #define MV88E6XXX_PTP_GC_TS_ARR_PTR 0x02 93 94 /* Offset 0x03: Port Arrival Interrupt Enable */ 95 #define MV88E6XXX_PTP_GC_PORT_ARR_INT_EN 0x03 96 97 /* Offset 0x04: Port Departure Interrupt Enable */ 98 #define MV88E6XXX_PTP_GC_PORT_DEP_INT_EN 0x04 99 100 /* Offset 0x05: Configuration */ 101 #define MV88E6XXX_PTP_GC_CONFIG 0x05 102 #define MV88E6XXX_PTP_GC_CONFIG_DIS_OVERWRITE BIT(1) 103 #define MV88E6XXX_PTP_GC_CONFIG_DIS_TS BIT(0) 104 105 /* Offset 0x8: Interrupt Status */ 106 #define MV88E6XXX_PTP_GC_INT_STATUS 0x08 107 108 /* Offset 0x9/0xa: Global Time */ 109 #define MV88E6XXX_PTP_GC_TIME_LO 0x09 110 #define MV88E6XXX_PTP_GC_TIME_HI 0x0A 111 112 /* 6165 Per Port Registers */ 113 /* Offset 0: Arrival Time 0 Status */ 114 #define MV88E6165_PORT_PTP_ARR0_STS 0x00 115 116 /* Offset 0x01/0x02: PTP Arrival 0 Time */ 117 #define MV88E6165_PORT_PTP_ARR0_TIME_LO 0x01 118 #define MV88E6165_PORT_PTP_ARR0_TIME_HI 0x02 119 120 /* Offset 0x03: PTP Arrival 0 Sequence ID */ 121 #define MV88E6165_PORT_PTP_ARR0_SEQID 0x03 122 123 /* Offset 0x04: PTP Arrival 1 Status */ 124 #define MV88E6165_PORT_PTP_ARR1_STS 0x04 125 126 /* Offset 0x05/0x6E: PTP Arrival 1 Time */ 127 #define MV88E6165_PORT_PTP_ARR1_TIME_LO 0x05 128 #define MV88E6165_PORT_PTP_ARR1_TIME_HI 0x06 129 130 /* Offset 0x07: PTP Arrival 1 Sequence ID */ 131 #define MV88E6165_PORT_PTP_ARR1_SEQID 0x07 132 133 /* Offset 0x08: PTP Departure Status */ 134 #define MV88E6165_PORT_PTP_DEP_STS 0x08 135 136 /* Offset 0x09/0x0a: PTP Deperture Time */ 137 #define MV88E6165_PORT_PTP_DEP_TIME_LO 0x09 138 #define MV88E6165_PORT_PTP_DEP_TIME_HI 0x0a 139 140 /* Offset 0x0b: PTP Departure Sequence ID */ 141 #define MV88E6165_PORT_PTP_DEP_SEQID 0x0b 142 143 /* Offset 0x0d: Port Status */ 144 #define MV88E6164_PORT_STATUS 0x0d 145 146 #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP 147 148 long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp); 149 int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip); 150 void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip); 151 152 #define ptp_to_chip(ptp) container_of(ptp, struct mv88e6xxx_chip, \ 153 ptp_clock_info) 154 155 extern const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops; 156 extern const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops; 157 158 #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */ 159 160 static inline long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp) 161 { 162 return -1; 163 } 164 165 static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip) 166 { 167 return 0; 168 } 169 170 static inline void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip) 171 { 172 } 173 174 static const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {}; 175 static const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {}; 176 177 #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */ 178 179 #endif /* _MV88E6XXX_PTP_H */ 180