12fa8d3afSBrandon Streiff /* 22fa8d3afSBrandon Streiff * Marvell 88E6xxx Switch PTP support 32fa8d3afSBrandon Streiff * 42fa8d3afSBrandon Streiff * Copyright (c) 2008 Marvell Semiconductor 52fa8d3afSBrandon Streiff * 62fa8d3afSBrandon Streiff * Copyright (c) 2017 National Instruments 72fa8d3afSBrandon Streiff * Erik Hons <erik.hons@ni.com> 82fa8d3afSBrandon Streiff * Brandon Streiff <brandon.streiff@ni.com> 92fa8d3afSBrandon Streiff * Dane Wagner <dane.wagner@ni.com> 102fa8d3afSBrandon Streiff * 112fa8d3afSBrandon Streiff * This program is free software; you can redistribute it and/or modify 122fa8d3afSBrandon Streiff * it under the terms of the GNU General Public License as published by 132fa8d3afSBrandon Streiff * the Free Software Foundation; either version 2 of the License, or 142fa8d3afSBrandon Streiff * (at your option) any later version. 152fa8d3afSBrandon Streiff */ 162fa8d3afSBrandon Streiff 172fa8d3afSBrandon Streiff #ifndef _MV88E6XXX_PTP_H 182fa8d3afSBrandon Streiff #define _MV88E6XXX_PTP_H 192fa8d3afSBrandon Streiff 202fa8d3afSBrandon Streiff #include "chip.h" 212fa8d3afSBrandon Streiff 222fa8d3afSBrandon Streiff /* Offset 0x00: TAI Global Config */ 232fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_CFG 0x00 244eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_CAP_OVERWRITE 0x8000 254eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_CAP_CTR_START 0x4000 264eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_EVREQ_FALLING 0x2000 274eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_TRIG_ACTIVE_LO 0x1000 284eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_IRL_ENABLE 0x0400 294eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_TRIG_IRQ_EN 0x0200 304eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_EVREQ_IRQ_EN 0x0100 314eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_TRIG_LOCK 0x0080 324eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_BLOCK_UPDATE 0x0008 334eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_MULTI_PTP 0x0004 344eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_TRIG_MODE_ONESHOT 0x0002 354eb3be29SBrandon Streiff #define MV88E6XXX_TAI_CFG_TRIG_ENABLE 0x0001 362fa8d3afSBrandon Streiff 372fa8d3afSBrandon Streiff /* Offset 0x01: Timestamp Clock Period (ps) */ 382fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_CLOCK_PERIOD 0x01 392fa8d3afSBrandon Streiff 402fa8d3afSBrandon Streiff /* Offset 0x02/0x03: Trigger Generation Amount */ 412fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO 0x02 422fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI 0x03 432fa8d3afSBrandon Streiff 442fa8d3afSBrandon Streiff /* Offset 0x04: Clock Compensation */ 452fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_TRIG_CLOCK_COMP 0x04 462fa8d3afSBrandon Streiff 472fa8d3afSBrandon Streiff /* Offset 0x05: Trigger Configuration */ 482fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_TRIG_CFG 0x05 492fa8d3afSBrandon Streiff 502fa8d3afSBrandon Streiff /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */ 512fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_IRL_AMOUNT 0x06 522fa8d3afSBrandon Streiff 532fa8d3afSBrandon Streiff /* Offset 0x07: Ingress Rate Limiter Compensation */ 542fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_IRL_COMP 0x07 552fa8d3afSBrandon Streiff 562fa8d3afSBrandon Streiff /* Offset 0x08: Ingress Rate Limiter Compensation */ 572fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_IRL_COMP_PS 0x08 582fa8d3afSBrandon Streiff 592fa8d3afSBrandon Streiff /* Offset 0x09: Event Status */ 602fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_EVENT_STATUS 0x09 614eb3be29SBrandon Streiff #define MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG 0x4000 624eb3be29SBrandon Streiff #define MV88E6XXX_TAI_EVENT_STATUS_ERROR 0x0200 634eb3be29SBrandon Streiff #define MV88E6XXX_TAI_EVENT_STATUS_VALID 0x0100 644eb3be29SBrandon Streiff #define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK 0x00ff 652fa8d3afSBrandon Streiff 662fa8d3afSBrandon Streiff /* Offset 0x0A/0x0B: Event Time */ 672fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_EVENT_TIME_LO 0x0a 682fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_EVENT_TYPE_HI 0x0b 692fa8d3afSBrandon Streiff 702fa8d3afSBrandon Streiff /* Offset 0x0E/0x0F: PTP Global Time */ 712fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_TIME_LO 0x0e 722fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_TIME_HI 0x0f 732fa8d3afSBrandon Streiff 742fa8d3afSBrandon Streiff /* Offset 0x10/0x11: Trig Generation Time */ 752fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_TRIG_TIME_LO 0x10 762fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_TRIG_TIME_HI 0x11 772fa8d3afSBrandon Streiff 782fa8d3afSBrandon Streiff /* Offset 0x12: Lock Status */ 792fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_LOCK_STATUS 0x12 802fa8d3afSBrandon Streiff 812fa8d3afSBrandon Streiff #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP 822fa8d3afSBrandon Streiff 83c6fe0ad2SBrandon Streiff long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp); 842fa8d3afSBrandon Streiff int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip); 852fa8d3afSBrandon Streiff void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip); 862fa8d3afSBrandon Streiff 87c6fe0ad2SBrandon Streiff #define ptp_to_chip(ptp) container_of(ptp, struct mv88e6xxx_chip, \ 88c6fe0ad2SBrandon Streiff ptp_clock_info) 89c6fe0ad2SBrandon Streiff 902fa8d3afSBrandon Streiff #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */ 912fa8d3afSBrandon Streiff 9246182452SArnd Bergmann static inline long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp) 93c6fe0ad2SBrandon Streiff { 94c6fe0ad2SBrandon Streiff return -1; 95c6fe0ad2SBrandon Streiff } 96c6fe0ad2SBrandon Streiff 972fa8d3afSBrandon Streiff static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip) 982fa8d3afSBrandon Streiff { 992fa8d3afSBrandon Streiff return 0; 1002fa8d3afSBrandon Streiff } 1012fa8d3afSBrandon Streiff 10246182452SArnd Bergmann static inline void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip) 1032fa8d3afSBrandon Streiff { 1042fa8d3afSBrandon Streiff } 1052fa8d3afSBrandon Streiff 1062fa8d3afSBrandon Streiff #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */ 1072fa8d3afSBrandon Streiff 1082fa8d3afSBrandon Streiff #endif /* _MV88E6XXX_PTP_H */ 109