1 /* 2 * Marvell 88E6xxx Switch PTP support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2017 National Instruments 7 * Erik Hons <erik.hons@ni.com> 8 * Brandon Streiff <brandon.streiff@ni.com> 9 * Dane Wagner <dane.wagner@ni.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "chip.h" 18 #include "global2.h" 19 #include "ptp.h" 20 21 /* Raw timestamps are in units of 8-ns clock periods. */ 22 #define CC_SHIFT 28 23 #define CC_MULT (8 << CC_SHIFT) 24 #define CC_MULT_NUM (1 << 9) 25 #define CC_MULT_DEM 15625ULL 26 27 #define TAI_EVENT_WORK_INTERVAL msecs_to_jiffies(100) 28 29 #define cc_to_chip(cc) container_of(cc, struct mv88e6xxx_chip, tstamp_cc) 30 #define dw_overflow_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \ 31 overflow_work) 32 #define dw_tai_event_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \ 33 tai_event_work) 34 35 static int mv88e6xxx_tai_read(struct mv88e6xxx_chip *chip, int addr, 36 u16 *data, int len) 37 { 38 if (!chip->info->ops->avb_ops->tai_read) 39 return -EOPNOTSUPP; 40 41 return chip->info->ops->avb_ops->tai_read(chip, addr, data, len); 42 } 43 44 static int mv88e6xxx_tai_write(struct mv88e6xxx_chip *chip, int addr, u16 data) 45 { 46 if (!chip->info->ops->avb_ops->tai_write) 47 return -EOPNOTSUPP; 48 49 return chip->info->ops->avb_ops->tai_write(chip, addr, data); 50 } 51 52 /* TODO: places where this are called should be using pinctrl */ 53 static int mv88e6xxx_set_gpio_func(struct mv88e6xxx_chip *chip, int pin, 54 int func, int input) 55 { 56 int err; 57 58 if (!chip->info->ops->gpio_ops) 59 return -EOPNOTSUPP; 60 61 err = chip->info->ops->gpio_ops->set_dir(chip, pin, input); 62 if (err) 63 return err; 64 65 return chip->info->ops->gpio_ops->set_pctl(chip, pin, func); 66 } 67 68 static u64 mv88e6xxx_ptp_clock_read(const struct cyclecounter *cc) 69 { 70 struct mv88e6xxx_chip *chip = cc_to_chip(cc); 71 u16 phc_time[2]; 72 int err; 73 74 err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_TIME_LO, phc_time, 75 ARRAY_SIZE(phc_time)); 76 if (err) 77 return 0; 78 else 79 return ((u32)phc_time[1] << 16) | phc_time[0]; 80 } 81 82 /* mv88e6xxx_config_eventcap - configure TAI event capture 83 * @event: PTP_CLOCK_PPS (internal) or PTP_CLOCK_EXTTS (external) 84 * @rising: zero for falling-edge trigger, else rising-edge trigger 85 * 86 * This will also reset the capture sequence counter. 87 */ 88 static int mv88e6xxx_config_eventcap(struct mv88e6xxx_chip *chip, int event, 89 int rising) 90 { 91 u16 global_config; 92 u16 cap_config; 93 int err; 94 95 chip->evcap_config = MV88E6XXX_TAI_CFG_CAP_OVERWRITE | 96 MV88E6XXX_TAI_CFG_CAP_CTR_START; 97 if (!rising) 98 chip->evcap_config |= MV88E6XXX_TAI_CFG_EVREQ_FALLING; 99 100 global_config = (chip->evcap_config | chip->trig_config); 101 err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_CFG, global_config); 102 if (err) 103 return err; 104 105 if (event == PTP_CLOCK_PPS) { 106 cap_config = MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG; 107 } else if (event == PTP_CLOCK_EXTTS) { 108 /* if STATUS_CAP_TRIG is unset we capture PTP_EVREQ events */ 109 cap_config = 0; 110 } else { 111 return -EINVAL; 112 } 113 114 /* Write the capture config; this also clears the capture counter */ 115 err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, 116 cap_config); 117 118 return err; 119 } 120 121 static void mv88e6xxx_tai_event_work(struct work_struct *ugly) 122 { 123 struct delayed_work *dw = to_delayed_work(ugly); 124 struct mv88e6xxx_chip *chip = dw_tai_event_to_chip(dw); 125 struct ptp_clock_event ev; 126 u16 status[4]; 127 u32 raw_ts; 128 int err; 129 130 mutex_lock(&chip->reg_lock); 131 err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_EVENT_STATUS, 132 status, ARRAY_SIZE(status)); 133 mutex_unlock(&chip->reg_lock); 134 135 if (err) { 136 dev_err(chip->dev, "failed to read TAI status register\n"); 137 return; 138 } 139 if (status[0] & MV88E6XXX_TAI_EVENT_STATUS_ERROR) { 140 dev_warn(chip->dev, "missed event capture\n"); 141 return; 142 } 143 if (!(status[0] & MV88E6XXX_TAI_EVENT_STATUS_VALID)) 144 goto out; 145 146 raw_ts = ((u32)status[2] << 16) | status[1]; 147 148 /* Clear the valid bit so the next timestamp can come in */ 149 status[0] &= ~MV88E6XXX_TAI_EVENT_STATUS_VALID; 150 mutex_lock(&chip->reg_lock); 151 err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, status[0]); 152 mutex_unlock(&chip->reg_lock); 153 154 /* This is an external timestamp */ 155 ev.type = PTP_CLOCK_EXTTS; 156 157 /* We only have one timestamping channel. */ 158 ev.index = 0; 159 mutex_lock(&chip->reg_lock); 160 ev.timestamp = timecounter_cyc2time(&chip->tstamp_tc, raw_ts); 161 mutex_unlock(&chip->reg_lock); 162 163 ptp_clock_event(chip->ptp_clock, &ev); 164 out: 165 schedule_delayed_work(&chip->tai_event_work, TAI_EVENT_WORK_INTERVAL); 166 } 167 168 static int mv88e6xxx_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 169 { 170 struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); 171 int neg_adj = 0; 172 u32 diff, mult; 173 u64 adj; 174 175 if (scaled_ppm < 0) { 176 neg_adj = 1; 177 scaled_ppm = -scaled_ppm; 178 } 179 mult = CC_MULT; 180 adj = CC_MULT_NUM; 181 adj *= scaled_ppm; 182 diff = div_u64(adj, CC_MULT_DEM); 183 184 mutex_lock(&chip->reg_lock); 185 186 timecounter_read(&chip->tstamp_tc); 187 chip->tstamp_cc.mult = neg_adj ? mult - diff : mult + diff; 188 189 mutex_unlock(&chip->reg_lock); 190 191 return 0; 192 } 193 194 static int mv88e6xxx_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 195 { 196 struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); 197 198 mutex_lock(&chip->reg_lock); 199 timecounter_adjtime(&chip->tstamp_tc, delta); 200 mutex_unlock(&chip->reg_lock); 201 202 return 0; 203 } 204 205 static int mv88e6xxx_ptp_gettime(struct ptp_clock_info *ptp, 206 struct timespec64 *ts) 207 { 208 struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); 209 u64 ns; 210 211 mutex_lock(&chip->reg_lock); 212 ns = timecounter_read(&chip->tstamp_tc); 213 mutex_unlock(&chip->reg_lock); 214 215 *ts = ns_to_timespec64(ns); 216 217 return 0; 218 } 219 220 static int mv88e6xxx_ptp_settime(struct ptp_clock_info *ptp, 221 const struct timespec64 *ts) 222 { 223 struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); 224 u64 ns; 225 226 ns = timespec64_to_ns(ts); 227 228 mutex_lock(&chip->reg_lock); 229 timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc, ns); 230 mutex_unlock(&chip->reg_lock); 231 232 return 0; 233 } 234 235 static int mv88e6xxx_ptp_enable_extts(struct mv88e6xxx_chip *chip, 236 struct ptp_clock_request *rq, int on) 237 { 238 int rising = (rq->extts.flags & PTP_RISING_EDGE); 239 int func; 240 int pin; 241 int err; 242 243 pin = ptp_find_pin(chip->ptp_clock, PTP_PF_EXTTS, rq->extts.index); 244 245 if (pin < 0) 246 return -EBUSY; 247 248 mutex_lock(&chip->reg_lock); 249 250 if (on) { 251 func = MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ; 252 253 err = mv88e6xxx_set_gpio_func(chip, pin, func, true); 254 if (err) 255 goto out; 256 257 schedule_delayed_work(&chip->tai_event_work, 258 TAI_EVENT_WORK_INTERVAL); 259 260 err = mv88e6xxx_config_eventcap(chip, PTP_CLOCK_EXTTS, rising); 261 } else { 262 func = MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO; 263 264 err = mv88e6xxx_set_gpio_func(chip, pin, func, true); 265 266 cancel_delayed_work_sync(&chip->tai_event_work); 267 } 268 269 out: 270 mutex_unlock(&chip->reg_lock); 271 272 return err; 273 } 274 275 static int mv88e6xxx_ptp_enable(struct ptp_clock_info *ptp, 276 struct ptp_clock_request *rq, int on) 277 { 278 struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); 279 280 switch (rq->type) { 281 case PTP_CLK_REQ_EXTTS: 282 return mv88e6xxx_ptp_enable_extts(chip, rq, on); 283 default: 284 return -EOPNOTSUPP; 285 } 286 } 287 288 static int mv88e6xxx_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin, 289 enum ptp_pin_function func, unsigned int chan) 290 { 291 switch (func) { 292 case PTP_PF_NONE: 293 case PTP_PF_EXTTS: 294 break; 295 case PTP_PF_PEROUT: 296 case PTP_PF_PHYSYNC: 297 return -EOPNOTSUPP; 298 } 299 return 0; 300 } 301 302 /* With a 125MHz input clock, the 32-bit timestamp counter overflows in ~34.3 303 * seconds; this task forces periodic reads so that we don't miss any. 304 */ 305 #define MV88E6XXX_TAI_OVERFLOW_PERIOD (HZ * 16) 306 static void mv88e6xxx_ptp_overflow_check(struct work_struct *work) 307 { 308 struct delayed_work *dw = to_delayed_work(work); 309 struct mv88e6xxx_chip *chip = dw_overflow_to_chip(dw); 310 struct timespec64 ts; 311 312 mv88e6xxx_ptp_gettime(&chip->ptp_clock_info, &ts); 313 314 schedule_delayed_work(&chip->overflow_work, 315 MV88E6XXX_TAI_OVERFLOW_PERIOD); 316 } 317 318 int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip) 319 { 320 int i; 321 322 /* Set up the cycle counter */ 323 memset(&chip->tstamp_cc, 0, sizeof(chip->tstamp_cc)); 324 chip->tstamp_cc.read = mv88e6xxx_ptp_clock_read; 325 chip->tstamp_cc.mask = CYCLECOUNTER_MASK(32); 326 chip->tstamp_cc.mult = CC_MULT; 327 chip->tstamp_cc.shift = CC_SHIFT; 328 329 timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc, 330 ktime_to_ns(ktime_get_real())); 331 332 INIT_DELAYED_WORK(&chip->overflow_work, mv88e6xxx_ptp_overflow_check); 333 INIT_DELAYED_WORK(&chip->tai_event_work, mv88e6xxx_tai_event_work); 334 335 chip->ptp_clock_info.owner = THIS_MODULE; 336 snprintf(chip->ptp_clock_info.name, sizeof(chip->ptp_clock_info.name), 337 dev_name(chip->dev)); 338 chip->ptp_clock_info.max_adj = 1000000; 339 340 chip->ptp_clock_info.n_ext_ts = 1; 341 chip->ptp_clock_info.n_per_out = 0; 342 chip->ptp_clock_info.n_pins = mv88e6xxx_num_gpio(chip); 343 chip->ptp_clock_info.pps = 0; 344 345 for (i = 0; i < chip->ptp_clock_info.n_pins; ++i) { 346 struct ptp_pin_desc *ppd = &chip->pin_config[i]; 347 348 snprintf(ppd->name, sizeof(ppd->name), "mv88e6xxx_gpio%d", i); 349 ppd->index = i; 350 ppd->func = PTP_PF_NONE; 351 } 352 chip->ptp_clock_info.pin_config = chip->pin_config; 353 354 chip->ptp_clock_info.adjfine = mv88e6xxx_ptp_adjfine; 355 chip->ptp_clock_info.adjtime = mv88e6xxx_ptp_adjtime; 356 chip->ptp_clock_info.gettime64 = mv88e6xxx_ptp_gettime; 357 chip->ptp_clock_info.settime64 = mv88e6xxx_ptp_settime; 358 chip->ptp_clock_info.enable = mv88e6xxx_ptp_enable; 359 chip->ptp_clock_info.verify = mv88e6xxx_ptp_verify; 360 chip->ptp_clock_info.do_aux_work = mv88e6xxx_hwtstamp_work; 361 362 chip->ptp_clock = ptp_clock_register(&chip->ptp_clock_info, chip->dev); 363 if (IS_ERR(chip->ptp_clock)) 364 return PTR_ERR(chip->ptp_clock); 365 366 schedule_delayed_work(&chip->overflow_work, 367 MV88E6XXX_TAI_OVERFLOW_PERIOD); 368 369 return 0; 370 } 371 372 void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip) 373 { 374 if (chip->ptp_clock) { 375 cancel_delayed_work_sync(&chip->overflow_work); 376 cancel_delayed_work_sync(&chip->tai_event_work); 377 378 ptp_clock_unregister(chip->ptp_clock); 379 chip->ptp_clock = NULL; 380 } 381 } 382