1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch PTP support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2017 National Instruments 8 * Erik Hons <erik.hons@ni.com> 9 * Brandon Streiff <brandon.streiff@ni.com> 10 * Dane Wagner <dane.wagner@ni.com> 11 */ 12 13 #include "chip.h" 14 #include "global2.h" 15 #include "hwtstamp.h" 16 #include "ptp.h" 17 18 /* Raw timestamps are in units of 8-ns clock periods. */ 19 #define CC_SHIFT 28 20 #define CC_MULT (8 << CC_SHIFT) 21 #define CC_MULT_NUM (1 << 9) 22 #define CC_MULT_DEM 15625ULL 23 24 #define TAI_EVENT_WORK_INTERVAL msecs_to_jiffies(100) 25 26 #define cc_to_chip(cc) container_of(cc, struct mv88e6xxx_chip, tstamp_cc) 27 #define dw_overflow_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \ 28 overflow_work) 29 #define dw_tai_event_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \ 30 tai_event_work) 31 32 static int mv88e6xxx_tai_read(struct mv88e6xxx_chip *chip, int addr, 33 u16 *data, int len) 34 { 35 if (!chip->info->ops->avb_ops->tai_read) 36 return -EOPNOTSUPP; 37 38 return chip->info->ops->avb_ops->tai_read(chip, addr, data, len); 39 } 40 41 static int mv88e6xxx_tai_write(struct mv88e6xxx_chip *chip, int addr, u16 data) 42 { 43 if (!chip->info->ops->avb_ops->tai_write) 44 return -EOPNOTSUPP; 45 46 return chip->info->ops->avb_ops->tai_write(chip, addr, data); 47 } 48 49 /* TODO: places where this are called should be using pinctrl */ 50 static int mv88e6352_set_gpio_func(struct mv88e6xxx_chip *chip, int pin, 51 int func, int input) 52 { 53 int err; 54 55 if (!chip->info->ops->gpio_ops) 56 return -EOPNOTSUPP; 57 58 err = chip->info->ops->gpio_ops->set_dir(chip, pin, input); 59 if (err) 60 return err; 61 62 return chip->info->ops->gpio_ops->set_pctl(chip, pin, func); 63 } 64 65 static u64 mv88e6352_ptp_clock_read(const struct cyclecounter *cc) 66 { 67 struct mv88e6xxx_chip *chip = cc_to_chip(cc); 68 u16 phc_time[2]; 69 int err; 70 71 err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_TIME_LO, phc_time, 72 ARRAY_SIZE(phc_time)); 73 if (err) 74 return 0; 75 else 76 return ((u32)phc_time[1] << 16) | phc_time[0]; 77 } 78 79 static u64 mv88e6165_ptp_clock_read(const struct cyclecounter *cc) 80 { 81 struct mv88e6xxx_chip *chip = cc_to_chip(cc); 82 u16 phc_time[2]; 83 int err; 84 85 err = mv88e6xxx_tai_read(chip, MV88E6XXX_PTP_GC_TIME_LO, phc_time, 86 ARRAY_SIZE(phc_time)); 87 if (err) 88 return 0; 89 else 90 return ((u32)phc_time[1] << 16) | phc_time[0]; 91 } 92 93 /* mv88e6352_config_eventcap - configure TAI event capture 94 * @event: PTP_CLOCK_PPS (internal) or PTP_CLOCK_EXTTS (external) 95 * @rising: zero for falling-edge trigger, else rising-edge trigger 96 * 97 * This will also reset the capture sequence counter. 98 */ 99 static int mv88e6352_config_eventcap(struct mv88e6xxx_chip *chip, int event, 100 int rising) 101 { 102 u16 global_config; 103 u16 cap_config; 104 int err; 105 106 chip->evcap_config = MV88E6XXX_TAI_CFG_CAP_OVERWRITE | 107 MV88E6XXX_TAI_CFG_CAP_CTR_START; 108 if (!rising) 109 chip->evcap_config |= MV88E6XXX_TAI_CFG_EVREQ_FALLING; 110 111 global_config = (chip->evcap_config | chip->trig_config); 112 err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_CFG, global_config); 113 if (err) 114 return err; 115 116 if (event == PTP_CLOCK_PPS) { 117 cap_config = MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG; 118 } else if (event == PTP_CLOCK_EXTTS) { 119 /* if STATUS_CAP_TRIG is unset we capture PTP_EVREQ events */ 120 cap_config = 0; 121 } else { 122 return -EINVAL; 123 } 124 125 /* Write the capture config; this also clears the capture counter */ 126 err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, 127 cap_config); 128 129 return err; 130 } 131 132 static void mv88e6352_tai_event_work(struct work_struct *ugly) 133 { 134 struct delayed_work *dw = to_delayed_work(ugly); 135 struct mv88e6xxx_chip *chip = dw_tai_event_to_chip(dw); 136 struct ptp_clock_event ev; 137 u16 status[4]; 138 u32 raw_ts; 139 int err; 140 141 mv88e6xxx_reg_lock(chip); 142 err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_EVENT_STATUS, 143 status, ARRAY_SIZE(status)); 144 mv88e6xxx_reg_unlock(chip); 145 146 if (err) { 147 dev_err(chip->dev, "failed to read TAI status register\n"); 148 return; 149 } 150 if (status[0] & MV88E6XXX_TAI_EVENT_STATUS_ERROR) { 151 dev_warn(chip->dev, "missed event capture\n"); 152 return; 153 } 154 if (!(status[0] & MV88E6XXX_TAI_EVENT_STATUS_VALID)) 155 goto out; 156 157 raw_ts = ((u32)status[2] << 16) | status[1]; 158 159 /* Clear the valid bit so the next timestamp can come in */ 160 status[0] &= ~MV88E6XXX_TAI_EVENT_STATUS_VALID; 161 mv88e6xxx_reg_lock(chip); 162 err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, status[0]); 163 mv88e6xxx_reg_unlock(chip); 164 165 /* This is an external timestamp */ 166 ev.type = PTP_CLOCK_EXTTS; 167 168 /* We only have one timestamping channel. */ 169 ev.index = 0; 170 mv88e6xxx_reg_lock(chip); 171 ev.timestamp = timecounter_cyc2time(&chip->tstamp_tc, raw_ts); 172 mv88e6xxx_reg_unlock(chip); 173 174 ptp_clock_event(chip->ptp_clock, &ev); 175 out: 176 schedule_delayed_work(&chip->tai_event_work, TAI_EVENT_WORK_INTERVAL); 177 } 178 179 static int mv88e6xxx_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 180 { 181 struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); 182 int neg_adj = 0; 183 u32 diff, mult; 184 u64 adj; 185 186 if (scaled_ppm < 0) { 187 neg_adj = 1; 188 scaled_ppm = -scaled_ppm; 189 } 190 mult = CC_MULT; 191 adj = CC_MULT_NUM; 192 adj *= scaled_ppm; 193 diff = div_u64(adj, CC_MULT_DEM); 194 195 mv88e6xxx_reg_lock(chip); 196 197 timecounter_read(&chip->tstamp_tc); 198 chip->tstamp_cc.mult = neg_adj ? mult - diff : mult + diff; 199 200 mv88e6xxx_reg_unlock(chip); 201 202 return 0; 203 } 204 205 static int mv88e6xxx_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 206 { 207 struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); 208 209 mv88e6xxx_reg_lock(chip); 210 timecounter_adjtime(&chip->tstamp_tc, delta); 211 mv88e6xxx_reg_unlock(chip); 212 213 return 0; 214 } 215 216 static int mv88e6xxx_ptp_gettime(struct ptp_clock_info *ptp, 217 struct timespec64 *ts) 218 { 219 struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); 220 u64 ns; 221 222 mv88e6xxx_reg_lock(chip); 223 ns = timecounter_read(&chip->tstamp_tc); 224 mv88e6xxx_reg_unlock(chip); 225 226 *ts = ns_to_timespec64(ns); 227 228 return 0; 229 } 230 231 static int mv88e6xxx_ptp_settime(struct ptp_clock_info *ptp, 232 const struct timespec64 *ts) 233 { 234 struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); 235 u64 ns; 236 237 ns = timespec64_to_ns(ts); 238 239 mv88e6xxx_reg_lock(chip); 240 timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc, ns); 241 mv88e6xxx_reg_unlock(chip); 242 243 return 0; 244 } 245 246 static int mv88e6352_ptp_enable_extts(struct mv88e6xxx_chip *chip, 247 struct ptp_clock_request *rq, int on) 248 { 249 int rising = (rq->extts.flags & PTP_RISING_EDGE); 250 int func; 251 int pin; 252 int err; 253 254 pin = ptp_find_pin(chip->ptp_clock, PTP_PF_EXTTS, rq->extts.index); 255 256 if (pin < 0) 257 return -EBUSY; 258 259 mv88e6xxx_reg_lock(chip); 260 261 if (on) { 262 func = MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ; 263 264 err = mv88e6352_set_gpio_func(chip, pin, func, true); 265 if (err) 266 goto out; 267 268 schedule_delayed_work(&chip->tai_event_work, 269 TAI_EVENT_WORK_INTERVAL); 270 271 err = mv88e6352_config_eventcap(chip, PTP_CLOCK_EXTTS, rising); 272 } else { 273 func = MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO; 274 275 err = mv88e6352_set_gpio_func(chip, pin, func, true); 276 277 cancel_delayed_work_sync(&chip->tai_event_work); 278 } 279 280 out: 281 mv88e6xxx_reg_unlock(chip); 282 283 return err; 284 } 285 286 static int mv88e6352_ptp_enable(struct ptp_clock_info *ptp, 287 struct ptp_clock_request *rq, int on) 288 { 289 struct mv88e6xxx_chip *chip = ptp_to_chip(ptp); 290 291 switch (rq->type) { 292 case PTP_CLK_REQ_EXTTS: 293 return mv88e6352_ptp_enable_extts(chip, rq, on); 294 default: 295 return -EOPNOTSUPP; 296 } 297 } 298 299 static int mv88e6352_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin, 300 enum ptp_pin_function func, unsigned int chan) 301 { 302 switch (func) { 303 case PTP_PF_NONE: 304 case PTP_PF_EXTTS: 305 break; 306 case PTP_PF_PEROUT: 307 case PTP_PF_PHYSYNC: 308 return -EOPNOTSUPP; 309 } 310 return 0; 311 } 312 313 const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = { 314 .clock_read = mv88e6352_ptp_clock_read, 315 .ptp_enable = mv88e6352_ptp_enable, 316 .ptp_verify = mv88e6352_ptp_verify, 317 .event_work = mv88e6352_tai_event_work, 318 .port_enable = mv88e6352_hwtstamp_port_enable, 319 .port_disable = mv88e6352_hwtstamp_port_disable, 320 .n_ext_ts = 1, 321 .arr0_sts_reg = MV88E6XXX_PORT_PTP_ARR0_STS, 322 .arr1_sts_reg = MV88E6XXX_PORT_PTP_ARR1_STS, 323 .dep_sts_reg = MV88E6XXX_PORT_PTP_DEP_STS, 324 .rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 325 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 326 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 327 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 328 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 329 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 330 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 331 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 332 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 333 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ), 334 }; 335 336 const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = { 337 .clock_read = mv88e6165_ptp_clock_read, 338 .global_enable = mv88e6165_global_enable, 339 .global_disable = mv88e6165_global_disable, 340 .arr0_sts_reg = MV88E6165_PORT_PTP_ARR0_STS, 341 .arr1_sts_reg = MV88E6165_PORT_PTP_ARR1_STS, 342 .dep_sts_reg = MV88E6165_PORT_PTP_DEP_STS, 343 .rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 344 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 345 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 346 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 347 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 348 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 349 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ), 350 }; 351 352 static u64 mv88e6xxx_ptp_clock_read(const struct cyclecounter *cc) 353 { 354 struct mv88e6xxx_chip *chip = cc_to_chip(cc); 355 356 if (chip->info->ops->ptp_ops->clock_read) 357 return chip->info->ops->ptp_ops->clock_read(cc); 358 359 return 0; 360 } 361 362 /* With a 125MHz input clock, the 32-bit timestamp counter overflows in ~34.3 363 * seconds; this task forces periodic reads so that we don't miss any. 364 */ 365 #define MV88E6XXX_TAI_OVERFLOW_PERIOD (HZ * 16) 366 static void mv88e6xxx_ptp_overflow_check(struct work_struct *work) 367 { 368 struct delayed_work *dw = to_delayed_work(work); 369 struct mv88e6xxx_chip *chip = dw_overflow_to_chip(dw); 370 struct timespec64 ts; 371 372 mv88e6xxx_ptp_gettime(&chip->ptp_clock_info, &ts); 373 374 schedule_delayed_work(&chip->overflow_work, 375 MV88E6XXX_TAI_OVERFLOW_PERIOD); 376 } 377 378 int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip) 379 { 380 const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops; 381 int i; 382 383 /* Set up the cycle counter */ 384 memset(&chip->tstamp_cc, 0, sizeof(chip->tstamp_cc)); 385 chip->tstamp_cc.read = mv88e6xxx_ptp_clock_read; 386 chip->tstamp_cc.mask = CYCLECOUNTER_MASK(32); 387 chip->tstamp_cc.mult = CC_MULT; 388 chip->tstamp_cc.shift = CC_SHIFT; 389 390 timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc, 391 ktime_to_ns(ktime_get_real())); 392 393 INIT_DELAYED_WORK(&chip->overflow_work, mv88e6xxx_ptp_overflow_check); 394 if (ptp_ops->event_work) 395 INIT_DELAYED_WORK(&chip->tai_event_work, ptp_ops->event_work); 396 397 chip->ptp_clock_info.owner = THIS_MODULE; 398 snprintf(chip->ptp_clock_info.name, sizeof(chip->ptp_clock_info.name), 399 "%s", dev_name(chip->dev)); 400 chip->ptp_clock_info.max_adj = 1000000; 401 402 chip->ptp_clock_info.n_ext_ts = ptp_ops->n_ext_ts; 403 chip->ptp_clock_info.n_per_out = 0; 404 chip->ptp_clock_info.n_pins = mv88e6xxx_num_gpio(chip); 405 chip->ptp_clock_info.pps = 0; 406 407 for (i = 0; i < chip->ptp_clock_info.n_pins; ++i) { 408 struct ptp_pin_desc *ppd = &chip->pin_config[i]; 409 410 snprintf(ppd->name, sizeof(ppd->name), "mv88e6xxx_gpio%d", i); 411 ppd->index = i; 412 ppd->func = PTP_PF_NONE; 413 } 414 chip->ptp_clock_info.pin_config = chip->pin_config; 415 416 chip->ptp_clock_info.adjfine = mv88e6xxx_ptp_adjfine; 417 chip->ptp_clock_info.adjtime = mv88e6xxx_ptp_adjtime; 418 chip->ptp_clock_info.gettime64 = mv88e6xxx_ptp_gettime; 419 chip->ptp_clock_info.settime64 = mv88e6xxx_ptp_settime; 420 chip->ptp_clock_info.enable = ptp_ops->ptp_enable; 421 chip->ptp_clock_info.verify = ptp_ops->ptp_verify; 422 chip->ptp_clock_info.do_aux_work = mv88e6xxx_hwtstamp_work; 423 424 chip->ptp_clock = ptp_clock_register(&chip->ptp_clock_info, chip->dev); 425 if (IS_ERR(chip->ptp_clock)) 426 return PTR_ERR(chip->ptp_clock); 427 428 schedule_delayed_work(&chip->overflow_work, 429 MV88E6XXX_TAI_OVERFLOW_PERIOD); 430 431 return 0; 432 } 433 434 void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip) 435 { 436 if (chip->ptp_clock) { 437 cancel_delayed_work_sync(&chip->overflow_work); 438 if (chip->info->ops->ptp_ops->event_work) 439 cancel_delayed_work_sync(&chip->tai_event_work); 440 441 ptp_clock_unregister(chip->ptp_clock); 442 chip->ptp_clock = NULL; 443 } 444 } 445