12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
22fa8d3afSBrandon Streiff /*
32fa8d3afSBrandon Streiff * Marvell 88E6xxx Switch PTP support
42fa8d3afSBrandon Streiff *
52fa8d3afSBrandon Streiff * Copyright (c) 2008 Marvell Semiconductor
62fa8d3afSBrandon Streiff *
72fa8d3afSBrandon Streiff * Copyright (c) 2017 National Instruments
82fa8d3afSBrandon Streiff * Erik Hons <erik.hons@ni.com>
92fa8d3afSBrandon Streiff * Brandon Streiff <brandon.streiff@ni.com>
102fa8d3afSBrandon Streiff * Dane Wagner <dane.wagner@ni.com>
112fa8d3afSBrandon Streiff */
122fa8d3afSBrandon Streiff
132fa8d3afSBrandon Streiff #include "chip.h"
14*9627c981SKurt Kanzenbach #include "global1.h"
152fa8d3afSBrandon Streiff #include "global2.h"
16ffc705deSAndrew Lunn #include "hwtstamp.h"
172fa8d3afSBrandon Streiff #include "ptp.h"
182fa8d3afSBrandon Streiff
1971509614SHubert Feurstein #define MV88E6XXX_MAX_ADJ_PPB 1000000
2071509614SHubert Feurstein
2171509614SHubert Feurstein /* Family MV88E6250:
2271509614SHubert Feurstein * Raw timestamps are in units of 10-ns clock periods.
2371509614SHubert Feurstein *
2471509614SHubert Feurstein * clkadj = scaled_ppm * 10*2^28 / (10^6 * 2^16)
2571509614SHubert Feurstein * simplifies to
2671509614SHubert Feurstein * clkadj = scaled_ppm * 2^7 / 5^5
2771509614SHubert Feurstein */
2871509614SHubert Feurstein #define MV88E6250_CC_SHIFT 28
2971509614SHubert Feurstein #define MV88E6250_CC_MULT (10 << MV88E6250_CC_SHIFT)
3071509614SHubert Feurstein #define MV88E6250_CC_MULT_NUM (1 << 7)
3171509614SHubert Feurstein #define MV88E6250_CC_MULT_DEM 3125ULL
3271509614SHubert Feurstein
3371509614SHubert Feurstein /* Other families:
3471509614SHubert Feurstein * Raw timestamps are in units of 8-ns clock periods.
3571509614SHubert Feurstein *
3671509614SHubert Feurstein * clkadj = scaled_ppm * 8*2^28 / (10^6 * 2^16)
3771509614SHubert Feurstein * simplifies to
3871509614SHubert Feurstein * clkadj = scaled_ppm * 2^9 / 5^6
3971509614SHubert Feurstein */
4071509614SHubert Feurstein #define MV88E6XXX_CC_SHIFT 28
4171509614SHubert Feurstein #define MV88E6XXX_CC_MULT (8 << MV88E6XXX_CC_SHIFT)
4271509614SHubert Feurstein #define MV88E6XXX_CC_MULT_NUM (1 << 9)
4371509614SHubert Feurstein #define MV88E6XXX_CC_MULT_DEM 15625ULL
442fa8d3afSBrandon Streiff
452fa8d3afSBrandon Streiff #define TAI_EVENT_WORK_INTERVAL msecs_to_jiffies(100)
462fa8d3afSBrandon Streiff
472fa8d3afSBrandon Streiff #define cc_to_chip(cc) container_of(cc, struct mv88e6xxx_chip, tstamp_cc)
482fa8d3afSBrandon Streiff #define dw_overflow_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
492fa8d3afSBrandon Streiff overflow_work)
504eb3be29SBrandon Streiff #define dw_tai_event_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
514eb3be29SBrandon Streiff tai_event_work)
522fa8d3afSBrandon Streiff
mv88e6xxx_tai_read(struct mv88e6xxx_chip * chip,int addr,u16 * data,int len)532fa8d3afSBrandon Streiff static int mv88e6xxx_tai_read(struct mv88e6xxx_chip *chip, int addr,
542fa8d3afSBrandon Streiff u16 *data, int len)
552fa8d3afSBrandon Streiff {
562fa8d3afSBrandon Streiff if (!chip->info->ops->avb_ops->tai_read)
572fa8d3afSBrandon Streiff return -EOPNOTSUPP;
582fa8d3afSBrandon Streiff
592fa8d3afSBrandon Streiff return chip->info->ops->avb_ops->tai_read(chip, addr, data, len);
602fa8d3afSBrandon Streiff }
612fa8d3afSBrandon Streiff
mv88e6xxx_tai_write(struct mv88e6xxx_chip * chip,int addr,u16 data)624eb3be29SBrandon Streiff static int mv88e6xxx_tai_write(struct mv88e6xxx_chip *chip, int addr, u16 data)
634eb3be29SBrandon Streiff {
644eb3be29SBrandon Streiff if (!chip->info->ops->avb_ops->tai_write)
654eb3be29SBrandon Streiff return -EOPNOTSUPP;
664eb3be29SBrandon Streiff
674eb3be29SBrandon Streiff return chip->info->ops->avb_ops->tai_write(chip, addr, data);
684eb3be29SBrandon Streiff }
694eb3be29SBrandon Streiff
704eb3be29SBrandon Streiff /* TODO: places where this are called should be using pinctrl */
mv88e6352_set_gpio_func(struct mv88e6xxx_chip * chip,int pin,int func,int input)716d2ac8eeSAndrew Lunn static int mv88e6352_set_gpio_func(struct mv88e6xxx_chip *chip, int pin,
724eb3be29SBrandon Streiff int func, int input)
734eb3be29SBrandon Streiff {
744eb3be29SBrandon Streiff int err;
754eb3be29SBrandon Streiff
764eb3be29SBrandon Streiff if (!chip->info->ops->gpio_ops)
774eb3be29SBrandon Streiff return -EOPNOTSUPP;
784eb3be29SBrandon Streiff
794eb3be29SBrandon Streiff err = chip->info->ops->gpio_ops->set_dir(chip, pin, input);
804eb3be29SBrandon Streiff if (err)
814eb3be29SBrandon Streiff return err;
824eb3be29SBrandon Streiff
834eb3be29SBrandon Streiff return chip->info->ops->gpio_ops->set_pctl(chip, pin, func);
844eb3be29SBrandon Streiff }
854eb3be29SBrandon Streiff
mv88e6352_ptp_clock_read(const struct cyclecounter * cc)866d2ac8eeSAndrew Lunn static u64 mv88e6352_ptp_clock_read(const struct cyclecounter *cc)
872fa8d3afSBrandon Streiff {
882fa8d3afSBrandon Streiff struct mv88e6xxx_chip *chip = cc_to_chip(cc);
892fa8d3afSBrandon Streiff u16 phc_time[2];
902fa8d3afSBrandon Streiff int err;
912fa8d3afSBrandon Streiff
922fa8d3afSBrandon Streiff err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_TIME_LO, phc_time,
932fa8d3afSBrandon Streiff ARRAY_SIZE(phc_time));
942fa8d3afSBrandon Streiff if (err)
952fa8d3afSBrandon Streiff return 0;
962fa8d3afSBrandon Streiff else
972fa8d3afSBrandon Streiff return ((u32)phc_time[1] << 16) | phc_time[0];
982fa8d3afSBrandon Streiff }
992fa8d3afSBrandon Streiff
mv88e6165_ptp_clock_read(const struct cyclecounter * cc)100dfa54348SAndrew Lunn static u64 mv88e6165_ptp_clock_read(const struct cyclecounter *cc)
101dfa54348SAndrew Lunn {
102dfa54348SAndrew Lunn struct mv88e6xxx_chip *chip = cc_to_chip(cc);
103dfa54348SAndrew Lunn u16 phc_time[2];
104dfa54348SAndrew Lunn int err;
105dfa54348SAndrew Lunn
106dfa54348SAndrew Lunn err = mv88e6xxx_tai_read(chip, MV88E6XXX_PTP_GC_TIME_LO, phc_time,
107dfa54348SAndrew Lunn ARRAY_SIZE(phc_time));
108dfa54348SAndrew Lunn if (err)
109dfa54348SAndrew Lunn return 0;
110dfa54348SAndrew Lunn else
111dfa54348SAndrew Lunn return ((u32)phc_time[1] << 16) | phc_time[0];
112dfa54348SAndrew Lunn }
113dfa54348SAndrew Lunn
1146d2ac8eeSAndrew Lunn /* mv88e6352_config_eventcap - configure TAI event capture
1154eb3be29SBrandon Streiff * @event: PTP_CLOCK_PPS (internal) or PTP_CLOCK_EXTTS (external)
1164eb3be29SBrandon Streiff * @rising: zero for falling-edge trigger, else rising-edge trigger
1174eb3be29SBrandon Streiff *
1184eb3be29SBrandon Streiff * This will also reset the capture sequence counter.
1194eb3be29SBrandon Streiff */
mv88e6352_config_eventcap(struct mv88e6xxx_chip * chip,int event,int rising)1206d2ac8eeSAndrew Lunn static int mv88e6352_config_eventcap(struct mv88e6xxx_chip *chip, int event,
1214eb3be29SBrandon Streiff int rising)
1224eb3be29SBrandon Streiff {
1234eb3be29SBrandon Streiff u16 global_config;
1244eb3be29SBrandon Streiff u16 cap_config;
1254eb3be29SBrandon Streiff int err;
1264eb3be29SBrandon Streiff
1274eb3be29SBrandon Streiff chip->evcap_config = MV88E6XXX_TAI_CFG_CAP_OVERWRITE |
1284eb3be29SBrandon Streiff MV88E6XXX_TAI_CFG_CAP_CTR_START;
1294eb3be29SBrandon Streiff if (!rising)
1304eb3be29SBrandon Streiff chip->evcap_config |= MV88E6XXX_TAI_CFG_EVREQ_FALLING;
1314eb3be29SBrandon Streiff
1324eb3be29SBrandon Streiff global_config = (chip->evcap_config | chip->trig_config);
1334eb3be29SBrandon Streiff err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_CFG, global_config);
1344eb3be29SBrandon Streiff if (err)
1354eb3be29SBrandon Streiff return err;
1364eb3be29SBrandon Streiff
1374eb3be29SBrandon Streiff if (event == PTP_CLOCK_PPS) {
1384eb3be29SBrandon Streiff cap_config = MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG;
1394eb3be29SBrandon Streiff } else if (event == PTP_CLOCK_EXTTS) {
1404eb3be29SBrandon Streiff /* if STATUS_CAP_TRIG is unset we capture PTP_EVREQ events */
1414eb3be29SBrandon Streiff cap_config = 0;
1424eb3be29SBrandon Streiff } else {
1434eb3be29SBrandon Streiff return -EINVAL;
1444eb3be29SBrandon Streiff }
1454eb3be29SBrandon Streiff
1464eb3be29SBrandon Streiff /* Write the capture config; this also clears the capture counter */
1474eb3be29SBrandon Streiff err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS,
1484eb3be29SBrandon Streiff cap_config);
1494eb3be29SBrandon Streiff
1504eb3be29SBrandon Streiff return err;
1514eb3be29SBrandon Streiff }
1524eb3be29SBrandon Streiff
mv88e6352_tai_event_work(struct work_struct * ugly)1536d2ac8eeSAndrew Lunn static void mv88e6352_tai_event_work(struct work_struct *ugly)
1544eb3be29SBrandon Streiff {
1554eb3be29SBrandon Streiff struct delayed_work *dw = to_delayed_work(ugly);
1564eb3be29SBrandon Streiff struct mv88e6xxx_chip *chip = dw_tai_event_to_chip(dw);
1574eb3be29SBrandon Streiff struct ptp_clock_event ev;
1584eb3be29SBrandon Streiff u16 status[4];
1594eb3be29SBrandon Streiff u32 raw_ts;
1604eb3be29SBrandon Streiff int err;
1614eb3be29SBrandon Streiff
162c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1634eb3be29SBrandon Streiff err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_EVENT_STATUS,
1644eb3be29SBrandon Streiff status, ARRAY_SIZE(status));
165c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1664eb3be29SBrandon Streiff
1674eb3be29SBrandon Streiff if (err) {
1684eb3be29SBrandon Streiff dev_err(chip->dev, "failed to read TAI status register\n");
1694eb3be29SBrandon Streiff return;
1704eb3be29SBrandon Streiff }
1714eb3be29SBrandon Streiff if (status[0] & MV88E6XXX_TAI_EVENT_STATUS_ERROR) {
1724eb3be29SBrandon Streiff dev_warn(chip->dev, "missed event capture\n");
1734eb3be29SBrandon Streiff return;
1744eb3be29SBrandon Streiff }
1754eb3be29SBrandon Streiff if (!(status[0] & MV88E6XXX_TAI_EVENT_STATUS_VALID))
1764eb3be29SBrandon Streiff goto out;
1774eb3be29SBrandon Streiff
1784eb3be29SBrandon Streiff raw_ts = ((u32)status[2] << 16) | status[1];
1794eb3be29SBrandon Streiff
1804eb3be29SBrandon Streiff /* Clear the valid bit so the next timestamp can come in */
1814eb3be29SBrandon Streiff status[0] &= ~MV88E6XXX_TAI_EVENT_STATUS_VALID;
182c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1834eb3be29SBrandon Streiff err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, status[0]);
184c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1854eb3be29SBrandon Streiff
1864eb3be29SBrandon Streiff /* This is an external timestamp */
1874eb3be29SBrandon Streiff ev.type = PTP_CLOCK_EXTTS;
1884eb3be29SBrandon Streiff
1894eb3be29SBrandon Streiff /* We only have one timestamping channel. */
1904eb3be29SBrandon Streiff ev.index = 0;
191c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1924eb3be29SBrandon Streiff ev.timestamp = timecounter_cyc2time(&chip->tstamp_tc, raw_ts);
193c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1944eb3be29SBrandon Streiff
1954eb3be29SBrandon Streiff ptp_clock_event(chip->ptp_clock, &ev);
1964eb3be29SBrandon Streiff out:
1974eb3be29SBrandon Streiff schedule_delayed_work(&chip->tai_event_work, TAI_EVENT_WORK_INTERVAL);
1984eb3be29SBrandon Streiff }
1994eb3be29SBrandon Streiff
mv88e6xxx_ptp_adjfine(struct ptp_clock_info * ptp,long scaled_ppm)2002fa8d3afSBrandon Streiff static int mv88e6xxx_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
2012fa8d3afSBrandon Streiff {
2022fa8d3afSBrandon Streiff struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
20371509614SHubert Feurstein const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
2042fa8d3afSBrandon Streiff int neg_adj = 0;
2052fa8d3afSBrandon Streiff u32 diff, mult;
2062fa8d3afSBrandon Streiff u64 adj;
2072fa8d3afSBrandon Streiff
2082fa8d3afSBrandon Streiff if (scaled_ppm < 0) {
2092fa8d3afSBrandon Streiff neg_adj = 1;
2102fa8d3afSBrandon Streiff scaled_ppm = -scaled_ppm;
2112fa8d3afSBrandon Streiff }
21271509614SHubert Feurstein
21371509614SHubert Feurstein mult = ptp_ops->cc_mult;
21471509614SHubert Feurstein adj = ptp_ops->cc_mult_num;
2152fa8d3afSBrandon Streiff adj *= scaled_ppm;
21671509614SHubert Feurstein diff = div_u64(adj, ptp_ops->cc_mult_dem);
2172fa8d3afSBrandon Streiff
218c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
2192fa8d3afSBrandon Streiff
2202fa8d3afSBrandon Streiff timecounter_read(&chip->tstamp_tc);
2212fa8d3afSBrandon Streiff chip->tstamp_cc.mult = neg_adj ? mult - diff : mult + diff;
2222fa8d3afSBrandon Streiff
223c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
2242fa8d3afSBrandon Streiff
2252fa8d3afSBrandon Streiff return 0;
2262fa8d3afSBrandon Streiff }
2272fa8d3afSBrandon Streiff
mv88e6xxx_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)2282fa8d3afSBrandon Streiff static int mv88e6xxx_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
2292fa8d3afSBrandon Streiff {
2302fa8d3afSBrandon Streiff struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
2312fa8d3afSBrandon Streiff
232c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
2332fa8d3afSBrandon Streiff timecounter_adjtime(&chip->tstamp_tc, delta);
234c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
2352fa8d3afSBrandon Streiff
2362fa8d3afSBrandon Streiff return 0;
2372fa8d3afSBrandon Streiff }
2382fa8d3afSBrandon Streiff
mv88e6xxx_ptp_gettime(struct ptp_clock_info * ptp,struct timespec64 * ts)2392fa8d3afSBrandon Streiff static int mv88e6xxx_ptp_gettime(struct ptp_clock_info *ptp,
2402fa8d3afSBrandon Streiff struct timespec64 *ts)
2412fa8d3afSBrandon Streiff {
2422fa8d3afSBrandon Streiff struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
2432fa8d3afSBrandon Streiff u64 ns;
2442fa8d3afSBrandon Streiff
245c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
2462fa8d3afSBrandon Streiff ns = timecounter_read(&chip->tstamp_tc);
247c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
2482fa8d3afSBrandon Streiff
2492fa8d3afSBrandon Streiff *ts = ns_to_timespec64(ns);
2502fa8d3afSBrandon Streiff
2512fa8d3afSBrandon Streiff return 0;
2522fa8d3afSBrandon Streiff }
2532fa8d3afSBrandon Streiff
mv88e6xxx_ptp_settime(struct ptp_clock_info * ptp,const struct timespec64 * ts)2542fa8d3afSBrandon Streiff static int mv88e6xxx_ptp_settime(struct ptp_clock_info *ptp,
2552fa8d3afSBrandon Streiff const struct timespec64 *ts)
2562fa8d3afSBrandon Streiff {
2572fa8d3afSBrandon Streiff struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
2582fa8d3afSBrandon Streiff u64 ns;
2592fa8d3afSBrandon Streiff
2602fa8d3afSBrandon Streiff ns = timespec64_to_ns(ts);
2612fa8d3afSBrandon Streiff
262c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
2632fa8d3afSBrandon Streiff timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc, ns);
264c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
2652fa8d3afSBrandon Streiff
2662fa8d3afSBrandon Streiff return 0;
2672fa8d3afSBrandon Streiff }
2682fa8d3afSBrandon Streiff
mv88e6352_ptp_enable_extts(struct mv88e6xxx_chip * chip,struct ptp_clock_request * rq,int on)2696d2ac8eeSAndrew Lunn static int mv88e6352_ptp_enable_extts(struct mv88e6xxx_chip *chip,
2704eb3be29SBrandon Streiff struct ptp_clock_request *rq, int on)
2714eb3be29SBrandon Streiff {
2724eb3be29SBrandon Streiff int rising = (rq->extts.flags & PTP_RISING_EDGE);
2734eb3be29SBrandon Streiff int func;
2744eb3be29SBrandon Streiff int pin;
2754eb3be29SBrandon Streiff int err;
2764eb3be29SBrandon Streiff
2777d9465ebSJacob Keller /* Reject requests with unsupported flags */
2787d9465ebSJacob Keller if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
2797d9465ebSJacob Keller PTP_RISING_EDGE |
2806138e687SRichard Cochran PTP_FALLING_EDGE |
2816138e687SRichard Cochran PTP_STRICT_FLAGS))
2827d9465ebSJacob Keller return -EOPNOTSUPP;
2837d9465ebSJacob Keller
284c019b4beSRichard Cochran /* Reject requests to enable time stamping on both edges. */
285c019b4beSRichard Cochran if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
286c019b4beSRichard Cochran (rq->extts.flags & PTP_ENABLE_FEATURE) &&
287c019b4beSRichard Cochran (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
288c019b4beSRichard Cochran return -EOPNOTSUPP;
289c019b4beSRichard Cochran
2904eb3be29SBrandon Streiff pin = ptp_find_pin(chip->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
2914eb3be29SBrandon Streiff
2924eb3be29SBrandon Streiff if (pin < 0)
2934eb3be29SBrandon Streiff return -EBUSY;
2944eb3be29SBrandon Streiff
295c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
2964eb3be29SBrandon Streiff
2974eb3be29SBrandon Streiff if (on) {
2984eb3be29SBrandon Streiff func = MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ;
2994eb3be29SBrandon Streiff
3006d2ac8eeSAndrew Lunn err = mv88e6352_set_gpio_func(chip, pin, func, true);
3014eb3be29SBrandon Streiff if (err)
3024eb3be29SBrandon Streiff goto out;
3034eb3be29SBrandon Streiff
3044eb3be29SBrandon Streiff schedule_delayed_work(&chip->tai_event_work,
3054eb3be29SBrandon Streiff TAI_EVENT_WORK_INTERVAL);
3064eb3be29SBrandon Streiff
3076d2ac8eeSAndrew Lunn err = mv88e6352_config_eventcap(chip, PTP_CLOCK_EXTTS, rising);
3084eb3be29SBrandon Streiff } else {
3094eb3be29SBrandon Streiff func = MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO;
3104eb3be29SBrandon Streiff
3116d2ac8eeSAndrew Lunn err = mv88e6352_set_gpio_func(chip, pin, func, true);
3124eb3be29SBrandon Streiff
3134eb3be29SBrandon Streiff cancel_delayed_work_sync(&chip->tai_event_work);
3144eb3be29SBrandon Streiff }
3154eb3be29SBrandon Streiff
3164eb3be29SBrandon Streiff out:
317c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
3184eb3be29SBrandon Streiff
3194eb3be29SBrandon Streiff return err;
3204eb3be29SBrandon Streiff }
3214eb3be29SBrandon Streiff
mv88e6352_ptp_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)3226d2ac8eeSAndrew Lunn static int mv88e6352_ptp_enable(struct ptp_clock_info *ptp,
3232fa8d3afSBrandon Streiff struct ptp_clock_request *rq, int on)
3242fa8d3afSBrandon Streiff {
3254eb3be29SBrandon Streiff struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
3264eb3be29SBrandon Streiff
3274eb3be29SBrandon Streiff switch (rq->type) {
3284eb3be29SBrandon Streiff case PTP_CLK_REQ_EXTTS:
3296d2ac8eeSAndrew Lunn return mv88e6352_ptp_enable_extts(chip, rq, on);
3304eb3be29SBrandon Streiff default:
3312fa8d3afSBrandon Streiff return -EOPNOTSUPP;
3322fa8d3afSBrandon Streiff }
3334eb3be29SBrandon Streiff }
3342fa8d3afSBrandon Streiff
mv88e6352_ptp_verify(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)3356d2ac8eeSAndrew Lunn static int mv88e6352_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
3362fa8d3afSBrandon Streiff enum ptp_pin_function func, unsigned int chan)
3372fa8d3afSBrandon Streiff {
3384eb3be29SBrandon Streiff switch (func) {
3394eb3be29SBrandon Streiff case PTP_PF_NONE:
3404eb3be29SBrandon Streiff case PTP_PF_EXTTS:
3414eb3be29SBrandon Streiff break;
3424eb3be29SBrandon Streiff case PTP_PF_PEROUT:
3434eb3be29SBrandon Streiff case PTP_PF_PHYSYNC:
3442fa8d3afSBrandon Streiff return -EOPNOTSUPP;
3452fa8d3afSBrandon Streiff }
3464eb3be29SBrandon Streiff return 0;
3474eb3be29SBrandon Streiff }
3482fa8d3afSBrandon Streiff
3498858ccc8SHubert Feurstein const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {
3508858ccc8SHubert Feurstein .clock_read = mv88e6165_ptp_clock_read,
3518858ccc8SHubert Feurstein .global_enable = mv88e6165_global_enable,
3528858ccc8SHubert Feurstein .global_disable = mv88e6165_global_disable,
3538858ccc8SHubert Feurstein .arr0_sts_reg = MV88E6165_PORT_PTP_ARR0_STS,
3548858ccc8SHubert Feurstein .arr1_sts_reg = MV88E6165_PORT_PTP_ARR1_STS,
3558858ccc8SHubert Feurstein .dep_sts_reg = MV88E6165_PORT_PTP_DEP_STS,
3568858ccc8SHubert Feurstein .rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3578858ccc8SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3588858ccc8SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
3598858ccc8SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
3608858ccc8SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
3618858ccc8SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
3628858ccc8SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ),
36371509614SHubert Feurstein .cc_shift = MV88E6XXX_CC_SHIFT,
36471509614SHubert Feurstein .cc_mult = MV88E6XXX_CC_MULT,
36571509614SHubert Feurstein .cc_mult_num = MV88E6XXX_CC_MULT_NUM,
36671509614SHubert Feurstein .cc_mult_dem = MV88E6XXX_CC_MULT_DEM,
36771509614SHubert Feurstein };
36871509614SHubert Feurstein
36971509614SHubert Feurstein const struct mv88e6xxx_ptp_ops mv88e6250_ptp_ops = {
37071509614SHubert Feurstein .clock_read = mv88e6352_ptp_clock_read,
37171509614SHubert Feurstein .ptp_enable = mv88e6352_ptp_enable,
37271509614SHubert Feurstein .ptp_verify = mv88e6352_ptp_verify,
37371509614SHubert Feurstein .event_work = mv88e6352_tai_event_work,
37471509614SHubert Feurstein .port_enable = mv88e6352_hwtstamp_port_enable,
37571509614SHubert Feurstein .port_disable = mv88e6352_hwtstamp_port_disable,
37671509614SHubert Feurstein .n_ext_ts = 1,
37771509614SHubert Feurstein .arr0_sts_reg = MV88E6XXX_PORT_PTP_ARR0_STS,
37871509614SHubert Feurstein .arr1_sts_reg = MV88E6XXX_PORT_PTP_ARR1_STS,
37971509614SHubert Feurstein .dep_sts_reg = MV88E6XXX_PORT_PTP_DEP_STS,
38071509614SHubert Feurstein .rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
38171509614SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
38271509614SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
38371509614SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
38471509614SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
38571509614SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
38671509614SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
38771509614SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
38871509614SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
38971509614SHubert Feurstein (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ),
39071509614SHubert Feurstein .cc_shift = MV88E6250_CC_SHIFT,
39171509614SHubert Feurstein .cc_mult = MV88E6250_CC_MULT,
39271509614SHubert Feurstein .cc_mult_num = MV88E6250_CC_MULT_NUM,
39371509614SHubert Feurstein .cc_mult_dem = MV88E6250_CC_MULT_DEM,
3948858ccc8SHubert Feurstein };
3958858ccc8SHubert Feurstein
3966d2ac8eeSAndrew Lunn const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {
3976d2ac8eeSAndrew Lunn .clock_read = mv88e6352_ptp_clock_read,
3986d2ac8eeSAndrew Lunn .ptp_enable = mv88e6352_ptp_enable,
3996d2ac8eeSAndrew Lunn .ptp_verify = mv88e6352_ptp_verify,
4006d2ac8eeSAndrew Lunn .event_work = mv88e6352_tai_event_work,
401ffc705deSAndrew Lunn .port_enable = mv88e6352_hwtstamp_port_enable,
402ffc705deSAndrew Lunn .port_disable = mv88e6352_hwtstamp_port_disable,
4036d2ac8eeSAndrew Lunn .n_ext_ts = 1,
404ffc705deSAndrew Lunn .arr0_sts_reg = MV88E6XXX_PORT_PTP_ARR0_STS,
405ffc705deSAndrew Lunn .arr1_sts_reg = MV88E6XXX_PORT_PTP_ARR1_STS,
406ffc705deSAndrew Lunn .dep_sts_reg = MV88E6XXX_PORT_PTP_DEP_STS,
40748cb5e03SAndrew Lunn .rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
40848cb5e03SAndrew Lunn (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
40948cb5e03SAndrew Lunn (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
41048cb5e03SAndrew Lunn (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
41148cb5e03SAndrew Lunn (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
41248cb5e03SAndrew Lunn (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
41348cb5e03SAndrew Lunn (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
41448cb5e03SAndrew Lunn (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
41548cb5e03SAndrew Lunn (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
41648cb5e03SAndrew Lunn (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ),
41771509614SHubert Feurstein .cc_shift = MV88E6XXX_CC_SHIFT,
41871509614SHubert Feurstein .cc_mult = MV88E6XXX_CC_MULT,
41971509614SHubert Feurstein .cc_mult_num = MV88E6XXX_CC_MULT_NUM,
42071509614SHubert Feurstein .cc_mult_dem = MV88E6XXX_CC_MULT_DEM,
4216d2ac8eeSAndrew Lunn };
4226d2ac8eeSAndrew Lunn
423*9627c981SKurt Kanzenbach const struct mv88e6xxx_ptp_ops mv88e6390_ptp_ops = {
424*9627c981SKurt Kanzenbach .clock_read = mv88e6352_ptp_clock_read,
425*9627c981SKurt Kanzenbach .ptp_enable = mv88e6352_ptp_enable,
426*9627c981SKurt Kanzenbach .ptp_verify = mv88e6352_ptp_verify,
427*9627c981SKurt Kanzenbach .event_work = mv88e6352_tai_event_work,
428*9627c981SKurt Kanzenbach .port_enable = mv88e6352_hwtstamp_port_enable,
429*9627c981SKurt Kanzenbach .port_disable = mv88e6352_hwtstamp_port_disable,
430*9627c981SKurt Kanzenbach .set_ptp_cpu_port = mv88e6390_g1_set_ptp_cpu_port,
431*9627c981SKurt Kanzenbach .n_ext_ts = 1,
432*9627c981SKurt Kanzenbach .arr0_sts_reg = MV88E6XXX_PORT_PTP_ARR0_STS,
433*9627c981SKurt Kanzenbach .arr1_sts_reg = MV88E6XXX_PORT_PTP_ARR1_STS,
434*9627c981SKurt Kanzenbach .dep_sts_reg = MV88E6XXX_PORT_PTP_DEP_STS,
435*9627c981SKurt Kanzenbach .rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
436*9627c981SKurt Kanzenbach (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
437*9627c981SKurt Kanzenbach (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
438*9627c981SKurt Kanzenbach (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
439*9627c981SKurt Kanzenbach (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
440*9627c981SKurt Kanzenbach (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
441*9627c981SKurt Kanzenbach (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
442*9627c981SKurt Kanzenbach (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
443*9627c981SKurt Kanzenbach (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
444*9627c981SKurt Kanzenbach (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ),
445*9627c981SKurt Kanzenbach .cc_shift = MV88E6XXX_CC_SHIFT,
446*9627c981SKurt Kanzenbach .cc_mult = MV88E6XXX_CC_MULT,
447*9627c981SKurt Kanzenbach .cc_mult_num = MV88E6XXX_CC_MULT_NUM,
448*9627c981SKurt Kanzenbach .cc_mult_dem = MV88E6XXX_CC_MULT_DEM,
449*9627c981SKurt Kanzenbach };
450*9627c981SKurt Kanzenbach
mv88e6xxx_ptp_clock_read(const struct cyclecounter * cc)4516d2ac8eeSAndrew Lunn static u64 mv88e6xxx_ptp_clock_read(const struct cyclecounter *cc)
4526d2ac8eeSAndrew Lunn {
4536d2ac8eeSAndrew Lunn struct mv88e6xxx_chip *chip = cc_to_chip(cc);
4546d2ac8eeSAndrew Lunn
4556d2ac8eeSAndrew Lunn if (chip->info->ops->ptp_ops->clock_read)
4566d2ac8eeSAndrew Lunn return chip->info->ops->ptp_ops->clock_read(cc);
4576d2ac8eeSAndrew Lunn
4586d2ac8eeSAndrew Lunn return 0;
4596d2ac8eeSAndrew Lunn }
4606d2ac8eeSAndrew Lunn
4612fa8d3afSBrandon Streiff /* With a 125MHz input clock, the 32-bit timestamp counter overflows in ~34.3
4622fa8d3afSBrandon Streiff * seconds; this task forces periodic reads so that we don't miss any.
4632fa8d3afSBrandon Streiff */
4642fa8d3afSBrandon Streiff #define MV88E6XXX_TAI_OVERFLOW_PERIOD (HZ * 16)
mv88e6xxx_ptp_overflow_check(struct work_struct * work)4652fa8d3afSBrandon Streiff static void mv88e6xxx_ptp_overflow_check(struct work_struct *work)
4662fa8d3afSBrandon Streiff {
4672fa8d3afSBrandon Streiff struct delayed_work *dw = to_delayed_work(work);
4682fa8d3afSBrandon Streiff struct mv88e6xxx_chip *chip = dw_overflow_to_chip(dw);
4692fa8d3afSBrandon Streiff struct timespec64 ts;
4702fa8d3afSBrandon Streiff
4712fa8d3afSBrandon Streiff mv88e6xxx_ptp_gettime(&chip->ptp_clock_info, &ts);
4722fa8d3afSBrandon Streiff
4732fa8d3afSBrandon Streiff schedule_delayed_work(&chip->overflow_work,
4742fa8d3afSBrandon Streiff MV88E6XXX_TAI_OVERFLOW_PERIOD);
4752fa8d3afSBrandon Streiff }
4762fa8d3afSBrandon Streiff
mv88e6xxx_ptp_setup(struct mv88e6xxx_chip * chip)4772fa8d3afSBrandon Streiff int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip)
4782fa8d3afSBrandon Streiff {
4796d2ac8eeSAndrew Lunn const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
4804eb3be29SBrandon Streiff int i;
4814eb3be29SBrandon Streiff
4822fa8d3afSBrandon Streiff /* Set up the cycle counter */
4832fa8d3afSBrandon Streiff memset(&chip->tstamp_cc, 0, sizeof(chip->tstamp_cc));
4842fa8d3afSBrandon Streiff chip->tstamp_cc.read = mv88e6xxx_ptp_clock_read;
4852fa8d3afSBrandon Streiff chip->tstamp_cc.mask = CYCLECOUNTER_MASK(32);
48671509614SHubert Feurstein chip->tstamp_cc.mult = ptp_ops->cc_mult;
48771509614SHubert Feurstein chip->tstamp_cc.shift = ptp_ops->cc_shift;
4882fa8d3afSBrandon Streiff
4892fa8d3afSBrandon Streiff timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc,
4902fa8d3afSBrandon Streiff ktime_to_ns(ktime_get_real()));
4912fa8d3afSBrandon Streiff
4922fa8d3afSBrandon Streiff INIT_DELAYED_WORK(&chip->overflow_work, mv88e6xxx_ptp_overflow_check);
4936d2ac8eeSAndrew Lunn if (ptp_ops->event_work)
4946d2ac8eeSAndrew Lunn INIT_DELAYED_WORK(&chip->tai_event_work, ptp_ops->event_work);
4952fa8d3afSBrandon Streiff
4962fa8d3afSBrandon Streiff chip->ptp_clock_info.owner = THIS_MODULE;
4972fa8d3afSBrandon Streiff snprintf(chip->ptp_clock_info.name, sizeof(chip->ptp_clock_info.name),
4983f8b8696SFlorian Fainelli "%s", dev_name(chip->dev));
4992fa8d3afSBrandon Streiff
5006d2ac8eeSAndrew Lunn chip->ptp_clock_info.n_ext_ts = ptp_ops->n_ext_ts;
5014eb3be29SBrandon Streiff chip->ptp_clock_info.n_per_out = 0;
5024eb3be29SBrandon Streiff chip->ptp_clock_info.n_pins = mv88e6xxx_num_gpio(chip);
5034eb3be29SBrandon Streiff chip->ptp_clock_info.pps = 0;
5044eb3be29SBrandon Streiff
5054eb3be29SBrandon Streiff for (i = 0; i < chip->ptp_clock_info.n_pins; ++i) {
5064eb3be29SBrandon Streiff struct ptp_pin_desc *ppd = &chip->pin_config[i];
5074eb3be29SBrandon Streiff
5084eb3be29SBrandon Streiff snprintf(ppd->name, sizeof(ppd->name), "mv88e6xxx_gpio%d", i);
5094eb3be29SBrandon Streiff ppd->index = i;
5104eb3be29SBrandon Streiff ppd->func = PTP_PF_NONE;
5114eb3be29SBrandon Streiff }
5124eb3be29SBrandon Streiff chip->ptp_clock_info.pin_config = chip->pin_config;
5134eb3be29SBrandon Streiff
51471509614SHubert Feurstein chip->ptp_clock_info.max_adj = MV88E6XXX_MAX_ADJ_PPB;
5152fa8d3afSBrandon Streiff chip->ptp_clock_info.adjfine = mv88e6xxx_ptp_adjfine;
5162fa8d3afSBrandon Streiff chip->ptp_clock_info.adjtime = mv88e6xxx_ptp_adjtime;
5172fa8d3afSBrandon Streiff chip->ptp_clock_info.gettime64 = mv88e6xxx_ptp_gettime;
5182fa8d3afSBrandon Streiff chip->ptp_clock_info.settime64 = mv88e6xxx_ptp_settime;
5196d2ac8eeSAndrew Lunn chip->ptp_clock_info.enable = ptp_ops->ptp_enable;
5206d2ac8eeSAndrew Lunn chip->ptp_clock_info.verify = ptp_ops->ptp_verify;
521c6fe0ad2SBrandon Streiff chip->ptp_clock_info.do_aux_work = mv88e6xxx_hwtstamp_work;
5222fa8d3afSBrandon Streiff
523*9627c981SKurt Kanzenbach if (ptp_ops->set_ptp_cpu_port) {
524*9627c981SKurt Kanzenbach struct dsa_port *dp;
525*9627c981SKurt Kanzenbach int upstream = 0;
526*9627c981SKurt Kanzenbach int err;
527*9627c981SKurt Kanzenbach
528*9627c981SKurt Kanzenbach dsa_switch_for_each_user_port(dp, chip->ds) {
529*9627c981SKurt Kanzenbach upstream = dsa_upstream_port(chip->ds, dp->index);
530*9627c981SKurt Kanzenbach break;
531*9627c981SKurt Kanzenbach }
532*9627c981SKurt Kanzenbach
533*9627c981SKurt Kanzenbach err = ptp_ops->set_ptp_cpu_port(chip, upstream);
534*9627c981SKurt Kanzenbach if (err) {
535*9627c981SKurt Kanzenbach dev_err(chip->dev, "Failed to set PTP CPU destination port!\n");
536*9627c981SKurt Kanzenbach return err;
537*9627c981SKurt Kanzenbach }
538*9627c981SKurt Kanzenbach }
539*9627c981SKurt Kanzenbach
5402fa8d3afSBrandon Streiff chip->ptp_clock = ptp_clock_register(&chip->ptp_clock_info, chip->dev);
5412fa8d3afSBrandon Streiff if (IS_ERR(chip->ptp_clock))
5422fa8d3afSBrandon Streiff return PTR_ERR(chip->ptp_clock);
5432fa8d3afSBrandon Streiff
5442fa8d3afSBrandon Streiff schedule_delayed_work(&chip->overflow_work,
5452fa8d3afSBrandon Streiff MV88E6XXX_TAI_OVERFLOW_PERIOD);
5462fa8d3afSBrandon Streiff
5472fa8d3afSBrandon Streiff return 0;
5482fa8d3afSBrandon Streiff }
5492fa8d3afSBrandon Streiff
mv88e6xxx_ptp_free(struct mv88e6xxx_chip * chip)5502fa8d3afSBrandon Streiff void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip)
5512fa8d3afSBrandon Streiff {
5522fa8d3afSBrandon Streiff if (chip->ptp_clock) {
5532fa8d3afSBrandon Streiff cancel_delayed_work_sync(&chip->overflow_work);
5546d2ac8eeSAndrew Lunn if (chip->info->ops->ptp_ops->event_work)
5554eb3be29SBrandon Streiff cancel_delayed_work_sync(&chip->tai_event_work);
5562fa8d3afSBrandon Streiff
5572fa8d3afSBrandon Streiff ptp_clock_unregister(chip->ptp_clock);
5582fa8d3afSBrandon Streiff chip->ptp_clock = NULL;
5592fa8d3afSBrandon Streiff }
5602fa8d3afSBrandon Streiff }
561