1 /* 2 * Marvell 88E6xxx Switch Port Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #ifndef _MV88E6XXX_PORT_H 16 #define _MV88E6XXX_PORT_H 17 18 #include "chip.h" 19 20 /* Offset 0x00: Port Status Register */ 21 #define MV88E6XXX_PORT_STS 0x00 22 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 23 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000 24 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 25 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000 26 #define MV88E6XXX_PORT_STS_LINK 0x0800 27 #define MV88E6XXX_PORT_STS_DUPLEX 0x0400 28 #define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 29 #define MV88E6XXX_PORT_STS_SPEED_10 0x0000 30 #define MV88E6XXX_PORT_STS_SPEED_100 0x0100 31 #define MV88E6XXX_PORT_STS_SPEED_1000 0x0200 32 #define MV88E6352_PORT_STS_EEE 0x0040 33 #define MV88E6165_PORT_STS_AM_DIS 0x0040 34 #define MV88E6185_PORT_STS_MGMII 0x0040 35 #define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 36 #define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 37 #define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f 38 #define MV88E6XXX_PORT_STS_CMODE_100BASE_X 0x0008 39 #define MV88E6XXX_PORT_STS_CMODE_1000BASE_X 0x0009 40 #define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a 41 #define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b 42 #define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c 43 #define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d 44 45 /* Offset 0x01: MAC (or PCS or Physical) Control Register */ 46 #define MV88E6XXX_PORT_MAC_CTL 0x01 47 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 48 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 49 #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 50 #define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 51 #define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 52 #define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 53 #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040 54 #define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020 55 #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010 56 #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008 57 #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004 58 #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003 59 #define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000 60 #define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001 61 #define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002 62 #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002 63 #define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003 64 #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 65 66 /* Offset 0x02: Jamming Control Register */ 67 #define MV88E6097_PORT_JAM_CTL 0x02 68 #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00 69 #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff 70 71 /* Offset 0x02: Flow Control Register */ 72 #define MV88E6390_PORT_FLOW_CTL 0x02 73 #define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000 74 #define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00 75 #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000 76 #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100 77 #define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff 78 79 /* Offset 0x03: Switch Identifier Register */ 80 #define MV88E6XXX_PORT_SWITCH_ID 0x03 81 #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0 82 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0 83 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950 84 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990 85 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00 86 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10 87 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060 88 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150 89 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210 90 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610 91 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650 92 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710 93 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720 94 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750 95 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760 96 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900 97 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910 98 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70 99 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400 100 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900 101 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100 102 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400 103 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410 104 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520 105 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710 106 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750 107 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900 108 #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f 109 110 /* Offset 0x04: Port Control Register */ 111 #define MV88E6XXX_PORT_CTL0 0x04 112 #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000 113 #define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK 0x4000 114 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000 115 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000 116 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000 117 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000 118 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000 119 #define MV88E6XXX_PORT_CTL0_HEADER 0x0800 120 #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400 121 #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200 122 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300 123 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000 124 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100 125 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200 126 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300 127 #define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100 128 #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080 129 #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040 130 #define MV88E6185_PORT_CTL0_USE_IP 0x0020 131 #define MV88E6185_PORT_CTL0_USE_TAG 0x0010 132 #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004 133 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK 0x000c 134 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA 0x0000 135 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA 0x0004 136 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA 0x0008 137 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA 0x000c 138 #define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003 139 #define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000 140 #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001 141 #define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002 142 #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003 143 144 /* Offset 0x05: Port Control 1 */ 145 #define MV88E6XXX_PORT_CTL1 0x05 146 #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000 147 #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff 148 149 /* Offset 0x06: Port Based VLAN Map */ 150 #define MV88E6XXX_PORT_BASE_VLAN 0x06 151 #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000 152 153 /* Offset 0x07: Default Port VLAN ID & Priority */ 154 #define MV88E6XXX_PORT_DEFAULT_VLAN 0x07 155 #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff 156 157 /* Offset 0x08: Port Control 2 Register */ 158 #define MV88E6XXX_PORT_CTL2 0x08 159 #define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000 160 #define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000 161 #define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000 162 #define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000 163 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000 164 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000 165 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000 166 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000 167 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00 168 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000 169 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400 170 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800 171 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00 172 #define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200 173 #define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100 174 #define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080 175 #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040 176 #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020 177 #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010 178 #define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f 179 180 /* Offset 0x09: Egress Rate Control */ 181 #define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09 182 183 /* Offset 0x0A: Egress Rate Control 2 */ 184 #define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a 185 186 /* Offset 0x0B: Port Association Vector */ 187 #define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b 188 #define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000 189 #define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000 190 #define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000 191 #define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000 192 #define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800 193 194 /* Offset 0x0C: Port ATU Control */ 195 #define MV88E6XXX_PORT_ATU_CTL 0x0c 196 197 /* Offset 0x0D: Priority Override Register */ 198 #define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d 199 200 /* Offset 0x0E: Policy Control Register */ 201 #define MV88E6XXX_PORT_POLICY_CTL 0x0e 202 203 /* Offset 0x0F: Port Special Ether Type */ 204 #define MV88E6XXX_PORT_ETH_TYPE 0x0f 205 #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100 206 207 /* Offset 0x10: InDiscards Low Counter */ 208 #define MV88E6XXX_PORT_IN_DISCARD_LO 0x10 209 210 /* Offset 0x11: InDiscards High Counter */ 211 #define MV88E6XXX_PORT_IN_DISCARD_HI 0x11 212 213 /* Offset 0x12: InFiltered Counter */ 214 #define MV88E6XXX_PORT_IN_FILTERED 0x12 215 216 /* Offset 0x13: OutFiltered Counter */ 217 #define MV88E6XXX_PORT_OUT_FILTERED 0x13 218 219 /* Offset 0x18: IEEE Priority Mapping Table */ 220 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18 221 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000 222 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000 223 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000 224 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000 225 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000 226 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000 227 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000 228 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000 229 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000 230 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00 231 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff 232 233 /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */ 234 #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18 235 236 /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */ 237 #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19 238 239 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 240 u16 *val); 241 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 242 u16 val); 243 244 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 245 phy_interface_t mode); 246 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 247 phy_interface_t mode); 248 249 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 250 251 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup); 252 253 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 254 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 255 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 256 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 257 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 258 259 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 260 261 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 262 263 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 264 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 265 266 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 267 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 268 269 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 270 u16 mode); 271 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 272 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 273 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 274 enum mv88e6xxx_egress_mode mode); 275 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 276 enum mv88e6xxx_frame_mode mode); 277 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 278 enum mv88e6xxx_frame_mode mode); 279 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 280 bool unicast, bool multicast); 281 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 282 bool unicast, bool multicast); 283 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 284 u16 etype); 285 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 286 bool message_port); 287 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 288 size_t size); 289 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 290 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 291 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 292 u8 out); 293 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 294 u8 out); 295 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 296 phy_interface_t mode); 297 int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 298 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port); 299 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 300 int upstream_port); 301 302 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 303 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 304 305 #endif /* _MV88E6XXX_PORT_H */ 306