xref: /openbmc/linux/drivers/net/dsa/mv88e6xxx/port.h (revision 91db9311)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Marvell 88E6xxx Switch Port Registers support
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  *
7  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9  */
10 
11 #ifndef _MV88E6XXX_PORT_H
12 #define _MV88E6XXX_PORT_H
13 
14 #include "chip.h"
15 
16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS			0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN		0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE		0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW		0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT		0x1000
22 #define MV88E6250_PORT_STS_LINK				0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK		0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF		0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF	0x0900
26 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL		0x0a00
27 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL	0x0b00
28 #define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF		0x0c00
29 #define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF	0x0d00
30 #define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL		0x0e00
31 #define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL	0x0f00
32 #define MV88E6XXX_PORT_STS_LINK			0x0800
33 #define MV88E6XXX_PORT_STS_DUPLEX		0x0400
34 #define MV88E6XXX_PORT_STS_SPEED_MASK		0x0300
35 #define MV88E6XXX_PORT_STS_SPEED_10		0x0000
36 #define MV88E6XXX_PORT_STS_SPEED_100		0x0100
37 #define MV88E6XXX_PORT_STS_SPEED_1000		0x0200
38 #define MV88E6XXX_PORT_STS_SPEED_10000		0x0300
39 #define MV88E6352_PORT_STS_EEE			0x0040
40 #define MV88E6165_PORT_STS_AM_DIS		0x0040
41 #define MV88E6185_PORT_STS_MGMII		0x0040
42 #define MV88E6XXX_PORT_STS_TX_PAUSED		0x0020
43 #define MV88E6XXX_PORT_STS_FLOW_CTL		0x0010
44 #define MV88E6XXX_PORT_STS_CMODE_MASK		0x000f
45 #define MV88E6XXX_PORT_STS_CMODE_100BASE_X	0x0008
46 #define MV88E6XXX_PORT_STS_CMODE_1000BASE_X	0x0009
47 #define MV88E6XXX_PORT_STS_CMODE_SGMII		0x000a
48 #define MV88E6XXX_PORT_STS_CMODE_2500BASEX	0x000b
49 #define MV88E6XXX_PORT_STS_CMODE_XAUI		0x000c
50 #define MV88E6XXX_PORT_STS_CMODE_RXAUI		0x000d
51 #define MV88E6185_PORT_STS_CDUPLEX		0x0008
52 #define MV88E6185_PORT_STS_CMODE_MASK		0x0007
53 #define MV88E6185_PORT_STS_CMODE_GMII_FD	0x0000
54 #define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS	0x0001
55 #define MV88E6185_PORT_STS_CMODE_MII_100	0x0002
56 #define MV88E6185_PORT_STS_CMODE_MII_10		0x0003
57 #define MV88E6185_PORT_STS_CMODE_SERDES		0x0004
58 #define MV88E6185_PORT_STS_CMODE_1000BASE_X	0x0005
59 #define MV88E6185_PORT_STS_CMODE_PHY		0x0006
60 #define MV88E6185_PORT_STS_CMODE_DISABLED	0x0007
61 
62 /* Offset 0x01: MAC (or PCS or Physical) Control Register */
63 #define MV88E6XXX_PORT_MAC_CTL				0x01
64 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK	0x8000
65 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK	0x4000
66 #define MV88E6185_PORT_MAC_CTL_SYNC_OK			0x4000
67 #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED		0x2000
68 #define MV88E6390_PORT_MAC_CTL_ALTSPEED			0x1000
69 #define MV88E6352_PORT_MAC_CTL_200BASE			0x1000
70 #define MV88E6185_PORT_MAC_CTL_AN_EN			0x0400
71 #define MV88E6185_PORT_MAC_CTL_AN_RESTART		0x0200
72 #define MV88E6185_PORT_MAC_CTL_AN_DONE			0x0100
73 #define MV88E6XXX_PORT_MAC_CTL_FC			0x0080
74 #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC			0x0040
75 #define MV88E6XXX_PORT_MAC_CTL_LINK_UP			0x0020
76 #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK		0x0010
77 #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL		0x0008
78 #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX		0x0004
79 #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK		0x0003
80 #define MV88E6XXX_PORT_MAC_CTL_SPEED_10			0x0000
81 #define MV88E6XXX_PORT_MAC_CTL_SPEED_100		0x0001
82 #define MV88E6065_PORT_MAC_CTL_SPEED_200		0x0002
83 #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000		0x0002
84 #define MV88E6390_PORT_MAC_CTL_SPEED_10000		0x0003
85 #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED		0x0003
86 
87 /* Offset 0x02: Jamming Control Register */
88 #define MV88E6097_PORT_JAM_CTL			0x02
89 #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK	0xff00
90 #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK	0x00ff
91 
92 /* Offset 0x02: Flow Control Register */
93 #define MV88E6390_PORT_FLOW_CTL			0x02
94 #define MV88E6390_PORT_FLOW_CTL_UPDATE		0x8000
95 #define MV88E6390_PORT_FLOW_CTL_PTR_MASK	0x7f00
96 #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN	0x0000
97 #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT	0x0100
98 #define MV88E6390_PORT_FLOW_CTL_DATA_MASK	0x00ff
99 
100 /* Offset 0x03: Switch Identifier Register */
101 #define MV88E6XXX_PORT_SWITCH_ID		0x03
102 #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK	0xfff0
103 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085	0x04a0
104 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095	0x0950
105 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097	0x0990
106 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X	0x0a00
107 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X	0x0a10
108 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131	0x1060
109 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320	0x1150
110 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123	0x1210
111 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161	0x1610
112 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165	0x1650
113 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171	0x1710
114 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172	0x1720
115 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175	0x1750
116 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176	0x1760
117 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190	0x1900
118 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191	0x1910
119 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185	0x1a70
120 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240	0x2400
121 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6250	0x2500
122 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290	0x2900
123 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321	0x3100
124 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141	0x3400
125 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341	0x3410
126 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352	0x3520
127 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350	0x3710
128 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351	0x3750
129 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390	0x3900
130 #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK	0x000f
131 
132 /* Offset 0x04: Port Control Register */
133 #define MV88E6XXX_PORT_CTL0					0x04
134 #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG			0x8000
135 #define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK			0x4000
136 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK			0x3000
137 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED		0x0000
138 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED		0x1000
139 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED			0x2000
140 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA		0x3000
141 #define MV88E6XXX_PORT_CTL0_HEADER				0x0800
142 #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP			0x0400
143 #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG				0x0200
144 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK			0x0300
145 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL			0x0000
146 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA			0x0100
147 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER			0x0200
148 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA		0x0300
149 #define MV88E6XXX_PORT_CTL0_DSA_TAG				0x0100
150 #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL				0x0080
151 #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH				0x0040
152 #define MV88E6185_PORT_CTL0_USE_IP				0x0020
153 #define MV88E6185_PORT_CTL0_USE_TAG				0x0010
154 #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN			0x0004
155 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK			0x000c
156 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA		0x0000
157 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA	0x0004
158 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA	0x0008
159 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA	0x000c
160 #define MV88E6XXX_PORT_CTL0_STATE_MASK				0x0003
161 #define MV88E6XXX_PORT_CTL0_STATE_DISABLED			0x0000
162 #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING			0x0001
163 #define MV88E6XXX_PORT_CTL0_STATE_LEARNING			0x0002
164 #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING			0x0003
165 
166 /* Offset 0x05: Port Control 1 */
167 #define MV88E6XXX_PORT_CTL1			0x05
168 #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT	0x8000
169 #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK	0x00ff
170 
171 /* Offset 0x06: Port Based VLAN Map */
172 #define MV88E6XXX_PORT_BASE_VLAN		0x06
173 #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK	0xf000
174 
175 /* Offset 0x07: Default Port VLAN ID & Priority */
176 #define MV88E6XXX_PORT_DEFAULT_VLAN		0x07
177 #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK	0x0fff
178 
179 /* Offset 0x08: Port Control 2 Register */
180 #define MV88E6XXX_PORT_CTL2				0x08
181 #define MV88E6XXX_PORT_CTL2_IGNORE_FCS			0x8000
182 #define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE		0x4000
183 #define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE		0x2000
184 #define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE		0x1000
185 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK		0x3000
186 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522		0x0000
187 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048		0x1000
188 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240		0x2000
189 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK		0x0c00
190 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED		0x0000
191 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK		0x0400
192 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK		0x0800
193 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE		0x0c00
194 #define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED		0x0200
195 #define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED		0x0100
196 #define MV88E6XXX_PORT_CTL2_MAP_DA			0x0080
197 #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD		0x0040
198 #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR		0x0020
199 #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR		0x0010
200 #define MV88E6095_PORT_CTL2_CPU_PORT_MASK		0x000f
201 
202 /* Offset 0x09: Egress Rate Control */
203 #define MV88E6XXX_PORT_EGRESS_RATE_CTL1		0x09
204 
205 /* Offset 0x0A: Egress Rate Control 2 */
206 #define MV88E6XXX_PORT_EGRESS_RATE_CTL2		0x0a
207 
208 /* Offset 0x0B: Port Association Vector */
209 #define MV88E6XXX_PORT_ASSOC_VECTOR			0x0b
210 #define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1		0x8000
211 #define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT		0x4000
212 #define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT		0x2000
213 #define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG	0x1000
214 #define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED	0x0800
215 
216 /* Offset 0x0C: Port ATU Control */
217 #define MV88E6XXX_PORT_ATU_CTL		0x0c
218 
219 /* Offset 0x0D: Priority Override Register */
220 #define MV88E6XXX_PORT_PRI_OVERRIDE	0x0d
221 
222 /* Offset 0x0E: Policy Control Register */
223 #define MV88E6XXX_PORT_POLICY_CTL	0x0e
224 
225 /* Offset 0x0F: Port Special Ether Type */
226 #define MV88E6XXX_PORT_ETH_TYPE		0x0f
227 #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT	0x9100
228 
229 /* Offset 0x10: InDiscards Low Counter */
230 #define MV88E6XXX_PORT_IN_DISCARD_LO	0x10
231 
232 /* Offset 0x11: InDiscards High Counter */
233 #define MV88E6XXX_PORT_IN_DISCARD_HI	0x11
234 
235 /* Offset 0x12: InFiltered Counter */
236 #define MV88E6XXX_PORT_IN_FILTERED	0x12
237 
238 /* Offset 0x13: OutFiltered Counter */
239 #define MV88E6XXX_PORT_OUT_FILTERED	0x13
240 
241 /* Offset 0x18: IEEE Priority Mapping Table */
242 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE			0x18
243 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE		0x8000
244 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK			0x7000
245 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP		0x0000
246 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP	0x1000
247 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP	0x2000
248 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP	0x3000
249 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP	0x5000
250 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP	0x6000
251 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP	0x7000
252 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK		0x0e00
253 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK		0x01ff
254 
255 /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
256 #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123	0x18
257 
258 /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
259 #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567	0x19
260 
261 /* Offset 0x1a: Magic undocumented errata register */
262 #define PORT_RESERVED_1A			0x1a
263 #define PORT_RESERVED_1A_BUSY			BIT(15)
264 #define PORT_RESERVED_1A_WRITE			BIT(14)
265 #define PORT_RESERVED_1A_READ			0
266 #define PORT_RESERVED_1A_PORT_SHIFT		5
267 #define PORT_RESERVED_1A_BLOCK			(0xf << 10)
268 #define PORT_RESERVED_1A_CTRL_PORT		4
269 #define PORT_RESERVED_1A_DATA_PORT		5
270 
271 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
272 			u16 *val);
273 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
274 			 u16 val);
275 
276 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
277 			     int pause);
278 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
279 				   phy_interface_t mode);
280 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
281 				   phy_interface_t mode);
282 
283 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
284 
285 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup);
286 
287 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
288 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
289 int mv88e6250_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
290 int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
291 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
292 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
293 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
294 
295 phy_interface_t mv88e6341_port_max_speed_mode(int port);
296 phy_interface_t mv88e6390_port_max_speed_mode(int port);
297 phy_interface_t mv88e6390x_port_max_speed_mode(int port);
298 
299 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
300 
301 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
302 
303 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);
304 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);
305 
306 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);
307 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);
308 
309 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
310 				  u16 mode);
311 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
312 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
313 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
314 				   enum mv88e6xxx_egress_mode mode);
315 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
316 				  enum mv88e6xxx_frame_mode mode);
317 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
318 				  enum mv88e6xxx_frame_mode mode);
319 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
320 				     bool unicast, bool multicast);
321 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
322 				     bool unicast, bool multicast);
323 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
324 				  u16 etype);
325 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
326 				    bool message_port);
327 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
328 				  size_t size);
329 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
330 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
331 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
332 			       u8 out);
333 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
334 			       u8 out);
335 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
336 			     phy_interface_t mode);
337 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
338 			      phy_interface_t mode);
339 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
340 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
341 int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
342 			      struct phylink_link_state *state);
343 int mv88e6250_port_link_state(struct mv88e6xxx_chip *chip, int port,
344 			      struct phylink_link_state *state);
345 int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
346 			      struct phylink_link_state *state);
347 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port);
348 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
349 				     int upstream_port);
350 
351 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
352 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);
353 
354 #endif /* _MV88E6XXX_PORT_H */
355