1 /* 2 * Marvell 88E6xxx Switch Port Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #ifndef _MV88E6XXX_PORT_H 16 #define _MV88E6XXX_PORT_H 17 18 #include "chip.h" 19 20 /* Offset 0x00: Port Status Register */ 21 #define MV88E6XXX_PORT_STS 0x00 22 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 23 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000 24 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 25 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000 26 #define MV88E6XXX_PORT_STS_LINK 0x0800 27 #define MV88E6XXX_PORT_STS_DUPLEX 0x0400 28 #define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 29 #define MV88E6XXX_PORT_STS_SPEED_10 0x0000 30 #define MV88E6XXX_PORT_STS_SPEED_100 0x0100 31 #define MV88E6XXX_PORT_STS_SPEED_1000 0x0200 32 #define MV88E6XXX_PORT_STS_SPEED_10000 0x0300 33 #define MV88E6352_PORT_STS_EEE 0x0040 34 #define MV88E6165_PORT_STS_AM_DIS 0x0040 35 #define MV88E6185_PORT_STS_MGMII 0x0040 36 #define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 37 #define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 38 #define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f 39 #define MV88E6XXX_PORT_STS_CMODE_100BASE_X 0x0008 40 #define MV88E6XXX_PORT_STS_CMODE_1000BASE_X 0x0009 41 #define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a 42 #define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b 43 #define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c 44 #define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d 45 #define MV88E6185_PORT_STS_CDUPLEX 0x0008 46 #define MV88E6185_PORT_STS_CMODE_MASK 0x0007 47 #define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000 48 #define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x0001 49 #define MV88E6185_PORT_STS_CMODE_MII_100 0x0002 50 #define MV88E6185_PORT_STS_CMODE_MII_10 0x0003 51 #define MV88E6185_PORT_STS_CMODE_SERDES 0x0004 52 #define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005 53 #define MV88E6185_PORT_STS_CMODE_PHY 0x0006 54 #define MV88E6185_PORT_STS_CMODE_DISABLED 0x0007 55 56 /* Offset 0x01: MAC (or PCS or Physical) Control Register */ 57 #define MV88E6XXX_PORT_MAC_CTL 0x01 58 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 59 #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 60 #define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x4000 61 #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 62 #define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 63 #define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 64 #define MV88E6185_PORT_MAC_CTL_AN_EN 0x0400 65 #define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x0200 66 #define MV88E6185_PORT_MAC_CTL_AN_DONE 0x0100 67 #define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 68 #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040 69 #define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020 70 #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010 71 #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008 72 #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004 73 #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003 74 #define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000 75 #define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001 76 #define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002 77 #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002 78 #define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003 79 #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 80 81 /* Offset 0x02: Jamming Control Register */ 82 #define MV88E6097_PORT_JAM_CTL 0x02 83 #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00 84 #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff 85 86 /* Offset 0x02: Flow Control Register */ 87 #define MV88E6390_PORT_FLOW_CTL 0x02 88 #define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000 89 #define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00 90 #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000 91 #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100 92 #define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff 93 94 /* Offset 0x03: Switch Identifier Register */ 95 #define MV88E6XXX_PORT_SWITCH_ID 0x03 96 #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0 97 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0 98 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950 99 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990 100 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00 101 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10 102 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060 103 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150 104 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210 105 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610 106 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650 107 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710 108 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720 109 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750 110 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760 111 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900 112 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910 113 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70 114 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400 115 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900 116 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100 117 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400 118 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410 119 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520 120 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710 121 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750 122 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900 123 #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f 124 125 /* Offset 0x04: Port Control Register */ 126 #define MV88E6XXX_PORT_CTL0 0x04 127 #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000 128 #define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK 0x4000 129 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000 130 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000 131 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000 132 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000 133 #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000 134 #define MV88E6XXX_PORT_CTL0_HEADER 0x0800 135 #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400 136 #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200 137 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300 138 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000 139 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100 140 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200 141 #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300 142 #define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100 143 #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080 144 #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040 145 #define MV88E6185_PORT_CTL0_USE_IP 0x0020 146 #define MV88E6185_PORT_CTL0_USE_TAG 0x0010 147 #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004 148 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK 0x000c 149 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA 0x0000 150 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA 0x0004 151 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA 0x0008 152 #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA 0x000c 153 #define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003 154 #define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000 155 #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001 156 #define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002 157 #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003 158 159 /* Offset 0x05: Port Control 1 */ 160 #define MV88E6XXX_PORT_CTL1 0x05 161 #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000 162 #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff 163 164 /* Offset 0x06: Port Based VLAN Map */ 165 #define MV88E6XXX_PORT_BASE_VLAN 0x06 166 #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000 167 168 /* Offset 0x07: Default Port VLAN ID & Priority */ 169 #define MV88E6XXX_PORT_DEFAULT_VLAN 0x07 170 #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff 171 172 /* Offset 0x08: Port Control 2 Register */ 173 #define MV88E6XXX_PORT_CTL2 0x08 174 #define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000 175 #define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000 176 #define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000 177 #define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000 178 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000 179 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000 180 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000 181 #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000 182 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00 183 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000 184 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400 185 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800 186 #define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00 187 #define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200 188 #define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100 189 #define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080 190 #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040 191 #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020 192 #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010 193 #define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f 194 195 /* Offset 0x09: Egress Rate Control */ 196 #define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09 197 198 /* Offset 0x0A: Egress Rate Control 2 */ 199 #define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a 200 201 /* Offset 0x0B: Port Association Vector */ 202 #define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b 203 #define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000 204 #define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000 205 #define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000 206 #define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000 207 #define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800 208 209 /* Offset 0x0C: Port ATU Control */ 210 #define MV88E6XXX_PORT_ATU_CTL 0x0c 211 212 /* Offset 0x0D: Priority Override Register */ 213 #define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d 214 215 /* Offset 0x0E: Policy Control Register */ 216 #define MV88E6XXX_PORT_POLICY_CTL 0x0e 217 218 /* Offset 0x0F: Port Special Ether Type */ 219 #define MV88E6XXX_PORT_ETH_TYPE 0x0f 220 #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100 221 222 /* Offset 0x10: InDiscards Low Counter */ 223 #define MV88E6XXX_PORT_IN_DISCARD_LO 0x10 224 225 /* Offset 0x11: InDiscards High Counter */ 226 #define MV88E6XXX_PORT_IN_DISCARD_HI 0x11 227 228 /* Offset 0x12: InFiltered Counter */ 229 #define MV88E6XXX_PORT_IN_FILTERED 0x12 230 231 /* Offset 0x13: OutFiltered Counter */ 232 #define MV88E6XXX_PORT_OUT_FILTERED 0x13 233 234 /* Offset 0x18: IEEE Priority Mapping Table */ 235 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18 236 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000 237 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000 238 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000 239 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000 240 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000 241 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000 242 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000 243 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000 244 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000 245 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00 246 #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff 247 248 /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */ 249 #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18 250 251 /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */ 252 #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19 253 254 /* Offset 0x1a: Magic undocumented errata register */ 255 #define PORT_RESERVED_1A 0x1a 256 #define PORT_RESERVED_1A_BUSY BIT(15) 257 #define PORT_RESERVED_1A_WRITE BIT(14) 258 #define PORT_RESERVED_1A_READ 0 259 #define PORT_RESERVED_1A_PORT_SHIFT 5 260 #define PORT_RESERVED_1A_BLOCK (0xf << 10) 261 #define PORT_RESERVED_1A_CTRL_PORT 4 262 #define PORT_RESERVED_1A_DATA_PORT 5 263 264 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 265 u16 *val); 266 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 267 u16 val); 268 269 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 270 int pause); 271 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 272 phy_interface_t mode); 273 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 274 phy_interface_t mode); 275 276 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 277 278 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup); 279 280 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 281 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 282 int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 283 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 284 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 285 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 286 287 phy_interface_t mv88e6341_port_max_speed_mode(int port); 288 phy_interface_t mv88e6390_port_max_speed_mode(int port); 289 phy_interface_t mv88e6390x_port_max_speed_mode(int port); 290 291 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 292 293 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 294 295 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 296 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 297 298 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 299 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 300 301 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 302 u16 mode); 303 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 304 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 305 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 306 enum mv88e6xxx_egress_mode mode); 307 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 308 enum mv88e6xxx_frame_mode mode); 309 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 310 enum mv88e6xxx_frame_mode mode); 311 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 312 bool unicast, bool multicast); 313 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 314 bool unicast, bool multicast); 315 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 316 u16 etype); 317 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 318 bool message_port); 319 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 320 size_t size); 321 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 322 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 323 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 324 u8 out); 325 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 326 u8 out); 327 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 328 phy_interface_t mode); 329 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 330 phy_interface_t mode); 331 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 332 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 333 int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port, 334 struct phylink_link_state *state); 335 int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port, 336 struct phylink_link_state *state); 337 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port); 338 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 339 int upstream_port); 340 341 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 342 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 343 344 #endif /* _MV88E6XXX_PORT_H */ 345