118abed21SVivien Didelot /* 218abed21SVivien Didelot * Marvell 88E6xxx Switch Port Registers support 318abed21SVivien Didelot * 418abed21SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 518abed21SVivien Didelot * 64333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 74333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 818abed21SVivien Didelot * 918abed21SVivien Didelot * This program is free software; you can redistribute it and/or modify 1018abed21SVivien Didelot * it under the terms of the GNU General Public License as published by 1118abed21SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 1218abed21SVivien Didelot * (at your option) any later version. 1318abed21SVivien Didelot */ 1418abed21SVivien Didelot 1518abed21SVivien Didelot #ifndef _MV88E6XXX_PORT_H 1618abed21SVivien Didelot #define _MV88E6XXX_PORT_H 1718abed21SVivien Didelot 184d5f2ba7SVivien Didelot #include "chip.h" 1918abed21SVivien Didelot 20d2a160b5SVivien Didelot #define PORT_STATUS 0x00 21d2a160b5SVivien Didelot #define PORT_STATUS_PAUSE_EN BIT(15) 22d2a160b5SVivien Didelot #define PORT_STATUS_MY_PAUSE BIT(14) 23d2a160b5SVivien Didelot #define PORT_STATUS_HD_FLOW BIT(13) 24d2a160b5SVivien Didelot #define PORT_STATUS_PHY_DETECT BIT(12) 25d2a160b5SVivien Didelot #define PORT_STATUS_LINK BIT(11) 26d2a160b5SVivien Didelot #define PORT_STATUS_DUPLEX BIT(10) 27d2a160b5SVivien Didelot #define PORT_STATUS_SPEED_MASK 0x0300 28d2a160b5SVivien Didelot #define PORT_STATUS_SPEED_10 0x0000 29d2a160b5SVivien Didelot #define PORT_STATUS_SPEED_100 0x0100 30d2a160b5SVivien Didelot #define PORT_STATUS_SPEED_1000 0x0200 31d2a160b5SVivien Didelot #define PORT_STATUS_EEE BIT(6) /* 6352 */ 32d2a160b5SVivien Didelot #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */ 33d2a160b5SVivien Didelot #define PORT_STATUS_MGMII BIT(6) /* 6185 */ 34d2a160b5SVivien Didelot #define PORT_STATUS_TX_PAUSED BIT(5) 35d2a160b5SVivien Didelot #define PORT_STATUS_FLOW_CTRL BIT(4) 36d2a160b5SVivien Didelot #define PORT_STATUS_CMODE_MASK 0x0f 37d2a160b5SVivien Didelot #define PORT_STATUS_CMODE_100BASE_X 0x8 38d2a160b5SVivien Didelot #define PORT_STATUS_CMODE_1000BASE_X 0x9 39d2a160b5SVivien Didelot #define PORT_STATUS_CMODE_SGMII 0xa 40d2a160b5SVivien Didelot #define PORT_STATUS_CMODE_2500BASEX 0xb 41d2a160b5SVivien Didelot #define PORT_STATUS_CMODE_XAUI 0xc 42d2a160b5SVivien Didelot #define PORT_STATUS_CMODE_RXAUI 0xd 43d2a160b5SVivien Didelot #define PORT_PCS_CTRL 0x01 44d2a160b5SVivien Didelot #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15) 45d2a160b5SVivien Didelot #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14) 46d2a160b5SVivien Didelot #define PORT_PCS_CTRL_FORCE_SPEED BIT(13) /* 6390 */ 47d2a160b5SVivien Didelot #define PORT_PCS_CTRL_ALTSPEED BIT(12) /* 6390 */ 48d2a160b5SVivien Didelot #define PORT_PCS_CTRL_200BASE BIT(12) /* 6352 */ 49d2a160b5SVivien Didelot #define PORT_PCS_CTRL_FC BIT(7) 50d2a160b5SVivien Didelot #define PORT_PCS_CTRL_FORCE_FC BIT(6) 51d2a160b5SVivien Didelot #define PORT_PCS_CTRL_LINK_UP BIT(5) 52d2a160b5SVivien Didelot #define PORT_PCS_CTRL_FORCE_LINK BIT(4) 53d2a160b5SVivien Didelot #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3) 54d2a160b5SVivien Didelot #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2) 55d2a160b5SVivien Didelot #define PORT_PCS_CTRL_SPEED_MASK (0x03) 56d2a160b5SVivien Didelot #define PORT_PCS_CTRL_SPEED_10 (0x00) 57d2a160b5SVivien Didelot #define PORT_PCS_CTRL_SPEED_100 (0x01) 58d2a160b5SVivien Didelot #define PORT_PCS_CTRL_SPEED_200 (0x02) /* 6065 and non Gb chips */ 59d2a160b5SVivien Didelot #define PORT_PCS_CTRL_SPEED_1000 (0x02) 60d2a160b5SVivien Didelot #define PORT_PCS_CTRL_SPEED_10000 (0x03) /* 6390X */ 61d2a160b5SVivien Didelot #define PORT_PCS_CTRL_SPEED_UNFORCED (0x03) 62d2a160b5SVivien Didelot #define PORT_PAUSE_CTRL 0x02 63d2a160b5SVivien Didelot #define PORT_FLOW_CTRL_LIMIT_IN ((0x00 << 8) | BIT(15)) 64d2a160b5SVivien Didelot #define PORT_FLOW_CTRL_LIMIT_OUT ((0x01 << 8) | BIT(15)) 65d2a160b5SVivien Didelot #define PORT_SWITCH_ID 0x03 66d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6085 0x04a 67d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6095 0x095 68d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6097 0x099 69d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6131 0x106 70d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6320 0x115 71d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6123 0x121 72d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6141 0x340 73d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6161 0x161 74d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6165 0x165 75d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6171 0x171 76d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6172 0x172 77d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6175 0x175 78d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6176 0x176 79d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7 80d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6190 0x190 81d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6190X 0x0a0 82d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6191 0x191 83d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6240 0x240 84d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6290 0x290 85d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6321 0x310 86d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6341 0x341 87d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6352 0x352 88d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6350 0x371 89d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6351 0x375 90d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6390 0x390 91d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6390X 0x0a1 92d2a160b5SVivien Didelot #define PORT_CONTROL 0x04 93d2a160b5SVivien Didelot #define PORT_CONTROL_USE_CORE_TAG BIT(15) 94d2a160b5SVivien Didelot #define PORT_CONTROL_DROP_ON_LOCK BIT(14) 95d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12) 96d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12) 97d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12) 98d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12) 99d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_MASK (0x3 << 12) 100d2a160b5SVivien Didelot #define PORT_CONTROL_HEADER BIT(11) 101d2a160b5SVivien Didelot #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10) 102d2a160b5SVivien Didelot #define PORT_CONTROL_DOUBLE_TAG BIT(9) 103d2a160b5SVivien Didelot #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8) 104d2a160b5SVivien Didelot #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8) 105d2a160b5SVivien Didelot #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8) 106d2a160b5SVivien Didelot #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8) 107d2a160b5SVivien Didelot #define PORT_CONTROL_FRAME_MASK (0x3 << 8) 108d2a160b5SVivien Didelot #define PORT_CONTROL_DSA_TAG BIT(8) 109d2a160b5SVivien Didelot #define PORT_CONTROL_VLAN_TUNNEL BIT(7) 110d2a160b5SVivien Didelot #define PORT_CONTROL_TAG_IF_BOTH BIT(6) 111d2a160b5SVivien Didelot #define PORT_CONTROL_USE_IP BIT(5) 112d2a160b5SVivien Didelot #define PORT_CONTROL_USE_TAG BIT(4) 113d2a160b5SVivien Didelot #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2) 114d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_FLOODS_MASK (0x3 << 2) 115d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_DA (0x0 << 2) 116d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_MC_DA (0x1 << 2) 117d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_UC_DA (0x2 << 2) 118d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_FLOODS_ALL_UNKNOWN_DA (0x3 << 2) 119d2a160b5SVivien Didelot #define PORT_CONTROL_STATE_MASK 0x03 120d2a160b5SVivien Didelot #define PORT_CONTROL_STATE_DISABLED 0x00 121d2a160b5SVivien Didelot #define PORT_CONTROL_STATE_BLOCKING 0x01 122d2a160b5SVivien Didelot #define PORT_CONTROL_STATE_LEARNING 0x02 123d2a160b5SVivien Didelot #define PORT_CONTROL_STATE_FORWARDING 0x03 124d2a160b5SVivien Didelot #define PORT_CONTROL_1 0x05 125d2a160b5SVivien Didelot #define PORT_CONTROL_1_MESSAGE_PORT BIT(15) 126d2a160b5SVivien Didelot #define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0) 127d2a160b5SVivien Didelot #define PORT_BASE_VLAN 0x06 128d2a160b5SVivien Didelot #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12) 129d2a160b5SVivien Didelot #define PORT_DEFAULT_VLAN 0x07 130d2a160b5SVivien Didelot #define PORT_DEFAULT_VLAN_MASK 0xfff 131d2a160b5SVivien Didelot #define PORT_CONTROL_2 0x08 132d2a160b5SVivien Didelot #define PORT_CONTROL_2_IGNORE_FCS BIT(15) 133d2a160b5SVivien Didelot #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) 134d2a160b5SVivien Didelot #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) 135d2a160b5SVivien Didelot #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) 136cd782656SVivien Didelot #define PORT_CONTROL_2_JUMBO_MASK (0x03 << 12) 137d2a160b5SVivien Didelot #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) 138d2a160b5SVivien Didelot #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) 139d2a160b5SVivien Didelot #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) 140d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) 141d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) 142d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) 143d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) 144d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) 145d2a160b5SVivien Didelot #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) 146d2a160b5SVivien Didelot #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) 147d2a160b5SVivien Didelot #define PORT_CONTROL_2_MAP_DA BIT(7) 148d2a160b5SVivien Didelot #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) 149d2a160b5SVivien Didelot #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) 150d2a160b5SVivien Didelot #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) 151d2a160b5SVivien Didelot #define PORT_CONTROL_2_UPSTREAM_MASK 0x0f 152d2a160b5SVivien Didelot #define PORT_RATE_CONTROL 0x09 153d2a160b5SVivien Didelot #define PORT_RATE_CONTROL_2 0x0a 154d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR 0x0b 155d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) 156d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) 157d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) 158d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) 159d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) 160d2a160b5SVivien Didelot #define PORT_ATU_CONTROL 0x0c 161d2a160b5SVivien Didelot #define PORT_PRI_OVERRIDE 0x0d 162d2a160b5SVivien Didelot #define PORT_ETH_TYPE 0x0f 163d2a160b5SVivien Didelot #define PORT_ETH_TYPE_DEFAULT 0x9100 164d2a160b5SVivien Didelot #define PORT_IN_DISCARD_LO 0x10 165d2a160b5SVivien Didelot #define PORT_IN_DISCARD_HI 0x11 166d2a160b5SVivien Didelot #define PORT_IN_FILTERED 0x12 167d2a160b5SVivien Didelot #define PORT_OUT_FILTERED 0x13 168d2a160b5SVivien Didelot #define PORT_TAG_REGMAP_0123 0x18 169d2a160b5SVivien Didelot #define PORT_TAG_REGMAP_4567 0x19 170d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE 0x18 /* 6390 */ 171d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_UPDATE BIT(15) 172d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP (0x0 << 12) 173d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP (0x1 << 12) 174d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP (0x2 << 12) 175d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP (0x3 << 12) 176d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP (0x5 << 12) 177d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP (0x6 << 12) 178d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP (0x7 << 12) 179d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT 9 180d2a160b5SVivien Didelot 18118abed21SVivien Didelot int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 18218abed21SVivien Didelot u16 *val); 18318abed21SVivien Didelot int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 18418abed21SVivien Didelot u16 val); 18518abed21SVivien Didelot 186a0a0f622SVivien Didelot int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 187a0a0f622SVivien Didelot phy_interface_t mode); 188a0a0f622SVivien Didelot int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 189a0a0f622SVivien Didelot phy_interface_t mode); 190a0a0f622SVivien Didelot 19108ef7f10SVivien Didelot int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 19208ef7f10SVivien Didelot 1937f1ae07bSVivien Didelot int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup); 1947f1ae07bSVivien Didelot 19596a2b40cSVivien Didelot int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 19696a2b40cSVivien Didelot int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 19796a2b40cSVivien Didelot int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 19896a2b40cSVivien Didelot int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 19996a2b40cSVivien Didelot int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 20096a2b40cSVivien Didelot 201e28def33SVivien Didelot int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 202e28def33SVivien Didelot 2035a7921f4SVivien Didelot int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 2045a7921f4SVivien Didelot 205b4e48c50SVivien Didelot int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 206b4e48c50SVivien Didelot int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 207b4e48c50SVivien Didelot 20877064f37SVivien Didelot int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 20977064f37SVivien Didelot int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 21077064f37SVivien Didelot 211385a0995SVivien Didelot int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 212385a0995SVivien Didelot u16 mode); 213ef0a7318SAndrew Lunn int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 214ef0a7318SAndrew Lunn int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 21556995cbcSAndrew Lunn int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 21631bef4e9SVivien Didelot enum mv88e6xxx_egress_mode mode); 21756995cbcSAndrew Lunn int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 21856995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 21956995cbcSAndrew Lunn int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 22056995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 221601aeed3SVivien Didelot int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 222601aeed3SVivien Didelot bool unicast, bool multicast); 223601aeed3SVivien Didelot int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 224601aeed3SVivien Didelot bool unicast, bool multicast); 22556995cbcSAndrew Lunn int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 22656995cbcSAndrew Lunn u16 etype); 227ea698f4fSVivien Didelot int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 228ea698f4fSVivien Didelot bool message_port); 229cd782656SVivien Didelot int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 230cd782656SVivien Didelot size_t size); 231ef70b111SAndrew Lunn int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 232ef70b111SAndrew Lunn int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 2330898432cSVivien Didelot int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 2340898432cSVivien Didelot u8 out); 2350898432cSVivien Didelot int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 2360898432cSVivien Didelot u8 out); 237f39908d3SAndrew Lunn int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 238f39908d3SAndrew Lunn phy_interface_t mode); 239f39908d3SAndrew Lunn int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 240a23b2961SAndrew Lunn int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port); 241a23b2961SAndrew Lunn int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 242a23b2961SAndrew Lunn int upstream_port); 243c8c94891SVivien Didelot 244c8c94891SVivien Didelot int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 2459dbfb4e1SVivien Didelot int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 246c8c94891SVivien Didelot 24718abed21SVivien Didelot #endif /* _MV88E6XXX_PORT_H */ 248