118abed21SVivien Didelot /* 218abed21SVivien Didelot * Marvell 88E6xxx Switch Port Registers support 318abed21SVivien Didelot * 418abed21SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 518abed21SVivien Didelot * 618abed21SVivien Didelot * Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com> 718abed21SVivien Didelot * 818abed21SVivien Didelot * This program is free software; you can redistribute it and/or modify 918abed21SVivien Didelot * it under the terms of the GNU General Public License as published by 1018abed21SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 1118abed21SVivien Didelot * (at your option) any later version. 1218abed21SVivien Didelot */ 1318abed21SVivien Didelot 1418abed21SVivien Didelot #ifndef _MV88E6XXX_PORT_H 1518abed21SVivien Didelot #define _MV88E6XXX_PORT_H 1618abed21SVivien Didelot 1718abed21SVivien Didelot #include "mv88e6xxx.h" 1818abed21SVivien Didelot 1918abed21SVivien Didelot int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 2018abed21SVivien Didelot u16 *val); 2118abed21SVivien Didelot int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 2218abed21SVivien Didelot u16 val); 2318abed21SVivien Didelot 24a0a0f622SVivien Didelot int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 25a0a0f622SVivien Didelot phy_interface_t mode); 26a0a0f622SVivien Didelot int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 27a0a0f622SVivien Didelot phy_interface_t mode); 28a0a0f622SVivien Didelot 2908ef7f10SVivien Didelot int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 3008ef7f10SVivien Didelot 317f1ae07bSVivien Didelot int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup); 327f1ae07bSVivien Didelot 3396a2b40cSVivien Didelot int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 3496a2b40cSVivien Didelot int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 3596a2b40cSVivien Didelot int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 3696a2b40cSVivien Didelot int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 3796a2b40cSVivien Didelot int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 3896a2b40cSVivien Didelot 39e28def33SVivien Didelot int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 40e28def33SVivien Didelot 415a7921f4SVivien Didelot int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 425a7921f4SVivien Didelot 43b4e48c50SVivien Didelot int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 44b4e48c50SVivien Didelot int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 45b4e48c50SVivien Didelot 4677064f37SVivien Didelot int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 4777064f37SVivien Didelot int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 4877064f37SVivien Didelot 49385a0995SVivien Didelot int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 50385a0995SVivien Didelot u16 mode); 51ef0a7318SAndrew Lunn int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 52ef0a7318SAndrew Lunn int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 5356995cbcSAndrew Lunn int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 5456995cbcSAndrew Lunn u16 mode); 5556995cbcSAndrew Lunn int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 5656995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 5756995cbcSAndrew Lunn int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 5856995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 59601aeed3SVivien Didelot int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 60601aeed3SVivien Didelot bool unicast, bool multicast); 61601aeed3SVivien Didelot int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 62601aeed3SVivien Didelot bool unicast, bool multicast); 6356995cbcSAndrew Lunn int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 6456995cbcSAndrew Lunn u16 etype); 65ea698f4fSVivien Didelot int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 66ea698f4fSVivien Didelot bool message_port); 675f436666SAndrew Lunn int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port); 68ef70b111SAndrew Lunn int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 69ef70b111SAndrew Lunn int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 70b35d322aSAndrew Lunn int mv88e6097_port_pause_config(struct mv88e6xxx_chip *chip, int port); 713ce0e65eSAndrew Lunn int mv88e6390_port_pause_config(struct mv88e6xxx_chip *chip, int port); 72f39908d3SAndrew Lunn int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 73f39908d3SAndrew Lunn phy_interface_t mode); 74f39908d3SAndrew Lunn int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 75a23b2961SAndrew Lunn int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port); 76a23b2961SAndrew Lunn int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 77a23b2961SAndrew Lunn int upstream_port); 78c8c94891SVivien Didelot 79c8c94891SVivien Didelot int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 80c8c94891SVivien Didelot 8118abed21SVivien Didelot #endif /* _MV88E6XXX_PORT_H */ 82