118abed21SVivien Didelot /* 218abed21SVivien Didelot * Marvell 88E6xxx Switch Port Registers support 318abed21SVivien Didelot * 418abed21SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 518abed21SVivien Didelot * 64333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 74333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 818abed21SVivien Didelot * 918abed21SVivien Didelot * This program is free software; you can redistribute it and/or modify 1018abed21SVivien Didelot * it under the terms of the GNU General Public License as published by 1118abed21SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 1218abed21SVivien Didelot * (at your option) any later version. 1318abed21SVivien Didelot */ 1418abed21SVivien Didelot 1518abed21SVivien Didelot #ifndef _MV88E6XXX_PORT_H 1618abed21SVivien Didelot #define _MV88E6XXX_PORT_H 1718abed21SVivien Didelot 184d5f2ba7SVivien Didelot #include "chip.h" 1918abed21SVivien Didelot 205f83dc93SVivien Didelot /* Offset 0x00: Port Status Register */ 215f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS 0x00 225f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 235f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000 245f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 255f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000 265f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_LINK 0x0800 275f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_DUPLEX 0x0400 285f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 295f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_10 0x0000 305f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_100 0x0100 315f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_1000 0x0200 325f83dc93SVivien Didelot #define MV88E6352_PORT_STS_EEE 0x0040 335f83dc93SVivien Didelot #define MV88E6165_PORT_STS_AM_DIS 0x0040 345f83dc93SVivien Didelot #define MV88E6185_PORT_STS_MGMII 0x0040 355f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 365f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 375f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f 385f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_100BASE_X 0x0008 395f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_1000BASE_X 0x0009 405f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a 415f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b 425f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c 435f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d 445f83dc93SVivien Didelot 455ee55577SVivien Didelot /* Offset 0x01: MAC (or PCS or Physical) Control Register */ 465ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL 0x01 475ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 485ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 495ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 505ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 515ee55577SVivien Didelot #define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 525ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 535ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040 545ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020 555ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010 565ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008 575ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004 585ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003 595ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000 605ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001 615ee55577SVivien Didelot #define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002 625ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002 635ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003 645ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 655ee55577SVivien Didelot 666c96bbfdSVivien Didelot /* Offset 0x02: Jamming Control Register */ 676c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL 0x02 686c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00 696c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff 706c96bbfdSVivien Didelot 716c96bbfdSVivien Didelot /* Offset 0x02: Flow Control Register */ 726c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL 0x02 736c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000 746c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00 756c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000 766c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100 776c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff 786c96bbfdSVivien Didelot 79107fcc10SVivien Didelot /* Offset 0x03: Switch Identifier Register */ 80107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID 0x03 81107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0 82107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0 83107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950 84107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990 85107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00 86107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10 87107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060 88107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150 89107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210 90107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610 91107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650 92107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710 93107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720 94107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750 95107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760 96107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900 97107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910 98107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70 99107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400 100107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900 101107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100 102107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400 103107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410 104107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520 105107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710 106107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750 107107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900 108107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f 109107fcc10SVivien Didelot 110a89b433bSVivien Didelot /* Offset 0x04: Port Control Register */ 111a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0 0x04 112a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000 113a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK 0x4000 114a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000 115a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000 116a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000 117a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000 118a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000 119a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_HEADER 0x0800 120a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400 121a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200 122a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300 123a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000 124a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100 125a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200 126a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300 127a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100 128a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080 129a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040 130a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_USE_IP 0x0020 131a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_USE_TAG 0x0010 132a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004 133a89b433bSVivien Didelot #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK 0x000c 134a89b433bSVivien Didelot #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA 0x0000 135a89b433bSVivien Didelot #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA 0x0004 136a89b433bSVivien Didelot #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA 0x0008 137a89b433bSVivien Didelot #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA 0x000c 138a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003 139a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000 140a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001 141a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002 142a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003 143a89b433bSVivien Didelot 144cd985bbfSVivien Didelot /* Offset 0x05: Port Control 1 */ 145cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1 0x05 146cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000 147cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff 148cd985bbfSVivien Didelot 1497e5cc5f1SVivien Didelot /* Offset 0x06: Port Based VLAN Map */ 1507e5cc5f1SVivien Didelot #define MV88E6XXX_PORT_BASE_VLAN 0x06 1517e5cc5f1SVivien Didelot #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000 1527e5cc5f1SVivien Didelot 153b7929fb3SVivien Didelot /* Offset 0x07: Default Port VLAN ID & Priority */ 154b7929fb3SVivien Didelot #define MV88E6XXX_PORT_DEFAULT_VLAN 0x07 155b7929fb3SVivien Didelot #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff 156b7929fb3SVivien Didelot 157d2a160b5SVivien Didelot #define PORT_CONTROL_2 0x08 158d2a160b5SVivien Didelot #define PORT_CONTROL_2_IGNORE_FCS BIT(15) 159d2a160b5SVivien Didelot #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) 160d2a160b5SVivien Didelot #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) 161d2a160b5SVivien Didelot #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) 162cd782656SVivien Didelot #define PORT_CONTROL_2_JUMBO_MASK (0x03 << 12) 163d2a160b5SVivien Didelot #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) 164d2a160b5SVivien Didelot #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) 165d2a160b5SVivien Didelot #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) 166d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) 167d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) 168d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) 169d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) 170d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) 171d2a160b5SVivien Didelot #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) 172d2a160b5SVivien Didelot #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) 173d2a160b5SVivien Didelot #define PORT_CONTROL_2_MAP_DA BIT(7) 174d2a160b5SVivien Didelot #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) 175d2a160b5SVivien Didelot #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) 176d2a160b5SVivien Didelot #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) 177d2a160b5SVivien Didelot #define PORT_CONTROL_2_UPSTREAM_MASK 0x0f 178d2a160b5SVivien Didelot #define PORT_RATE_CONTROL 0x09 179d2a160b5SVivien Didelot #define PORT_RATE_CONTROL_2 0x0a 180d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR 0x0b 181d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) 182d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) 183d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) 184d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) 185d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) 186d2a160b5SVivien Didelot #define PORT_ATU_CONTROL 0x0c 187d2a160b5SVivien Didelot #define PORT_PRI_OVERRIDE 0x0d 188d2a160b5SVivien Didelot #define PORT_ETH_TYPE 0x0f 189d2a160b5SVivien Didelot #define PORT_ETH_TYPE_DEFAULT 0x9100 190d2a160b5SVivien Didelot #define PORT_IN_DISCARD_LO 0x10 191d2a160b5SVivien Didelot #define PORT_IN_DISCARD_HI 0x11 192d2a160b5SVivien Didelot #define PORT_IN_FILTERED 0x12 193d2a160b5SVivien Didelot #define PORT_OUT_FILTERED 0x13 194d2a160b5SVivien Didelot #define PORT_TAG_REGMAP_0123 0x18 195d2a160b5SVivien Didelot #define PORT_TAG_REGMAP_4567 0x19 196d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE 0x18 /* 6390 */ 197d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_UPDATE BIT(15) 198d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP (0x0 << 12) 199d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP (0x1 << 12) 200d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP (0x2 << 12) 201d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP (0x3 << 12) 202d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP (0x5 << 12) 203d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP (0x6 << 12) 204d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP (0x7 << 12) 205d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT 9 206d2a160b5SVivien Didelot 20718abed21SVivien Didelot int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 20818abed21SVivien Didelot u16 *val); 20918abed21SVivien Didelot int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 21018abed21SVivien Didelot u16 val); 21118abed21SVivien Didelot 212a0a0f622SVivien Didelot int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 213a0a0f622SVivien Didelot phy_interface_t mode); 214a0a0f622SVivien Didelot int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 215a0a0f622SVivien Didelot phy_interface_t mode); 216a0a0f622SVivien Didelot 21708ef7f10SVivien Didelot int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 21808ef7f10SVivien Didelot 2197f1ae07bSVivien Didelot int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup); 2207f1ae07bSVivien Didelot 22196a2b40cSVivien Didelot int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 22296a2b40cSVivien Didelot int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 22396a2b40cSVivien Didelot int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 22496a2b40cSVivien Didelot int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 22596a2b40cSVivien Didelot int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 22696a2b40cSVivien Didelot 227e28def33SVivien Didelot int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 228e28def33SVivien Didelot 2295a7921f4SVivien Didelot int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 2305a7921f4SVivien Didelot 231b4e48c50SVivien Didelot int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 232b4e48c50SVivien Didelot int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 233b4e48c50SVivien Didelot 23477064f37SVivien Didelot int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 23577064f37SVivien Didelot int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 23677064f37SVivien Didelot 237385a0995SVivien Didelot int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 238385a0995SVivien Didelot u16 mode); 239ef0a7318SAndrew Lunn int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 240ef0a7318SAndrew Lunn int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 24156995cbcSAndrew Lunn int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 24231bef4e9SVivien Didelot enum mv88e6xxx_egress_mode mode); 24356995cbcSAndrew Lunn int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 24456995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 24556995cbcSAndrew Lunn int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 24656995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 247601aeed3SVivien Didelot int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 248601aeed3SVivien Didelot bool unicast, bool multicast); 249601aeed3SVivien Didelot int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 250601aeed3SVivien Didelot bool unicast, bool multicast); 25156995cbcSAndrew Lunn int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 25256995cbcSAndrew Lunn u16 etype); 253ea698f4fSVivien Didelot int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 254ea698f4fSVivien Didelot bool message_port); 255cd782656SVivien Didelot int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 256cd782656SVivien Didelot size_t size); 257ef70b111SAndrew Lunn int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 258ef70b111SAndrew Lunn int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 2590898432cSVivien Didelot int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 2600898432cSVivien Didelot u8 out); 2610898432cSVivien Didelot int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 2620898432cSVivien Didelot u8 out); 263f39908d3SAndrew Lunn int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 264f39908d3SAndrew Lunn phy_interface_t mode); 265f39908d3SAndrew Lunn int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 266a23b2961SAndrew Lunn int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port); 267a23b2961SAndrew Lunn int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 268a23b2961SAndrew Lunn int upstream_port); 269c8c94891SVivien Didelot 270c8c94891SVivien Didelot int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 2719dbfb4e1SVivien Didelot int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 272c8c94891SVivien Didelot 27318abed21SVivien Didelot #endif /* _MV88E6XXX_PORT_H */ 274