118abed21SVivien Didelot /* 218abed21SVivien Didelot * Marvell 88E6xxx Switch Port Registers support 318abed21SVivien Didelot * 418abed21SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 518abed21SVivien Didelot * 64333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 74333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 818abed21SVivien Didelot * 918abed21SVivien Didelot * This program is free software; you can redistribute it and/or modify 1018abed21SVivien Didelot * it under the terms of the GNU General Public License as published by 1118abed21SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 1218abed21SVivien Didelot * (at your option) any later version. 1318abed21SVivien Didelot */ 1418abed21SVivien Didelot 1518abed21SVivien Didelot #ifndef _MV88E6XXX_PORT_H 1618abed21SVivien Didelot #define _MV88E6XXX_PORT_H 1718abed21SVivien Didelot 184d5f2ba7SVivien Didelot #include "chip.h" 1918abed21SVivien Didelot 205f83dc93SVivien Didelot /* Offset 0x00: Port Status Register */ 215f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS 0x00 225f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 235f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000 245f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 255f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000 265f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_LINK 0x0800 275f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_DUPLEX 0x0400 285f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 295f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_10 0x0000 305f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_100 0x0100 315f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_1000 0x0200 325f83dc93SVivien Didelot #define MV88E6352_PORT_STS_EEE 0x0040 335f83dc93SVivien Didelot #define MV88E6165_PORT_STS_AM_DIS 0x0040 345f83dc93SVivien Didelot #define MV88E6185_PORT_STS_MGMII 0x0040 355f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 365f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 375f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f 385f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_100BASE_X 0x0008 395f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_1000BASE_X 0x0009 405f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a 415f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b 425f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c 435f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d 445f83dc93SVivien Didelot 455ee55577SVivien Didelot /* Offset 0x01: MAC (or PCS or Physical) Control Register */ 465ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL 0x01 475ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 485ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 495ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 505ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 515ee55577SVivien Didelot #define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 525ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 535ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040 545ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020 555ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010 565ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008 575ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004 585ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003 595ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000 605ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001 615ee55577SVivien Didelot #define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002 625ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002 635ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003 645ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 655ee55577SVivien Didelot 666c96bbfdSVivien Didelot /* Offset 0x02: Jamming Control Register */ 676c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL 0x02 686c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00 696c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff 706c96bbfdSVivien Didelot 716c96bbfdSVivien Didelot /* Offset 0x02: Flow Control Register */ 726c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL 0x02 736c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000 746c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00 756c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000 766c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100 776c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff 786c96bbfdSVivien Didelot 79d2a160b5SVivien Didelot #define PORT_SWITCH_ID 0x03 80d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6085 0x04a 81d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6095 0x095 82d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6097 0x099 83d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6131 0x106 84d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6320 0x115 85d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6123 0x121 86d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6141 0x340 87d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6161 0x161 88d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6165 0x165 89d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6171 0x171 90d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6172 0x172 91d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6175 0x175 92d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6176 0x176 93d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7 94d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6190 0x190 95d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6190X 0x0a0 96d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6191 0x191 97d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6240 0x240 98d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6290 0x290 99d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6321 0x310 100d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6341 0x341 101d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6352 0x352 102d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6350 0x371 103d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6351 0x375 104d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6390 0x390 105d2a160b5SVivien Didelot #define PORT_SWITCH_ID_PROD_NUM_6390X 0x0a1 106d2a160b5SVivien Didelot #define PORT_CONTROL 0x04 107d2a160b5SVivien Didelot #define PORT_CONTROL_USE_CORE_TAG BIT(15) 108d2a160b5SVivien Didelot #define PORT_CONTROL_DROP_ON_LOCK BIT(14) 109d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12) 110d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12) 111d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12) 112d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12) 113d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_MASK (0x3 << 12) 114d2a160b5SVivien Didelot #define PORT_CONTROL_HEADER BIT(11) 115d2a160b5SVivien Didelot #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10) 116d2a160b5SVivien Didelot #define PORT_CONTROL_DOUBLE_TAG BIT(9) 117d2a160b5SVivien Didelot #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8) 118d2a160b5SVivien Didelot #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8) 119d2a160b5SVivien Didelot #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8) 120d2a160b5SVivien Didelot #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8) 121d2a160b5SVivien Didelot #define PORT_CONTROL_FRAME_MASK (0x3 << 8) 122d2a160b5SVivien Didelot #define PORT_CONTROL_DSA_TAG BIT(8) 123d2a160b5SVivien Didelot #define PORT_CONTROL_VLAN_TUNNEL BIT(7) 124d2a160b5SVivien Didelot #define PORT_CONTROL_TAG_IF_BOTH BIT(6) 125d2a160b5SVivien Didelot #define PORT_CONTROL_USE_IP BIT(5) 126d2a160b5SVivien Didelot #define PORT_CONTROL_USE_TAG BIT(4) 127d2a160b5SVivien Didelot #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2) 128d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_FLOODS_MASK (0x3 << 2) 129d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_DA (0x0 << 2) 130d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_MC_DA (0x1 << 2) 131d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_UC_DA (0x2 << 2) 132d2a160b5SVivien Didelot #define PORT_CONTROL_EGRESS_FLOODS_ALL_UNKNOWN_DA (0x3 << 2) 133d2a160b5SVivien Didelot #define PORT_CONTROL_STATE_MASK 0x03 134d2a160b5SVivien Didelot #define PORT_CONTROL_STATE_DISABLED 0x00 135d2a160b5SVivien Didelot #define PORT_CONTROL_STATE_BLOCKING 0x01 136d2a160b5SVivien Didelot #define PORT_CONTROL_STATE_LEARNING 0x02 137d2a160b5SVivien Didelot #define PORT_CONTROL_STATE_FORWARDING 0x03 138d2a160b5SVivien Didelot #define PORT_CONTROL_1 0x05 139d2a160b5SVivien Didelot #define PORT_CONTROL_1_MESSAGE_PORT BIT(15) 140d2a160b5SVivien Didelot #define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0) 141d2a160b5SVivien Didelot #define PORT_BASE_VLAN 0x06 142d2a160b5SVivien Didelot #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12) 143d2a160b5SVivien Didelot #define PORT_DEFAULT_VLAN 0x07 144d2a160b5SVivien Didelot #define PORT_DEFAULT_VLAN_MASK 0xfff 145d2a160b5SVivien Didelot #define PORT_CONTROL_2 0x08 146d2a160b5SVivien Didelot #define PORT_CONTROL_2_IGNORE_FCS BIT(15) 147d2a160b5SVivien Didelot #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) 148d2a160b5SVivien Didelot #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) 149d2a160b5SVivien Didelot #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) 150cd782656SVivien Didelot #define PORT_CONTROL_2_JUMBO_MASK (0x03 << 12) 151d2a160b5SVivien Didelot #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) 152d2a160b5SVivien Didelot #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) 153d2a160b5SVivien Didelot #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) 154d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) 155d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) 156d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) 157d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) 158d2a160b5SVivien Didelot #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) 159d2a160b5SVivien Didelot #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) 160d2a160b5SVivien Didelot #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) 161d2a160b5SVivien Didelot #define PORT_CONTROL_2_MAP_DA BIT(7) 162d2a160b5SVivien Didelot #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) 163d2a160b5SVivien Didelot #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) 164d2a160b5SVivien Didelot #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) 165d2a160b5SVivien Didelot #define PORT_CONTROL_2_UPSTREAM_MASK 0x0f 166d2a160b5SVivien Didelot #define PORT_RATE_CONTROL 0x09 167d2a160b5SVivien Didelot #define PORT_RATE_CONTROL_2 0x0a 168d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR 0x0b 169d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) 170d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) 171d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) 172d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) 173d2a160b5SVivien Didelot #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) 174d2a160b5SVivien Didelot #define PORT_ATU_CONTROL 0x0c 175d2a160b5SVivien Didelot #define PORT_PRI_OVERRIDE 0x0d 176d2a160b5SVivien Didelot #define PORT_ETH_TYPE 0x0f 177d2a160b5SVivien Didelot #define PORT_ETH_TYPE_DEFAULT 0x9100 178d2a160b5SVivien Didelot #define PORT_IN_DISCARD_LO 0x10 179d2a160b5SVivien Didelot #define PORT_IN_DISCARD_HI 0x11 180d2a160b5SVivien Didelot #define PORT_IN_FILTERED 0x12 181d2a160b5SVivien Didelot #define PORT_OUT_FILTERED 0x13 182d2a160b5SVivien Didelot #define PORT_TAG_REGMAP_0123 0x18 183d2a160b5SVivien Didelot #define PORT_TAG_REGMAP_4567 0x19 184d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE 0x18 /* 6390 */ 185d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_UPDATE BIT(15) 186d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP (0x0 << 12) 187d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP (0x1 << 12) 188d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP (0x2 << 12) 189d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP (0x3 << 12) 190d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP (0x5 << 12) 191d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP (0x6 << 12) 192d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP (0x7 << 12) 193d2a160b5SVivien Didelot #define PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT 9 194d2a160b5SVivien Didelot 19518abed21SVivien Didelot int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 19618abed21SVivien Didelot u16 *val); 19718abed21SVivien Didelot int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 19818abed21SVivien Didelot u16 val); 19918abed21SVivien Didelot 200a0a0f622SVivien Didelot int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 201a0a0f622SVivien Didelot phy_interface_t mode); 202a0a0f622SVivien Didelot int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 203a0a0f622SVivien Didelot phy_interface_t mode); 204a0a0f622SVivien Didelot 20508ef7f10SVivien Didelot int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 20608ef7f10SVivien Didelot 2077f1ae07bSVivien Didelot int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup); 2087f1ae07bSVivien Didelot 20996a2b40cSVivien Didelot int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 21096a2b40cSVivien Didelot int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 21196a2b40cSVivien Didelot int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 21296a2b40cSVivien Didelot int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 21396a2b40cSVivien Didelot int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 21496a2b40cSVivien Didelot 215e28def33SVivien Didelot int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 216e28def33SVivien Didelot 2175a7921f4SVivien Didelot int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 2185a7921f4SVivien Didelot 219b4e48c50SVivien Didelot int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 220b4e48c50SVivien Didelot int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 221b4e48c50SVivien Didelot 22277064f37SVivien Didelot int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 22377064f37SVivien Didelot int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 22477064f37SVivien Didelot 225385a0995SVivien Didelot int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 226385a0995SVivien Didelot u16 mode); 227ef0a7318SAndrew Lunn int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 228ef0a7318SAndrew Lunn int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 22956995cbcSAndrew Lunn int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 23031bef4e9SVivien Didelot enum mv88e6xxx_egress_mode mode); 23156995cbcSAndrew Lunn int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 23256995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 23356995cbcSAndrew Lunn int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 23456995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 235601aeed3SVivien Didelot int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 236601aeed3SVivien Didelot bool unicast, bool multicast); 237601aeed3SVivien Didelot int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 238601aeed3SVivien Didelot bool unicast, bool multicast); 23956995cbcSAndrew Lunn int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 24056995cbcSAndrew Lunn u16 etype); 241ea698f4fSVivien Didelot int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 242ea698f4fSVivien Didelot bool message_port); 243cd782656SVivien Didelot int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 244cd782656SVivien Didelot size_t size); 245ef70b111SAndrew Lunn int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 246ef70b111SAndrew Lunn int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 2470898432cSVivien Didelot int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 2480898432cSVivien Didelot u8 out); 2490898432cSVivien Didelot int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 2500898432cSVivien Didelot u8 out); 251f39908d3SAndrew Lunn int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 252f39908d3SAndrew Lunn phy_interface_t mode); 253f39908d3SAndrew Lunn int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 254a23b2961SAndrew Lunn int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port); 255a23b2961SAndrew Lunn int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 256a23b2961SAndrew Lunn int upstream_port); 257c8c94891SVivien Didelot 258c8c94891SVivien Didelot int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 2599dbfb4e1SVivien Didelot int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 260c8c94891SVivien Didelot 26118abed21SVivien Didelot #endif /* _MV88E6XXX_PORT_H */ 262