118abed21SVivien Didelot /* 218abed21SVivien Didelot * Marvell 88E6xxx Switch Port Registers support 318abed21SVivien Didelot * 418abed21SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 518abed21SVivien Didelot * 64333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 74333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 818abed21SVivien Didelot * 918abed21SVivien Didelot * This program is free software; you can redistribute it and/or modify 1018abed21SVivien Didelot * it under the terms of the GNU General Public License as published by 1118abed21SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 1218abed21SVivien Didelot * (at your option) any later version. 1318abed21SVivien Didelot */ 1418abed21SVivien Didelot 1518abed21SVivien Didelot #ifndef _MV88E6XXX_PORT_H 1618abed21SVivien Didelot #define _MV88E6XXX_PORT_H 1718abed21SVivien Didelot 184d5f2ba7SVivien Didelot #include "chip.h" 1918abed21SVivien Didelot 205f83dc93SVivien Didelot /* Offset 0x00: Port Status Register */ 215f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS 0x00 225f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 235f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000 245f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 255f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000 265f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_LINK 0x0800 275f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_DUPLEX 0x0400 285f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 295f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_10 0x0000 305f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_100 0x0100 315f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_1000 0x0200 32c9a2356fSRussell King #define MV88E6XXX_PORT_STS_SPEED_10000 0x0300 335f83dc93SVivien Didelot #define MV88E6352_PORT_STS_EEE 0x0040 345f83dc93SVivien Didelot #define MV88E6165_PORT_STS_AM_DIS 0x0040 355f83dc93SVivien Didelot #define MV88E6185_PORT_STS_MGMII 0x0040 365f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 375f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 385f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f 395f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_100BASE_X 0x0008 405f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_1000BASE_X 0x0009 415f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a 425f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b 435f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c 445f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d 455f83dc93SVivien Didelot 465ee55577SVivien Didelot /* Offset 0x01: MAC (or PCS or Physical) Control Register */ 475ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL 0x01 485ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 495ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 505ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 515ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 525ee55577SVivien Didelot #define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 535ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 545ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040 555ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020 565ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010 575ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008 585ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004 595ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003 605ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000 615ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001 625ee55577SVivien Didelot #define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002 635ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002 645ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003 655ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 665ee55577SVivien Didelot 676c96bbfdSVivien Didelot /* Offset 0x02: Jamming Control Register */ 686c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL 0x02 696c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00 706c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff 716c96bbfdSVivien Didelot 726c96bbfdSVivien Didelot /* Offset 0x02: Flow Control Register */ 736c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL 0x02 746c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000 756c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00 766c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000 776c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100 786c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff 796c96bbfdSVivien Didelot 80107fcc10SVivien Didelot /* Offset 0x03: Switch Identifier Register */ 81107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID 0x03 82107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0 83107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0 84107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950 85107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990 86107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00 87107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10 88107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060 89107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150 90107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210 91107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610 92107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650 93107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710 94107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720 95107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750 96107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760 97107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900 98107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910 99107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70 100107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400 101107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900 102107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100 103107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400 104107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410 105107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520 106107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710 107107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750 108107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900 109107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f 110107fcc10SVivien Didelot 111a89b433bSVivien Didelot /* Offset 0x04: Port Control Register */ 112a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0 0x04 113a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000 114a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK 0x4000 115a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000 116a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000 117a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000 118a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000 119a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000 120a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_HEADER 0x0800 121a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400 122a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200 123a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300 124a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000 125a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100 126a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200 127a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300 128a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100 129a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080 130a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040 131a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_USE_IP 0x0020 132a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_USE_TAG 0x0010 133a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004 134a89b433bSVivien Didelot #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK 0x000c 135a89b433bSVivien Didelot #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA 0x0000 136a89b433bSVivien Didelot #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA 0x0004 137a89b433bSVivien Didelot #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA 0x0008 138a89b433bSVivien Didelot #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA 0x000c 139a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003 140a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000 141a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001 142a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002 143a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003 144a89b433bSVivien Didelot 145cd985bbfSVivien Didelot /* Offset 0x05: Port Control 1 */ 146cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1 0x05 147cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000 148cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff 149cd985bbfSVivien Didelot 1507e5cc5f1SVivien Didelot /* Offset 0x06: Port Based VLAN Map */ 1517e5cc5f1SVivien Didelot #define MV88E6XXX_PORT_BASE_VLAN 0x06 1527e5cc5f1SVivien Didelot #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000 1537e5cc5f1SVivien Didelot 154b7929fb3SVivien Didelot /* Offset 0x07: Default Port VLAN ID & Priority */ 155b7929fb3SVivien Didelot #define MV88E6XXX_PORT_DEFAULT_VLAN 0x07 156b7929fb3SVivien Didelot #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff 157b7929fb3SVivien Didelot 15881c6edb2SVivien Didelot /* Offset 0x08: Port Control 2 Register */ 15981c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2 0x08 16081c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000 16181c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000 16281c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000 16381c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000 16481c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000 16581c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000 16681c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000 16781c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000 16881c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00 16981c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000 17081c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400 17181c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800 17281c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00 17381c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200 17481c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100 17581c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080 17681c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040 17781c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020 17881c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010 17981c6edb2SVivien Didelot #define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f 18081c6edb2SVivien Didelot 1812cb8cb14SVivien Didelot /* Offset 0x09: Egress Rate Control */ 1822cb8cb14SVivien Didelot #define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09 1832cb8cb14SVivien Didelot 1842cb8cb14SVivien Didelot /* Offset 0x0A: Egress Rate Control 2 */ 1852cb8cb14SVivien Didelot #define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a 1862cb8cb14SVivien Didelot 1872a4614e4SVivien Didelot /* Offset 0x0B: Port Association Vector */ 1882a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b 1892a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000 1902a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000 1912a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000 1922a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000 1932a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800 1942a4614e4SVivien Didelot 195b8109594SVivien Didelot /* Offset 0x0C: Port ATU Control */ 196b8109594SVivien Didelot #define MV88E6XXX_PORT_ATU_CTL 0x0c 197b8109594SVivien Didelot 198b8109594SVivien Didelot /* Offset 0x0D: Priority Override Register */ 199b8109594SVivien Didelot #define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d 200b8109594SVivien Didelot 201b8109594SVivien Didelot /* Offset 0x0E: Policy Control Register */ 202b8109594SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL 0x0e 203b8109594SVivien Didelot 204b8109594SVivien Didelot /* Offset 0x0F: Port Special Ether Type */ 205b8109594SVivien Didelot #define MV88E6XXX_PORT_ETH_TYPE 0x0f 206b8109594SVivien Didelot #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100 207b8109594SVivien Didelot 208b8109594SVivien Didelot /* Offset 0x10: InDiscards Low Counter */ 209b8109594SVivien Didelot #define MV88E6XXX_PORT_IN_DISCARD_LO 0x10 210b8109594SVivien Didelot 211b8109594SVivien Didelot /* Offset 0x11: InDiscards High Counter */ 212b8109594SVivien Didelot #define MV88E6XXX_PORT_IN_DISCARD_HI 0x11 213b8109594SVivien Didelot 214b8109594SVivien Didelot /* Offset 0x12: InFiltered Counter */ 215b8109594SVivien Didelot #define MV88E6XXX_PORT_IN_FILTERED 0x12 216b8109594SVivien Didelot 217b8109594SVivien Didelot /* Offset 0x13: OutFiltered Counter */ 218b8109594SVivien Didelot #define MV88E6XXX_PORT_OUT_FILTERED 0x13 219b8109594SVivien Didelot 2208009df9eSVivien Didelot /* Offset 0x18: IEEE Priority Mapping Table */ 2218009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18 2228009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000 223ddcbabf4SVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000 2248009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000 2258009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000 2268009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000 2278009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000 2288009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000 2298009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000 2308009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000 231ddcbabf4SVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00 232ddcbabf4SVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff 2338009df9eSVivien Didelot 2348009df9eSVivien Didelot /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */ 2358009df9eSVivien Didelot #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18 2368009df9eSVivien Didelot 2378009df9eSVivien Didelot /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */ 2388009df9eSVivien Didelot #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19 239d2a160b5SVivien Didelot 24018abed21SVivien Didelot int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 24118abed21SVivien Didelot u16 *val); 24218abed21SVivien Didelot int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 24318abed21SVivien Didelot u16 val); 24418abed21SVivien Didelot 24554186b91SAndrew Lunn int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 24654186b91SAndrew Lunn int pause); 247a0a0f622SVivien Didelot int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 248a0a0f622SVivien Didelot phy_interface_t mode); 249a0a0f622SVivien Didelot int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 250a0a0f622SVivien Didelot phy_interface_t mode); 251a0a0f622SVivien Didelot 25208ef7f10SVivien Didelot int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 25308ef7f10SVivien Didelot 2547f1ae07bSVivien Didelot int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup); 2557f1ae07bSVivien Didelot 25696a2b40cSVivien Didelot int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 25796a2b40cSVivien Didelot int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 25896a2b40cSVivien Didelot int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 25996a2b40cSVivien Didelot int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 26096a2b40cSVivien Didelot int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed); 26196a2b40cSVivien Didelot 262e28def33SVivien Didelot int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 263e28def33SVivien Didelot 2645a7921f4SVivien Didelot int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 2655a7921f4SVivien Didelot 266b4e48c50SVivien Didelot int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 267b4e48c50SVivien Didelot int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 268b4e48c50SVivien Didelot 26977064f37SVivien Didelot int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 27077064f37SVivien Didelot int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 27177064f37SVivien Didelot 272385a0995SVivien Didelot int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 273385a0995SVivien Didelot u16 mode); 274ef0a7318SAndrew Lunn int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 275ef0a7318SAndrew Lunn int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 27656995cbcSAndrew Lunn int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 27731bef4e9SVivien Didelot enum mv88e6xxx_egress_mode mode); 27856995cbcSAndrew Lunn int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 27956995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 28056995cbcSAndrew Lunn int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 28156995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 282601aeed3SVivien Didelot int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 283601aeed3SVivien Didelot bool unicast, bool multicast); 284601aeed3SVivien Didelot int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 285601aeed3SVivien Didelot bool unicast, bool multicast); 28656995cbcSAndrew Lunn int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 28756995cbcSAndrew Lunn u16 etype); 288ea698f4fSVivien Didelot int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 289ea698f4fSVivien Didelot bool message_port); 290cd782656SVivien Didelot int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 291cd782656SVivien Didelot size_t size); 292ef70b111SAndrew Lunn int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 293ef70b111SAndrew Lunn int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 2940898432cSVivien Didelot int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 2950898432cSVivien Didelot u8 out); 2960898432cSVivien Didelot int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 2970898432cSVivien Didelot u8 out); 298f39908d3SAndrew Lunn int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 299f39908d3SAndrew Lunn phy_interface_t mode); 300f39908d3SAndrew Lunn int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 301c9a2356fSRussell King int mv88e6xxx_port_link_state(struct mv88e6xxx_chip *chip, int port, 302c9a2356fSRussell King struct phylink_link_state *state); 303a23b2961SAndrew Lunn int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port); 304a23b2961SAndrew Lunn int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 305a23b2961SAndrew Lunn int upstream_port); 306c8c94891SVivien Didelot 307c8c94891SVivien Didelot int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 3089dbfb4e1SVivien Didelot int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 309c8c94891SVivien Didelot 31018abed21SVivien Didelot #endif /* _MV88E6XXX_PORT_H */ 311