12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 218abed21SVivien Didelot /* 318abed21SVivien Didelot * Marvell 88E6xxx Switch Port Registers support 418abed21SVivien Didelot * 518abed21SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 618abed21SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 918abed21SVivien Didelot */ 1018abed21SVivien Didelot 1118abed21SVivien Didelot #ifndef _MV88E6XXX_PORT_H 1218abed21SVivien Didelot #define _MV88E6XXX_PORT_H 1318abed21SVivien Didelot 144d5f2ba7SVivien Didelot #include "chip.h" 1518abed21SVivien Didelot 165f83dc93SVivien Didelot /* Offset 0x00: Port Status Register */ 175f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS 0x00 185f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 195f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000 205f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 215f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000 22ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_LINK 0x1000 23ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00 24ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800 25ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900 26ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL 0x0a00 27ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL 0x0b00 28ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF 0x0c00 29ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF 0x0d00 30ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL 0x0e00 31ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL 0x0f00 325f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_LINK 0x0800 335f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_DUPLEX 0x0400 345f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 355f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_10 0x0000 365f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_100 0x0100 375f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_1000 0x0200 38c9a2356fSRussell King #define MV88E6XXX_PORT_STS_SPEED_10000 0x0300 395f83dc93SVivien Didelot #define MV88E6352_PORT_STS_EEE 0x0040 405f83dc93SVivien Didelot #define MV88E6165_PORT_STS_AM_DIS 0x0040 415f83dc93SVivien Didelot #define MV88E6185_PORT_STS_MGMII 0x0040 425f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 435f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 445f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f 45d4ebf12bSRussell King (Oracle) #define MV88E6XXX_PORT_STS_CMODE_MII_PHY 0x0001 46d4ebf12bSRussell King (Oracle) #define MV88E6XXX_PORT_STS_CMODE_MII 0x0002 47d4ebf12bSRussell King (Oracle) #define MV88E6XXX_PORT_STS_CMODE_GMII 0x0003 48d4ebf12bSRussell King (Oracle) #define MV88E6XXX_PORT_STS_CMODE_RMII_PHY 0x0004 49d4ebf12bSRussell King (Oracle) #define MV88E6XXX_PORT_STS_CMODE_RMII 0x0005 50927441adSMarek Behún #define MV88E6XXX_PORT_STS_CMODE_RGMII 0x0007 513bbb8867SMarek Behún #define MV88E6XXX_PORT_STS_CMODE_100BASEX 0x0008 523bbb8867SMarek Behún #define MV88E6XXX_PORT_STS_CMODE_1000BASEX 0x0009 535f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a 545f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b 555f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c 565f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d 57de776d0dSPavana Sharma #define MV88E6393X_PORT_STS_CMODE_5GBASER 0x000c 58de776d0dSPavana Sharma #define MV88E6393X_PORT_STS_CMODE_10GBASER 0x000d 59de776d0dSPavana Sharma #define MV88E6393X_PORT_STS_CMODE_USXGMII 0x000e 606c422e34SRussell King #define MV88E6185_PORT_STS_CDUPLEX 0x0008 616c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_MASK 0x0007 626c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000 636c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x0001 646c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_MII_100 0x0002 656c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_MII_10 0x0003 666c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_SERDES 0x0004 676c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005 686c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_PHY 0x0006 696c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_DISABLED 0x0007 705f83dc93SVivien Didelot 715ee55577SVivien Didelot /* Offset 0x01: MAC (or PCS or Physical) Control Register */ 725ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL 0x01 735ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 745ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 756c422e34SRussell King #define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x4000 765ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 775ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 785ee55577SVivien Didelot #define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 79de776d0dSPavana Sharma #define MV88E6XXX_PORT_MAC_CTL_EEE 0x0200 80de776d0dSPavana Sharma #define MV88E6XXX_PORT_MAC_CTL_FORCE_EEE 0x0100 816c422e34SRussell King #define MV88E6185_PORT_MAC_CTL_AN_EN 0x0400 826c422e34SRussell King #define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x0200 836c422e34SRussell King #define MV88E6185_PORT_MAC_CTL_AN_DONE 0x0100 845ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 855ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040 865ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020 875ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010 885ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008 895ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004 905ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003 915ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000 925ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001 935ee55577SVivien Didelot #define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002 945ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002 955ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003 965ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 975ee55577SVivien Didelot 986c96bbfdSVivien Didelot /* Offset 0x02: Jamming Control Register */ 996c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL 0x02 1006c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00 1016c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff 1026c96bbfdSVivien Didelot 1036c96bbfdSVivien Didelot /* Offset 0x02: Flow Control Register */ 1046c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL 0x02 1056c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000 1066c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00 1076c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000 1086c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100 1096c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff 1106c96bbfdSVivien Didelot 111107fcc10SVivien Didelot /* Offset 0x03: Switch Identifier Register */ 112107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID 0x03 113107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0 114107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0 115107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950 116107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990 117107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00 118107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10 119107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060 120107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150 121107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210 122107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610 123107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650 124107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710 125107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720 126107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750 127107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760 128107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900 129107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910 130de776d0dSPavana Sharma #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191X 0x1920 131de776d0dSPavana Sharma #define MV88E6XXX_PORT_SWITCH_ID_PROD_6193X 0x1930 132107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70 13349022647SHubert Feurstein #define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200 134107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400 1351f71836fSRasmus Villemoes #define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500 136*12899f29SAlexis Lothoré #define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 0x2610 137107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900 138107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100 139107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400 140107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410 141107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520 142107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710 143107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750 144107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900 145de776d0dSPavana Sharma #define MV88E6XXX_PORT_SWITCH_ID_PROD_6393X 0x3930 146107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f 147107fcc10SVivien Didelot 148a89b433bSVivien Didelot /* Offset 0x04: Port Control Register */ 149a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0 0x04 150a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000 15134ea415fSHans Schultz #define MV88E6XXX_PORT_CTL0_SA_FILT_MASK 0xc000 15234ea415fSHans Schultz #define MV88E6XXX_PORT_CTL0_SA_FILT_DISABLED 0x0000 15334ea415fSHans Schultz #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK 0x4000 15434ea415fSHans Schultz #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_UNLOCK 0x8000 15534ea415fSHans Schultz #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_CPU 0xc000 156a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000 157a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000 158a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000 159a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000 160a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000 161a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_HEADER 0x0800 162a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400 163a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200 164a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300 165a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000 166a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100 167a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200 168a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300 169a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100 170a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080 171a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040 172a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_USE_IP 0x0020 173a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_USE_TAG 0x0010 174a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004 175a8b659e7SVladimir Oltean #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC 0x0004 176a8b659e7SVladimir Oltean #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC 0x0008 177a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003 178a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000 179a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001 180a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002 181a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003 182a89b433bSVivien Didelot 183cd985bbfSVivien Didelot /* Offset 0x05: Port Control 1 */ 184cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1 0x05 185cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000 18657e661aaSTobias Waldekranz #define MV88E6XXX_PORT_CTL1_TRUNK_PORT 0x4000 18757e661aaSTobias Waldekranz #define MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK 0x0f00 18857e661aaSTobias Waldekranz #define MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT 8 189cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff 190cd985bbfSVivien Didelot 1917e5cc5f1SVivien Didelot /* Offset 0x06: Port Based VLAN Map */ 1927e5cc5f1SVivien Didelot #define MV88E6XXX_PORT_BASE_VLAN 0x06 1937e5cc5f1SVivien Didelot #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000 1947e5cc5f1SVivien Didelot 195b7929fb3SVivien Didelot /* Offset 0x07: Default Port VLAN ID & Priority */ 196b7929fb3SVivien Didelot #define MV88E6XXX_PORT_DEFAULT_VLAN 0x07 197b7929fb3SVivien Didelot #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff 198b7929fb3SVivien Didelot 19981c6edb2SVivien Didelot /* Offset 0x08: Port Control 2 Register */ 20081c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2 0x08 20181c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000 20281c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000 20381c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000 20481c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000 20581c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000 20681c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000 20781c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000 20881c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000 20981c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00 21081c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000 21181c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400 21281c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800 21381c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00 21481c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200 21581c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100 21681c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080 21781c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040 21881c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020 21981c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010 22081c6edb2SVivien Didelot #define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f 22181c6edb2SVivien Didelot 2222cb8cb14SVivien Didelot /* Offset 0x09: Egress Rate Control */ 2232cb8cb14SVivien Didelot #define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09 2242cb8cb14SVivien Didelot 2252cb8cb14SVivien Didelot /* Offset 0x0A: Egress Rate Control 2 */ 2262cb8cb14SVivien Didelot #define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a 2272cb8cb14SVivien Didelot 2282a4614e4SVivien Didelot /* Offset 0x0B: Port Association Vector */ 2292a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b 2302a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000 2312a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000 2322a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000 2332a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000 2342a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800 2352a4614e4SVivien Didelot 236b8109594SVivien Didelot /* Offset 0x0C: Port ATU Control */ 237b8109594SVivien Didelot #define MV88E6XXX_PORT_ATU_CTL 0x0c 238b8109594SVivien Didelot 239b8109594SVivien Didelot /* Offset 0x0D: Priority Override Register */ 240b8109594SVivien Didelot #define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d 241b8109594SVivien Didelot 242b8109594SVivien Didelot /* Offset 0x0E: Policy Control Register */ 243b8109594SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL 0x0e 244f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_DA_MASK 0xc000 245f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_SA_MASK 0x3000 246f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK 0x0c00 247f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK 0x0300 248f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK 0x00c0 249f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK 0x0030 250f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK 0x000c 251f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK 0x0003 252f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_NORMAL 0x0000 253f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_MIRROR 0x0001 254f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_TRAP 0x0002 255f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_DISCARD 0x0003 256b8109594SVivien Didelot 257de776d0dSPavana Sharma /* Offset 0x0E: Policy & MGMT Control Register (FAMILY_6393X) */ 258de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL 0x0e 259de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE 0x8000 260de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_MASK 0x3f00 261de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_DATA_MASK 0x00ff 262de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO 0x2000 263de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI 0x2100 264de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO 0x2400 265de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI 0x2500 266de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST 0x3000 267de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST 0x3800 268de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI 0x00e0 269de776d0dSPavana Sharma 270b8109594SVivien Didelot /* Offset 0x0F: Port Special Ether Type */ 271b8109594SVivien Didelot #define MV88E6XXX_PORT_ETH_TYPE 0x0f 272b8109594SVivien Didelot #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100 273b8109594SVivien Didelot 274b8109594SVivien Didelot /* Offset 0x10: InDiscards Low Counter */ 275b8109594SVivien Didelot #define MV88E6XXX_PORT_IN_DISCARD_LO 0x10 276b8109594SVivien Didelot 277de776d0dSPavana Sharma /* Offset 0x10: Extended Port Control Command */ 278de776d0dSPavana Sharma #define MV88E6393X_PORT_EPC_CMD 0x10 279de776d0dSPavana Sharma #define MV88E6393X_PORT_EPC_CMD_BUSY 0x8000 2801323e0c6SMarco Migliore #define MV88E6393X_PORT_EPC_CMD_WRITE 0x3000 281de776d0dSPavana Sharma #define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE 0x02 282de776d0dSPavana Sharma 283de776d0dSPavana Sharma /* Offset 0x11: Extended Port Control Data */ 284de776d0dSPavana Sharma #define MV88E6393X_PORT_EPC_DATA 0x11 285de776d0dSPavana Sharma 286b8109594SVivien Didelot /* Offset 0x11: InDiscards High Counter */ 287b8109594SVivien Didelot #define MV88E6XXX_PORT_IN_DISCARD_HI 0x11 288b8109594SVivien Didelot 289b8109594SVivien Didelot /* Offset 0x12: InFiltered Counter */ 290b8109594SVivien Didelot #define MV88E6XXX_PORT_IN_FILTERED 0x12 291b8109594SVivien Didelot 292b8109594SVivien Didelot /* Offset 0x13: OutFiltered Counter */ 293b8109594SVivien Didelot #define MV88E6XXX_PORT_OUT_FILTERED 0x13 294b8109594SVivien Didelot 2958009df9eSVivien Didelot /* Offset 0x18: IEEE Priority Mapping Table */ 2968009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18 2978009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000 298ddcbabf4SVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000 2998009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000 3008009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000 3018009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000 3028009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000 3038009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000 3048009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000 3058009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000 306ddcbabf4SVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00 307ddcbabf4SVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff 3088009df9eSVivien Didelot 3098009df9eSVivien Didelot /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */ 3108009df9eSVivien Didelot #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18 3118009df9eSVivien Didelot 3128009df9eSVivien Didelot /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */ 3138009df9eSVivien Didelot #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19 314d2a160b5SVivien Didelot 315ea89098eSAndrew Lunn /* Offset 0x1a: Magic undocumented errata register */ 31660907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A 0x1a 31760907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_BUSY 0x8000 31860907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_WRITE 0x4000 31960907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_READ 0x0000 32060907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT 5 32160907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT 10 32260907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT 0x04 32360907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT 0x05 3247a3007d2SMarek Behún #define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE 0x8000 3257a3007d2SMarek Behún #define MV88E6341_PORT_RESERVED_1A_SGMII_AN 0x2000 326ea89098eSAndrew Lunn 32718abed21SVivien Didelot int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 32818abed21SVivien Didelot u16 *val); 32918abed21SVivien Didelot int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 33018abed21SVivien Didelot u16 val); 331de776d0dSPavana Sharma int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, 332de776d0dSPavana Sharma int bit, int val); 33318abed21SVivien Didelot 33454186b91SAndrew Lunn int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 33554186b91SAndrew Lunn int pause); 33691e87045SSteffen Bätz int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 33791e87045SSteffen Bätz phy_interface_t mode); 338a0a0f622SVivien Didelot int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 339a0a0f622SVivien Didelot phy_interface_t mode); 340a0a0f622SVivien Didelot int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 341a0a0f622SVivien Didelot phy_interface_t mode); 342a0a0f622SVivien Didelot 34308ef7f10SVivien Didelot int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 34408ef7f10SVivien Didelot 3454efe7662SChris Packham int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 3464efe7662SChris Packham int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 3474efe7662SChris Packham 348f365c6f7SRussell King int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 349f365c6f7SRussell King int speed, int duplex); 350f365c6f7SRussell King int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 351f365c6f7SRussell King int speed, int duplex); 352f365c6f7SRussell King int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 353f365c6f7SRussell King int speed, int duplex); 354f365c6f7SRussell King int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 355f365c6f7SRussell King int speed, int duplex); 356f365c6f7SRussell King int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 357f365c6f7SRussell King int speed, int duplex); 358f365c6f7SRussell King int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 359f365c6f7SRussell King int speed, int duplex); 360de776d0dSPavana Sharma int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 361de776d0dSPavana Sharma int speed, int duplex); 36296a2b40cSVivien Didelot 36318e1b742SAlexis Lothoré phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip, 36418e1b742SAlexis Lothoré int port); 36518e1b742SAlexis Lothoré phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip, 36618e1b742SAlexis Lothoré int port); 36718e1b742SAlexis Lothoré phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip, 36818e1b742SAlexis Lothoré int port); 36918e1b742SAlexis Lothoré phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip, 37018e1b742SAlexis Lothoré int port); 3717cbbee05SAndrew Lunn 372e28def33SVivien Didelot int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 373e28def33SVivien Didelot 3745a7921f4SVivien Didelot int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 3755a7921f4SVivien Didelot 376b4e48c50SVivien Didelot int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 377b4e48c50SVivien Didelot int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 378b4e48c50SVivien Didelot 37977064f37SVivien Didelot int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 38077064f37SVivien Didelot int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 38177064f37SVivien Didelot 38234ea415fSHans Schultz int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, 38334ea415fSHans Schultz bool locked); 38434ea415fSHans Schultz 385385a0995SVivien Didelot int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 386385a0995SVivien Didelot u16 mode); 387ef0a7318SAndrew Lunn int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 388ef0a7318SAndrew Lunn int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 38956995cbcSAndrew Lunn int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 39031bef4e9SVivien Didelot enum mv88e6xxx_egress_mode mode); 39156995cbcSAndrew Lunn int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 39256995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 39356995cbcSAndrew Lunn int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 39456995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 395a8b659e7SVladimir Oltean int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 396a8b659e7SVladimir Oltean int port, bool unicast); 397a8b659e7SVladimir Oltean int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 398a8b659e7SVladimir Oltean int port, bool multicast); 399a8b659e7SVladimir Oltean int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, 400a8b659e7SVladimir Oltean bool unicast); 401a8b659e7SVladimir Oltean int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, 402a8b659e7SVladimir Oltean bool multicast); 403f3a2cd32SVivien Didelot int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 404f3a2cd32SVivien Didelot enum mv88e6xxx_policy_mapping mapping, 405f3a2cd32SVivien Didelot enum mv88e6xxx_policy_action action); 4066584b260SMarek Behún int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, 4076584b260SMarek Behún enum mv88e6xxx_policy_mapping mapping, 4086584b260SMarek Behún enum mv88e6xxx_policy_action action); 40956995cbcSAndrew Lunn int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 41056995cbcSAndrew Lunn u16 etype); 411de776d0dSPavana Sharma int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, 412de776d0dSPavana Sharma enum mv88e6xxx_egress_direction direction, 413de776d0dSPavana Sharma int port); 414de776d0dSPavana Sharma int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 415de776d0dSPavana Sharma int upstream_port); 416de776d0dSPavana Sharma int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 417de776d0dSPavana Sharma int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 418de776d0dSPavana Sharma u16 etype); 419ea698f4fSVivien Didelot int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 420ea698f4fSVivien Didelot bool message_port); 42157e661aaSTobias Waldekranz int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, 42257e661aaSTobias Waldekranz bool trunk, u8 id); 423cd782656SVivien Didelot int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 424cd782656SVivien Didelot size_t size); 425ef70b111SAndrew Lunn int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 426ef70b111SAndrew Lunn int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 427041bd545STobias Waldekranz int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, 428041bd545STobias Waldekranz u16 pav); 4290898432cSVivien Didelot int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 4300898432cSVivien Didelot u8 out); 4310898432cSVivien Didelot int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 4320898432cSVivien Didelot u8 out); 4337a3007d2SMarek Behún int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 4347a3007d2SMarek Behún phy_interface_t mode); 435fdc71eeaSAndrew Lunn int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 436fdc71eeaSAndrew Lunn phy_interface_t mode); 437f39908d3SAndrew Lunn int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 438f39908d3SAndrew Lunn phy_interface_t mode); 439de776d0dSPavana Sharma int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 440de776d0dSPavana Sharma phy_interface_t mode); 4412d2e1dd2SAndrew Lunn int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 4422d2e1dd2SAndrew Lunn int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 4438b6836d8SVladimir Oltean int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, 4448b6836d8SVladimir Oltean bool drop_untagged); 4457af4a361STobias Waldekranz int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map); 446a23b2961SAndrew Lunn int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 447a23b2961SAndrew Lunn int upstream_port); 448f0942e00SIwan R Timmer int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 449f0942e00SIwan R Timmer enum mv88e6xxx_egress_direction direction, 450f0942e00SIwan R Timmer bool mirror); 451c8c94891SVivien Didelot 452c8c94891SVivien Didelot int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 4539dbfb4e1SVivien Didelot int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 454c8c94891SVivien Didelot 45560907013SMarek Behún int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block, 45660907013SMarek Behún int port, int reg, u16 val); 45760907013SMarek Behún int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip); 45860907013SMarek Behún int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port, 45960907013SMarek Behún int reg, u16 *val); 46060907013SMarek Behún 46118abed21SVivien Didelot #endif /* _MV88E6XXX_PORT_H */ 462