1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Port Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/if_bridge.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 16 #include "chip.h" 17 #include "port.h" 18 #include "serdes.h" 19 20 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 21 u16 *val) 22 { 23 int addr = chip->info->port_base_addr + port; 24 25 return mv88e6xxx_read(chip, addr, reg, val); 26 } 27 28 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 29 u16 val) 30 { 31 int addr = chip->info->port_base_addr + port; 32 33 return mv88e6xxx_write(chip, addr, reg, val); 34 } 35 36 /* Offset 0x00: MAC (or PCS or Physical) Status Register 37 * 38 * For most devices, this is read only. However the 6185 has the MyPause 39 * bit read/write. 40 */ 41 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 42 int pause) 43 { 44 u16 reg; 45 int err; 46 47 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 48 if (err) 49 return err; 50 51 if (pause) 52 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; 53 else 54 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; 55 56 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 57 } 58 59 /* Offset 0x01: MAC (or PCS or Physical) Control Register 60 * 61 * Link, Duplex and Flow Control have one force bit, one value bit. 62 * 63 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. 64 * Alternative values require the 200BASE (or AltSpeed) bit 12 set. 65 * Newer chips need a ForcedSpd bit 13 set to consider the value. 66 */ 67 68 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 69 phy_interface_t mode) 70 { 71 u16 reg; 72 int err; 73 74 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 75 if (err) 76 return err; 77 78 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 79 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK); 80 81 switch (mode) { 82 case PHY_INTERFACE_MODE_RGMII_RXID: 83 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; 84 break; 85 case PHY_INTERFACE_MODE_RGMII_TXID: 86 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 87 break; 88 case PHY_INTERFACE_MODE_RGMII_ID: 89 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 90 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 91 break; 92 case PHY_INTERFACE_MODE_RGMII: 93 break; 94 default: 95 return 0; 96 } 97 98 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 99 if (err) 100 return err; 101 102 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, 103 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", 104 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); 105 106 return 0; 107 } 108 109 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 110 phy_interface_t mode) 111 { 112 if (port < 5) 113 return -EOPNOTSUPP; 114 115 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 116 } 117 118 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 119 phy_interface_t mode) 120 { 121 if (port != 0) 122 return -EOPNOTSUPP; 123 124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 125 } 126 127 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) 128 { 129 u16 reg; 130 int err; 131 132 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 133 if (err) 134 return err; 135 136 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 137 MV88E6XXX_PORT_MAC_CTL_LINK_UP); 138 139 switch (link) { 140 case LINK_FORCED_DOWN: 141 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; 142 break; 143 case LINK_FORCED_UP: 144 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 145 MV88E6XXX_PORT_MAC_CTL_LINK_UP; 146 break; 147 case LINK_UNFORCED: 148 /* normal link detection */ 149 break; 150 default: 151 return -EINVAL; 152 } 153 154 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 155 if (err) 156 return err; 157 158 dev_dbg(chip->dev, "p%d: %s link %s\n", port, 159 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", 160 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); 161 162 return 0; 163 } 164 165 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip, 166 int port, int speed, bool alt_bit, 167 bool force_bit, int duplex) 168 { 169 u16 reg, ctrl; 170 int err; 171 172 switch (speed) { 173 case 10: 174 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 175 break; 176 case 100: 177 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 178 break; 179 case 200: 180 if (alt_bit) 181 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 182 MV88E6390_PORT_MAC_CTL_ALTSPEED; 183 else 184 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200; 185 break; 186 case 1000: 187 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 188 break; 189 case 2500: 190 if (alt_bit) 191 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 192 MV88E6390_PORT_MAC_CTL_ALTSPEED; 193 else 194 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000; 195 break; 196 case 10000: 197 /* all bits set, fall through... */ 198 case SPEED_UNFORCED: 199 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 200 break; 201 default: 202 return -EOPNOTSUPP; 203 } 204 205 switch (duplex) { 206 case DUPLEX_HALF: 207 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 208 break; 209 case DUPLEX_FULL: 210 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 211 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 212 break; 213 case DUPLEX_UNFORCED: 214 /* normal duplex detection */ 215 break; 216 default: 217 return -EOPNOTSUPP; 218 } 219 220 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 221 if (err) 222 return err; 223 224 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 225 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 226 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); 227 228 if (alt_bit) 229 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; 230 if (force_bit) { 231 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 232 if (speed != SPEED_UNFORCED) 233 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 234 } 235 reg |= ctrl; 236 237 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 238 if (err) 239 return err; 240 241 if (speed) 242 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 243 else 244 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 245 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 246 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 247 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 248 249 return 0; 250 } 251 252 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */ 253 int mv88e6065_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 254 int speed, int duplex) 255 { 256 if (speed == SPEED_MAX) 257 speed = 200; 258 259 if (speed > 200) 260 return -EOPNOTSUPP; 261 262 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */ 263 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 264 duplex); 265 } 266 267 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ 268 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 269 int speed, int duplex) 270 { 271 if (speed == SPEED_MAX) 272 speed = 1000; 273 274 if (speed == 200 || speed > 1000) 275 return -EOPNOTSUPP; 276 277 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 278 duplex); 279 } 280 281 /* Support 10, 100 Mbps (e.g. 88E6250 family) */ 282 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 283 int speed, int duplex) 284 { 285 if (speed == SPEED_MAX) 286 speed = 100; 287 288 if (speed > 100) 289 return -EOPNOTSUPP; 290 291 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 292 duplex); 293 } 294 295 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */ 296 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 297 int speed, int duplex) 298 { 299 if (speed == SPEED_MAX) 300 speed = port < 5 ? 1000 : 2500; 301 302 if (speed > 2500) 303 return -EOPNOTSUPP; 304 305 if (speed == 200 && port != 0) 306 return -EOPNOTSUPP; 307 308 if (speed == 2500 && port < 5) 309 return -EOPNOTSUPP; 310 311 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true, 312 duplex); 313 } 314 315 phy_interface_t mv88e6341_port_max_speed_mode(int port) 316 { 317 if (port == 5) 318 return PHY_INTERFACE_MODE_2500BASEX; 319 320 return PHY_INTERFACE_MODE_NA; 321 } 322 323 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ 324 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 325 int speed, int duplex) 326 { 327 if (speed == SPEED_MAX) 328 speed = 1000; 329 330 if (speed > 1000) 331 return -EOPNOTSUPP; 332 333 if (speed == 200 && port < 5) 334 return -EOPNOTSUPP; 335 336 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false, 337 duplex); 338 } 339 340 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ 341 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 342 int speed, int duplex) 343 { 344 if (speed == SPEED_MAX) 345 speed = port < 9 ? 1000 : 2500; 346 347 if (speed > 2500) 348 return -EOPNOTSUPP; 349 350 if (speed == 200 && port != 0) 351 return -EOPNOTSUPP; 352 353 if (speed == 2500 && port < 9) 354 return -EOPNOTSUPP; 355 356 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 357 duplex); 358 } 359 360 phy_interface_t mv88e6390_port_max_speed_mode(int port) 361 { 362 if (port == 9 || port == 10) 363 return PHY_INTERFACE_MODE_2500BASEX; 364 365 return PHY_INTERFACE_MODE_NA; 366 } 367 368 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ 369 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 370 int speed, int duplex) 371 { 372 if (speed == SPEED_MAX) 373 speed = port < 9 ? 1000 : 10000; 374 375 if (speed == 200 && port != 0) 376 return -EOPNOTSUPP; 377 378 if (speed >= 2500 && port < 9) 379 return -EOPNOTSUPP; 380 381 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 382 duplex); 383 } 384 385 phy_interface_t mv88e6390x_port_max_speed_mode(int port) 386 { 387 if (port == 9 || port == 10) 388 return PHY_INTERFACE_MODE_XAUI; 389 390 return PHY_INTERFACE_MODE_NA; 391 } 392 393 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 394 phy_interface_t mode, bool force) 395 { 396 u8 lane; 397 u16 cmode; 398 u16 reg; 399 int err; 400 401 /* Default to a slow mode, so freeing up SERDES interfaces for 402 * other ports which might use them for SFPs. 403 */ 404 if (mode == PHY_INTERFACE_MODE_NA) 405 mode = PHY_INTERFACE_MODE_1000BASEX; 406 407 switch (mode) { 408 case PHY_INTERFACE_MODE_1000BASEX: 409 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX; 410 break; 411 case PHY_INTERFACE_MODE_SGMII: 412 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII; 413 break; 414 case PHY_INTERFACE_MODE_2500BASEX: 415 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; 416 break; 417 case PHY_INTERFACE_MODE_XGMII: 418 case PHY_INTERFACE_MODE_XAUI: 419 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; 420 break; 421 case PHY_INTERFACE_MODE_RXAUI: 422 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; 423 break; 424 default: 425 cmode = 0; 426 } 427 428 /* cmode doesn't change, nothing to do for us unless forced */ 429 if (cmode == chip->ports[port].cmode && !force) 430 return 0; 431 432 lane = mv88e6xxx_serdes_get_lane(chip, port); 433 if (lane) { 434 if (chip->ports[port].serdes_irq) { 435 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 436 if (err) 437 return err; 438 } 439 440 err = mv88e6xxx_serdes_power_down(chip, port, lane); 441 if (err) 442 return err; 443 } 444 445 chip->ports[port].cmode = 0; 446 447 if (cmode) { 448 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 449 if (err) 450 return err; 451 452 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; 453 reg |= cmode; 454 455 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 456 if (err) 457 return err; 458 459 chip->ports[port].cmode = cmode; 460 461 lane = mv88e6xxx_serdes_get_lane(chip, port); 462 if (!lane) 463 return -ENODEV; 464 465 err = mv88e6xxx_serdes_power_up(chip, port, lane); 466 if (err) 467 return err; 468 469 if (chip->ports[port].serdes_irq) { 470 err = mv88e6xxx_serdes_irq_enable(chip, port, lane); 471 if (err) 472 return err; 473 } 474 } 475 476 return 0; 477 } 478 479 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 480 phy_interface_t mode) 481 { 482 if (port != 9 && port != 10) 483 return -EOPNOTSUPP; 484 485 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 486 } 487 488 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 489 phy_interface_t mode) 490 { 491 if (port != 9 && port != 10) 492 return -EOPNOTSUPP; 493 494 switch (mode) { 495 case PHY_INTERFACE_MODE_NA: 496 return 0; 497 case PHY_INTERFACE_MODE_XGMII: 498 case PHY_INTERFACE_MODE_XAUI: 499 case PHY_INTERFACE_MODE_RXAUI: 500 return -EINVAL; 501 default: 502 break; 503 } 504 505 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 506 } 507 508 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip, 509 int port) 510 { 511 int err, addr; 512 u16 reg, bits; 513 514 if (port != 5) 515 return -EOPNOTSUPP; 516 517 addr = chip->info->port_base_addr + port; 518 519 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); 520 if (err) 521 return err; 522 523 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE | 524 MV88E6341_PORT_RESERVED_1A_SGMII_AN; 525 526 if ((reg & bits) == bits) 527 return 0; 528 529 reg |= bits; 530 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); 531 } 532 533 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 534 phy_interface_t mode) 535 { 536 int err; 537 538 if (port != 5) 539 return -EOPNOTSUPP; 540 541 switch (mode) { 542 case PHY_INTERFACE_MODE_NA: 543 return 0; 544 case PHY_INTERFACE_MODE_XGMII: 545 case PHY_INTERFACE_MODE_XAUI: 546 case PHY_INTERFACE_MODE_RXAUI: 547 return -EINVAL; 548 default: 549 break; 550 } 551 552 err = mv88e6341_port_set_cmode_writable(chip, port); 553 if (err) 554 return err; 555 556 return mv88e6xxx_port_set_cmode(chip, port, mode, true); 557 } 558 559 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 560 { 561 int err; 562 u16 reg; 563 564 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 565 if (err) 566 return err; 567 568 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; 569 570 return 0; 571 } 572 573 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 574 { 575 int err; 576 u16 reg; 577 578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 579 if (err) 580 return err; 581 582 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; 583 584 return 0; 585 } 586 587 int mv88e6250_port_link_state(struct mv88e6xxx_chip *chip, int port, 588 struct phylink_link_state *state) 589 { 590 int err; 591 u16 reg; 592 593 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 594 if (err) 595 return err; 596 597 if (port < 5) { 598 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 599 case MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF: 600 state->speed = SPEED_10; 601 state->duplex = DUPLEX_HALF; 602 break; 603 case MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF: 604 state->speed = SPEED_100; 605 state->duplex = DUPLEX_HALF; 606 break; 607 case MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL: 608 state->speed = SPEED_10; 609 state->duplex = DUPLEX_FULL; 610 break; 611 case MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL: 612 state->speed = SPEED_100; 613 state->duplex = DUPLEX_FULL; 614 break; 615 default: 616 state->speed = SPEED_UNKNOWN; 617 state->duplex = DUPLEX_UNKNOWN; 618 break; 619 } 620 } else { 621 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 622 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF: 623 state->speed = SPEED_10; 624 state->duplex = DUPLEX_HALF; 625 break; 626 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF: 627 state->speed = SPEED_100; 628 state->duplex = DUPLEX_HALF; 629 break; 630 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL: 631 state->speed = SPEED_10; 632 state->duplex = DUPLEX_FULL; 633 break; 634 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL: 635 state->speed = SPEED_100; 636 state->duplex = DUPLEX_FULL; 637 break; 638 default: 639 state->speed = SPEED_UNKNOWN; 640 state->duplex = DUPLEX_UNKNOWN; 641 break; 642 } 643 } 644 645 state->link = !!(reg & MV88E6250_PORT_STS_LINK); 646 state->an_enabled = 1; 647 state->an_complete = state->link; 648 state->interface = PHY_INTERFACE_MODE_NA; 649 650 return 0; 651 } 652 653 int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port, 654 struct phylink_link_state *state) 655 { 656 int err; 657 u16 reg; 658 659 switch (chip->ports[port].cmode) { 660 case MV88E6XXX_PORT_STS_CMODE_RGMII: 661 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, 662 ®); 663 if (err) 664 return err; 665 666 if ((reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK) && 667 (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK)) 668 state->interface = PHY_INTERFACE_MODE_RGMII_ID; 669 else if (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK) 670 state->interface = PHY_INTERFACE_MODE_RGMII_RXID; 671 else if (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK) 672 state->interface = PHY_INTERFACE_MODE_RGMII_TXID; 673 else 674 state->interface = PHY_INTERFACE_MODE_RGMII; 675 break; 676 case MV88E6XXX_PORT_STS_CMODE_1000BASEX: 677 state->interface = PHY_INTERFACE_MODE_1000BASEX; 678 break; 679 case MV88E6XXX_PORT_STS_CMODE_SGMII: 680 state->interface = PHY_INTERFACE_MODE_SGMII; 681 break; 682 case MV88E6XXX_PORT_STS_CMODE_2500BASEX: 683 state->interface = PHY_INTERFACE_MODE_2500BASEX; 684 break; 685 case MV88E6XXX_PORT_STS_CMODE_XAUI: 686 state->interface = PHY_INTERFACE_MODE_XAUI; 687 break; 688 case MV88E6XXX_PORT_STS_CMODE_RXAUI: 689 state->interface = PHY_INTERFACE_MODE_RXAUI; 690 break; 691 default: 692 /* we do not support other cmode values here */ 693 state->interface = PHY_INTERFACE_MODE_NA; 694 } 695 696 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 697 if (err) 698 return err; 699 700 switch (reg & MV88E6XXX_PORT_STS_SPEED_MASK) { 701 case MV88E6XXX_PORT_STS_SPEED_10: 702 state->speed = SPEED_10; 703 break; 704 case MV88E6XXX_PORT_STS_SPEED_100: 705 state->speed = SPEED_100; 706 break; 707 case MV88E6XXX_PORT_STS_SPEED_1000: 708 state->speed = SPEED_1000; 709 break; 710 case MV88E6XXX_PORT_STS_SPEED_10000: 711 if ((reg & MV88E6XXX_PORT_STS_CMODE_MASK) == 712 MV88E6XXX_PORT_STS_CMODE_2500BASEX) 713 state->speed = SPEED_2500; 714 else 715 state->speed = SPEED_10000; 716 break; 717 } 718 719 state->duplex = reg & MV88E6XXX_PORT_STS_DUPLEX ? 720 DUPLEX_FULL : DUPLEX_HALF; 721 state->link = !!(reg & MV88E6XXX_PORT_STS_LINK); 722 state->an_enabled = 1; 723 state->an_complete = state->link; 724 725 return 0; 726 } 727 728 int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port, 729 struct phylink_link_state *state) 730 { 731 if (state->interface == PHY_INTERFACE_MODE_1000BASEX) { 732 u8 cmode = chip->ports[port].cmode; 733 734 /* When a port is in "Cross-chip serdes" mode, it uses 735 * 1000Base-X full duplex mode, but there is no automatic 736 * link detection. Use the sync OK status for link (as it 737 * would do for 1000Base-X mode.) 738 */ 739 if (cmode == MV88E6185_PORT_STS_CMODE_SERDES) { 740 u16 mac; 741 int err; 742 743 err = mv88e6xxx_port_read(chip, port, 744 MV88E6XXX_PORT_MAC_CTL, &mac); 745 if (err) 746 return err; 747 748 state->link = !!(mac & MV88E6185_PORT_MAC_CTL_SYNC_OK); 749 state->an_enabled = 1; 750 state->an_complete = 751 !!(mac & MV88E6185_PORT_MAC_CTL_AN_DONE); 752 state->duplex = 753 state->link ? DUPLEX_FULL : DUPLEX_UNKNOWN; 754 state->speed = 755 state->link ? SPEED_1000 : SPEED_UNKNOWN; 756 757 return 0; 758 } 759 } 760 761 return mv88e6352_port_link_state(chip, port, state); 762 } 763 764 /* Offset 0x02: Jamming Control 765 * 766 * Do not limit the period of time that this port can be paused for by 767 * the remote end or the period of time that this port can pause the 768 * remote end. 769 */ 770 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 771 u8 out) 772 { 773 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, 774 out << 8 | in); 775 } 776 777 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 778 u8 out) 779 { 780 int err; 781 782 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 783 MV88E6390_PORT_FLOW_CTL_UPDATE | 784 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in); 785 if (err) 786 return err; 787 788 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 789 MV88E6390_PORT_FLOW_CTL_UPDATE | 790 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out); 791 } 792 793 /* Offset 0x04: Port Control Register */ 794 795 static const char * const mv88e6xxx_port_state_names[] = { 796 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", 797 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", 798 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", 799 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", 800 }; 801 802 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) 803 { 804 u16 reg; 805 int err; 806 807 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 808 if (err) 809 return err; 810 811 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; 812 813 switch (state) { 814 case BR_STATE_DISABLED: 815 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED; 816 break; 817 case BR_STATE_BLOCKING: 818 case BR_STATE_LISTENING: 819 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 820 break; 821 case BR_STATE_LEARNING: 822 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 823 break; 824 case BR_STATE_FORWARDING: 825 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 826 break; 827 default: 828 return -EINVAL; 829 } 830 831 reg |= state; 832 833 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 834 if (err) 835 return err; 836 837 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, 838 mv88e6xxx_port_state_names[state]); 839 840 return 0; 841 } 842 843 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 844 enum mv88e6xxx_egress_mode mode) 845 { 846 int err; 847 u16 reg; 848 849 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 850 if (err) 851 return err; 852 853 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; 854 855 switch (mode) { 856 case MV88E6XXX_EGRESS_MODE_UNMODIFIED: 857 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; 858 break; 859 case MV88E6XXX_EGRESS_MODE_UNTAGGED: 860 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; 861 break; 862 case MV88E6XXX_EGRESS_MODE_TAGGED: 863 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; 864 break; 865 case MV88E6XXX_EGRESS_MODE_ETHERTYPE: 866 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; 867 break; 868 default: 869 return -EINVAL; 870 } 871 872 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 873 } 874 875 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 876 enum mv88e6xxx_frame_mode mode) 877 { 878 int err; 879 u16 reg; 880 881 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 882 if (err) 883 return err; 884 885 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 886 887 switch (mode) { 888 case MV88E6XXX_FRAME_MODE_NORMAL: 889 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 890 break; 891 case MV88E6XXX_FRAME_MODE_DSA: 892 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 893 break; 894 default: 895 return -EINVAL; 896 } 897 898 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 899 } 900 901 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 902 enum mv88e6xxx_frame_mode mode) 903 { 904 int err; 905 u16 reg; 906 907 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 908 if (err) 909 return err; 910 911 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 912 913 switch (mode) { 914 case MV88E6XXX_FRAME_MODE_NORMAL: 915 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 916 break; 917 case MV88E6XXX_FRAME_MODE_DSA: 918 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 919 break; 920 case MV88E6XXX_FRAME_MODE_PROVIDER: 921 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; 922 break; 923 case MV88E6XXX_FRAME_MODE_ETHERTYPE: 924 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; 925 break; 926 default: 927 return -EINVAL; 928 } 929 930 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 931 } 932 933 static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 934 int port, bool unicast) 935 { 936 int err; 937 u16 reg; 938 939 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 940 if (err) 941 return err; 942 943 if (unicast) 944 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 945 else 946 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 947 948 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 949 } 950 951 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 952 bool unicast, bool multicast) 953 { 954 int err; 955 u16 reg; 956 957 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 958 if (err) 959 return err; 960 961 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK; 962 963 if (unicast && multicast) 964 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA; 965 else if (unicast) 966 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA; 967 else if (multicast) 968 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA; 969 else 970 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA; 971 972 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 973 } 974 975 /* Offset 0x05: Port Control 1 */ 976 977 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 978 bool message_port) 979 { 980 u16 val; 981 int err; 982 983 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 984 if (err) 985 return err; 986 987 if (message_port) 988 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 989 else 990 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 991 992 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 993 } 994 995 /* Offset 0x06: Port Based VLAN Map */ 996 997 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) 998 { 999 const u16 mask = mv88e6xxx_port_mask(chip); 1000 u16 reg; 1001 int err; 1002 1003 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1004 if (err) 1005 return err; 1006 1007 reg &= ~mask; 1008 reg |= map & mask; 1009 1010 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1011 if (err) 1012 return err; 1013 1014 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); 1015 1016 return 0; 1017 } 1018 1019 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) 1020 { 1021 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1022 u16 reg; 1023 int err; 1024 1025 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1026 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1027 if (err) 1028 return err; 1029 1030 *fid = (reg & 0xf000) >> 12; 1031 1032 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1033 if (upper_mask) { 1034 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1035 ®); 1036 if (err) 1037 return err; 1038 1039 *fid |= (reg & upper_mask) << 4; 1040 } 1041 1042 return 0; 1043 } 1044 1045 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) 1046 { 1047 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1048 u16 reg; 1049 int err; 1050 1051 if (fid >= mv88e6xxx_num_databases(chip)) 1052 return -EINVAL; 1053 1054 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1055 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1056 if (err) 1057 return err; 1058 1059 reg &= 0x0fff; 1060 reg |= (fid & 0x000f) << 12; 1061 1062 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1063 if (err) 1064 return err; 1065 1066 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1067 if (upper_mask) { 1068 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1069 ®); 1070 if (err) 1071 return err; 1072 1073 reg &= ~upper_mask; 1074 reg |= (fid >> 4) & upper_mask; 1075 1076 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, 1077 reg); 1078 if (err) 1079 return err; 1080 } 1081 1082 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); 1083 1084 return 0; 1085 } 1086 1087 /* Offset 0x07: Default Port VLAN ID & Priority */ 1088 1089 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) 1090 { 1091 u16 reg; 1092 int err; 1093 1094 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1095 ®); 1096 if (err) 1097 return err; 1098 1099 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1100 1101 return 0; 1102 } 1103 1104 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) 1105 { 1106 u16 reg; 1107 int err; 1108 1109 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1110 ®); 1111 if (err) 1112 return err; 1113 1114 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1115 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1116 1117 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1118 reg); 1119 if (err) 1120 return err; 1121 1122 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); 1123 1124 return 0; 1125 } 1126 1127 /* Offset 0x08: Port Control 2 Register */ 1128 1129 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 1130 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", 1131 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", 1132 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", 1133 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", 1134 }; 1135 1136 static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 1137 int port, bool multicast) 1138 { 1139 int err; 1140 u16 reg; 1141 1142 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1143 if (err) 1144 return err; 1145 1146 if (multicast) 1147 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1148 else 1149 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1150 1151 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1152 } 1153 1154 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 1155 bool unicast, bool multicast) 1156 { 1157 int err; 1158 1159 err = mv88e6185_port_set_forward_unknown(chip, port, unicast); 1160 if (err) 1161 return err; 1162 1163 return mv88e6185_port_set_default_forward(chip, port, multicast); 1164 } 1165 1166 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1167 int upstream_port) 1168 { 1169 int err; 1170 u16 reg; 1171 1172 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1173 if (err) 1174 return err; 1175 1176 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; 1177 reg |= upstream_port; 1178 1179 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1180 } 1181 1182 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 1183 enum mv88e6xxx_egress_direction direction, 1184 bool mirror) 1185 { 1186 bool *mirror_port; 1187 u16 reg; 1188 u16 bit; 1189 int err; 1190 1191 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1192 if (err) 1193 return err; 1194 1195 switch (direction) { 1196 case MV88E6XXX_EGRESS_DIR_INGRESS: 1197 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR; 1198 mirror_port = &chip->ports[port].mirror_ingress; 1199 break; 1200 case MV88E6XXX_EGRESS_DIR_EGRESS: 1201 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR; 1202 mirror_port = &chip->ports[port].mirror_egress; 1203 break; 1204 default: 1205 return -EINVAL; 1206 } 1207 1208 reg &= ~bit; 1209 if (mirror) 1210 reg |= bit; 1211 1212 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1213 if (!err) 1214 *mirror_port = mirror; 1215 1216 return err; 1217 } 1218 1219 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 1220 u16 mode) 1221 { 1222 u16 reg; 1223 int err; 1224 1225 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1226 if (err) 1227 return err; 1228 1229 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1230 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1231 1232 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1233 if (err) 1234 return err; 1235 1236 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, 1237 mv88e6xxx_port_8021q_mode_names[mode]); 1238 1239 return 0; 1240 } 1241 1242 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port) 1243 { 1244 u16 reg; 1245 int err; 1246 1247 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1248 if (err) 1249 return err; 1250 1251 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; 1252 1253 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1254 } 1255 1256 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 1257 size_t size) 1258 { 1259 u16 reg; 1260 int err; 1261 1262 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1263 if (err) 1264 return err; 1265 1266 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; 1267 1268 if (size <= 1522) 1269 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; 1270 else if (size <= 2048) 1271 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; 1272 else if (size <= 10240) 1273 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; 1274 else 1275 return -ERANGE; 1276 1277 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1278 } 1279 1280 /* Offset 0x09: Port Rate Control */ 1281 1282 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1283 { 1284 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1285 0x0000); 1286 } 1287 1288 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1289 { 1290 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1291 0x0001); 1292 } 1293 1294 /* Offset 0x0C: Port ATU Control */ 1295 1296 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) 1297 { 1298 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); 1299 } 1300 1301 /* Offset 0x0D: (Priority) Override Register */ 1302 1303 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) 1304 { 1305 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); 1306 } 1307 1308 /* Offset 0x0f: Port Ether type */ 1309 1310 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1311 u16 etype) 1312 { 1313 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); 1314 } 1315 1316 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] 1317 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] 1318 */ 1319 1320 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1321 { 1322 int err; 1323 1324 /* Use a direct priority mapping for all IEEE tagged frames */ 1325 err = mv88e6xxx_port_write(chip, port, 1326 MV88E6095_PORT_IEEE_PRIO_REMAP_0123, 1327 0x3210); 1328 if (err) 1329 return err; 1330 1331 return mv88e6xxx_port_write(chip, port, 1332 MV88E6095_PORT_IEEE_PRIO_REMAP_4567, 1333 0x7654); 1334 } 1335 1336 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, 1337 int port, u16 table, u8 ptr, u16 data) 1338 { 1339 u16 reg; 1340 1341 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | 1342 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | 1343 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK); 1344 1345 return mv88e6xxx_port_write(chip, port, 1346 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); 1347 } 1348 1349 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1350 { 1351 int err, i; 1352 u16 table; 1353 1354 for (i = 0; i <= 7; i++) { 1355 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; 1356 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, 1357 (i | i << 4)); 1358 if (err) 1359 return err; 1360 1361 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP; 1362 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1363 if (err) 1364 return err; 1365 1366 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP; 1367 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1368 if (err) 1369 return err; 1370 1371 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP; 1372 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1373 if (err) 1374 return err; 1375 } 1376 1377 return 0; 1378 } 1379 1380 /* Offset 0x0E: Policy Control Register */ 1381 1382 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1383 enum mv88e6xxx_policy_mapping mapping, 1384 enum mv88e6xxx_policy_action action) 1385 { 1386 u16 reg, mask, val; 1387 int shift; 1388 int err; 1389 1390 switch (mapping) { 1391 case MV88E6XXX_POLICY_MAPPING_DA: 1392 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK); 1393 mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK; 1394 break; 1395 case MV88E6XXX_POLICY_MAPPING_SA: 1396 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK); 1397 mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK; 1398 break; 1399 case MV88E6XXX_POLICY_MAPPING_VTU: 1400 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK); 1401 mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK; 1402 break; 1403 case MV88E6XXX_POLICY_MAPPING_ETYPE: 1404 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK); 1405 mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK; 1406 break; 1407 case MV88E6XXX_POLICY_MAPPING_PPPOE: 1408 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK); 1409 mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK; 1410 break; 1411 case MV88E6XXX_POLICY_MAPPING_VBAS: 1412 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK); 1413 mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK; 1414 break; 1415 case MV88E6XXX_POLICY_MAPPING_OPT82: 1416 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK); 1417 mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK; 1418 break; 1419 case MV88E6XXX_POLICY_MAPPING_UDP: 1420 shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK); 1421 mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK; 1422 break; 1423 default: 1424 return -EOPNOTSUPP; 1425 } 1426 1427 switch (action) { 1428 case MV88E6XXX_POLICY_ACTION_NORMAL: 1429 val = MV88E6XXX_PORT_POLICY_CTL_NORMAL; 1430 break; 1431 case MV88E6XXX_POLICY_ACTION_MIRROR: 1432 val = MV88E6XXX_PORT_POLICY_CTL_MIRROR; 1433 break; 1434 case MV88E6XXX_POLICY_ACTION_TRAP: 1435 val = MV88E6XXX_PORT_POLICY_CTL_TRAP; 1436 break; 1437 case MV88E6XXX_POLICY_ACTION_DISCARD: 1438 val = MV88E6XXX_PORT_POLICY_CTL_DISCARD; 1439 break; 1440 default: 1441 return -EOPNOTSUPP; 1442 } 1443 1444 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); 1445 if (err) 1446 return err; 1447 1448 reg &= ~mask; 1449 reg |= (val << shift) & mask; 1450 1451 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); 1452 } 1453