1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Port Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/if_bridge.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 16 #include "chip.h" 17 #include "global2.h" 18 #include "port.h" 19 #include "serdes.h" 20 21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 22 u16 *val) 23 { 24 int addr = chip->info->port_base_addr + port; 25 26 return mv88e6xxx_read(chip, addr, reg, val); 27 } 28 29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, 30 int bit, int val) 31 { 32 int addr = chip->info->port_base_addr + port; 33 34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); 35 } 36 37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 38 u16 val) 39 { 40 int addr = chip->info->port_base_addr + port; 41 42 return mv88e6xxx_write(chip, addr, reg, val); 43 } 44 45 /* Offset 0x00: MAC (or PCS or Physical) Status Register 46 * 47 * For most devices, this is read only. However the 6185 has the MyPause 48 * bit read/write. 49 */ 50 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 51 int pause) 52 { 53 u16 reg; 54 int err; 55 56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 57 if (err) 58 return err; 59 60 if (pause) 61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; 62 else 63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; 64 65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 66 } 67 68 /* Offset 0x01: MAC (or PCS or Physical) Control Register 69 * 70 * Link, Duplex and Flow Control have one force bit, one value bit. 71 * 72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. 73 * Alternative values require the 200BASE (or AltSpeed) bit 12 set. 74 * Newer chips need a ForcedSpd bit 13 set to consider the value. 75 */ 76 77 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 78 phy_interface_t mode) 79 { 80 u16 reg; 81 int err; 82 83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 84 if (err) 85 return err; 86 87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 88 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK); 89 90 switch (mode) { 91 case PHY_INTERFACE_MODE_RGMII_RXID: 92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; 93 break; 94 case PHY_INTERFACE_MODE_RGMII_TXID: 95 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 96 break; 97 case PHY_INTERFACE_MODE_RGMII_ID: 98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 99 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 100 break; 101 case PHY_INTERFACE_MODE_RGMII: 102 break; 103 default: 104 return 0; 105 } 106 107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 108 if (err) 109 return err; 110 111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, 112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", 113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); 114 115 return 0; 116 } 117 118 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 119 phy_interface_t mode) 120 { 121 if (port < 5) 122 return -EOPNOTSUPP; 123 124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 125 } 126 127 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 128 phy_interface_t mode) 129 { 130 if (port != 0) 131 return -EOPNOTSUPP; 132 133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 134 } 135 136 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) 137 { 138 u16 reg; 139 int err; 140 141 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 142 if (err) 143 return err; 144 145 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 146 MV88E6XXX_PORT_MAC_CTL_LINK_UP); 147 148 switch (link) { 149 case LINK_FORCED_DOWN: 150 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; 151 break; 152 case LINK_FORCED_UP: 153 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 154 MV88E6XXX_PORT_MAC_CTL_LINK_UP; 155 break; 156 case LINK_UNFORCED: 157 /* normal link detection */ 158 break; 159 default: 160 return -EINVAL; 161 } 162 163 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 164 if (err) 165 return err; 166 167 dev_dbg(chip->dev, "p%d: %s link %s\n", port, 168 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", 169 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); 170 171 return 0; 172 } 173 174 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 175 { 176 const struct mv88e6xxx_ops *ops = chip->info->ops; 177 int err = 0; 178 int link; 179 180 if (isup) 181 link = LINK_FORCED_UP; 182 else 183 link = LINK_FORCED_DOWN; 184 185 if (ops->port_set_link) 186 err = ops->port_set_link(chip, port, link); 187 188 return err; 189 } 190 191 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 192 { 193 const struct mv88e6xxx_ops *ops = chip->info->ops; 194 int err = 0; 195 int link; 196 197 if (mode == MLO_AN_INBAND) 198 link = LINK_UNFORCED; 199 else if (isup) 200 link = LINK_FORCED_UP; 201 else 202 link = LINK_FORCED_DOWN; 203 204 if (ops->port_set_link) 205 err = ops->port_set_link(chip, port, link); 206 207 return err; 208 } 209 210 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip, 211 int port, int speed, bool alt_bit, 212 bool force_bit, int duplex) 213 { 214 u16 reg, ctrl; 215 int err; 216 217 switch (speed) { 218 case 10: 219 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 220 break; 221 case 100: 222 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 223 break; 224 case 200: 225 if (alt_bit) 226 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 227 MV88E6390_PORT_MAC_CTL_ALTSPEED; 228 else 229 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200; 230 break; 231 case 1000: 232 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 233 break; 234 case 2500: 235 if (alt_bit) 236 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 237 MV88E6390_PORT_MAC_CTL_ALTSPEED; 238 else 239 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000; 240 break; 241 case 10000: 242 /* all bits set, fall through... */ 243 case SPEED_UNFORCED: 244 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 245 break; 246 default: 247 return -EOPNOTSUPP; 248 } 249 250 switch (duplex) { 251 case DUPLEX_HALF: 252 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 253 break; 254 case DUPLEX_FULL: 255 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 256 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 257 break; 258 case DUPLEX_UNFORCED: 259 /* normal duplex detection */ 260 break; 261 default: 262 return -EOPNOTSUPP; 263 } 264 265 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 266 if (err) 267 return err; 268 269 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 270 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 271 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); 272 273 if (alt_bit) 274 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; 275 if (force_bit) { 276 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 277 if (speed != SPEED_UNFORCED) 278 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 279 } 280 reg |= ctrl; 281 282 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 283 if (err) 284 return err; 285 286 if (speed != SPEED_UNFORCED) 287 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 288 else 289 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 290 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 291 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 292 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 293 294 return 0; 295 } 296 297 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */ 298 int mv88e6065_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 299 int speed, int duplex) 300 { 301 if (speed == SPEED_MAX) 302 speed = 200; 303 304 if (speed > 200) 305 return -EOPNOTSUPP; 306 307 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */ 308 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 309 duplex); 310 } 311 312 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ 313 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 314 int speed, int duplex) 315 { 316 if (speed == SPEED_MAX) 317 speed = 1000; 318 319 if (speed == 200 || speed > 1000) 320 return -EOPNOTSUPP; 321 322 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 323 duplex); 324 } 325 326 /* Support 10, 100 Mbps (e.g. 88E6250 family) */ 327 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 328 int speed, int duplex) 329 { 330 if (speed == SPEED_MAX) 331 speed = 100; 332 333 if (speed > 100) 334 return -EOPNOTSUPP; 335 336 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 337 duplex); 338 } 339 340 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */ 341 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 342 int speed, int duplex) 343 { 344 if (speed == SPEED_MAX) 345 speed = port < 5 ? 1000 : 2500; 346 347 if (speed > 2500) 348 return -EOPNOTSUPP; 349 350 if (speed == 200 && port != 0) 351 return -EOPNOTSUPP; 352 353 if (speed == 2500 && port < 5) 354 return -EOPNOTSUPP; 355 356 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true, 357 duplex); 358 } 359 360 phy_interface_t mv88e6341_port_max_speed_mode(int port) 361 { 362 if (port == 5) 363 return PHY_INTERFACE_MODE_2500BASEX; 364 365 return PHY_INTERFACE_MODE_NA; 366 } 367 368 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ 369 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 370 int speed, int duplex) 371 { 372 if (speed == SPEED_MAX) 373 speed = 1000; 374 375 if (speed > 1000) 376 return -EOPNOTSUPP; 377 378 if (speed == 200 && port < 5) 379 return -EOPNOTSUPP; 380 381 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false, 382 duplex); 383 } 384 385 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ 386 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 387 int speed, int duplex) 388 { 389 if (speed == SPEED_MAX) 390 speed = port < 9 ? 1000 : 2500; 391 392 if (speed > 2500) 393 return -EOPNOTSUPP; 394 395 if (speed == 200 && port != 0) 396 return -EOPNOTSUPP; 397 398 if (speed == 2500 && port < 9) 399 return -EOPNOTSUPP; 400 401 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 402 duplex); 403 } 404 405 phy_interface_t mv88e6390_port_max_speed_mode(int port) 406 { 407 if (port == 9 || port == 10) 408 return PHY_INTERFACE_MODE_2500BASEX; 409 410 return PHY_INTERFACE_MODE_NA; 411 } 412 413 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ 414 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 415 int speed, int duplex) 416 { 417 if (speed == SPEED_MAX) 418 speed = port < 9 ? 1000 : 10000; 419 420 if (speed == 200 && port != 0) 421 return -EOPNOTSUPP; 422 423 if (speed >= 2500 && port < 9) 424 return -EOPNOTSUPP; 425 426 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 427 duplex); 428 } 429 430 phy_interface_t mv88e6390x_port_max_speed_mode(int port) 431 { 432 if (port == 9 || port == 10) 433 return PHY_INTERFACE_MODE_XAUI; 434 435 return PHY_INTERFACE_MODE_NA; 436 } 437 438 /* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X) 439 * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register 440 * values for speeds 2500 & 5000 conflict. 441 */ 442 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 443 int speed, int duplex) 444 { 445 u16 reg, ctrl; 446 int err; 447 448 if (speed == SPEED_MAX) 449 speed = (port > 0 && port < 9) ? 1000 : 10000; 450 451 if (speed == 200 && port != 0) 452 return -EOPNOTSUPP; 453 454 if (speed >= 2500 && port > 0 && port < 9) 455 return -EOPNOTSUPP; 456 457 switch (speed) { 458 case 10: 459 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 460 break; 461 case 100: 462 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 463 break; 464 case 200: 465 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 466 MV88E6390_PORT_MAC_CTL_ALTSPEED; 467 break; 468 case 1000: 469 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 470 break; 471 case 2500: 472 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 | 473 MV88E6390_PORT_MAC_CTL_ALTSPEED; 474 break; 475 case 5000: 476 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 477 MV88E6390_PORT_MAC_CTL_ALTSPEED; 478 break; 479 case 10000: 480 case SPEED_UNFORCED: 481 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 482 break; 483 default: 484 return -EOPNOTSUPP; 485 } 486 487 switch (duplex) { 488 case DUPLEX_HALF: 489 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 490 break; 491 case DUPLEX_FULL: 492 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 493 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 494 break; 495 case DUPLEX_UNFORCED: 496 /* normal duplex detection */ 497 break; 498 default: 499 return -EOPNOTSUPP; 500 } 501 502 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 503 if (err) 504 return err; 505 506 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 507 MV88E6390_PORT_MAC_CTL_ALTSPEED | 508 MV88E6390_PORT_MAC_CTL_FORCE_SPEED); 509 510 if (speed != SPEED_UNFORCED) 511 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 512 513 reg |= ctrl; 514 515 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 516 if (err) 517 return err; 518 519 if (speed != SPEED_UNFORCED) 520 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 521 else 522 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 523 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 524 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 525 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 526 527 return 0; 528 } 529 530 phy_interface_t mv88e6393x_port_max_speed_mode(int port) 531 { 532 if (port == 0 || port == 9 || port == 10) 533 return PHY_INTERFACE_MODE_10GBASER; 534 535 return PHY_INTERFACE_MODE_NA; 536 } 537 538 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 539 phy_interface_t mode, bool force) 540 { 541 u16 cmode; 542 int lane; 543 u16 reg; 544 int err; 545 546 /* Default to a slow mode, so freeing up SERDES interfaces for 547 * other ports which might use them for SFPs. 548 */ 549 if (mode == PHY_INTERFACE_MODE_NA) 550 mode = PHY_INTERFACE_MODE_1000BASEX; 551 552 switch (mode) { 553 case PHY_INTERFACE_MODE_RMII: 554 cmode = MV88E6XXX_PORT_STS_CMODE_RMII; 555 break; 556 case PHY_INTERFACE_MODE_1000BASEX: 557 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX; 558 break; 559 case PHY_INTERFACE_MODE_SGMII: 560 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII; 561 break; 562 case PHY_INTERFACE_MODE_2500BASEX: 563 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; 564 break; 565 case PHY_INTERFACE_MODE_5GBASER: 566 cmode = MV88E6393X_PORT_STS_CMODE_5GBASER; 567 break; 568 case PHY_INTERFACE_MODE_XGMII: 569 case PHY_INTERFACE_MODE_XAUI: 570 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; 571 break; 572 case PHY_INTERFACE_MODE_RXAUI: 573 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; 574 break; 575 case PHY_INTERFACE_MODE_10GBASER: 576 cmode = MV88E6393X_PORT_STS_CMODE_10GBASER; 577 break; 578 default: 579 cmode = 0; 580 } 581 582 /* cmode doesn't change, nothing to do for us unless forced */ 583 if (cmode == chip->ports[port].cmode && !force) 584 return 0; 585 586 lane = mv88e6xxx_serdes_get_lane(chip, port); 587 if (lane >= 0) { 588 if (chip->ports[port].serdes_irq) { 589 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 590 if (err) 591 return err; 592 } 593 594 err = mv88e6xxx_serdes_power_down(chip, port, lane); 595 if (err) 596 return err; 597 } 598 599 chip->ports[port].cmode = 0; 600 601 if (cmode) { 602 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 603 if (err) 604 return err; 605 606 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; 607 reg |= cmode; 608 609 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 610 if (err) 611 return err; 612 613 chip->ports[port].cmode = cmode; 614 615 lane = mv88e6xxx_serdes_get_lane(chip, port); 616 if (lane == -ENODEV) 617 return 0; 618 if (lane < 0) 619 return lane; 620 621 err = mv88e6xxx_serdes_power_up(chip, port, lane); 622 if (err) 623 return err; 624 625 if (chip->ports[port].serdes_irq) { 626 err = mv88e6xxx_serdes_irq_enable(chip, port, lane); 627 if (err) 628 return err; 629 } 630 } 631 632 return 0; 633 } 634 635 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 636 phy_interface_t mode) 637 { 638 if (port != 9 && port != 10) 639 return -EOPNOTSUPP; 640 641 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 642 } 643 644 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 645 phy_interface_t mode) 646 { 647 if (port != 9 && port != 10) 648 return -EOPNOTSUPP; 649 650 switch (mode) { 651 case PHY_INTERFACE_MODE_NA: 652 return 0; 653 case PHY_INTERFACE_MODE_XGMII: 654 case PHY_INTERFACE_MODE_XAUI: 655 case PHY_INTERFACE_MODE_RXAUI: 656 return -EINVAL; 657 default: 658 break; 659 } 660 661 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 662 } 663 664 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 665 phy_interface_t mode) 666 { 667 int err; 668 u16 reg; 669 670 if (port != 0 && port != 9 && port != 10) 671 return -EOPNOTSUPP; 672 673 /* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */ 674 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 675 if (err) 676 return err; 677 678 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE; 679 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE; 680 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 681 if (err) 682 return err; 683 684 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 685 } 686 687 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip, 688 int port) 689 { 690 int err, addr; 691 u16 reg, bits; 692 693 if (port != 5) 694 return -EOPNOTSUPP; 695 696 addr = chip->info->port_base_addr + port; 697 698 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); 699 if (err) 700 return err; 701 702 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE | 703 MV88E6341_PORT_RESERVED_1A_SGMII_AN; 704 705 if ((reg & bits) == bits) 706 return 0; 707 708 reg |= bits; 709 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); 710 } 711 712 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 713 phy_interface_t mode) 714 { 715 int err; 716 717 if (port != 5) 718 return -EOPNOTSUPP; 719 720 switch (mode) { 721 case PHY_INTERFACE_MODE_NA: 722 return 0; 723 case PHY_INTERFACE_MODE_XGMII: 724 case PHY_INTERFACE_MODE_XAUI: 725 case PHY_INTERFACE_MODE_RXAUI: 726 return -EINVAL; 727 default: 728 break; 729 } 730 731 err = mv88e6341_port_set_cmode_writable(chip, port); 732 if (err) 733 return err; 734 735 return mv88e6xxx_port_set_cmode(chip, port, mode, true); 736 } 737 738 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 739 { 740 int err; 741 u16 reg; 742 743 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 744 if (err) 745 return err; 746 747 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; 748 749 return 0; 750 } 751 752 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 753 { 754 int err; 755 u16 reg; 756 757 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 758 if (err) 759 return err; 760 761 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; 762 763 return 0; 764 } 765 766 /* Offset 0x02: Jamming Control 767 * 768 * Do not limit the period of time that this port can be paused for by 769 * the remote end or the period of time that this port can pause the 770 * remote end. 771 */ 772 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 773 u8 out) 774 { 775 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, 776 out << 8 | in); 777 } 778 779 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 780 u8 out) 781 { 782 int err; 783 784 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 785 MV88E6390_PORT_FLOW_CTL_UPDATE | 786 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in); 787 if (err) 788 return err; 789 790 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 791 MV88E6390_PORT_FLOW_CTL_UPDATE | 792 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out); 793 } 794 795 /* Offset 0x04: Port Control Register */ 796 797 static const char * const mv88e6xxx_port_state_names[] = { 798 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", 799 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", 800 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", 801 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", 802 }; 803 804 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) 805 { 806 u16 reg; 807 int err; 808 809 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 810 if (err) 811 return err; 812 813 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; 814 815 switch (state) { 816 case BR_STATE_DISABLED: 817 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED; 818 break; 819 case BR_STATE_BLOCKING: 820 case BR_STATE_LISTENING: 821 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 822 break; 823 case BR_STATE_LEARNING: 824 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 825 break; 826 case BR_STATE_FORWARDING: 827 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 828 break; 829 default: 830 return -EINVAL; 831 } 832 833 reg |= state; 834 835 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 836 if (err) 837 return err; 838 839 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, 840 mv88e6xxx_port_state_names[state]); 841 842 return 0; 843 } 844 845 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 846 enum mv88e6xxx_egress_mode mode) 847 { 848 int err; 849 u16 reg; 850 851 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 852 if (err) 853 return err; 854 855 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; 856 857 switch (mode) { 858 case MV88E6XXX_EGRESS_MODE_UNMODIFIED: 859 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; 860 break; 861 case MV88E6XXX_EGRESS_MODE_UNTAGGED: 862 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; 863 break; 864 case MV88E6XXX_EGRESS_MODE_TAGGED: 865 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; 866 break; 867 case MV88E6XXX_EGRESS_MODE_ETHERTYPE: 868 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; 869 break; 870 default: 871 return -EINVAL; 872 } 873 874 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 875 } 876 877 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 878 enum mv88e6xxx_frame_mode mode) 879 { 880 int err; 881 u16 reg; 882 883 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 884 if (err) 885 return err; 886 887 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 888 889 switch (mode) { 890 case MV88E6XXX_FRAME_MODE_NORMAL: 891 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 892 break; 893 case MV88E6XXX_FRAME_MODE_DSA: 894 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 895 break; 896 default: 897 return -EINVAL; 898 } 899 900 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 901 } 902 903 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 904 enum mv88e6xxx_frame_mode mode) 905 { 906 int err; 907 u16 reg; 908 909 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 910 if (err) 911 return err; 912 913 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 914 915 switch (mode) { 916 case MV88E6XXX_FRAME_MODE_NORMAL: 917 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 918 break; 919 case MV88E6XXX_FRAME_MODE_DSA: 920 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 921 break; 922 case MV88E6XXX_FRAME_MODE_PROVIDER: 923 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; 924 break; 925 case MV88E6XXX_FRAME_MODE_ETHERTYPE: 926 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; 927 break; 928 default: 929 return -EINVAL; 930 } 931 932 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 933 } 934 935 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 936 int port, bool unicast) 937 { 938 int err; 939 u16 reg; 940 941 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 942 if (err) 943 return err; 944 945 if (unicast) 946 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 947 else 948 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 949 950 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 951 } 952 953 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, 954 bool unicast) 955 { 956 int err; 957 u16 reg; 958 959 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 960 if (err) 961 return err; 962 963 if (unicast) 964 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 965 else 966 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 967 968 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 969 } 970 971 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, 972 bool multicast) 973 { 974 int err; 975 u16 reg; 976 977 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 978 if (err) 979 return err; 980 981 if (multicast) 982 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 983 else 984 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 985 986 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 987 } 988 989 /* Offset 0x05: Port Control 1 */ 990 991 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 992 bool message_port) 993 { 994 u16 val; 995 int err; 996 997 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 998 if (err) 999 return err; 1000 1001 if (message_port) 1002 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 1003 else 1004 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 1005 1006 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 1007 } 1008 1009 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, 1010 bool trunk, u8 id) 1011 { 1012 u16 val; 1013 int err; 1014 1015 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 1016 if (err) 1017 return err; 1018 1019 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK; 1020 1021 if (trunk) 1022 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT | 1023 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT); 1024 else 1025 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT; 1026 1027 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 1028 } 1029 1030 /* Offset 0x06: Port Based VLAN Map */ 1031 1032 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) 1033 { 1034 const u16 mask = mv88e6xxx_port_mask(chip); 1035 u16 reg; 1036 int err; 1037 1038 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1039 if (err) 1040 return err; 1041 1042 reg &= ~mask; 1043 reg |= map & mask; 1044 1045 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1046 if (err) 1047 return err; 1048 1049 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); 1050 1051 return 0; 1052 } 1053 1054 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) 1055 { 1056 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1057 u16 reg; 1058 int err; 1059 1060 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1061 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1062 if (err) 1063 return err; 1064 1065 *fid = (reg & 0xf000) >> 12; 1066 1067 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1068 if (upper_mask) { 1069 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1070 ®); 1071 if (err) 1072 return err; 1073 1074 *fid |= (reg & upper_mask) << 4; 1075 } 1076 1077 return 0; 1078 } 1079 1080 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) 1081 { 1082 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1083 u16 reg; 1084 int err; 1085 1086 if (fid >= mv88e6xxx_num_databases(chip)) 1087 return -EINVAL; 1088 1089 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1090 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1091 if (err) 1092 return err; 1093 1094 reg &= 0x0fff; 1095 reg |= (fid & 0x000f) << 12; 1096 1097 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1098 if (err) 1099 return err; 1100 1101 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1102 if (upper_mask) { 1103 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1104 ®); 1105 if (err) 1106 return err; 1107 1108 reg &= ~upper_mask; 1109 reg |= (fid >> 4) & upper_mask; 1110 1111 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, 1112 reg); 1113 if (err) 1114 return err; 1115 } 1116 1117 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); 1118 1119 return 0; 1120 } 1121 1122 /* Offset 0x07: Default Port VLAN ID & Priority */ 1123 1124 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) 1125 { 1126 u16 reg; 1127 int err; 1128 1129 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1130 ®); 1131 if (err) 1132 return err; 1133 1134 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1135 1136 return 0; 1137 } 1138 1139 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) 1140 { 1141 u16 reg; 1142 int err; 1143 1144 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1145 ®); 1146 if (err) 1147 return err; 1148 1149 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1150 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1151 1152 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1153 reg); 1154 if (err) 1155 return err; 1156 1157 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); 1158 1159 return 0; 1160 } 1161 1162 /* Offset 0x08: Port Control 2 Register */ 1163 1164 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 1165 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", 1166 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", 1167 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", 1168 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", 1169 }; 1170 1171 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 1172 int port, bool multicast) 1173 { 1174 int err; 1175 u16 reg; 1176 1177 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1178 if (err) 1179 return err; 1180 1181 if (multicast) 1182 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1183 else 1184 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1185 1186 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1187 } 1188 1189 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1190 int upstream_port) 1191 { 1192 int err; 1193 u16 reg; 1194 1195 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1196 if (err) 1197 return err; 1198 1199 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; 1200 reg |= upstream_port; 1201 1202 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1203 } 1204 1205 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 1206 enum mv88e6xxx_egress_direction direction, 1207 bool mirror) 1208 { 1209 bool *mirror_port; 1210 u16 reg; 1211 u16 bit; 1212 int err; 1213 1214 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1215 if (err) 1216 return err; 1217 1218 switch (direction) { 1219 case MV88E6XXX_EGRESS_DIR_INGRESS: 1220 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR; 1221 mirror_port = &chip->ports[port].mirror_ingress; 1222 break; 1223 case MV88E6XXX_EGRESS_DIR_EGRESS: 1224 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR; 1225 mirror_port = &chip->ports[port].mirror_egress; 1226 break; 1227 default: 1228 return -EINVAL; 1229 } 1230 1231 reg &= ~bit; 1232 if (mirror) 1233 reg |= bit; 1234 1235 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1236 if (!err) 1237 *mirror_port = mirror; 1238 1239 return err; 1240 } 1241 1242 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, 1243 bool locked) 1244 { 1245 u16 reg; 1246 int err; 1247 1248 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 1249 if (err) 1250 return err; 1251 1252 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK; 1253 if (locked) 1254 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK; 1255 1256 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1257 if (err) 1258 return err; 1259 1260 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®); 1261 if (err) 1262 return err; 1263 1264 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1265 if (locked) 1266 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1267 1268 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg); 1269 } 1270 1271 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 1272 u16 mode) 1273 { 1274 u16 reg; 1275 int err; 1276 1277 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1278 if (err) 1279 return err; 1280 1281 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1282 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1283 1284 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1285 if (err) 1286 return err; 1287 1288 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, 1289 mv88e6xxx_port_8021q_mode_names[mode]); 1290 1291 return 0; 1292 } 1293 1294 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, 1295 bool drop_untagged) 1296 { 1297 u16 old, new; 1298 int err; 1299 1300 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old); 1301 if (err) 1302 return err; 1303 1304 if (drop_untagged) 1305 new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1306 else 1307 new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1308 1309 if (new == old) 1310 return 0; 1311 1312 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new); 1313 } 1314 1315 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map) 1316 { 1317 u16 reg; 1318 int err; 1319 1320 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1321 if (err) 1322 return err; 1323 1324 if (map) 1325 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; 1326 else 1327 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA; 1328 1329 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1330 } 1331 1332 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 1333 size_t size) 1334 { 1335 u16 reg; 1336 int err; 1337 1338 size += VLAN_ETH_HLEN + ETH_FCS_LEN; 1339 1340 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1341 if (err) 1342 return err; 1343 1344 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; 1345 1346 if (size <= 1522) 1347 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; 1348 else if (size <= 2048) 1349 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; 1350 else if (size <= 10240) 1351 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; 1352 else 1353 return -ERANGE; 1354 1355 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1356 } 1357 1358 /* Offset 0x09: Port Rate Control */ 1359 1360 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1361 { 1362 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1363 0x0000); 1364 } 1365 1366 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1367 { 1368 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1369 0x0001); 1370 } 1371 1372 /* Offset 0x0B: Port Association Vector */ 1373 1374 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, 1375 u16 pav) 1376 { 1377 u16 reg, mask; 1378 int err; 1379 1380 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1381 ®); 1382 if (err) 1383 return err; 1384 1385 mask = mv88e6xxx_port_mask(chip); 1386 reg &= ~mask; 1387 reg |= pav & mask; 1388 1389 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1390 reg); 1391 } 1392 1393 /* Offset 0x0C: Port ATU Control */ 1394 1395 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) 1396 { 1397 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); 1398 } 1399 1400 /* Offset 0x0D: (Priority) Override Register */ 1401 1402 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) 1403 { 1404 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); 1405 } 1406 1407 /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */ 1408 1409 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port, 1410 u16 pointer, u8 *data) 1411 { 1412 u16 reg; 1413 int err; 1414 1415 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1416 pointer); 1417 if (err) 1418 return err; 1419 1420 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1421 ®); 1422 if (err) 1423 return err; 1424 1425 *data = reg; 1426 1427 return 0; 1428 } 1429 1430 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port, 1431 u16 pointer, u8 data) 1432 { 1433 u16 reg; 1434 1435 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data; 1436 1437 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1438 reg); 1439 } 1440 1441 static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip, 1442 u16 pointer, u8 data) 1443 { 1444 int err, port; 1445 1446 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1447 if (dsa_is_unused_port(chip->ds, port)) 1448 continue; 1449 1450 err = mv88e6393x_port_policy_write(chip, port, pointer, data); 1451 if (err) 1452 return err; 1453 } 1454 1455 return 0; 1456 } 1457 1458 int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, 1459 enum mv88e6xxx_egress_direction direction, 1460 int port) 1461 { 1462 u16 ptr; 1463 int err; 1464 1465 switch (direction) { 1466 case MV88E6XXX_EGRESS_DIR_INGRESS: 1467 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST; 1468 err = mv88e6393x_port_policy_write_all(chip, ptr, port); 1469 if (err) 1470 return err; 1471 break; 1472 case MV88E6XXX_EGRESS_DIR_EGRESS: 1473 ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST; 1474 err = mv88e6xxx_g2_write(chip, ptr, port); 1475 if (err) 1476 return err; 1477 break; 1478 } 1479 1480 return 0; 1481 } 1482 1483 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1484 int upstream_port) 1485 { 1486 u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST; 1487 u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI | 1488 upstream_port; 1489 1490 return mv88e6393x_port_policy_write(chip, port, ptr, data); 1491 } 1492 1493 int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 1494 { 1495 u16 ptr; 1496 int err; 1497 1498 /* Consider the frames with reserved multicast destination 1499 * addresses matching 01:80:c2:00:00:00 and 1500 * 01:80:c2:00:00:02 as MGMT. 1501 */ 1502 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO; 1503 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1504 if (err) 1505 return err; 1506 1507 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI; 1508 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1509 if (err) 1510 return err; 1511 1512 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO; 1513 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1514 if (err) 1515 return err; 1516 1517 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI; 1518 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1519 if (err) 1520 return err; 1521 1522 return 0; 1523 } 1524 1525 /* Offset 0x10 & 0x11: EPC */ 1526 1527 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) 1528 { 1529 int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY); 1530 1531 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); 1532 } 1533 1534 /* Port Ether type for 6393X family */ 1535 1536 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1537 u16 etype) 1538 { 1539 u16 val; 1540 int err; 1541 1542 err = mv88e6393x_port_epc_wait_ready(chip, port); 1543 if (err) 1544 return err; 1545 1546 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype); 1547 if (err) 1548 return err; 1549 1550 val = MV88E6393X_PORT_EPC_CMD_BUSY | 1551 MV88E6393X_PORT_EPC_CMD_WRITE | 1552 MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE; 1553 1554 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val); 1555 } 1556 1557 /* Offset 0x0f: Port Ether type */ 1558 1559 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1560 u16 etype) 1561 { 1562 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); 1563 } 1564 1565 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] 1566 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] 1567 */ 1568 1569 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1570 { 1571 int err; 1572 1573 /* Use a direct priority mapping for all IEEE tagged frames */ 1574 err = mv88e6xxx_port_write(chip, port, 1575 MV88E6095_PORT_IEEE_PRIO_REMAP_0123, 1576 0x3210); 1577 if (err) 1578 return err; 1579 1580 return mv88e6xxx_port_write(chip, port, 1581 MV88E6095_PORT_IEEE_PRIO_REMAP_4567, 1582 0x7654); 1583 } 1584 1585 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, 1586 int port, u16 table, u8 ptr, u16 data) 1587 { 1588 u16 reg; 1589 1590 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | 1591 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | 1592 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK); 1593 1594 return mv88e6xxx_port_write(chip, port, 1595 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); 1596 } 1597 1598 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1599 { 1600 int err, i; 1601 u16 table; 1602 1603 for (i = 0; i <= 7; i++) { 1604 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; 1605 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, 1606 (i | i << 4)); 1607 if (err) 1608 return err; 1609 1610 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP; 1611 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1612 if (err) 1613 return err; 1614 1615 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP; 1616 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1617 if (err) 1618 return err; 1619 1620 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP; 1621 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1622 if (err) 1623 return err; 1624 } 1625 1626 return 0; 1627 } 1628 1629 /* Offset 0x0E: Policy Control Register */ 1630 1631 static int 1632 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping, 1633 enum mv88e6xxx_policy_action action, 1634 u16 *mask, u16 *val, int *shift) 1635 { 1636 switch (mapping) { 1637 case MV88E6XXX_POLICY_MAPPING_DA: 1638 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK); 1639 *mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK; 1640 break; 1641 case MV88E6XXX_POLICY_MAPPING_SA: 1642 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK); 1643 *mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK; 1644 break; 1645 case MV88E6XXX_POLICY_MAPPING_VTU: 1646 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK); 1647 *mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK; 1648 break; 1649 case MV88E6XXX_POLICY_MAPPING_ETYPE: 1650 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK); 1651 *mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK; 1652 break; 1653 case MV88E6XXX_POLICY_MAPPING_PPPOE: 1654 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK); 1655 *mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK; 1656 break; 1657 case MV88E6XXX_POLICY_MAPPING_VBAS: 1658 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK); 1659 *mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK; 1660 break; 1661 case MV88E6XXX_POLICY_MAPPING_OPT82: 1662 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK); 1663 *mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK; 1664 break; 1665 case MV88E6XXX_POLICY_MAPPING_UDP: 1666 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK); 1667 *mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK; 1668 break; 1669 default: 1670 return -EOPNOTSUPP; 1671 } 1672 1673 switch (action) { 1674 case MV88E6XXX_POLICY_ACTION_NORMAL: 1675 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL; 1676 break; 1677 case MV88E6XXX_POLICY_ACTION_MIRROR: 1678 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR; 1679 break; 1680 case MV88E6XXX_POLICY_ACTION_TRAP: 1681 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP; 1682 break; 1683 case MV88E6XXX_POLICY_ACTION_DISCARD: 1684 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD; 1685 break; 1686 default: 1687 return -EOPNOTSUPP; 1688 } 1689 1690 return 0; 1691 } 1692 1693 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1694 enum mv88e6xxx_policy_mapping mapping, 1695 enum mv88e6xxx_policy_action action) 1696 { 1697 u16 reg, mask, val; 1698 int shift; 1699 int err; 1700 1701 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1702 &val, &shift); 1703 if (err) 1704 return err; 1705 1706 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); 1707 if (err) 1708 return err; 1709 1710 reg &= ~mask; 1711 reg |= (val << shift) & mask; 1712 1713 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); 1714 } 1715 1716 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1717 enum mv88e6xxx_policy_mapping mapping, 1718 enum mv88e6xxx_policy_action action) 1719 { 1720 u16 mask, val; 1721 int shift; 1722 int err; 1723 u16 ptr; 1724 u8 reg; 1725 1726 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1727 &val, &shift); 1728 if (err) 1729 return err; 1730 1731 /* The 16-bit Port Policy CTL register from older chips is on 6393x 1732 * changed to Port Policy MGMT CTL, which can access more data, but 1733 * indirectly. The original 16-bit value is divided into two 8-bit 1734 * registers. 1735 */ 1736 ptr = shift / 8; 1737 shift %= 8; 1738 mask >>= ptr * 8; 1739 1740 err = mv88e6393x_port_policy_read(chip, port, ptr, ®); 1741 if (err) 1742 return err; 1743 1744 reg &= ~mask; 1745 reg |= (val << shift) & mask; 1746 1747 return mv88e6393x_port_policy_write(chip, port, ptr, reg); 1748 } 1749