1 /* 2 * Marvell 88E6xxx Switch Port Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/bitfield.h> 16 #include <linux/if_bridge.h> 17 #include <linux/phy.h> 18 #include <linux/phylink.h> 19 20 #include "chip.h" 21 #include "port.h" 22 #include "serdes.h" 23 24 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 25 u16 *val) 26 { 27 int addr = chip->info->port_base_addr + port; 28 29 return mv88e6xxx_read(chip, addr, reg, val); 30 } 31 32 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 33 u16 val) 34 { 35 int addr = chip->info->port_base_addr + port; 36 37 return mv88e6xxx_write(chip, addr, reg, val); 38 } 39 40 /* Offset 0x00: MAC (or PCS or Physical) Status Register 41 * 42 * For most devices, this is read only. However the 6185 has the MyPause 43 * bit read/write. 44 */ 45 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 46 int pause) 47 { 48 u16 reg; 49 int err; 50 51 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 52 if (err) 53 return err; 54 55 if (pause) 56 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; 57 else 58 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; 59 60 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 61 } 62 63 /* Offset 0x01: MAC (or PCS or Physical) Control Register 64 * 65 * Link, Duplex and Flow Control have one force bit, one value bit. 66 * 67 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. 68 * Alternative values require the 200BASE (or AltSpeed) bit 12 set. 69 * Newer chips need a ForcedSpd bit 13 set to consider the value. 70 */ 71 72 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 73 phy_interface_t mode) 74 { 75 u16 reg; 76 int err; 77 78 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 79 if (err) 80 return err; 81 82 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 83 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK); 84 85 switch (mode) { 86 case PHY_INTERFACE_MODE_RGMII_RXID: 87 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; 88 break; 89 case PHY_INTERFACE_MODE_RGMII_TXID: 90 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 91 break; 92 case PHY_INTERFACE_MODE_RGMII_ID: 93 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 94 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 95 break; 96 case PHY_INTERFACE_MODE_RGMII: 97 break; 98 default: 99 return 0; 100 } 101 102 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 103 if (err) 104 return err; 105 106 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, 107 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", 108 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); 109 110 return 0; 111 } 112 113 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 114 phy_interface_t mode) 115 { 116 if (port < 5) 117 return -EOPNOTSUPP; 118 119 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 120 } 121 122 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 123 phy_interface_t mode) 124 { 125 if (port != 0) 126 return -EOPNOTSUPP; 127 128 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 129 } 130 131 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) 132 { 133 u16 reg; 134 int err; 135 136 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 137 if (err) 138 return err; 139 140 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 141 MV88E6XXX_PORT_MAC_CTL_LINK_UP); 142 143 switch (link) { 144 case LINK_FORCED_DOWN: 145 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; 146 break; 147 case LINK_FORCED_UP: 148 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 149 MV88E6XXX_PORT_MAC_CTL_LINK_UP; 150 break; 151 case LINK_UNFORCED: 152 /* normal link detection */ 153 break; 154 default: 155 return -EINVAL; 156 } 157 158 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 159 if (err) 160 return err; 161 162 dev_dbg(chip->dev, "p%d: %s link %s\n", port, 163 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", 164 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); 165 166 return 0; 167 } 168 169 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup) 170 { 171 u16 reg; 172 int err; 173 174 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 175 if (err) 176 return err; 177 178 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 179 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); 180 181 switch (dup) { 182 case DUPLEX_HALF: 183 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 184 break; 185 case DUPLEX_FULL: 186 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 187 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 188 break; 189 case DUPLEX_UNFORCED: 190 /* normal duplex detection */ 191 break; 192 default: 193 return -EINVAL; 194 } 195 196 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 197 if (err) 198 return err; 199 200 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 201 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 202 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 203 204 return 0; 205 } 206 207 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port, 208 int speed, bool alt_bit, bool force_bit) 209 { 210 u16 reg, ctrl; 211 int err; 212 213 switch (speed) { 214 case 10: 215 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 216 break; 217 case 100: 218 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 219 break; 220 case 200: 221 if (alt_bit) 222 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 223 MV88E6390_PORT_MAC_CTL_ALTSPEED; 224 else 225 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200; 226 break; 227 case 1000: 228 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 229 break; 230 case 2500: 231 if (alt_bit) 232 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 233 MV88E6390_PORT_MAC_CTL_ALTSPEED; 234 else 235 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000; 236 break; 237 case 10000: 238 /* all bits set, fall through... */ 239 case SPEED_UNFORCED: 240 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 241 break; 242 default: 243 return -EOPNOTSUPP; 244 } 245 246 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 247 if (err) 248 return err; 249 250 reg &= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK; 251 if (alt_bit) 252 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; 253 if (force_bit) { 254 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 255 if (speed != SPEED_UNFORCED) 256 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 257 } 258 reg |= ctrl; 259 260 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 261 if (err) 262 return err; 263 264 if (speed) 265 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 266 else 267 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 268 269 return 0; 270 } 271 272 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */ 273 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 274 { 275 if (speed == SPEED_MAX) 276 speed = 200; 277 278 if (speed > 200) 279 return -EOPNOTSUPP; 280 281 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */ 282 return mv88e6xxx_port_set_speed(chip, port, speed, false, false); 283 } 284 285 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ 286 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 287 { 288 if (speed == SPEED_MAX) 289 speed = 1000; 290 291 if (speed == 200 || speed > 1000) 292 return -EOPNOTSUPP; 293 294 return mv88e6xxx_port_set_speed(chip, port, speed, false, false); 295 } 296 297 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */ 298 int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 299 { 300 if (speed == SPEED_MAX) 301 speed = port < 5 ? 1000 : 2500; 302 303 if (speed > 2500) 304 return -EOPNOTSUPP; 305 306 if (speed == 200 && port != 0) 307 return -EOPNOTSUPP; 308 309 if (speed == 2500 && port < 5) 310 return -EOPNOTSUPP; 311 312 return mv88e6xxx_port_set_speed(chip, port, speed, !port, true); 313 } 314 315 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ 316 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 317 { 318 if (speed == SPEED_MAX) 319 speed = 1000; 320 321 if (speed > 1000) 322 return -EOPNOTSUPP; 323 324 if (speed == 200 && port < 5) 325 return -EOPNOTSUPP; 326 327 return mv88e6xxx_port_set_speed(chip, port, speed, true, false); 328 } 329 330 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ 331 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 332 { 333 if (speed == SPEED_MAX) 334 speed = port < 9 ? 1000 : 2500; 335 336 if (speed > 2500) 337 return -EOPNOTSUPP; 338 339 if (speed == 200 && port != 0) 340 return -EOPNOTSUPP; 341 342 if (speed == 2500 && port < 9) 343 return -EOPNOTSUPP; 344 345 return mv88e6xxx_port_set_speed(chip, port, speed, true, true); 346 } 347 348 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ 349 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 350 { 351 if (speed == SPEED_MAX) 352 speed = port < 9 ? 1000 : 10000; 353 354 if (speed == 200 && port != 0) 355 return -EOPNOTSUPP; 356 357 if (speed >= 2500 && port < 9) 358 return -EOPNOTSUPP; 359 360 return mv88e6xxx_port_set_speed(chip, port, speed, true, true); 361 } 362 363 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 364 phy_interface_t mode) 365 { 366 int lane; 367 u16 cmode; 368 u16 reg; 369 int err; 370 371 if (port != 9 && port != 10) 372 return -EOPNOTSUPP; 373 374 /* Default to a slow mode, so freeing up SERDES interfaces for 375 * other ports which might use them for SFPs. 376 */ 377 if (mode == PHY_INTERFACE_MODE_NA) 378 mode = PHY_INTERFACE_MODE_1000BASEX; 379 380 switch (mode) { 381 case PHY_INTERFACE_MODE_1000BASEX: 382 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASE_X; 383 break; 384 case PHY_INTERFACE_MODE_SGMII: 385 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII; 386 break; 387 case PHY_INTERFACE_MODE_2500BASEX: 388 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; 389 break; 390 case PHY_INTERFACE_MODE_XGMII: 391 case PHY_INTERFACE_MODE_XAUI: 392 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; 393 break; 394 case PHY_INTERFACE_MODE_RXAUI: 395 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; 396 break; 397 default: 398 cmode = 0; 399 } 400 401 /* cmode doesn't change, nothing to do for us */ 402 if (cmode == chip->ports[port].cmode) 403 return 0; 404 405 lane = mv88e6390x_serdes_get_lane(chip, port); 406 if (lane < 0) 407 return lane; 408 409 if (chip->ports[port].serdes_irq) { 410 err = mv88e6390_serdes_irq_disable(chip, port, lane); 411 if (err) 412 return err; 413 } 414 415 err = mv88e6390x_serdes_power(chip, port, false); 416 if (err) 417 return err; 418 419 if (cmode) { 420 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 421 if (err) 422 return err; 423 424 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; 425 reg |= cmode; 426 427 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 428 if (err) 429 return err; 430 431 err = mv88e6390x_serdes_power(chip, port, true); 432 if (err) 433 return err; 434 435 if (chip->ports[port].serdes_irq) { 436 err = mv88e6390_serdes_irq_enable(chip, port, lane); 437 if (err) 438 return err; 439 } 440 } 441 442 chip->ports[port].cmode = cmode; 443 444 return 0; 445 } 446 447 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 448 phy_interface_t mode) 449 { 450 switch (mode) { 451 case PHY_INTERFACE_MODE_XGMII: 452 case PHY_INTERFACE_MODE_XAUI: 453 case PHY_INTERFACE_MODE_RXAUI: 454 return -EINVAL; 455 default: 456 break; 457 } 458 459 return mv88e6390x_port_set_cmode(chip, port, mode); 460 } 461 462 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 463 { 464 int err; 465 u16 reg; 466 467 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 468 if (err) 469 return err; 470 471 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; 472 473 return 0; 474 } 475 476 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 477 { 478 int err; 479 u16 reg; 480 481 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 482 if (err) 483 return err; 484 485 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; 486 487 return 0; 488 } 489 490 int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port, 491 struct phylink_link_state *state) 492 { 493 int err; 494 u16 reg; 495 496 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 497 if (err) 498 return err; 499 500 switch (reg & MV88E6XXX_PORT_STS_SPEED_MASK) { 501 case MV88E6XXX_PORT_STS_SPEED_10: 502 state->speed = SPEED_10; 503 break; 504 case MV88E6XXX_PORT_STS_SPEED_100: 505 state->speed = SPEED_100; 506 break; 507 case MV88E6XXX_PORT_STS_SPEED_1000: 508 state->speed = SPEED_1000; 509 break; 510 case MV88E6XXX_PORT_STS_SPEED_10000: 511 if ((reg & MV88E6XXX_PORT_STS_CMODE_MASK) == 512 MV88E6XXX_PORT_STS_CMODE_2500BASEX) 513 state->speed = SPEED_2500; 514 else 515 state->speed = SPEED_10000; 516 break; 517 } 518 519 state->duplex = reg & MV88E6XXX_PORT_STS_DUPLEX ? 520 DUPLEX_FULL : DUPLEX_HALF; 521 state->link = !!(reg & MV88E6XXX_PORT_STS_LINK); 522 state->an_enabled = 1; 523 state->an_complete = state->link; 524 525 return 0; 526 } 527 528 int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port, 529 struct phylink_link_state *state) 530 { 531 if (state->interface == PHY_INTERFACE_MODE_1000BASEX) { 532 u8 cmode = chip->ports[port].cmode; 533 534 /* When a port is in "Cross-chip serdes" mode, it uses 535 * 1000Base-X full duplex mode, but there is no automatic 536 * link detection. Use the sync OK status for link (as it 537 * would do for 1000Base-X mode.) 538 */ 539 if (cmode == MV88E6185_PORT_STS_CMODE_SERDES) { 540 u16 mac; 541 int err; 542 543 err = mv88e6xxx_port_read(chip, port, 544 MV88E6XXX_PORT_MAC_CTL, &mac); 545 if (err) 546 return err; 547 548 state->link = !!(mac & MV88E6185_PORT_MAC_CTL_SYNC_OK); 549 state->an_enabled = 1; 550 state->an_complete = 551 !!(mac & MV88E6185_PORT_MAC_CTL_AN_DONE); 552 state->duplex = 553 state->link ? DUPLEX_FULL : DUPLEX_UNKNOWN; 554 state->speed = 555 state->link ? SPEED_1000 : SPEED_UNKNOWN; 556 557 return 0; 558 } 559 } 560 561 return mv88e6352_port_link_state(chip, port, state); 562 } 563 564 /* Offset 0x02: Jamming Control 565 * 566 * Do not limit the period of time that this port can be paused for by 567 * the remote end or the period of time that this port can pause the 568 * remote end. 569 */ 570 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 571 u8 out) 572 { 573 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, 574 out << 8 | in); 575 } 576 577 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 578 u8 out) 579 { 580 int err; 581 582 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 583 MV88E6390_PORT_FLOW_CTL_UPDATE | 584 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in); 585 if (err) 586 return err; 587 588 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 589 MV88E6390_PORT_FLOW_CTL_UPDATE | 590 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out); 591 } 592 593 /* Offset 0x04: Port Control Register */ 594 595 static const char * const mv88e6xxx_port_state_names[] = { 596 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", 597 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", 598 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", 599 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", 600 }; 601 602 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) 603 { 604 u16 reg; 605 int err; 606 607 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 608 if (err) 609 return err; 610 611 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; 612 613 switch (state) { 614 case BR_STATE_DISABLED: 615 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED; 616 break; 617 case BR_STATE_BLOCKING: 618 case BR_STATE_LISTENING: 619 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 620 break; 621 case BR_STATE_LEARNING: 622 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 623 break; 624 case BR_STATE_FORWARDING: 625 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 626 break; 627 default: 628 return -EINVAL; 629 } 630 631 reg |= state; 632 633 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 634 if (err) 635 return err; 636 637 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, 638 mv88e6xxx_port_state_names[state]); 639 640 return 0; 641 } 642 643 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 644 enum mv88e6xxx_egress_mode mode) 645 { 646 int err; 647 u16 reg; 648 649 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 650 if (err) 651 return err; 652 653 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; 654 655 switch (mode) { 656 case MV88E6XXX_EGRESS_MODE_UNMODIFIED: 657 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; 658 break; 659 case MV88E6XXX_EGRESS_MODE_UNTAGGED: 660 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; 661 break; 662 case MV88E6XXX_EGRESS_MODE_TAGGED: 663 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; 664 break; 665 case MV88E6XXX_EGRESS_MODE_ETHERTYPE: 666 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; 667 break; 668 default: 669 return -EINVAL; 670 } 671 672 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 673 } 674 675 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 676 enum mv88e6xxx_frame_mode mode) 677 { 678 int err; 679 u16 reg; 680 681 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 682 if (err) 683 return err; 684 685 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 686 687 switch (mode) { 688 case MV88E6XXX_FRAME_MODE_NORMAL: 689 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 690 break; 691 case MV88E6XXX_FRAME_MODE_DSA: 692 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 693 break; 694 default: 695 return -EINVAL; 696 } 697 698 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 699 } 700 701 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 702 enum mv88e6xxx_frame_mode mode) 703 { 704 int err; 705 u16 reg; 706 707 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 708 if (err) 709 return err; 710 711 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 712 713 switch (mode) { 714 case MV88E6XXX_FRAME_MODE_NORMAL: 715 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 716 break; 717 case MV88E6XXX_FRAME_MODE_DSA: 718 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 719 break; 720 case MV88E6XXX_FRAME_MODE_PROVIDER: 721 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; 722 break; 723 case MV88E6XXX_FRAME_MODE_ETHERTYPE: 724 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; 725 break; 726 default: 727 return -EINVAL; 728 } 729 730 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 731 } 732 733 static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 734 int port, bool unicast) 735 { 736 int err; 737 u16 reg; 738 739 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 740 if (err) 741 return err; 742 743 if (unicast) 744 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 745 else 746 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 747 748 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 749 } 750 751 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 752 bool unicast, bool multicast) 753 { 754 int err; 755 u16 reg; 756 757 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 758 if (err) 759 return err; 760 761 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK; 762 763 if (unicast && multicast) 764 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA; 765 else if (unicast) 766 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA; 767 else if (multicast) 768 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA; 769 else 770 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA; 771 772 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 773 } 774 775 /* Offset 0x05: Port Control 1 */ 776 777 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 778 bool message_port) 779 { 780 u16 val; 781 int err; 782 783 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 784 if (err) 785 return err; 786 787 if (message_port) 788 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 789 else 790 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 791 792 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 793 } 794 795 /* Offset 0x06: Port Based VLAN Map */ 796 797 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) 798 { 799 const u16 mask = mv88e6xxx_port_mask(chip); 800 u16 reg; 801 int err; 802 803 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 804 if (err) 805 return err; 806 807 reg &= ~mask; 808 reg |= map & mask; 809 810 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 811 if (err) 812 return err; 813 814 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); 815 816 return 0; 817 } 818 819 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) 820 { 821 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 822 u16 reg; 823 int err; 824 825 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 826 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 827 if (err) 828 return err; 829 830 *fid = (reg & 0xf000) >> 12; 831 832 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 833 if (upper_mask) { 834 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 835 ®); 836 if (err) 837 return err; 838 839 *fid |= (reg & upper_mask) << 4; 840 } 841 842 return 0; 843 } 844 845 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) 846 { 847 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 848 u16 reg; 849 int err; 850 851 if (fid >= mv88e6xxx_num_databases(chip)) 852 return -EINVAL; 853 854 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 855 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 856 if (err) 857 return err; 858 859 reg &= 0x0fff; 860 reg |= (fid & 0x000f) << 12; 861 862 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 863 if (err) 864 return err; 865 866 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 867 if (upper_mask) { 868 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 869 ®); 870 if (err) 871 return err; 872 873 reg &= ~upper_mask; 874 reg |= (fid >> 4) & upper_mask; 875 876 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, 877 reg); 878 if (err) 879 return err; 880 } 881 882 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); 883 884 return 0; 885 } 886 887 /* Offset 0x07: Default Port VLAN ID & Priority */ 888 889 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) 890 { 891 u16 reg; 892 int err; 893 894 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 895 ®); 896 if (err) 897 return err; 898 899 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 900 901 return 0; 902 } 903 904 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) 905 { 906 u16 reg; 907 int err; 908 909 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 910 ®); 911 if (err) 912 return err; 913 914 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 915 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 916 917 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 918 reg); 919 if (err) 920 return err; 921 922 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); 923 924 return 0; 925 } 926 927 /* Offset 0x08: Port Control 2 Register */ 928 929 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 930 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", 931 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", 932 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", 933 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", 934 }; 935 936 static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 937 int port, bool multicast) 938 { 939 int err; 940 u16 reg; 941 942 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 943 if (err) 944 return err; 945 946 if (multicast) 947 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 948 else 949 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 950 951 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 952 } 953 954 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 955 bool unicast, bool multicast) 956 { 957 int err; 958 959 err = mv88e6185_port_set_forward_unknown(chip, port, unicast); 960 if (err) 961 return err; 962 963 return mv88e6185_port_set_default_forward(chip, port, multicast); 964 } 965 966 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 967 int upstream_port) 968 { 969 int err; 970 u16 reg; 971 972 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 973 if (err) 974 return err; 975 976 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; 977 reg |= upstream_port; 978 979 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 980 } 981 982 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 983 u16 mode) 984 { 985 u16 reg; 986 int err; 987 988 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 989 if (err) 990 return err; 991 992 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 993 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 994 995 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 996 if (err) 997 return err; 998 999 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, 1000 mv88e6xxx_port_8021q_mode_names[mode]); 1001 1002 return 0; 1003 } 1004 1005 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port) 1006 { 1007 u16 reg; 1008 int err; 1009 1010 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1011 if (err) 1012 return err; 1013 1014 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; 1015 1016 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1017 } 1018 1019 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 1020 size_t size) 1021 { 1022 u16 reg; 1023 int err; 1024 1025 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1026 if (err) 1027 return err; 1028 1029 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; 1030 1031 if (size <= 1522) 1032 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; 1033 else if (size <= 2048) 1034 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; 1035 else if (size <= 10240) 1036 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; 1037 else 1038 return -ERANGE; 1039 1040 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1041 } 1042 1043 /* Offset 0x09: Port Rate Control */ 1044 1045 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1046 { 1047 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1048 0x0000); 1049 } 1050 1051 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1052 { 1053 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1054 0x0001); 1055 } 1056 1057 /* Offset 0x0C: Port ATU Control */ 1058 1059 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) 1060 { 1061 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); 1062 } 1063 1064 /* Offset 0x0D: (Priority) Override Register */ 1065 1066 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) 1067 { 1068 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); 1069 } 1070 1071 /* Offset 0x0f: Port Ether type */ 1072 1073 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1074 u16 etype) 1075 { 1076 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); 1077 } 1078 1079 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] 1080 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] 1081 */ 1082 1083 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1084 { 1085 int err; 1086 1087 /* Use a direct priority mapping for all IEEE tagged frames */ 1088 err = mv88e6xxx_port_write(chip, port, 1089 MV88E6095_PORT_IEEE_PRIO_REMAP_0123, 1090 0x3210); 1091 if (err) 1092 return err; 1093 1094 return mv88e6xxx_port_write(chip, port, 1095 MV88E6095_PORT_IEEE_PRIO_REMAP_4567, 1096 0x7654); 1097 } 1098 1099 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, 1100 int port, u16 table, u8 ptr, u16 data) 1101 { 1102 u16 reg; 1103 1104 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | 1105 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | 1106 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK); 1107 1108 return mv88e6xxx_port_write(chip, port, 1109 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); 1110 } 1111 1112 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1113 { 1114 int err, i; 1115 u16 table; 1116 1117 for (i = 0; i <= 7; i++) { 1118 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; 1119 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, 1120 (i | i << 4)); 1121 if (err) 1122 return err; 1123 1124 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP; 1125 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1126 if (err) 1127 return err; 1128 1129 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP; 1130 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1131 if (err) 1132 return err; 1133 1134 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP; 1135 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1136 if (err) 1137 return err; 1138 } 1139 1140 return 0; 1141 } 1142