1 /* 2 * Marvell 88E6xxx Switch Port Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/bitfield.h> 16 #include <linux/if_bridge.h> 17 #include <linux/phy.h> 18 #include <linux/phylink.h> 19 20 #include "chip.h" 21 #include "port.h" 22 #include "serdes.h" 23 24 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 25 u16 *val) 26 { 27 int addr = chip->info->port_base_addr + port; 28 29 return mv88e6xxx_read(chip, addr, reg, val); 30 } 31 32 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 33 u16 val) 34 { 35 int addr = chip->info->port_base_addr + port; 36 37 return mv88e6xxx_write(chip, addr, reg, val); 38 } 39 40 /* Offset 0x00: MAC (or PCS or Physical) Status Register 41 * 42 * For most devices, this is read only. However the 6185 has the MyPause 43 * bit read/write. 44 */ 45 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 46 int pause) 47 { 48 u16 reg; 49 int err; 50 51 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 52 if (err) 53 return err; 54 55 if (pause) 56 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; 57 else 58 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; 59 60 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 61 } 62 63 /* Offset 0x01: MAC (or PCS or Physical) Control Register 64 * 65 * Link, Duplex and Flow Control have one force bit, one value bit. 66 * 67 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. 68 * Alternative values require the 200BASE (or AltSpeed) bit 12 set. 69 * Newer chips need a ForcedSpd bit 13 set to consider the value. 70 */ 71 72 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 73 phy_interface_t mode) 74 { 75 u16 reg; 76 int err; 77 78 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 79 if (err) 80 return err; 81 82 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 83 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK); 84 85 switch (mode) { 86 case PHY_INTERFACE_MODE_RGMII_RXID: 87 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; 88 break; 89 case PHY_INTERFACE_MODE_RGMII_TXID: 90 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 91 break; 92 case PHY_INTERFACE_MODE_RGMII_ID: 93 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 94 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 95 break; 96 case PHY_INTERFACE_MODE_RGMII: 97 break; 98 default: 99 return 0; 100 } 101 102 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 103 if (err) 104 return err; 105 106 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, 107 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", 108 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); 109 110 return 0; 111 } 112 113 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 114 phy_interface_t mode) 115 { 116 if (port < 5) 117 return -EOPNOTSUPP; 118 119 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 120 } 121 122 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 123 phy_interface_t mode) 124 { 125 if (port != 0) 126 return -EOPNOTSUPP; 127 128 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 129 } 130 131 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) 132 { 133 u16 reg; 134 int err; 135 136 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 137 if (err) 138 return err; 139 140 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 141 MV88E6XXX_PORT_MAC_CTL_LINK_UP); 142 143 switch (link) { 144 case LINK_FORCED_DOWN: 145 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; 146 break; 147 case LINK_FORCED_UP: 148 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 149 MV88E6XXX_PORT_MAC_CTL_LINK_UP; 150 break; 151 case LINK_UNFORCED: 152 /* normal link detection */ 153 break; 154 default: 155 return -EINVAL; 156 } 157 158 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 159 if (err) 160 return err; 161 162 dev_dbg(chip->dev, "p%d: %s link %s\n", port, 163 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", 164 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); 165 166 return 0; 167 } 168 169 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup) 170 { 171 u16 reg; 172 int err; 173 174 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 175 if (err) 176 return err; 177 178 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 179 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); 180 181 switch (dup) { 182 case DUPLEX_HALF: 183 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 184 break; 185 case DUPLEX_FULL: 186 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 187 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 188 break; 189 case DUPLEX_UNFORCED: 190 /* normal duplex detection */ 191 break; 192 default: 193 return -EINVAL; 194 } 195 196 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 197 if (err) 198 return err; 199 200 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 201 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 202 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 203 204 return 0; 205 } 206 207 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port, 208 int speed, bool alt_bit, bool force_bit) 209 { 210 u16 reg, ctrl; 211 int err; 212 213 switch (speed) { 214 case 10: 215 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 216 break; 217 case 100: 218 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 219 break; 220 case 200: 221 if (alt_bit) 222 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 223 MV88E6390_PORT_MAC_CTL_ALTSPEED; 224 else 225 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200; 226 break; 227 case 1000: 228 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 229 break; 230 case 2500: 231 if (alt_bit) 232 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 233 MV88E6390_PORT_MAC_CTL_ALTSPEED; 234 else 235 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000; 236 break; 237 case 10000: 238 /* all bits set, fall through... */ 239 case SPEED_UNFORCED: 240 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 241 break; 242 default: 243 return -EOPNOTSUPP; 244 } 245 246 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 247 if (err) 248 return err; 249 250 reg &= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK; 251 if (alt_bit) 252 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; 253 if (force_bit) { 254 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 255 if (speed != SPEED_UNFORCED) 256 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 257 } 258 reg |= ctrl; 259 260 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 261 if (err) 262 return err; 263 264 if (speed) 265 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 266 else 267 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 268 269 return 0; 270 } 271 272 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */ 273 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 274 { 275 if (speed == SPEED_MAX) 276 speed = 200; 277 278 if (speed > 200) 279 return -EOPNOTSUPP; 280 281 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */ 282 return mv88e6xxx_port_set_speed(chip, port, speed, false, false); 283 } 284 285 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ 286 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 287 { 288 if (speed == SPEED_MAX) 289 speed = 1000; 290 291 if (speed == 200 || speed > 1000) 292 return -EOPNOTSUPP; 293 294 return mv88e6xxx_port_set_speed(chip, port, speed, false, false); 295 } 296 297 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */ 298 int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 299 { 300 if (speed == SPEED_MAX) 301 speed = port < 5 ? 1000 : 2500; 302 303 if (speed > 2500) 304 return -EOPNOTSUPP; 305 306 if (speed == 200 && port != 0) 307 return -EOPNOTSUPP; 308 309 if (speed == 2500 && port < 5) 310 return -EOPNOTSUPP; 311 312 return mv88e6xxx_port_set_speed(chip, port, speed, !port, true); 313 } 314 315 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ 316 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 317 { 318 if (speed == SPEED_MAX) 319 speed = 1000; 320 321 if (speed > 1000) 322 return -EOPNOTSUPP; 323 324 if (speed == 200 && port < 5) 325 return -EOPNOTSUPP; 326 327 return mv88e6xxx_port_set_speed(chip, port, speed, true, false); 328 } 329 330 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ 331 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 332 { 333 if (speed == SPEED_MAX) 334 speed = port < 9 ? 1000 : 2500; 335 336 if (speed > 2500) 337 return -EOPNOTSUPP; 338 339 if (speed == 200 && port != 0) 340 return -EOPNOTSUPP; 341 342 if (speed == 2500 && port < 9) 343 return -EOPNOTSUPP; 344 345 return mv88e6xxx_port_set_speed(chip, port, speed, true, true); 346 } 347 348 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ 349 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 350 { 351 if (speed == SPEED_MAX) 352 speed = port < 9 ? 1000 : 10000; 353 354 if (speed == 200 && port != 0) 355 return -EOPNOTSUPP; 356 357 if (speed >= 2500 && port < 9) 358 return -EOPNOTSUPP; 359 360 return mv88e6xxx_port_set_speed(chip, port, speed, true, true); 361 } 362 363 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 364 phy_interface_t mode) 365 { 366 int lane; 367 u16 cmode; 368 u16 reg; 369 int err; 370 371 if (port != 9 && port != 10) 372 return -EOPNOTSUPP; 373 374 /* Default to a slow mode, so freeing up SERDES interfaces for 375 * other ports which might use them for SFPs. 376 */ 377 if (mode == PHY_INTERFACE_MODE_NA) 378 mode = PHY_INTERFACE_MODE_1000BASEX; 379 380 switch (mode) { 381 case PHY_INTERFACE_MODE_1000BASEX: 382 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASE_X; 383 break; 384 case PHY_INTERFACE_MODE_SGMII: 385 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII; 386 break; 387 case PHY_INTERFACE_MODE_2500BASEX: 388 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; 389 break; 390 case PHY_INTERFACE_MODE_XGMII: 391 case PHY_INTERFACE_MODE_XAUI: 392 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; 393 break; 394 case PHY_INTERFACE_MODE_RXAUI: 395 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; 396 break; 397 default: 398 cmode = 0; 399 } 400 401 lane = mv88e6390x_serdes_get_lane(chip, port); 402 if (lane < 0) 403 return lane; 404 405 if (chip->ports[port].serdes_irq) { 406 err = mv88e6390_serdes_irq_disable(chip, port, lane); 407 if (err) 408 return err; 409 } 410 411 err = mv88e6390_serdes_power(chip, port, false); 412 if (err) 413 return err; 414 415 if (cmode) { 416 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 417 if (err) 418 return err; 419 420 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; 421 reg |= cmode; 422 423 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 424 if (err) 425 return err; 426 427 err = mv88e6390_serdes_power(chip, port, true); 428 if (err) 429 return err; 430 431 if (chip->ports[port].serdes_irq) { 432 err = mv88e6390_serdes_irq_enable(chip, port, lane); 433 if (err) 434 return err; 435 } 436 } 437 438 chip->ports[port].cmode = cmode; 439 440 return 0; 441 } 442 443 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 444 phy_interface_t mode) 445 { 446 switch (mode) { 447 case PHY_INTERFACE_MODE_XGMII: 448 case PHY_INTERFACE_MODE_XAUI: 449 case PHY_INTERFACE_MODE_RXAUI: 450 return -EINVAL; 451 default: 452 break; 453 } 454 455 return mv88e6390x_port_set_cmode(chip, port, mode); 456 } 457 458 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 459 { 460 int err; 461 u16 reg; 462 463 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 464 if (err) 465 return err; 466 467 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; 468 469 return 0; 470 } 471 472 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 473 { 474 int err; 475 u16 reg; 476 477 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 478 if (err) 479 return err; 480 481 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; 482 483 return 0; 484 } 485 486 int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port, 487 struct phylink_link_state *state) 488 { 489 int err; 490 u16 reg; 491 492 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 493 if (err) 494 return err; 495 496 switch (reg & MV88E6XXX_PORT_STS_SPEED_MASK) { 497 case MV88E6XXX_PORT_STS_SPEED_10: 498 state->speed = SPEED_10; 499 break; 500 case MV88E6XXX_PORT_STS_SPEED_100: 501 state->speed = SPEED_100; 502 break; 503 case MV88E6XXX_PORT_STS_SPEED_1000: 504 state->speed = SPEED_1000; 505 break; 506 case MV88E6XXX_PORT_STS_SPEED_10000: 507 if ((reg & MV88E6XXX_PORT_STS_CMODE_MASK) == 508 MV88E6XXX_PORT_STS_CMODE_2500BASEX) 509 state->speed = SPEED_2500; 510 else 511 state->speed = SPEED_10000; 512 break; 513 } 514 515 state->duplex = reg & MV88E6XXX_PORT_STS_DUPLEX ? 516 DUPLEX_FULL : DUPLEX_HALF; 517 state->link = !!(reg & MV88E6XXX_PORT_STS_LINK); 518 state->an_enabled = 1; 519 state->an_complete = state->link; 520 521 return 0; 522 } 523 524 int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port, 525 struct phylink_link_state *state) 526 { 527 if (state->interface == PHY_INTERFACE_MODE_1000BASEX) { 528 u8 cmode = chip->ports[port].cmode; 529 530 /* When a port is in "Cross-chip serdes" mode, it uses 531 * 1000Base-X full duplex mode, but there is no automatic 532 * link detection. Use the sync OK status for link (as it 533 * would do for 1000Base-X mode.) 534 */ 535 if (cmode == MV88E6185_PORT_STS_CMODE_SERDES) { 536 u16 mac; 537 int err; 538 539 err = mv88e6xxx_port_read(chip, port, 540 MV88E6XXX_PORT_MAC_CTL, &mac); 541 if (err) 542 return err; 543 544 state->link = !!(mac & MV88E6185_PORT_MAC_CTL_SYNC_OK); 545 state->an_enabled = 1; 546 state->an_complete = 547 !!(mac & MV88E6185_PORT_MAC_CTL_AN_DONE); 548 state->duplex = 549 state->link ? DUPLEX_FULL : DUPLEX_UNKNOWN; 550 state->speed = 551 state->link ? SPEED_1000 : SPEED_UNKNOWN; 552 553 return 0; 554 } 555 } 556 557 return mv88e6352_port_link_state(chip, port, state); 558 } 559 560 /* Offset 0x02: Jamming Control 561 * 562 * Do not limit the period of time that this port can be paused for by 563 * the remote end or the period of time that this port can pause the 564 * remote end. 565 */ 566 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 567 u8 out) 568 { 569 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, 570 out << 8 | in); 571 } 572 573 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 574 u8 out) 575 { 576 int err; 577 578 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 579 MV88E6390_PORT_FLOW_CTL_UPDATE | 580 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in); 581 if (err) 582 return err; 583 584 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 585 MV88E6390_PORT_FLOW_CTL_UPDATE | 586 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out); 587 } 588 589 /* Offset 0x04: Port Control Register */ 590 591 static const char * const mv88e6xxx_port_state_names[] = { 592 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", 593 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", 594 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", 595 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", 596 }; 597 598 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) 599 { 600 u16 reg; 601 int err; 602 603 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 604 if (err) 605 return err; 606 607 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; 608 609 switch (state) { 610 case BR_STATE_DISABLED: 611 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED; 612 break; 613 case BR_STATE_BLOCKING: 614 case BR_STATE_LISTENING: 615 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 616 break; 617 case BR_STATE_LEARNING: 618 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 619 break; 620 case BR_STATE_FORWARDING: 621 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 622 break; 623 default: 624 return -EINVAL; 625 } 626 627 reg |= state; 628 629 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 630 if (err) 631 return err; 632 633 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, 634 mv88e6xxx_port_state_names[state]); 635 636 return 0; 637 } 638 639 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 640 enum mv88e6xxx_egress_mode mode) 641 { 642 int err; 643 u16 reg; 644 645 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 646 if (err) 647 return err; 648 649 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; 650 651 switch (mode) { 652 case MV88E6XXX_EGRESS_MODE_UNMODIFIED: 653 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; 654 break; 655 case MV88E6XXX_EGRESS_MODE_UNTAGGED: 656 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; 657 break; 658 case MV88E6XXX_EGRESS_MODE_TAGGED: 659 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; 660 break; 661 case MV88E6XXX_EGRESS_MODE_ETHERTYPE: 662 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; 663 break; 664 default: 665 return -EINVAL; 666 } 667 668 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 669 } 670 671 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 672 enum mv88e6xxx_frame_mode mode) 673 { 674 int err; 675 u16 reg; 676 677 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 678 if (err) 679 return err; 680 681 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 682 683 switch (mode) { 684 case MV88E6XXX_FRAME_MODE_NORMAL: 685 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 686 break; 687 case MV88E6XXX_FRAME_MODE_DSA: 688 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 689 break; 690 default: 691 return -EINVAL; 692 } 693 694 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 695 } 696 697 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 698 enum mv88e6xxx_frame_mode mode) 699 { 700 int err; 701 u16 reg; 702 703 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 704 if (err) 705 return err; 706 707 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 708 709 switch (mode) { 710 case MV88E6XXX_FRAME_MODE_NORMAL: 711 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 712 break; 713 case MV88E6XXX_FRAME_MODE_DSA: 714 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 715 break; 716 case MV88E6XXX_FRAME_MODE_PROVIDER: 717 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; 718 break; 719 case MV88E6XXX_FRAME_MODE_ETHERTYPE: 720 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; 721 break; 722 default: 723 return -EINVAL; 724 } 725 726 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 727 } 728 729 static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 730 int port, bool unicast) 731 { 732 int err; 733 u16 reg; 734 735 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 736 if (err) 737 return err; 738 739 if (unicast) 740 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 741 else 742 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 743 744 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 745 } 746 747 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 748 bool unicast, bool multicast) 749 { 750 int err; 751 u16 reg; 752 753 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 754 if (err) 755 return err; 756 757 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK; 758 759 if (unicast && multicast) 760 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA; 761 else if (unicast) 762 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA; 763 else if (multicast) 764 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA; 765 else 766 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA; 767 768 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 769 } 770 771 /* Offset 0x05: Port Control 1 */ 772 773 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 774 bool message_port) 775 { 776 u16 val; 777 int err; 778 779 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 780 if (err) 781 return err; 782 783 if (message_port) 784 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 785 else 786 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 787 788 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 789 } 790 791 /* Offset 0x06: Port Based VLAN Map */ 792 793 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) 794 { 795 const u16 mask = mv88e6xxx_port_mask(chip); 796 u16 reg; 797 int err; 798 799 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 800 if (err) 801 return err; 802 803 reg &= ~mask; 804 reg |= map & mask; 805 806 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 807 if (err) 808 return err; 809 810 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); 811 812 return 0; 813 } 814 815 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) 816 { 817 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 818 u16 reg; 819 int err; 820 821 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 822 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 823 if (err) 824 return err; 825 826 *fid = (reg & 0xf000) >> 12; 827 828 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 829 if (upper_mask) { 830 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 831 ®); 832 if (err) 833 return err; 834 835 *fid |= (reg & upper_mask) << 4; 836 } 837 838 return 0; 839 } 840 841 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) 842 { 843 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 844 u16 reg; 845 int err; 846 847 if (fid >= mv88e6xxx_num_databases(chip)) 848 return -EINVAL; 849 850 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 851 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 852 if (err) 853 return err; 854 855 reg &= 0x0fff; 856 reg |= (fid & 0x000f) << 12; 857 858 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 859 if (err) 860 return err; 861 862 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 863 if (upper_mask) { 864 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 865 ®); 866 if (err) 867 return err; 868 869 reg &= ~upper_mask; 870 reg |= (fid >> 4) & upper_mask; 871 872 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, 873 reg); 874 if (err) 875 return err; 876 } 877 878 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); 879 880 return 0; 881 } 882 883 /* Offset 0x07: Default Port VLAN ID & Priority */ 884 885 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) 886 { 887 u16 reg; 888 int err; 889 890 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 891 ®); 892 if (err) 893 return err; 894 895 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 896 897 return 0; 898 } 899 900 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) 901 { 902 u16 reg; 903 int err; 904 905 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 906 ®); 907 if (err) 908 return err; 909 910 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 911 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 912 913 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 914 reg); 915 if (err) 916 return err; 917 918 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); 919 920 return 0; 921 } 922 923 /* Offset 0x08: Port Control 2 Register */ 924 925 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 926 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", 927 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", 928 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", 929 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", 930 }; 931 932 static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 933 int port, bool multicast) 934 { 935 int err; 936 u16 reg; 937 938 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 939 if (err) 940 return err; 941 942 if (multicast) 943 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 944 else 945 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 946 947 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 948 } 949 950 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, 951 bool unicast, bool multicast) 952 { 953 int err; 954 955 err = mv88e6185_port_set_forward_unknown(chip, port, unicast); 956 if (err) 957 return err; 958 959 return mv88e6185_port_set_default_forward(chip, port, multicast); 960 } 961 962 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 963 int upstream_port) 964 { 965 int err; 966 u16 reg; 967 968 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 969 if (err) 970 return err; 971 972 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; 973 reg |= upstream_port; 974 975 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 976 } 977 978 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 979 u16 mode) 980 { 981 u16 reg; 982 int err; 983 984 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 985 if (err) 986 return err; 987 988 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 989 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 990 991 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 992 if (err) 993 return err; 994 995 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, 996 mv88e6xxx_port_8021q_mode_names[mode]); 997 998 return 0; 999 } 1000 1001 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port) 1002 { 1003 u16 reg; 1004 int err; 1005 1006 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1007 if (err) 1008 return err; 1009 1010 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; 1011 1012 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1013 } 1014 1015 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 1016 size_t size) 1017 { 1018 u16 reg; 1019 int err; 1020 1021 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1022 if (err) 1023 return err; 1024 1025 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; 1026 1027 if (size <= 1522) 1028 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; 1029 else if (size <= 2048) 1030 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; 1031 else if (size <= 10240) 1032 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; 1033 else 1034 return -ERANGE; 1035 1036 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1037 } 1038 1039 /* Offset 0x09: Port Rate Control */ 1040 1041 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1042 { 1043 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1044 0x0000); 1045 } 1046 1047 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1048 { 1049 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1050 0x0001); 1051 } 1052 1053 /* Offset 0x0C: Port ATU Control */ 1054 1055 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) 1056 { 1057 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); 1058 } 1059 1060 /* Offset 0x0D: (Priority) Override Register */ 1061 1062 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) 1063 { 1064 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); 1065 } 1066 1067 /* Offset 0x0f: Port Ether type */ 1068 1069 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1070 u16 etype) 1071 { 1072 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); 1073 } 1074 1075 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] 1076 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] 1077 */ 1078 1079 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1080 { 1081 int err; 1082 1083 /* Use a direct priority mapping for all IEEE tagged frames */ 1084 err = mv88e6xxx_port_write(chip, port, 1085 MV88E6095_PORT_IEEE_PRIO_REMAP_0123, 1086 0x3210); 1087 if (err) 1088 return err; 1089 1090 return mv88e6xxx_port_write(chip, port, 1091 MV88E6095_PORT_IEEE_PRIO_REMAP_4567, 1092 0x7654); 1093 } 1094 1095 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, 1096 int port, u16 table, u8 ptr, u16 data) 1097 { 1098 u16 reg; 1099 1100 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | 1101 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | 1102 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK); 1103 1104 return mv88e6xxx_port_write(chip, port, 1105 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); 1106 } 1107 1108 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1109 { 1110 int err, i; 1111 u16 table; 1112 1113 for (i = 0; i <= 7; i++) { 1114 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; 1115 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, 1116 (i | i << 4)); 1117 if (err) 1118 return err; 1119 1120 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP; 1121 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1122 if (err) 1123 return err; 1124 1125 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP; 1126 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1127 if (err) 1128 return err; 1129 1130 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP; 1131 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1132 if (err) 1133 return err; 1134 } 1135 1136 return 0; 1137 } 1138