1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Port Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/if_bridge.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 16 #include "chip.h" 17 #include "global2.h" 18 #include "port.h" 19 #include "serdes.h" 20 21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 22 u16 *val) 23 { 24 int addr = chip->info->port_base_addr + port; 25 26 return mv88e6xxx_read(chip, addr, reg, val); 27 } 28 29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, 30 int bit, int val) 31 { 32 int addr = chip->info->port_base_addr + port; 33 34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); 35 } 36 37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 38 u16 val) 39 { 40 int addr = chip->info->port_base_addr + port; 41 42 return mv88e6xxx_write(chip, addr, reg, val); 43 } 44 45 /* Offset 0x00: MAC (or PCS or Physical) Status Register 46 * 47 * For most devices, this is read only. However the 6185 has the MyPause 48 * bit read/write. 49 */ 50 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 51 int pause) 52 { 53 u16 reg; 54 int err; 55 56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 57 if (err) 58 return err; 59 60 if (pause) 61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; 62 else 63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; 64 65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 66 } 67 68 /* Offset 0x01: MAC (or PCS or Physical) Control Register 69 * 70 * Link, Duplex and Flow Control have one force bit, one value bit. 71 * 72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. 73 * Alternative values require the 200BASE (or AltSpeed) bit 12 set. 74 * Newer chips need a ForcedSpd bit 13 set to consider the value. 75 */ 76 77 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 78 phy_interface_t mode) 79 { 80 u16 reg; 81 int err; 82 83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 84 if (err) 85 return err; 86 87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 88 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK); 89 90 switch (mode) { 91 case PHY_INTERFACE_MODE_RGMII_RXID: 92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; 93 break; 94 case PHY_INTERFACE_MODE_RGMII_TXID: 95 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 96 break; 97 case PHY_INTERFACE_MODE_RGMII_ID: 98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 99 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 100 break; 101 case PHY_INTERFACE_MODE_RGMII: 102 break; 103 default: 104 return 0; 105 } 106 107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 108 if (err) 109 return err; 110 111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, 112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", 113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); 114 115 return 0; 116 } 117 118 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 119 phy_interface_t mode) 120 { 121 if (port < 5) 122 return -EOPNOTSUPP; 123 124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 125 } 126 127 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 128 phy_interface_t mode) 129 { 130 if (port != 0) 131 return -EOPNOTSUPP; 132 133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 134 } 135 136 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) 137 { 138 u16 reg; 139 int err; 140 141 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 142 if (err) 143 return err; 144 145 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 146 MV88E6XXX_PORT_MAC_CTL_LINK_UP); 147 148 switch (link) { 149 case LINK_FORCED_DOWN: 150 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; 151 break; 152 case LINK_FORCED_UP: 153 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 154 MV88E6XXX_PORT_MAC_CTL_LINK_UP; 155 break; 156 case LINK_UNFORCED: 157 /* normal link detection */ 158 break; 159 default: 160 return -EINVAL; 161 } 162 163 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 164 if (err) 165 return err; 166 167 dev_dbg(chip->dev, "p%d: %s link %s\n", port, 168 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", 169 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); 170 171 return 0; 172 } 173 174 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 175 { 176 const struct mv88e6xxx_ops *ops = chip->info->ops; 177 int err = 0; 178 int link; 179 180 if (isup) 181 link = LINK_FORCED_UP; 182 else 183 link = LINK_FORCED_DOWN; 184 185 if (ops->port_set_link) 186 err = ops->port_set_link(chip, port, link); 187 188 return err; 189 } 190 191 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 192 { 193 const struct mv88e6xxx_ops *ops = chip->info->ops; 194 int err = 0; 195 int link; 196 197 if (mode == MLO_AN_INBAND) 198 link = LINK_UNFORCED; 199 else if (isup) 200 link = LINK_FORCED_UP; 201 else 202 link = LINK_FORCED_DOWN; 203 204 if (ops->port_set_link) 205 err = ops->port_set_link(chip, port, link); 206 207 return err; 208 } 209 210 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip, 211 int port, int speed, bool alt_bit, 212 bool force_bit, int duplex) 213 { 214 u16 reg, ctrl; 215 int err; 216 217 switch (speed) { 218 case 10: 219 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 220 break; 221 case 100: 222 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 223 break; 224 case 200: 225 if (alt_bit) 226 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 227 MV88E6390_PORT_MAC_CTL_ALTSPEED; 228 else 229 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200; 230 break; 231 case 1000: 232 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 233 break; 234 case 2500: 235 if (alt_bit) 236 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 237 MV88E6390_PORT_MAC_CTL_ALTSPEED; 238 else 239 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000; 240 break; 241 case 10000: 242 /* all bits set, fall through... */ 243 case SPEED_UNFORCED: 244 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 245 break; 246 default: 247 return -EOPNOTSUPP; 248 } 249 250 switch (duplex) { 251 case DUPLEX_HALF: 252 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 253 break; 254 case DUPLEX_FULL: 255 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 256 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 257 break; 258 case DUPLEX_UNFORCED: 259 /* normal duplex detection */ 260 break; 261 default: 262 return -EOPNOTSUPP; 263 } 264 265 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 266 if (err) 267 return err; 268 269 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 270 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 271 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); 272 273 if (alt_bit) 274 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; 275 if (force_bit) { 276 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 277 if (speed != SPEED_UNFORCED) 278 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 279 } 280 reg |= ctrl; 281 282 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 283 if (err) 284 return err; 285 286 if (speed != SPEED_UNFORCED) 287 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 288 else 289 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 290 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 291 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 292 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 293 294 return 0; 295 } 296 297 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ 298 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 299 int speed, int duplex) 300 { 301 if (speed == SPEED_MAX) 302 speed = 1000; 303 304 if (speed == 200 || speed > 1000) 305 return -EOPNOTSUPP; 306 307 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 308 duplex); 309 } 310 311 /* Support 10, 100 Mbps (e.g. 88E6250 family) */ 312 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 313 int speed, int duplex) 314 { 315 if (speed == SPEED_MAX) 316 speed = 100; 317 318 if (speed > 100) 319 return -EOPNOTSUPP; 320 321 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 322 duplex); 323 } 324 325 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */ 326 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 327 int speed, int duplex) 328 { 329 if (speed == SPEED_MAX) 330 speed = port < 5 ? 1000 : 2500; 331 332 if (speed > 2500) 333 return -EOPNOTSUPP; 334 335 if (speed == 200 && port != 0) 336 return -EOPNOTSUPP; 337 338 if (speed == 2500 && port < 5) 339 return -EOPNOTSUPP; 340 341 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true, 342 duplex); 343 } 344 345 phy_interface_t mv88e6341_port_max_speed_mode(int port) 346 { 347 if (port == 5) 348 return PHY_INTERFACE_MODE_2500BASEX; 349 350 return PHY_INTERFACE_MODE_NA; 351 } 352 353 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ 354 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 355 int speed, int duplex) 356 { 357 if (speed == SPEED_MAX) 358 speed = 1000; 359 360 if (speed > 1000) 361 return -EOPNOTSUPP; 362 363 if (speed == 200 && port < 5) 364 return -EOPNOTSUPP; 365 366 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false, 367 duplex); 368 } 369 370 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ 371 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 372 int speed, int duplex) 373 { 374 if (speed == SPEED_MAX) 375 speed = port < 9 ? 1000 : 2500; 376 377 if (speed > 2500) 378 return -EOPNOTSUPP; 379 380 if (speed == 200 && port != 0) 381 return -EOPNOTSUPP; 382 383 if (speed == 2500 && port < 9) 384 return -EOPNOTSUPP; 385 386 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 387 duplex); 388 } 389 390 phy_interface_t mv88e6390_port_max_speed_mode(int port) 391 { 392 if (port == 9 || port == 10) 393 return PHY_INTERFACE_MODE_2500BASEX; 394 395 return PHY_INTERFACE_MODE_NA; 396 } 397 398 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ 399 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 400 int speed, int duplex) 401 { 402 if (speed == SPEED_MAX) 403 speed = port < 9 ? 1000 : 10000; 404 405 if (speed == 200 && port != 0) 406 return -EOPNOTSUPP; 407 408 if (speed >= 2500 && port < 9) 409 return -EOPNOTSUPP; 410 411 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 412 duplex); 413 } 414 415 phy_interface_t mv88e6390x_port_max_speed_mode(int port) 416 { 417 if (port == 9 || port == 10) 418 return PHY_INTERFACE_MODE_XAUI; 419 420 return PHY_INTERFACE_MODE_NA; 421 } 422 423 /* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X) 424 * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register 425 * values for speeds 2500 & 5000 conflict. 426 */ 427 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 428 int speed, int duplex) 429 { 430 u16 reg, ctrl; 431 int err; 432 433 if (speed == SPEED_MAX) 434 speed = (port > 0 && port < 9) ? 1000 : 10000; 435 436 if (speed == 200 && port != 0) 437 return -EOPNOTSUPP; 438 439 if (speed >= 2500 && port > 0 && port < 9) 440 return -EOPNOTSUPP; 441 442 switch (speed) { 443 case 10: 444 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 445 break; 446 case 100: 447 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 448 break; 449 case 200: 450 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 451 MV88E6390_PORT_MAC_CTL_ALTSPEED; 452 break; 453 case 1000: 454 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 455 break; 456 case 2500: 457 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 | 458 MV88E6390_PORT_MAC_CTL_ALTSPEED; 459 break; 460 case 5000: 461 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 462 MV88E6390_PORT_MAC_CTL_ALTSPEED; 463 break; 464 case 10000: 465 case SPEED_UNFORCED: 466 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 467 break; 468 default: 469 return -EOPNOTSUPP; 470 } 471 472 switch (duplex) { 473 case DUPLEX_HALF: 474 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 475 break; 476 case DUPLEX_FULL: 477 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 478 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 479 break; 480 case DUPLEX_UNFORCED: 481 /* normal duplex detection */ 482 break; 483 default: 484 return -EOPNOTSUPP; 485 } 486 487 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 488 if (err) 489 return err; 490 491 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 492 MV88E6390_PORT_MAC_CTL_ALTSPEED | 493 MV88E6390_PORT_MAC_CTL_FORCE_SPEED); 494 495 if (speed != SPEED_UNFORCED) 496 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 497 498 reg |= ctrl; 499 500 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 501 if (err) 502 return err; 503 504 if (speed != SPEED_UNFORCED) 505 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 506 else 507 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 508 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 509 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 510 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 511 512 return 0; 513 } 514 515 phy_interface_t mv88e6393x_port_max_speed_mode(int port) 516 { 517 if (port == 0 || port == 9 || port == 10) 518 return PHY_INTERFACE_MODE_10GBASER; 519 520 return PHY_INTERFACE_MODE_NA; 521 } 522 523 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 524 phy_interface_t mode, bool force) 525 { 526 u16 cmode; 527 int lane; 528 u16 reg; 529 int err; 530 531 /* Default to a slow mode, so freeing up SERDES interfaces for 532 * other ports which might use them for SFPs. 533 */ 534 if (mode == PHY_INTERFACE_MODE_NA) 535 mode = PHY_INTERFACE_MODE_1000BASEX; 536 537 switch (mode) { 538 case PHY_INTERFACE_MODE_RMII: 539 cmode = MV88E6XXX_PORT_STS_CMODE_RMII; 540 break; 541 case PHY_INTERFACE_MODE_1000BASEX: 542 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX; 543 break; 544 case PHY_INTERFACE_MODE_SGMII: 545 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII; 546 break; 547 case PHY_INTERFACE_MODE_2500BASEX: 548 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; 549 break; 550 case PHY_INTERFACE_MODE_5GBASER: 551 cmode = MV88E6393X_PORT_STS_CMODE_5GBASER; 552 break; 553 case PHY_INTERFACE_MODE_XGMII: 554 case PHY_INTERFACE_MODE_XAUI: 555 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; 556 break; 557 case PHY_INTERFACE_MODE_RXAUI: 558 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; 559 break; 560 case PHY_INTERFACE_MODE_10GBASER: 561 cmode = MV88E6393X_PORT_STS_CMODE_10GBASER; 562 break; 563 default: 564 cmode = 0; 565 } 566 567 /* cmode doesn't change, nothing to do for us unless forced */ 568 if (cmode == chip->ports[port].cmode && !force) 569 return 0; 570 571 lane = mv88e6xxx_serdes_get_lane(chip, port); 572 if (lane >= 0) { 573 if (chip->ports[port].serdes_irq) { 574 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 575 if (err) 576 return err; 577 } 578 579 err = mv88e6xxx_serdes_power_down(chip, port, lane); 580 if (err) 581 return err; 582 } 583 584 chip->ports[port].cmode = 0; 585 586 if (cmode) { 587 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 588 if (err) 589 return err; 590 591 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; 592 reg |= cmode; 593 594 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 595 if (err) 596 return err; 597 598 chip->ports[port].cmode = cmode; 599 600 lane = mv88e6xxx_serdes_get_lane(chip, port); 601 if (lane == -ENODEV) 602 return 0; 603 if (lane < 0) 604 return lane; 605 606 err = mv88e6xxx_serdes_power_up(chip, port, lane); 607 if (err) 608 return err; 609 610 if (chip->ports[port].serdes_irq) { 611 err = mv88e6xxx_serdes_irq_enable(chip, port, lane); 612 if (err) 613 return err; 614 } 615 } 616 617 return 0; 618 } 619 620 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 621 phy_interface_t mode) 622 { 623 if (port != 9 && port != 10) 624 return -EOPNOTSUPP; 625 626 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 627 } 628 629 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 630 phy_interface_t mode) 631 { 632 if (port != 9 && port != 10) 633 return -EOPNOTSUPP; 634 635 switch (mode) { 636 case PHY_INTERFACE_MODE_NA: 637 return 0; 638 case PHY_INTERFACE_MODE_XGMII: 639 case PHY_INTERFACE_MODE_XAUI: 640 case PHY_INTERFACE_MODE_RXAUI: 641 return -EINVAL; 642 default: 643 break; 644 } 645 646 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 647 } 648 649 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 650 phy_interface_t mode) 651 { 652 int err; 653 u16 reg; 654 655 if (port != 0 && port != 9 && port != 10) 656 return -EOPNOTSUPP; 657 658 /* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */ 659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 660 if (err) 661 return err; 662 663 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE; 664 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE; 665 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 666 if (err) 667 return err; 668 669 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 670 } 671 672 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip, 673 int port) 674 { 675 int err, addr; 676 u16 reg, bits; 677 678 if (port != 5) 679 return -EOPNOTSUPP; 680 681 addr = chip->info->port_base_addr + port; 682 683 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); 684 if (err) 685 return err; 686 687 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE | 688 MV88E6341_PORT_RESERVED_1A_SGMII_AN; 689 690 if ((reg & bits) == bits) 691 return 0; 692 693 reg |= bits; 694 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); 695 } 696 697 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 698 phy_interface_t mode) 699 { 700 int err; 701 702 if (port != 5) 703 return -EOPNOTSUPP; 704 705 switch (mode) { 706 case PHY_INTERFACE_MODE_NA: 707 return 0; 708 case PHY_INTERFACE_MODE_XGMII: 709 case PHY_INTERFACE_MODE_XAUI: 710 case PHY_INTERFACE_MODE_RXAUI: 711 return -EINVAL; 712 default: 713 break; 714 } 715 716 err = mv88e6341_port_set_cmode_writable(chip, port); 717 if (err) 718 return err; 719 720 return mv88e6xxx_port_set_cmode(chip, port, mode, true); 721 } 722 723 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 724 { 725 int err; 726 u16 reg; 727 728 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 729 if (err) 730 return err; 731 732 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; 733 734 return 0; 735 } 736 737 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 738 { 739 int err; 740 u16 reg; 741 742 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 743 if (err) 744 return err; 745 746 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; 747 748 return 0; 749 } 750 751 /* Offset 0x02: Jamming Control 752 * 753 * Do not limit the period of time that this port can be paused for by 754 * the remote end or the period of time that this port can pause the 755 * remote end. 756 */ 757 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 758 u8 out) 759 { 760 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, 761 out << 8 | in); 762 } 763 764 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 765 u8 out) 766 { 767 int err; 768 769 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 770 MV88E6390_PORT_FLOW_CTL_UPDATE | 771 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in); 772 if (err) 773 return err; 774 775 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 776 MV88E6390_PORT_FLOW_CTL_UPDATE | 777 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out); 778 } 779 780 /* Offset 0x04: Port Control Register */ 781 782 static const char * const mv88e6xxx_port_state_names[] = { 783 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", 784 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", 785 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", 786 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", 787 }; 788 789 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) 790 { 791 u16 reg; 792 int err; 793 794 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 795 if (err) 796 return err; 797 798 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; 799 800 switch (state) { 801 case BR_STATE_DISABLED: 802 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED; 803 break; 804 case BR_STATE_BLOCKING: 805 case BR_STATE_LISTENING: 806 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 807 break; 808 case BR_STATE_LEARNING: 809 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 810 break; 811 case BR_STATE_FORWARDING: 812 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 813 break; 814 default: 815 return -EINVAL; 816 } 817 818 reg |= state; 819 820 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 821 if (err) 822 return err; 823 824 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, 825 mv88e6xxx_port_state_names[state]); 826 827 return 0; 828 } 829 830 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 831 enum mv88e6xxx_egress_mode mode) 832 { 833 int err; 834 u16 reg; 835 836 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 837 if (err) 838 return err; 839 840 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; 841 842 switch (mode) { 843 case MV88E6XXX_EGRESS_MODE_UNMODIFIED: 844 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; 845 break; 846 case MV88E6XXX_EGRESS_MODE_UNTAGGED: 847 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; 848 break; 849 case MV88E6XXX_EGRESS_MODE_TAGGED: 850 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; 851 break; 852 case MV88E6XXX_EGRESS_MODE_ETHERTYPE: 853 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; 854 break; 855 default: 856 return -EINVAL; 857 } 858 859 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 860 } 861 862 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 863 enum mv88e6xxx_frame_mode mode) 864 { 865 int err; 866 u16 reg; 867 868 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 869 if (err) 870 return err; 871 872 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 873 874 switch (mode) { 875 case MV88E6XXX_FRAME_MODE_NORMAL: 876 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 877 break; 878 case MV88E6XXX_FRAME_MODE_DSA: 879 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 880 break; 881 default: 882 return -EINVAL; 883 } 884 885 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 886 } 887 888 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 889 enum mv88e6xxx_frame_mode mode) 890 { 891 int err; 892 u16 reg; 893 894 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 895 if (err) 896 return err; 897 898 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 899 900 switch (mode) { 901 case MV88E6XXX_FRAME_MODE_NORMAL: 902 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 903 break; 904 case MV88E6XXX_FRAME_MODE_DSA: 905 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 906 break; 907 case MV88E6XXX_FRAME_MODE_PROVIDER: 908 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; 909 break; 910 case MV88E6XXX_FRAME_MODE_ETHERTYPE: 911 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; 912 break; 913 default: 914 return -EINVAL; 915 } 916 917 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 918 } 919 920 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 921 int port, bool unicast) 922 { 923 int err; 924 u16 reg; 925 926 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 927 if (err) 928 return err; 929 930 if (unicast) 931 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 932 else 933 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 934 935 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 936 } 937 938 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, 939 bool unicast) 940 { 941 int err; 942 u16 reg; 943 944 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 945 if (err) 946 return err; 947 948 if (unicast) 949 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 950 else 951 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 952 953 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 954 } 955 956 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, 957 bool multicast) 958 { 959 int err; 960 u16 reg; 961 962 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 963 if (err) 964 return err; 965 966 if (multicast) 967 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 968 else 969 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 970 971 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 972 } 973 974 /* Offset 0x05: Port Control 1 */ 975 976 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 977 bool message_port) 978 { 979 u16 val; 980 int err; 981 982 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 983 if (err) 984 return err; 985 986 if (message_port) 987 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 988 else 989 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 990 991 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 992 } 993 994 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, 995 bool trunk, u8 id) 996 { 997 u16 val; 998 int err; 999 1000 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 1001 if (err) 1002 return err; 1003 1004 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK; 1005 1006 if (trunk) 1007 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT | 1008 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT); 1009 else 1010 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT; 1011 1012 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 1013 } 1014 1015 /* Offset 0x06: Port Based VLAN Map */ 1016 1017 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) 1018 { 1019 const u16 mask = mv88e6xxx_port_mask(chip); 1020 u16 reg; 1021 int err; 1022 1023 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1024 if (err) 1025 return err; 1026 1027 reg &= ~mask; 1028 reg |= map & mask; 1029 1030 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1031 if (err) 1032 return err; 1033 1034 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); 1035 1036 return 0; 1037 } 1038 1039 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) 1040 { 1041 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1042 u16 reg; 1043 int err; 1044 1045 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1046 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1047 if (err) 1048 return err; 1049 1050 *fid = (reg & 0xf000) >> 12; 1051 1052 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1053 if (upper_mask) { 1054 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1055 ®); 1056 if (err) 1057 return err; 1058 1059 *fid |= (reg & upper_mask) << 4; 1060 } 1061 1062 return 0; 1063 } 1064 1065 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) 1066 { 1067 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1068 u16 reg; 1069 int err; 1070 1071 if (fid >= mv88e6xxx_num_databases(chip)) 1072 return -EINVAL; 1073 1074 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1075 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1076 if (err) 1077 return err; 1078 1079 reg &= 0x0fff; 1080 reg |= (fid & 0x000f) << 12; 1081 1082 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1083 if (err) 1084 return err; 1085 1086 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1087 if (upper_mask) { 1088 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1089 ®); 1090 if (err) 1091 return err; 1092 1093 reg &= ~upper_mask; 1094 reg |= (fid >> 4) & upper_mask; 1095 1096 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, 1097 reg); 1098 if (err) 1099 return err; 1100 } 1101 1102 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); 1103 1104 return 0; 1105 } 1106 1107 /* Offset 0x07: Default Port VLAN ID & Priority */ 1108 1109 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) 1110 { 1111 u16 reg; 1112 int err; 1113 1114 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1115 ®); 1116 if (err) 1117 return err; 1118 1119 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1120 1121 return 0; 1122 } 1123 1124 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) 1125 { 1126 u16 reg; 1127 int err; 1128 1129 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1130 ®); 1131 if (err) 1132 return err; 1133 1134 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1135 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1136 1137 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1138 reg); 1139 if (err) 1140 return err; 1141 1142 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); 1143 1144 return 0; 1145 } 1146 1147 /* Offset 0x08: Port Control 2 Register */ 1148 1149 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 1150 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", 1151 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", 1152 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", 1153 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", 1154 }; 1155 1156 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 1157 int port, bool multicast) 1158 { 1159 int err; 1160 u16 reg; 1161 1162 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1163 if (err) 1164 return err; 1165 1166 if (multicast) 1167 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1168 else 1169 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1170 1171 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1172 } 1173 1174 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1175 int upstream_port) 1176 { 1177 int err; 1178 u16 reg; 1179 1180 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1181 if (err) 1182 return err; 1183 1184 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; 1185 reg |= upstream_port; 1186 1187 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1188 } 1189 1190 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 1191 enum mv88e6xxx_egress_direction direction, 1192 bool mirror) 1193 { 1194 bool *mirror_port; 1195 u16 reg; 1196 u16 bit; 1197 int err; 1198 1199 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1200 if (err) 1201 return err; 1202 1203 switch (direction) { 1204 case MV88E6XXX_EGRESS_DIR_INGRESS: 1205 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR; 1206 mirror_port = &chip->ports[port].mirror_ingress; 1207 break; 1208 case MV88E6XXX_EGRESS_DIR_EGRESS: 1209 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR; 1210 mirror_port = &chip->ports[port].mirror_egress; 1211 break; 1212 default: 1213 return -EINVAL; 1214 } 1215 1216 reg &= ~bit; 1217 if (mirror) 1218 reg |= bit; 1219 1220 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1221 if (!err) 1222 *mirror_port = mirror; 1223 1224 return err; 1225 } 1226 1227 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, 1228 bool locked) 1229 { 1230 u16 reg; 1231 int err; 1232 1233 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 1234 if (err) 1235 return err; 1236 1237 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK; 1238 if (locked) 1239 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK; 1240 1241 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1242 if (err) 1243 return err; 1244 1245 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®); 1246 if (err) 1247 return err; 1248 1249 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1250 if (locked) 1251 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1252 1253 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg); 1254 } 1255 1256 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 1257 u16 mode) 1258 { 1259 u16 reg; 1260 int err; 1261 1262 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1263 if (err) 1264 return err; 1265 1266 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1267 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1268 1269 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1270 if (err) 1271 return err; 1272 1273 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, 1274 mv88e6xxx_port_8021q_mode_names[mode]); 1275 1276 return 0; 1277 } 1278 1279 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, 1280 bool drop_untagged) 1281 { 1282 u16 old, new; 1283 int err; 1284 1285 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old); 1286 if (err) 1287 return err; 1288 1289 if (drop_untagged) 1290 new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1291 else 1292 new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1293 1294 if (new == old) 1295 return 0; 1296 1297 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new); 1298 } 1299 1300 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map) 1301 { 1302 u16 reg; 1303 int err; 1304 1305 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1306 if (err) 1307 return err; 1308 1309 if (map) 1310 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; 1311 else 1312 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA; 1313 1314 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1315 } 1316 1317 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 1318 size_t size) 1319 { 1320 u16 reg; 1321 int err; 1322 1323 size += VLAN_ETH_HLEN + ETH_FCS_LEN; 1324 1325 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1326 if (err) 1327 return err; 1328 1329 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; 1330 1331 if (size <= 1522) 1332 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; 1333 else if (size <= 2048) 1334 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; 1335 else if (size <= 10240) 1336 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; 1337 else 1338 return -ERANGE; 1339 1340 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1341 } 1342 1343 /* Offset 0x09: Port Rate Control */ 1344 1345 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1346 { 1347 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1348 0x0000); 1349 } 1350 1351 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1352 { 1353 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1354 0x0001); 1355 } 1356 1357 /* Offset 0x0B: Port Association Vector */ 1358 1359 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, 1360 u16 pav) 1361 { 1362 u16 reg, mask; 1363 int err; 1364 1365 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1366 ®); 1367 if (err) 1368 return err; 1369 1370 mask = mv88e6xxx_port_mask(chip); 1371 reg &= ~mask; 1372 reg |= pav & mask; 1373 1374 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1375 reg); 1376 } 1377 1378 /* Offset 0x0C: Port ATU Control */ 1379 1380 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) 1381 { 1382 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); 1383 } 1384 1385 /* Offset 0x0D: (Priority) Override Register */ 1386 1387 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) 1388 { 1389 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); 1390 } 1391 1392 /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */ 1393 1394 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port, 1395 u16 pointer, u8 *data) 1396 { 1397 u16 reg; 1398 int err; 1399 1400 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1401 pointer); 1402 if (err) 1403 return err; 1404 1405 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1406 ®); 1407 if (err) 1408 return err; 1409 1410 *data = reg; 1411 1412 return 0; 1413 } 1414 1415 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port, 1416 u16 pointer, u8 data) 1417 { 1418 u16 reg; 1419 1420 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data; 1421 1422 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1423 reg); 1424 } 1425 1426 static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip, 1427 u16 pointer, u8 data) 1428 { 1429 int err, port; 1430 1431 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1432 if (dsa_is_unused_port(chip->ds, port)) 1433 continue; 1434 1435 err = mv88e6393x_port_policy_write(chip, port, pointer, data); 1436 if (err) 1437 return err; 1438 } 1439 1440 return 0; 1441 } 1442 1443 int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, 1444 enum mv88e6xxx_egress_direction direction, 1445 int port) 1446 { 1447 u16 ptr; 1448 int err; 1449 1450 switch (direction) { 1451 case MV88E6XXX_EGRESS_DIR_INGRESS: 1452 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST; 1453 err = mv88e6393x_port_policy_write_all(chip, ptr, port); 1454 if (err) 1455 return err; 1456 break; 1457 case MV88E6XXX_EGRESS_DIR_EGRESS: 1458 ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST; 1459 err = mv88e6xxx_g2_write(chip, ptr, port); 1460 if (err) 1461 return err; 1462 break; 1463 } 1464 1465 return 0; 1466 } 1467 1468 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1469 int upstream_port) 1470 { 1471 u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST; 1472 u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI | 1473 upstream_port; 1474 1475 return mv88e6393x_port_policy_write(chip, port, ptr, data); 1476 } 1477 1478 int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 1479 { 1480 u16 ptr; 1481 int err; 1482 1483 /* Consider the frames with reserved multicast destination 1484 * addresses matching 01:80:c2:00:00:00 and 1485 * 01:80:c2:00:00:02 as MGMT. 1486 */ 1487 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO; 1488 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1489 if (err) 1490 return err; 1491 1492 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI; 1493 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1494 if (err) 1495 return err; 1496 1497 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO; 1498 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1499 if (err) 1500 return err; 1501 1502 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI; 1503 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1504 if (err) 1505 return err; 1506 1507 return 0; 1508 } 1509 1510 /* Offset 0x10 & 0x11: EPC */ 1511 1512 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) 1513 { 1514 int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY); 1515 1516 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); 1517 } 1518 1519 /* Port Ether type for 6393X family */ 1520 1521 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1522 u16 etype) 1523 { 1524 u16 val; 1525 int err; 1526 1527 err = mv88e6393x_port_epc_wait_ready(chip, port); 1528 if (err) 1529 return err; 1530 1531 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype); 1532 if (err) 1533 return err; 1534 1535 val = MV88E6393X_PORT_EPC_CMD_BUSY | 1536 MV88E6393X_PORT_EPC_CMD_WRITE | 1537 MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE; 1538 1539 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val); 1540 } 1541 1542 /* Offset 0x0f: Port Ether type */ 1543 1544 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1545 u16 etype) 1546 { 1547 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); 1548 } 1549 1550 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] 1551 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] 1552 */ 1553 1554 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1555 { 1556 int err; 1557 1558 /* Use a direct priority mapping for all IEEE tagged frames */ 1559 err = mv88e6xxx_port_write(chip, port, 1560 MV88E6095_PORT_IEEE_PRIO_REMAP_0123, 1561 0x3210); 1562 if (err) 1563 return err; 1564 1565 return mv88e6xxx_port_write(chip, port, 1566 MV88E6095_PORT_IEEE_PRIO_REMAP_4567, 1567 0x7654); 1568 } 1569 1570 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, 1571 int port, u16 table, u8 ptr, u16 data) 1572 { 1573 u16 reg; 1574 1575 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | 1576 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | 1577 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK); 1578 1579 return mv88e6xxx_port_write(chip, port, 1580 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); 1581 } 1582 1583 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1584 { 1585 int err, i; 1586 u16 table; 1587 1588 for (i = 0; i <= 7; i++) { 1589 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; 1590 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, 1591 (i | i << 4)); 1592 if (err) 1593 return err; 1594 1595 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP; 1596 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1597 if (err) 1598 return err; 1599 1600 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP; 1601 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1602 if (err) 1603 return err; 1604 1605 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP; 1606 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1607 if (err) 1608 return err; 1609 } 1610 1611 return 0; 1612 } 1613 1614 /* Offset 0x0E: Policy Control Register */ 1615 1616 static int 1617 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping, 1618 enum mv88e6xxx_policy_action action, 1619 u16 *mask, u16 *val, int *shift) 1620 { 1621 switch (mapping) { 1622 case MV88E6XXX_POLICY_MAPPING_DA: 1623 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK); 1624 *mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK; 1625 break; 1626 case MV88E6XXX_POLICY_MAPPING_SA: 1627 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK); 1628 *mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK; 1629 break; 1630 case MV88E6XXX_POLICY_MAPPING_VTU: 1631 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK); 1632 *mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK; 1633 break; 1634 case MV88E6XXX_POLICY_MAPPING_ETYPE: 1635 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK); 1636 *mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK; 1637 break; 1638 case MV88E6XXX_POLICY_MAPPING_PPPOE: 1639 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK); 1640 *mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK; 1641 break; 1642 case MV88E6XXX_POLICY_MAPPING_VBAS: 1643 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK); 1644 *mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK; 1645 break; 1646 case MV88E6XXX_POLICY_MAPPING_OPT82: 1647 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK); 1648 *mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK; 1649 break; 1650 case MV88E6XXX_POLICY_MAPPING_UDP: 1651 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK); 1652 *mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK; 1653 break; 1654 default: 1655 return -EOPNOTSUPP; 1656 } 1657 1658 switch (action) { 1659 case MV88E6XXX_POLICY_ACTION_NORMAL: 1660 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL; 1661 break; 1662 case MV88E6XXX_POLICY_ACTION_MIRROR: 1663 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR; 1664 break; 1665 case MV88E6XXX_POLICY_ACTION_TRAP: 1666 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP; 1667 break; 1668 case MV88E6XXX_POLICY_ACTION_DISCARD: 1669 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD; 1670 break; 1671 default: 1672 return -EOPNOTSUPP; 1673 } 1674 1675 return 0; 1676 } 1677 1678 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1679 enum mv88e6xxx_policy_mapping mapping, 1680 enum mv88e6xxx_policy_action action) 1681 { 1682 u16 reg, mask, val; 1683 int shift; 1684 int err; 1685 1686 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1687 &val, &shift); 1688 if (err) 1689 return err; 1690 1691 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); 1692 if (err) 1693 return err; 1694 1695 reg &= ~mask; 1696 reg |= (val << shift) & mask; 1697 1698 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); 1699 } 1700 1701 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1702 enum mv88e6xxx_policy_mapping mapping, 1703 enum mv88e6xxx_policy_action action) 1704 { 1705 u16 mask, val; 1706 int shift; 1707 int err; 1708 u16 ptr; 1709 u8 reg; 1710 1711 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1712 &val, &shift); 1713 if (err) 1714 return err; 1715 1716 /* The 16-bit Port Policy CTL register from older chips is on 6393x 1717 * changed to Port Policy MGMT CTL, which can access more data, but 1718 * indirectly. The original 16-bit value is divided into two 8-bit 1719 * registers. 1720 */ 1721 ptr = shift / 8; 1722 shift %= 8; 1723 mask >>= ptr * 8; 1724 1725 err = mv88e6393x_port_policy_read(chip, port, ptr, ®); 1726 if (err) 1727 return err; 1728 1729 reg &= ~mask; 1730 reg |= (val << shift) & mask; 1731 1732 return mv88e6393x_port_policy_write(chip, port, ptr, reg); 1733 } 1734