1 /* 2 * Marvell 88E6xxx Switch Port Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include "mv88e6xxx.h" 15 #include "port.h" 16 17 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 18 u16 *val) 19 { 20 int addr = chip->info->port_base_addr + port; 21 22 return mv88e6xxx_read(chip, addr, reg, val); 23 } 24 25 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 26 u16 val) 27 { 28 int addr = chip->info->port_base_addr + port; 29 30 return mv88e6xxx_write(chip, addr, reg, val); 31 } 32 33 /* Offset 0x01: MAC (or PCS or Physical) Control Register 34 * 35 * Link, Duplex and Flow Control have one force bit, one value bit. 36 * 37 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. 38 * Alternative values require the 200BASE (or AltSpeed) bit 12 set. 39 * Newer chips need a ForcedSpd bit 13 set to consider the value. 40 */ 41 42 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 43 phy_interface_t mode) 44 { 45 u16 reg; 46 int err; 47 48 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®); 49 if (err) 50 return err; 51 52 reg &= ~(PORT_PCS_CTRL_RGMII_DELAY_RXCLK | 53 PORT_PCS_CTRL_RGMII_DELAY_TXCLK); 54 55 switch (mode) { 56 case PHY_INTERFACE_MODE_RGMII_RXID: 57 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK; 58 break; 59 case PHY_INTERFACE_MODE_RGMII_TXID: 60 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK; 61 break; 62 case PHY_INTERFACE_MODE_RGMII_ID: 63 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK | 64 PORT_PCS_CTRL_RGMII_DELAY_TXCLK; 65 break; 66 case PHY_INTERFACE_MODE_RGMII: 67 break; 68 default: 69 return 0; 70 } 71 72 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg); 73 if (err) 74 return err; 75 76 netdev_dbg(chip->ds->ports[port].netdev, "delay RXCLK %s, TXCLK %s\n", 77 reg & PORT_PCS_CTRL_RGMII_DELAY_RXCLK ? "yes" : "no", 78 reg & PORT_PCS_CTRL_RGMII_DELAY_TXCLK ? "yes" : "no"); 79 80 return 0; 81 } 82 83 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 84 phy_interface_t mode) 85 { 86 if (port < 5) 87 return -EOPNOTSUPP; 88 89 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 90 } 91 92 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 93 phy_interface_t mode) 94 { 95 if (port != 0) 96 return -EOPNOTSUPP; 97 98 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 99 } 100 101 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) 102 { 103 u16 reg; 104 int err; 105 106 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®); 107 if (err) 108 return err; 109 110 reg &= ~(PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP); 111 112 switch (link) { 113 case LINK_FORCED_DOWN: 114 reg |= PORT_PCS_CTRL_FORCE_LINK; 115 break; 116 case LINK_FORCED_UP: 117 reg |= PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP; 118 break; 119 case LINK_UNFORCED: 120 /* normal link detection */ 121 break; 122 default: 123 return -EINVAL; 124 } 125 126 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg); 127 if (err) 128 return err; 129 130 netdev_dbg(chip->ds->ports[port].netdev, "%s link %s\n", 131 reg & PORT_PCS_CTRL_FORCE_LINK ? "Force" : "Unforce", 132 reg & PORT_PCS_CTRL_LINK_UP ? "up" : "down"); 133 134 return 0; 135 } 136 137 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup) 138 { 139 u16 reg; 140 int err; 141 142 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®); 143 if (err) 144 return err; 145 146 reg &= ~(PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL); 147 148 switch (dup) { 149 case DUPLEX_HALF: 150 reg |= PORT_PCS_CTRL_FORCE_DUPLEX; 151 break; 152 case DUPLEX_FULL: 153 reg |= PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL; 154 break; 155 case DUPLEX_UNFORCED: 156 /* normal duplex detection */ 157 break; 158 default: 159 return -EINVAL; 160 } 161 162 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg); 163 if (err) 164 return err; 165 166 netdev_dbg(chip->ds->ports[port].netdev, "%s %s duplex\n", 167 reg & PORT_PCS_CTRL_FORCE_DUPLEX ? "Force" : "Unforce", 168 reg & PORT_PCS_CTRL_DUPLEX_FULL ? "full" : "half"); 169 170 return 0; 171 } 172 173 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port, 174 int speed, bool alt_bit, bool force_bit) 175 { 176 u16 reg, ctrl; 177 int err; 178 179 switch (speed) { 180 case 10: 181 ctrl = PORT_PCS_CTRL_SPEED_10; 182 break; 183 case 100: 184 ctrl = PORT_PCS_CTRL_SPEED_100; 185 break; 186 case 200: 187 if (alt_bit) 188 ctrl = PORT_PCS_CTRL_SPEED_100 | PORT_PCS_CTRL_ALTSPEED; 189 else 190 ctrl = PORT_PCS_CTRL_SPEED_200; 191 break; 192 case 1000: 193 ctrl = PORT_PCS_CTRL_SPEED_1000; 194 break; 195 case 2500: 196 ctrl = PORT_PCS_CTRL_SPEED_1000 | PORT_PCS_CTRL_ALTSPEED; 197 break; 198 case 10000: 199 /* all bits set, fall through... */ 200 case SPEED_UNFORCED: 201 ctrl = PORT_PCS_CTRL_SPEED_UNFORCED; 202 break; 203 default: 204 return -EOPNOTSUPP; 205 } 206 207 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®); 208 if (err) 209 return err; 210 211 reg &= ~PORT_PCS_CTRL_SPEED_MASK; 212 if (alt_bit) 213 reg &= ~PORT_PCS_CTRL_ALTSPEED; 214 if (force_bit) { 215 reg &= ~PORT_PCS_CTRL_FORCE_SPEED; 216 if (speed != SPEED_UNFORCED) 217 ctrl |= PORT_PCS_CTRL_FORCE_SPEED; 218 } 219 reg |= ctrl; 220 221 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg); 222 if (err) 223 return err; 224 225 if (speed) 226 netdev_dbg(chip->ds->ports[port].netdev, 227 "Speed set to %d Mbps\n", speed); 228 else 229 netdev_dbg(chip->ds->ports[port].netdev, "Speed unforced\n"); 230 231 return 0; 232 } 233 234 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */ 235 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 236 { 237 if (speed == SPEED_MAX) 238 speed = 200; 239 240 if (speed > 200) 241 return -EOPNOTSUPP; 242 243 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */ 244 return mv88e6xxx_port_set_speed(chip, port, speed, false, false); 245 } 246 247 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ 248 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 249 { 250 if (speed == SPEED_MAX) 251 speed = 1000; 252 253 if (speed == 200 || speed > 1000) 254 return -EOPNOTSUPP; 255 256 return mv88e6xxx_port_set_speed(chip, port, speed, false, false); 257 } 258 259 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ 260 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 261 { 262 if (speed == SPEED_MAX) 263 speed = 1000; 264 265 if (speed > 1000) 266 return -EOPNOTSUPP; 267 268 if (speed == 200 && port < 5) 269 return -EOPNOTSUPP; 270 271 return mv88e6xxx_port_set_speed(chip, port, speed, true, false); 272 } 273 274 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ 275 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 276 { 277 if (speed == SPEED_MAX) 278 speed = port < 9 ? 1000 : 2500; 279 280 if (speed > 2500) 281 return -EOPNOTSUPP; 282 283 if (speed == 200 && port != 0) 284 return -EOPNOTSUPP; 285 286 if (speed == 2500 && port < 9) 287 return -EOPNOTSUPP; 288 289 return mv88e6xxx_port_set_speed(chip, port, speed, true, true); 290 } 291 292 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ 293 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) 294 { 295 if (speed == SPEED_MAX) 296 speed = port < 9 ? 1000 : 10000; 297 298 if (speed == 200 && port != 0) 299 return -EOPNOTSUPP; 300 301 if (speed >= 2500 && port < 9) 302 return -EOPNOTSUPP; 303 304 return mv88e6xxx_port_set_speed(chip, port, speed, true, true); 305 } 306 307 /* Offset 0x02: Pause Control 308 * 309 * Do not limit the period of time that this port can be paused for by 310 * the remote end or the period of time that this port can pause the 311 * remote end. 312 */ 313 int mv88e6097_port_pause_config(struct mv88e6xxx_chip *chip, int port) 314 { 315 return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000); 316 } 317 318 int mv88e6390_port_pause_config(struct mv88e6xxx_chip *chip, int port) 319 { 320 int err; 321 322 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 323 PORT_FLOW_CTRL_LIMIT_IN | 0); 324 if (err) 325 return err; 326 327 return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 328 PORT_FLOW_CTRL_LIMIT_OUT | 0); 329 } 330 331 /* Offset 0x04: Port Control Register */ 332 333 static const char * const mv88e6xxx_port_state_names[] = { 334 [PORT_CONTROL_STATE_DISABLED] = "Disabled", 335 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening", 336 [PORT_CONTROL_STATE_LEARNING] = "Learning", 337 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding", 338 }; 339 340 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) 341 { 342 u16 reg; 343 int err; 344 345 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®); 346 if (err) 347 return err; 348 349 reg &= ~PORT_CONTROL_STATE_MASK; 350 reg |= state; 351 352 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 353 if (err) 354 return err; 355 356 netdev_dbg(chip->ds->ports[port].netdev, "PortState set to %s\n", 357 mv88e6xxx_port_state_names[state]); 358 359 return 0; 360 } 361 362 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 363 u16 mode) 364 { 365 int err; 366 u16 reg; 367 368 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®); 369 if (err) 370 return err; 371 372 reg &= ~PORT_CONTROL_EGRESS_MASK; 373 reg |= mode; 374 375 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 376 } 377 378 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 379 enum mv88e6xxx_frame_mode mode) 380 { 381 int err; 382 u16 reg; 383 384 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®); 385 if (err) 386 return err; 387 388 reg &= ~PORT_CONTROL_FRAME_MODE_DSA; 389 390 switch (mode) { 391 case MV88E6XXX_FRAME_MODE_NORMAL: 392 reg |= PORT_CONTROL_FRAME_MODE_NORMAL; 393 break; 394 case MV88E6XXX_FRAME_MODE_DSA: 395 reg |= PORT_CONTROL_FRAME_MODE_DSA; 396 break; 397 default: 398 return -EINVAL; 399 } 400 401 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 402 } 403 404 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 405 enum mv88e6xxx_frame_mode mode) 406 { 407 int err; 408 u16 reg; 409 410 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®); 411 if (err) 412 return err; 413 414 reg &= ~PORT_CONTROL_FRAME_MASK; 415 416 switch (mode) { 417 case MV88E6XXX_FRAME_MODE_NORMAL: 418 reg |= PORT_CONTROL_FRAME_MODE_NORMAL; 419 break; 420 case MV88E6XXX_FRAME_MODE_DSA: 421 reg |= PORT_CONTROL_FRAME_MODE_DSA; 422 break; 423 case MV88E6XXX_FRAME_MODE_PROVIDER: 424 reg |= PORT_CONTROL_FRAME_MODE_PROVIDER; 425 break; 426 case MV88E6XXX_FRAME_MODE_ETHERTYPE: 427 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA; 428 break; 429 default: 430 return -EINVAL; 431 } 432 433 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 434 } 435 436 int mv88e6085_port_set_egress_unknowns(struct mv88e6xxx_chip *chip, int port, 437 bool on) 438 { 439 int err; 440 u16 reg; 441 442 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®); 443 if (err) 444 return err; 445 446 if (on) 447 reg |= PORT_CONTROL_FORWARD_UNKNOWN; 448 else 449 reg &= ~PORT_CONTROL_FORWARD_UNKNOWN; 450 451 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 452 } 453 454 int mv88e6351_port_set_egress_unknowns(struct mv88e6xxx_chip *chip, int port, 455 bool on) 456 { 457 int err; 458 u16 reg; 459 460 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®); 461 if (err) 462 return err; 463 464 if (on) 465 reg |= PORT_CONTROL_EGRESS_ALL_UNKNOWN_DA; 466 else 467 reg &= ~PORT_CONTROL_EGRESS_ALL_UNKNOWN_DA; 468 469 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 470 } 471 472 /* Offset 0x05: Port Control 1 */ 473 474 /* Offset 0x06: Port Based VLAN Map */ 475 476 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) 477 { 478 const u16 mask = GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 479 u16 reg; 480 int err; 481 482 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®); 483 if (err) 484 return err; 485 486 reg &= ~mask; 487 reg |= map & mask; 488 489 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg); 490 if (err) 491 return err; 492 493 netdev_dbg(chip->ds->ports[port].netdev, "VLANTable set to %.3x\n", 494 map); 495 496 return 0; 497 } 498 499 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) 500 { 501 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 502 u16 reg; 503 int err; 504 505 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 506 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®); 507 if (err) 508 return err; 509 510 *fid = (reg & 0xf000) >> 12; 511 512 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 513 if (upper_mask) { 514 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®); 515 if (err) 516 return err; 517 518 *fid |= (reg & upper_mask) << 4; 519 } 520 521 return 0; 522 } 523 524 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) 525 { 526 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 527 u16 reg; 528 int err; 529 530 if (fid >= mv88e6xxx_num_databases(chip)) 531 return -EINVAL; 532 533 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 534 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®); 535 if (err) 536 return err; 537 538 reg &= 0x0fff; 539 reg |= (fid & 0x000f) << 12; 540 541 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg); 542 if (err) 543 return err; 544 545 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 546 if (upper_mask) { 547 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®); 548 if (err) 549 return err; 550 551 reg &= ~upper_mask; 552 reg |= (fid >> 4) & upper_mask; 553 554 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg); 555 if (err) 556 return err; 557 } 558 559 netdev_dbg(chip->ds->ports[port].netdev, "FID set to %u\n", fid); 560 561 return 0; 562 } 563 564 /* Offset 0x07: Default Port VLAN ID & Priority */ 565 566 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) 567 { 568 u16 reg; 569 int err; 570 571 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®); 572 if (err) 573 return err; 574 575 *pvid = reg & PORT_DEFAULT_VLAN_MASK; 576 577 return 0; 578 } 579 580 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) 581 { 582 u16 reg; 583 int err; 584 585 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®); 586 if (err) 587 return err; 588 589 reg &= ~PORT_DEFAULT_VLAN_MASK; 590 reg |= pvid & PORT_DEFAULT_VLAN_MASK; 591 592 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg); 593 if (err) 594 return err; 595 596 netdev_dbg(chip->ds->ports[port].netdev, "DefaultVID set to %u\n", 597 pvid); 598 599 return 0; 600 } 601 602 /* Offset 0x08: Port Control 2 Register */ 603 604 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 605 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled", 606 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback", 607 [PORT_CONTROL_2_8021Q_CHECK] = "Check", 608 [PORT_CONTROL_2_8021Q_SECURE] = "Secure", 609 }; 610 611 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 612 u16 mode) 613 { 614 u16 reg; 615 int err; 616 617 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®); 618 if (err) 619 return err; 620 621 reg &= ~PORT_CONTROL_2_8021Q_MASK; 622 reg |= mode & PORT_CONTROL_2_8021Q_MASK; 623 624 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); 625 if (err) 626 return err; 627 628 netdev_dbg(chip->ds->ports[port].netdev, "802.1QMode set to %s\n", 629 mv88e6xxx_port_8021q_mode_names[mode]); 630 631 return 0; 632 } 633 634 int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port) 635 { 636 u16 reg; 637 int err; 638 639 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®); 640 if (err) 641 return err; 642 643 reg |= PORT_CONTROL_2_JUMBO_10240; 644 645 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); 646 } 647 648 /* Offset 0x09: Port Rate Control */ 649 650 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 651 { 652 return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0000); 653 } 654 655 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 656 { 657 return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0001); 658 } 659 660 /* Offset 0x0f: Port Ether type */ 661 662 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 663 u16 etype) 664 { 665 return mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE, etype); 666 } 667 668 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] 669 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] 670 */ 671 672 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 673 { 674 int err; 675 676 /* Use a direct priority mapping for all IEEE tagged frames */ 677 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123, 0x3210); 678 if (err) 679 return err; 680 681 return mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567, 0x7654); 682 } 683 684 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, 685 int port, u16 table, 686 u8 pointer, u16 data) 687 { 688 u16 reg; 689 690 reg = PORT_IEEE_PRIO_MAP_TABLE_UPDATE | 691 table | 692 (pointer << PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT) | 693 data; 694 695 return mv88e6xxx_port_write(chip, port, PORT_IEEE_PRIO_MAP_TABLE, reg); 696 } 697 698 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 699 { 700 int err, i; 701 702 for (i = 0; i <= 7; i++) { 703 err = mv88e6xxx_port_ieeepmt_write( 704 chip, port, PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP, 705 i, (i | i << 4)); 706 if (err) 707 return err; 708 709 err = mv88e6xxx_port_ieeepmt_write( 710 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP, 711 i, i); 712 if (err) 713 return err; 714 715 err = mv88e6xxx_port_ieeepmt_write( 716 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP, 717 i, i); 718 if (err) 719 return err; 720 721 err = mv88e6xxx_port_ieeepmt_write( 722 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP, 723 i, i); 724 if (err) 725 return err; 726 } 727 728 return 0; 729 } 730