1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Port Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/if_bridge.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 16 #include "chip.h" 17 #include "global2.h" 18 #include "port.h" 19 #include "serdes.h" 20 21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 22 u16 *val) 23 { 24 int addr = chip->info->port_base_addr + port; 25 26 return mv88e6xxx_read(chip, addr, reg, val); 27 } 28 29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, 30 int bit, int val) 31 { 32 int addr = chip->info->port_base_addr + port; 33 34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); 35 } 36 37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 38 u16 val) 39 { 40 int addr = chip->info->port_base_addr + port; 41 42 return mv88e6xxx_write(chip, addr, reg, val); 43 } 44 45 /* Offset 0x00: MAC (or PCS or Physical) Status Register 46 * 47 * For most devices, this is read only. However the 6185 has the MyPause 48 * bit read/write. 49 */ 50 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 51 int pause) 52 { 53 u16 reg; 54 int err; 55 56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 57 if (err) 58 return err; 59 60 if (pause) 61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; 62 else 63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; 64 65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 66 } 67 68 /* Offset 0x01: MAC (or PCS or Physical) Control Register 69 * 70 * Link, Duplex and Flow Control have one force bit, one value bit. 71 * 72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. 73 * Alternative values require the 200BASE (or AltSpeed) bit 12 set. 74 * Newer chips need a ForcedSpd bit 13 set to consider the value. 75 */ 76 77 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 78 phy_interface_t mode) 79 { 80 u16 reg; 81 int err; 82 83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 84 if (err) 85 return err; 86 87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 88 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK); 89 90 switch (mode) { 91 case PHY_INTERFACE_MODE_RGMII_RXID: 92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; 93 break; 94 case PHY_INTERFACE_MODE_RGMII_TXID: 95 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 96 break; 97 case PHY_INTERFACE_MODE_RGMII_ID: 98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 99 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 100 break; 101 case PHY_INTERFACE_MODE_RGMII: 102 break; 103 default: 104 return 0; 105 } 106 107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 108 if (err) 109 return err; 110 111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, 112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", 113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); 114 115 return 0; 116 } 117 118 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 119 phy_interface_t mode) 120 { 121 if (port < 5) 122 return -EOPNOTSUPP; 123 124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 125 } 126 127 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 128 phy_interface_t mode) 129 { 130 if (port != 0) 131 return -EOPNOTSUPP; 132 133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 134 } 135 136 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) 137 { 138 u16 reg; 139 int err; 140 141 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 142 if (err) 143 return err; 144 145 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 146 MV88E6XXX_PORT_MAC_CTL_LINK_UP); 147 148 switch (link) { 149 case LINK_FORCED_DOWN: 150 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; 151 break; 152 case LINK_FORCED_UP: 153 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 154 MV88E6XXX_PORT_MAC_CTL_LINK_UP; 155 break; 156 case LINK_UNFORCED: 157 /* normal link detection */ 158 break; 159 default: 160 return -EINVAL; 161 } 162 163 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 164 if (err) 165 return err; 166 167 dev_dbg(chip->dev, "p%d: %s link %s\n", port, 168 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", 169 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); 170 171 return 0; 172 } 173 174 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 175 { 176 const struct mv88e6xxx_ops *ops = chip->info->ops; 177 int err = 0; 178 int link; 179 180 if (isup) 181 link = LINK_FORCED_UP; 182 else 183 link = LINK_FORCED_DOWN; 184 185 if (ops->port_set_link) 186 err = ops->port_set_link(chip, port, link); 187 188 return err; 189 } 190 191 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 192 { 193 const struct mv88e6xxx_ops *ops = chip->info->ops; 194 int err = 0; 195 int link; 196 197 if (mode == MLO_AN_INBAND) 198 link = LINK_UNFORCED; 199 else if (isup) 200 link = LINK_FORCED_UP; 201 else 202 link = LINK_FORCED_DOWN; 203 204 if (ops->port_set_link) 205 err = ops->port_set_link(chip, port, link); 206 207 return err; 208 } 209 210 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip, 211 int port, int speed, bool alt_bit, 212 bool force_bit, int duplex) 213 { 214 u16 reg, ctrl; 215 int err; 216 217 switch (speed) { 218 case 10: 219 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 220 break; 221 case 100: 222 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 223 break; 224 case 200: 225 if (alt_bit) 226 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 227 MV88E6390_PORT_MAC_CTL_ALTSPEED; 228 else 229 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200; 230 break; 231 case 1000: 232 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 233 break; 234 case 2500: 235 if (alt_bit) 236 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 237 MV88E6390_PORT_MAC_CTL_ALTSPEED; 238 else 239 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000; 240 break; 241 case 10000: 242 /* all bits set, fall through... */ 243 case SPEED_UNFORCED: 244 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 245 break; 246 default: 247 return -EOPNOTSUPP; 248 } 249 250 switch (duplex) { 251 case DUPLEX_HALF: 252 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 253 break; 254 case DUPLEX_FULL: 255 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 256 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 257 break; 258 case DUPLEX_UNFORCED: 259 /* normal duplex detection */ 260 break; 261 default: 262 return -EOPNOTSUPP; 263 } 264 265 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 266 if (err) 267 return err; 268 269 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 270 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 271 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); 272 273 if (alt_bit) 274 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; 275 if (force_bit) { 276 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 277 if (speed != SPEED_UNFORCED) 278 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 279 } 280 reg |= ctrl; 281 282 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 283 if (err) 284 return err; 285 286 if (speed != SPEED_UNFORCED) 287 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 288 else 289 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 290 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 291 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 292 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 293 294 return 0; 295 } 296 297 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */ 298 int mv88e6065_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 299 int speed, int duplex) 300 { 301 if (speed == SPEED_MAX) 302 speed = 200; 303 304 if (speed > 200) 305 return -EOPNOTSUPP; 306 307 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */ 308 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 309 duplex); 310 } 311 312 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ 313 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 314 int speed, int duplex) 315 { 316 if (speed == SPEED_MAX) 317 speed = 1000; 318 319 if (speed == 200 || speed > 1000) 320 return -EOPNOTSUPP; 321 322 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 323 duplex); 324 } 325 326 /* Support 10, 100 Mbps (e.g. 88E6250 family) */ 327 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 328 int speed, int duplex) 329 { 330 if (speed == SPEED_MAX) 331 speed = 100; 332 333 if (speed > 100) 334 return -EOPNOTSUPP; 335 336 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 337 duplex); 338 } 339 340 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */ 341 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 342 int speed, int duplex) 343 { 344 if (speed == SPEED_MAX) 345 speed = port < 5 ? 1000 : 2500; 346 347 if (speed > 2500) 348 return -EOPNOTSUPP; 349 350 if (speed == 200 && port != 0) 351 return -EOPNOTSUPP; 352 353 if (speed == 2500 && port < 5) 354 return -EOPNOTSUPP; 355 356 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true, 357 duplex); 358 } 359 360 phy_interface_t mv88e6341_port_max_speed_mode(int port) 361 { 362 if (port == 5) 363 return PHY_INTERFACE_MODE_2500BASEX; 364 365 return PHY_INTERFACE_MODE_NA; 366 } 367 368 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ 369 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 370 int speed, int duplex) 371 { 372 if (speed == SPEED_MAX) 373 speed = 1000; 374 375 if (speed > 1000) 376 return -EOPNOTSUPP; 377 378 if (speed == 200 && port < 5) 379 return -EOPNOTSUPP; 380 381 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false, 382 duplex); 383 } 384 385 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ 386 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 387 int speed, int duplex) 388 { 389 if (speed == SPEED_MAX) 390 speed = port < 9 ? 1000 : 2500; 391 392 if (speed > 2500) 393 return -EOPNOTSUPP; 394 395 if (speed == 200 && port != 0) 396 return -EOPNOTSUPP; 397 398 if (speed == 2500 && port < 9) 399 return -EOPNOTSUPP; 400 401 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 402 duplex); 403 } 404 405 phy_interface_t mv88e6390_port_max_speed_mode(int port) 406 { 407 if (port == 9 || port == 10) 408 return PHY_INTERFACE_MODE_2500BASEX; 409 410 return PHY_INTERFACE_MODE_NA; 411 } 412 413 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ 414 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 415 int speed, int duplex) 416 { 417 if (speed == SPEED_MAX) 418 speed = port < 9 ? 1000 : 10000; 419 420 if (speed == 200 && port != 0) 421 return -EOPNOTSUPP; 422 423 if (speed >= 2500 && port < 9) 424 return -EOPNOTSUPP; 425 426 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 427 duplex); 428 } 429 430 phy_interface_t mv88e6390x_port_max_speed_mode(int port) 431 { 432 if (port == 9 || port == 10) 433 return PHY_INTERFACE_MODE_XAUI; 434 435 return PHY_INTERFACE_MODE_NA; 436 } 437 438 /* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X) 439 * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register 440 * values for speeds 2500 & 5000 conflict. 441 */ 442 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 443 int speed, int duplex) 444 { 445 u16 reg, ctrl; 446 int err; 447 448 if (speed == SPEED_MAX) 449 speed = (port > 0 && port < 9) ? 1000 : 10000; 450 451 if (speed == 200 && port != 0) 452 return -EOPNOTSUPP; 453 454 if (speed >= 2500 && port > 0 && port < 9) 455 return -EOPNOTSUPP; 456 457 switch (speed) { 458 case 10: 459 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 460 break; 461 case 100: 462 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 463 break; 464 case 200: 465 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 466 MV88E6390_PORT_MAC_CTL_ALTSPEED; 467 break; 468 case 1000: 469 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 470 break; 471 case 2500: 472 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 | 473 MV88E6390_PORT_MAC_CTL_ALTSPEED; 474 break; 475 case 5000: 476 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 477 MV88E6390_PORT_MAC_CTL_ALTSPEED; 478 break; 479 case 10000: 480 case SPEED_UNFORCED: 481 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 482 break; 483 default: 484 return -EOPNOTSUPP; 485 } 486 487 switch (duplex) { 488 case DUPLEX_HALF: 489 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 490 break; 491 case DUPLEX_FULL: 492 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 493 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 494 break; 495 case DUPLEX_UNFORCED: 496 /* normal duplex detection */ 497 break; 498 default: 499 return -EOPNOTSUPP; 500 } 501 502 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 503 if (err) 504 return err; 505 506 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 507 MV88E6390_PORT_MAC_CTL_ALTSPEED | 508 MV88E6390_PORT_MAC_CTL_FORCE_SPEED); 509 510 if (speed != SPEED_UNFORCED) 511 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 512 513 reg |= ctrl; 514 515 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 516 if (err) 517 return err; 518 519 if (speed != SPEED_UNFORCED) 520 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 521 else 522 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 523 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 524 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 525 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 526 527 return 0; 528 } 529 530 phy_interface_t mv88e6393x_port_max_speed_mode(int port) 531 { 532 if (port == 0 || port == 9 || port == 10) 533 return PHY_INTERFACE_MODE_10GBASER; 534 535 return PHY_INTERFACE_MODE_NA; 536 } 537 538 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 539 phy_interface_t mode, bool force) 540 { 541 u16 cmode; 542 int lane; 543 u16 reg; 544 int err; 545 546 /* Default to a slow mode, so freeing up SERDES interfaces for 547 * other ports which might use them for SFPs. 548 */ 549 if (mode == PHY_INTERFACE_MODE_NA) 550 mode = PHY_INTERFACE_MODE_1000BASEX; 551 552 switch (mode) { 553 case PHY_INTERFACE_MODE_1000BASEX: 554 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX; 555 break; 556 case PHY_INTERFACE_MODE_SGMII: 557 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII; 558 break; 559 case PHY_INTERFACE_MODE_2500BASEX: 560 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; 561 break; 562 case PHY_INTERFACE_MODE_5GBASER: 563 cmode = MV88E6393X_PORT_STS_CMODE_5GBASER; 564 break; 565 case PHY_INTERFACE_MODE_XGMII: 566 case PHY_INTERFACE_MODE_XAUI: 567 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; 568 break; 569 case PHY_INTERFACE_MODE_RXAUI: 570 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; 571 break; 572 case PHY_INTERFACE_MODE_10GBASER: 573 cmode = MV88E6393X_PORT_STS_CMODE_10GBASER; 574 break; 575 default: 576 cmode = 0; 577 } 578 579 /* cmode doesn't change, nothing to do for us unless forced */ 580 if (cmode == chip->ports[port].cmode && !force) 581 return 0; 582 583 lane = mv88e6xxx_serdes_get_lane(chip, port); 584 if (lane >= 0) { 585 if (chip->ports[port].serdes_irq) { 586 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 587 if (err) 588 return err; 589 } 590 591 err = mv88e6xxx_serdes_power_down(chip, port, lane); 592 if (err) 593 return err; 594 } 595 596 chip->ports[port].cmode = 0; 597 598 if (cmode) { 599 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 600 if (err) 601 return err; 602 603 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; 604 reg |= cmode; 605 606 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 607 if (err) 608 return err; 609 610 chip->ports[port].cmode = cmode; 611 612 lane = mv88e6xxx_serdes_get_lane(chip, port); 613 if (lane < 0) 614 return lane; 615 616 err = mv88e6xxx_serdes_power_up(chip, port, lane); 617 if (err) 618 return err; 619 620 if (chip->ports[port].serdes_irq) { 621 err = mv88e6xxx_serdes_irq_enable(chip, port, lane); 622 if (err) 623 return err; 624 } 625 } 626 627 return 0; 628 } 629 630 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 631 phy_interface_t mode) 632 { 633 if (port != 9 && port != 10) 634 return -EOPNOTSUPP; 635 636 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 637 } 638 639 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 640 phy_interface_t mode) 641 { 642 if (port != 9 && port != 10) 643 return -EOPNOTSUPP; 644 645 switch (mode) { 646 case PHY_INTERFACE_MODE_NA: 647 return 0; 648 case PHY_INTERFACE_MODE_XGMII: 649 case PHY_INTERFACE_MODE_XAUI: 650 case PHY_INTERFACE_MODE_RXAUI: 651 return -EINVAL; 652 default: 653 break; 654 } 655 656 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 657 } 658 659 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 660 phy_interface_t mode) 661 { 662 int err; 663 u16 reg; 664 665 if (port != 0 && port != 9 && port != 10) 666 return -EOPNOTSUPP; 667 668 /* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */ 669 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 670 if (err) 671 return err; 672 673 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE; 674 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE; 675 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 676 if (err) 677 return err; 678 679 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 680 } 681 682 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip, 683 int port) 684 { 685 int err, addr; 686 u16 reg, bits; 687 688 if (port != 5) 689 return -EOPNOTSUPP; 690 691 addr = chip->info->port_base_addr + port; 692 693 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); 694 if (err) 695 return err; 696 697 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE | 698 MV88E6341_PORT_RESERVED_1A_SGMII_AN; 699 700 if ((reg & bits) == bits) 701 return 0; 702 703 reg |= bits; 704 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); 705 } 706 707 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 708 phy_interface_t mode) 709 { 710 int err; 711 712 if (port != 5) 713 return -EOPNOTSUPP; 714 715 switch (mode) { 716 case PHY_INTERFACE_MODE_NA: 717 return 0; 718 case PHY_INTERFACE_MODE_XGMII: 719 case PHY_INTERFACE_MODE_XAUI: 720 case PHY_INTERFACE_MODE_RXAUI: 721 return -EINVAL; 722 default: 723 break; 724 } 725 726 err = mv88e6341_port_set_cmode_writable(chip, port); 727 if (err) 728 return err; 729 730 return mv88e6xxx_port_set_cmode(chip, port, mode, true); 731 } 732 733 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 734 { 735 int err; 736 u16 reg; 737 738 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 739 if (err) 740 return err; 741 742 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; 743 744 return 0; 745 } 746 747 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 748 { 749 int err; 750 u16 reg; 751 752 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 753 if (err) 754 return err; 755 756 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; 757 758 return 0; 759 } 760 761 /* Offset 0x02: Jamming Control 762 * 763 * Do not limit the period of time that this port can be paused for by 764 * the remote end or the period of time that this port can pause the 765 * remote end. 766 */ 767 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 768 u8 out) 769 { 770 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, 771 out << 8 | in); 772 } 773 774 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 775 u8 out) 776 { 777 int err; 778 779 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 780 MV88E6390_PORT_FLOW_CTL_UPDATE | 781 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in); 782 if (err) 783 return err; 784 785 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 786 MV88E6390_PORT_FLOW_CTL_UPDATE | 787 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out); 788 } 789 790 /* Offset 0x04: Port Control Register */ 791 792 static const char * const mv88e6xxx_port_state_names[] = { 793 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", 794 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", 795 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", 796 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", 797 }; 798 799 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) 800 { 801 u16 reg; 802 int err; 803 804 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 805 if (err) 806 return err; 807 808 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; 809 810 switch (state) { 811 case BR_STATE_DISABLED: 812 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED; 813 break; 814 case BR_STATE_BLOCKING: 815 case BR_STATE_LISTENING: 816 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 817 break; 818 case BR_STATE_LEARNING: 819 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 820 break; 821 case BR_STATE_FORWARDING: 822 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 823 break; 824 default: 825 return -EINVAL; 826 } 827 828 reg |= state; 829 830 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 831 if (err) 832 return err; 833 834 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, 835 mv88e6xxx_port_state_names[state]); 836 837 return 0; 838 } 839 840 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 841 enum mv88e6xxx_egress_mode mode) 842 { 843 int err; 844 u16 reg; 845 846 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 847 if (err) 848 return err; 849 850 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; 851 852 switch (mode) { 853 case MV88E6XXX_EGRESS_MODE_UNMODIFIED: 854 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; 855 break; 856 case MV88E6XXX_EGRESS_MODE_UNTAGGED: 857 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; 858 break; 859 case MV88E6XXX_EGRESS_MODE_TAGGED: 860 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; 861 break; 862 case MV88E6XXX_EGRESS_MODE_ETHERTYPE: 863 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; 864 break; 865 default: 866 return -EINVAL; 867 } 868 869 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 870 } 871 872 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 873 enum mv88e6xxx_frame_mode mode) 874 { 875 int err; 876 u16 reg; 877 878 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 879 if (err) 880 return err; 881 882 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 883 884 switch (mode) { 885 case MV88E6XXX_FRAME_MODE_NORMAL: 886 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 887 break; 888 case MV88E6XXX_FRAME_MODE_DSA: 889 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 890 break; 891 default: 892 return -EINVAL; 893 } 894 895 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 896 } 897 898 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 899 enum mv88e6xxx_frame_mode mode) 900 { 901 int err; 902 u16 reg; 903 904 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 905 if (err) 906 return err; 907 908 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 909 910 switch (mode) { 911 case MV88E6XXX_FRAME_MODE_NORMAL: 912 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 913 break; 914 case MV88E6XXX_FRAME_MODE_DSA: 915 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 916 break; 917 case MV88E6XXX_FRAME_MODE_PROVIDER: 918 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; 919 break; 920 case MV88E6XXX_FRAME_MODE_ETHERTYPE: 921 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; 922 break; 923 default: 924 return -EINVAL; 925 } 926 927 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 928 } 929 930 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 931 int port, bool unicast) 932 { 933 int err; 934 u16 reg; 935 936 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 937 if (err) 938 return err; 939 940 if (unicast) 941 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 942 else 943 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 944 945 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 946 } 947 948 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, 949 bool unicast) 950 { 951 int err; 952 u16 reg; 953 954 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 955 if (err) 956 return err; 957 958 if (unicast) 959 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 960 else 961 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 962 963 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 964 } 965 966 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, 967 bool multicast) 968 { 969 int err; 970 u16 reg; 971 972 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 973 if (err) 974 return err; 975 976 if (multicast) 977 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 978 else 979 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 980 981 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 982 } 983 984 /* Offset 0x05: Port Control 1 */ 985 986 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 987 bool message_port) 988 { 989 u16 val; 990 int err; 991 992 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 993 if (err) 994 return err; 995 996 if (message_port) 997 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 998 else 999 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 1000 1001 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 1002 } 1003 1004 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, 1005 bool trunk, u8 id) 1006 { 1007 u16 val; 1008 int err; 1009 1010 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 1011 if (err) 1012 return err; 1013 1014 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK; 1015 1016 if (trunk) 1017 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT | 1018 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT); 1019 else 1020 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT; 1021 1022 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 1023 } 1024 1025 /* Offset 0x06: Port Based VLAN Map */ 1026 1027 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) 1028 { 1029 const u16 mask = mv88e6xxx_port_mask(chip); 1030 u16 reg; 1031 int err; 1032 1033 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1034 if (err) 1035 return err; 1036 1037 reg &= ~mask; 1038 reg |= map & mask; 1039 1040 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1041 if (err) 1042 return err; 1043 1044 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); 1045 1046 return 0; 1047 } 1048 1049 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) 1050 { 1051 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1052 u16 reg; 1053 int err; 1054 1055 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1056 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1057 if (err) 1058 return err; 1059 1060 *fid = (reg & 0xf000) >> 12; 1061 1062 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1063 if (upper_mask) { 1064 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1065 ®); 1066 if (err) 1067 return err; 1068 1069 *fid |= (reg & upper_mask) << 4; 1070 } 1071 1072 return 0; 1073 } 1074 1075 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) 1076 { 1077 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1078 u16 reg; 1079 int err; 1080 1081 if (fid >= mv88e6xxx_num_databases(chip)) 1082 return -EINVAL; 1083 1084 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1085 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1086 if (err) 1087 return err; 1088 1089 reg &= 0x0fff; 1090 reg |= (fid & 0x000f) << 12; 1091 1092 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1093 if (err) 1094 return err; 1095 1096 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1097 if (upper_mask) { 1098 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1099 ®); 1100 if (err) 1101 return err; 1102 1103 reg &= ~upper_mask; 1104 reg |= (fid >> 4) & upper_mask; 1105 1106 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, 1107 reg); 1108 if (err) 1109 return err; 1110 } 1111 1112 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); 1113 1114 return 0; 1115 } 1116 1117 /* Offset 0x07: Default Port VLAN ID & Priority */ 1118 1119 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) 1120 { 1121 u16 reg; 1122 int err; 1123 1124 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1125 ®); 1126 if (err) 1127 return err; 1128 1129 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1130 1131 return 0; 1132 } 1133 1134 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) 1135 { 1136 u16 reg; 1137 int err; 1138 1139 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1140 ®); 1141 if (err) 1142 return err; 1143 1144 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1145 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1146 1147 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1148 reg); 1149 if (err) 1150 return err; 1151 1152 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); 1153 1154 return 0; 1155 } 1156 1157 /* Offset 0x08: Port Control 2 Register */ 1158 1159 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 1160 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", 1161 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", 1162 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", 1163 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", 1164 }; 1165 1166 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 1167 int port, bool multicast) 1168 { 1169 int err; 1170 u16 reg; 1171 1172 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1173 if (err) 1174 return err; 1175 1176 if (multicast) 1177 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1178 else 1179 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1180 1181 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1182 } 1183 1184 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1185 int upstream_port) 1186 { 1187 int err; 1188 u16 reg; 1189 1190 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1191 if (err) 1192 return err; 1193 1194 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; 1195 reg |= upstream_port; 1196 1197 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1198 } 1199 1200 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 1201 enum mv88e6xxx_egress_direction direction, 1202 bool mirror) 1203 { 1204 bool *mirror_port; 1205 u16 reg; 1206 u16 bit; 1207 int err; 1208 1209 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1210 if (err) 1211 return err; 1212 1213 switch (direction) { 1214 case MV88E6XXX_EGRESS_DIR_INGRESS: 1215 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR; 1216 mirror_port = &chip->ports[port].mirror_ingress; 1217 break; 1218 case MV88E6XXX_EGRESS_DIR_EGRESS: 1219 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR; 1220 mirror_port = &chip->ports[port].mirror_egress; 1221 break; 1222 default: 1223 return -EINVAL; 1224 } 1225 1226 reg &= ~bit; 1227 if (mirror) 1228 reg |= bit; 1229 1230 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1231 if (!err) 1232 *mirror_port = mirror; 1233 1234 return err; 1235 } 1236 1237 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 1238 u16 mode) 1239 { 1240 u16 reg; 1241 int err; 1242 1243 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1244 if (err) 1245 return err; 1246 1247 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1248 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1249 1250 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1251 if (err) 1252 return err; 1253 1254 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, 1255 mv88e6xxx_port_8021q_mode_names[mode]); 1256 1257 return 0; 1258 } 1259 1260 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, 1261 bool drop_untagged) 1262 { 1263 u16 old, new; 1264 int err; 1265 1266 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old); 1267 if (err) 1268 return err; 1269 1270 if (drop_untagged) 1271 new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1272 else 1273 new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1274 1275 if (new == old) 1276 return 0; 1277 1278 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new); 1279 } 1280 1281 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port) 1282 { 1283 u16 reg; 1284 int err; 1285 1286 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1287 if (err) 1288 return err; 1289 1290 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; 1291 1292 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1293 } 1294 1295 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 1296 size_t size) 1297 { 1298 u16 reg; 1299 int err; 1300 1301 size += VLAN_ETH_HLEN + ETH_FCS_LEN; 1302 1303 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1304 if (err) 1305 return err; 1306 1307 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; 1308 1309 if (size <= 1522) 1310 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; 1311 else if (size <= 2048) 1312 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; 1313 else if (size <= 10240) 1314 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; 1315 else 1316 return -ERANGE; 1317 1318 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1319 } 1320 1321 /* Offset 0x09: Port Rate Control */ 1322 1323 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1324 { 1325 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1326 0x0000); 1327 } 1328 1329 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1330 { 1331 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1332 0x0001); 1333 } 1334 1335 /* Offset 0x0B: Port Association Vector */ 1336 1337 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, 1338 u16 pav) 1339 { 1340 u16 reg, mask; 1341 int err; 1342 1343 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1344 ®); 1345 if (err) 1346 return err; 1347 1348 mask = mv88e6xxx_port_mask(chip); 1349 reg &= ~mask; 1350 reg |= pav & mask; 1351 1352 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1353 reg); 1354 } 1355 1356 /* Offset 0x0C: Port ATU Control */ 1357 1358 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) 1359 { 1360 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); 1361 } 1362 1363 /* Offset 0x0D: (Priority) Override Register */ 1364 1365 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) 1366 { 1367 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); 1368 } 1369 1370 /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */ 1371 1372 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port, 1373 u16 pointer, u8 *data) 1374 { 1375 u16 reg; 1376 int err; 1377 1378 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1379 pointer); 1380 if (err) 1381 return err; 1382 1383 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1384 ®); 1385 if (err) 1386 return err; 1387 1388 *data = reg; 1389 1390 return 0; 1391 } 1392 1393 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port, 1394 u16 pointer, u8 data) 1395 { 1396 u16 reg; 1397 1398 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data; 1399 1400 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1401 reg); 1402 } 1403 1404 static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip, 1405 u16 pointer, u8 data) 1406 { 1407 int err, port; 1408 1409 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1410 if (dsa_is_unused_port(chip->ds, port)) 1411 continue; 1412 1413 err = mv88e6393x_port_policy_write(chip, port, pointer, data); 1414 if (err) 1415 return err; 1416 } 1417 1418 return 0; 1419 } 1420 1421 int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, 1422 enum mv88e6xxx_egress_direction direction, 1423 int port) 1424 { 1425 u16 ptr; 1426 int err; 1427 1428 switch (direction) { 1429 case MV88E6XXX_EGRESS_DIR_INGRESS: 1430 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST; 1431 err = mv88e6393x_port_policy_write_all(chip, ptr, port); 1432 if (err) 1433 return err; 1434 break; 1435 case MV88E6XXX_EGRESS_DIR_EGRESS: 1436 ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST; 1437 err = mv88e6xxx_g2_write(chip, ptr, port); 1438 if (err) 1439 return err; 1440 break; 1441 } 1442 1443 return 0; 1444 } 1445 1446 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1447 int upstream_port) 1448 { 1449 u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST; 1450 u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI | 1451 upstream_port; 1452 1453 return mv88e6393x_port_policy_write(chip, port, ptr, data); 1454 } 1455 1456 int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 1457 { 1458 u16 ptr; 1459 int err; 1460 1461 /* Consider the frames with reserved multicast destination 1462 * addresses matching 01:80:c2:00:00:00 and 1463 * 01:80:c2:00:00:02 as MGMT. 1464 */ 1465 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO; 1466 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1467 if (err) 1468 return err; 1469 1470 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI; 1471 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1472 if (err) 1473 return err; 1474 1475 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO; 1476 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1477 if (err) 1478 return err; 1479 1480 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI; 1481 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1482 if (err) 1483 return err; 1484 1485 return 0; 1486 } 1487 1488 /* Offset 0x10 & 0x11: EPC */ 1489 1490 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) 1491 { 1492 int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY); 1493 1494 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); 1495 } 1496 1497 /* Port Ether type for 6393X family */ 1498 1499 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1500 u16 etype) 1501 { 1502 u16 val; 1503 int err; 1504 1505 err = mv88e6393x_port_epc_wait_ready(chip, port); 1506 if (err) 1507 return err; 1508 1509 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype); 1510 if (err) 1511 return err; 1512 1513 val = MV88E6393X_PORT_EPC_CMD_BUSY | 1514 MV88E6393X_PORT_EPC_CMD_WRITE | 1515 MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE; 1516 1517 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val); 1518 } 1519 1520 /* Offset 0x0f: Port Ether type */ 1521 1522 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1523 u16 etype) 1524 { 1525 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); 1526 } 1527 1528 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] 1529 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] 1530 */ 1531 1532 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1533 { 1534 int err; 1535 1536 /* Use a direct priority mapping for all IEEE tagged frames */ 1537 err = mv88e6xxx_port_write(chip, port, 1538 MV88E6095_PORT_IEEE_PRIO_REMAP_0123, 1539 0x3210); 1540 if (err) 1541 return err; 1542 1543 return mv88e6xxx_port_write(chip, port, 1544 MV88E6095_PORT_IEEE_PRIO_REMAP_4567, 1545 0x7654); 1546 } 1547 1548 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, 1549 int port, u16 table, u8 ptr, u16 data) 1550 { 1551 u16 reg; 1552 1553 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | 1554 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | 1555 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK); 1556 1557 return mv88e6xxx_port_write(chip, port, 1558 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); 1559 } 1560 1561 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1562 { 1563 int err, i; 1564 u16 table; 1565 1566 for (i = 0; i <= 7; i++) { 1567 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; 1568 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, 1569 (i | i << 4)); 1570 if (err) 1571 return err; 1572 1573 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP; 1574 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1575 if (err) 1576 return err; 1577 1578 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP; 1579 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1580 if (err) 1581 return err; 1582 1583 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP; 1584 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1585 if (err) 1586 return err; 1587 } 1588 1589 return 0; 1590 } 1591 1592 /* Offset 0x0E: Policy Control Register */ 1593 1594 static int 1595 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping, 1596 enum mv88e6xxx_policy_action action, 1597 u16 *mask, u16 *val, int *shift) 1598 { 1599 switch (mapping) { 1600 case MV88E6XXX_POLICY_MAPPING_DA: 1601 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK); 1602 *mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK; 1603 break; 1604 case MV88E6XXX_POLICY_MAPPING_SA: 1605 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK); 1606 *mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK; 1607 break; 1608 case MV88E6XXX_POLICY_MAPPING_VTU: 1609 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK); 1610 *mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK; 1611 break; 1612 case MV88E6XXX_POLICY_MAPPING_ETYPE: 1613 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK); 1614 *mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK; 1615 break; 1616 case MV88E6XXX_POLICY_MAPPING_PPPOE: 1617 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK); 1618 *mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK; 1619 break; 1620 case MV88E6XXX_POLICY_MAPPING_VBAS: 1621 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK); 1622 *mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK; 1623 break; 1624 case MV88E6XXX_POLICY_MAPPING_OPT82: 1625 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK); 1626 *mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK; 1627 break; 1628 case MV88E6XXX_POLICY_MAPPING_UDP: 1629 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK); 1630 *mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK; 1631 break; 1632 default: 1633 return -EOPNOTSUPP; 1634 } 1635 1636 switch (action) { 1637 case MV88E6XXX_POLICY_ACTION_NORMAL: 1638 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL; 1639 break; 1640 case MV88E6XXX_POLICY_ACTION_MIRROR: 1641 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR; 1642 break; 1643 case MV88E6XXX_POLICY_ACTION_TRAP: 1644 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP; 1645 break; 1646 case MV88E6XXX_POLICY_ACTION_DISCARD: 1647 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD; 1648 break; 1649 default: 1650 return -EOPNOTSUPP; 1651 } 1652 1653 return 0; 1654 } 1655 1656 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1657 enum mv88e6xxx_policy_mapping mapping, 1658 enum mv88e6xxx_policy_action action) 1659 { 1660 u16 reg, mask, val; 1661 int shift; 1662 int err; 1663 1664 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1665 &val, &shift); 1666 if (err) 1667 return err; 1668 1669 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); 1670 if (err) 1671 return err; 1672 1673 reg &= ~mask; 1674 reg |= (val << shift) & mask; 1675 1676 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); 1677 } 1678 1679 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1680 enum mv88e6xxx_policy_mapping mapping, 1681 enum mv88e6xxx_policy_action action) 1682 { 1683 u16 mask, val; 1684 int shift; 1685 int err; 1686 u16 ptr; 1687 u8 reg; 1688 1689 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1690 &val, &shift); 1691 if (err) 1692 return err; 1693 1694 /* The 16-bit Port Policy CTL register from older chips is on 6393x 1695 * changed to Port Policy MGMT CTL, which can access more data, but 1696 * indirectly. The original 16-bit value is divided into two 8-bit 1697 * registers. 1698 */ 1699 ptr = shift / 8; 1700 shift %= 8; 1701 mask >>= ptr * 8; 1702 1703 err = mv88e6393x_port_policy_read(chip, port, ptr, ®); 1704 if (err) 1705 return err; 1706 1707 reg &= ~mask; 1708 reg |= (val << shift) & mask; 1709 1710 return mv88e6393x_port_policy_write(chip, port, ptr, reg); 1711 } 1712