xref: /openbmc/linux/drivers/net/dsa/mv88e6xxx/port.c (revision 2a598d0b)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Marvell 88E6xxx Switch Port Registers support
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  *
7  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9  */
10 
11 #include <linux/bitfield.h>
12 #include <linux/if_bridge.h>
13 #include <linux/phy.h>
14 #include <linux/phylink.h>
15 
16 #include "chip.h"
17 #include "global2.h"
18 #include "port.h"
19 #include "serdes.h"
20 
21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
22 			u16 *val)
23 {
24 	int addr = chip->info->port_base_addr + port;
25 
26 	return mv88e6xxx_read(chip, addr, reg, val);
27 }
28 
29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
30 			    int bit, int val)
31 {
32 	int addr = chip->info->port_base_addr + port;
33 
34 	return mv88e6xxx_wait_bit(chip, addr, reg, bit, val);
35 }
36 
37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
38 			 u16 val)
39 {
40 	int addr = chip->info->port_base_addr + port;
41 
42 	return mv88e6xxx_write(chip, addr, reg, val);
43 }
44 
45 /* Offset 0x00: MAC (or PCS or Physical) Status Register
46  *
47  * For most devices, this is read only. However the 6185 has the MyPause
48  * bit read/write.
49  */
50 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
51 			     int pause)
52 {
53 	u16 reg;
54 	int err;
55 
56 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
57 	if (err)
58 		return err;
59 
60 	if (pause)
61 		reg |= MV88E6XXX_PORT_STS_MY_PAUSE;
62 	else
63 		reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE;
64 
65 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
66 }
67 
68 /* Offset 0x01: MAC (or PCS or Physical) Control Register
69  *
70  * Link, Duplex and Flow Control have one force bit, one value bit.
71  *
72  * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
73  * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
74  * Newer chips need a ForcedSpd bit 13 set to consider the value.
75  */
76 
77 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
78 					  phy_interface_t mode)
79 {
80 	u16 reg;
81 	int err;
82 
83 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
84 	if (err)
85 		return err;
86 
87 	reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
88 		 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
89 
90 	switch (mode) {
91 	case PHY_INTERFACE_MODE_RGMII_RXID:
92 		reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
93 		break;
94 	case PHY_INTERFACE_MODE_RGMII_TXID:
95 		reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
96 		break;
97 	case PHY_INTERFACE_MODE_RGMII_ID:
98 		reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
99 			MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
100 		break;
101 	case PHY_INTERFACE_MODE_RGMII:
102 		break;
103 	default:
104 		return 0;
105 	}
106 
107 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
108 	if (err)
109 		return err;
110 
111 	dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
112 		reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
113 		reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
114 
115 	return 0;
116 }
117 
118 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
119 				   phy_interface_t mode)
120 {
121 	if (port < 5)
122 		return -EOPNOTSUPP;
123 
124 	return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
125 }
126 
127 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
128 				   phy_interface_t mode)
129 {
130 	if (port != 0)
131 		return -EOPNOTSUPP;
132 
133 	return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
134 }
135 
136 int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
137 				   phy_interface_t mode)
138 {
139 	if (port != 2 && port != 5 && port != 6)
140 		return -EOPNOTSUPP;
141 
142 	return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
143 }
144 
145 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
146 {
147 	u16 reg;
148 	int err;
149 
150 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
151 	if (err)
152 		return err;
153 
154 	reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
155 		 MV88E6XXX_PORT_MAC_CTL_LINK_UP);
156 
157 	switch (link) {
158 	case LINK_FORCED_DOWN:
159 		reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
160 		break;
161 	case LINK_FORCED_UP:
162 		reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
163 			MV88E6XXX_PORT_MAC_CTL_LINK_UP;
164 		break;
165 	case LINK_UNFORCED:
166 		/* normal link detection */
167 		break;
168 	default:
169 		return -EINVAL;
170 	}
171 
172 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
173 	if (err)
174 		return err;
175 
176 	dev_dbg(chip->dev, "p%d: %s link %s\n", port,
177 		reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
178 		reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
179 
180 	return 0;
181 }
182 
183 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
184 {
185 	const struct mv88e6xxx_ops *ops = chip->info->ops;
186 	int err = 0;
187 	int link;
188 
189 	if (isup)
190 		link = LINK_FORCED_UP;
191 	else
192 		link = LINK_FORCED_DOWN;
193 
194 	if (ops->port_set_link)
195 		err = ops->port_set_link(chip, port, link);
196 
197 	return err;
198 }
199 
200 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup)
201 {
202 	const struct mv88e6xxx_ops *ops = chip->info->ops;
203 	int err = 0;
204 	int link;
205 
206 	if (mode == MLO_AN_INBAND)
207 		link = LINK_UNFORCED;
208 	else if (isup)
209 		link = LINK_FORCED_UP;
210 	else
211 		link = LINK_FORCED_DOWN;
212 
213 	if (ops->port_set_link)
214 		err = ops->port_set_link(chip, port, link);
215 
216 	return err;
217 }
218 
219 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip,
220 					   int port, int speed, bool alt_bit,
221 					   bool force_bit, int duplex)
222 {
223 	u16 reg, ctrl;
224 	int err;
225 
226 	switch (speed) {
227 	case 10:
228 		ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
229 		break;
230 	case 100:
231 		ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
232 		break;
233 	case 200:
234 		if (alt_bit)
235 			ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
236 				MV88E6390_PORT_MAC_CTL_ALTSPEED;
237 		else
238 			ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
239 		break;
240 	case 1000:
241 		ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
242 		break;
243 	case 2500:
244 		if (alt_bit)
245 			ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
246 				MV88E6390_PORT_MAC_CTL_ALTSPEED;
247 		else
248 			ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000;
249 		break;
250 	case 10000:
251 		/* all bits set, fall through... */
252 	case SPEED_UNFORCED:
253 		ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
254 		break;
255 	default:
256 		return -EOPNOTSUPP;
257 	}
258 
259 	switch (duplex) {
260 	case DUPLEX_HALF:
261 		ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
262 		break;
263 	case DUPLEX_FULL:
264 		ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
265 			MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
266 		break;
267 	case DUPLEX_UNFORCED:
268 		/* normal duplex detection */
269 		break;
270 	default:
271 		return -EOPNOTSUPP;
272 	}
273 
274 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
275 	if (err)
276 		return err;
277 
278 	reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
279 		 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
280 		 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
281 
282 	if (alt_bit)
283 		reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
284 	if (force_bit) {
285 		reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
286 		if (speed != SPEED_UNFORCED)
287 			ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
288 	}
289 	reg |= ctrl;
290 
291 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
292 	if (err)
293 		return err;
294 
295 	if (speed != SPEED_UNFORCED)
296 		dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
297 	else
298 		dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
299 	dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
300 		reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
301 		reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
302 
303 	return 0;
304 }
305 
306 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
307 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
308 				    int speed, int duplex)
309 {
310 	if (speed == 200 || speed > 1000)
311 		return -EOPNOTSUPP;
312 
313 	return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
314 					       duplex);
315 }
316 
317 /* Support 10, 100 Mbps (e.g. 88E6250 family) */
318 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
319 				    int speed, int duplex)
320 {
321 	if (speed > 100)
322 		return -EOPNOTSUPP;
323 
324 	return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false,
325 					       duplex);
326 }
327 
328 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */
329 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
330 				    int speed, int duplex)
331 {
332 	if (speed > 2500)
333 		return -EOPNOTSUPP;
334 
335 	if (speed == 200 && port != 0)
336 		return -EOPNOTSUPP;
337 
338 	if (speed == 2500 && port < 5)
339 		return -EOPNOTSUPP;
340 
341 	return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true,
342 					       duplex);
343 }
344 
345 phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,
346 					      int port)
347 {
348 	if (port == 5)
349 		return PHY_INTERFACE_MODE_2500BASEX;
350 
351 	return PHY_INTERFACE_MODE_NA;
352 }
353 
354 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
355 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
356 				    int speed, int duplex)
357 {
358 	if (speed > 1000)
359 		return -EOPNOTSUPP;
360 
361 	if (speed == 200 && port < 5)
362 		return -EOPNOTSUPP;
363 
364 	return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false,
365 					       duplex);
366 }
367 
368 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
369 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
370 				    int speed, int duplex)
371 {
372 	if (speed > 2500)
373 		return -EOPNOTSUPP;
374 
375 	if (speed == 200 && port != 0)
376 		return -EOPNOTSUPP;
377 
378 	if (speed == 2500 && port < 9)
379 		return -EOPNOTSUPP;
380 
381 	return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
382 					       duplex);
383 }
384 
385 phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,
386 					      int port)
387 {
388 	if (port == 9 || port == 10)
389 		return PHY_INTERFACE_MODE_2500BASEX;
390 
391 	return PHY_INTERFACE_MODE_NA;
392 }
393 
394 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
395 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
396 				     int speed, int duplex)
397 {
398 	if (speed == 200 && port != 0)
399 		return -EOPNOTSUPP;
400 
401 	if (speed >= 2500 && port < 9)
402 		return -EOPNOTSUPP;
403 
404 	return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true,
405 					       duplex);
406 }
407 
408 phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
409 					       int port)
410 {
411 	if (port == 9 || port == 10)
412 		return PHY_INTERFACE_MODE_XAUI;
413 
414 	return PHY_INTERFACE_MODE_NA;
415 }
416 
417 /* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X)
418  * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register
419  * values for speeds 2500 & 5000 conflict.
420  */
421 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
422 				     int speed, int duplex)
423 {
424 	u16 reg, ctrl;
425 	int err;
426 
427 	if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 &&
428 	    speed > 2500)
429 		return -EOPNOTSUPP;
430 
431 	if (speed == 200 && port != 0)
432 		return -EOPNOTSUPP;
433 
434 	if (speed >= 2500 && port > 0 && port < 9)
435 		return -EOPNOTSUPP;
436 
437 	switch (speed) {
438 	case 10:
439 		ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
440 		break;
441 	case 100:
442 		ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
443 		break;
444 	case 200:
445 		ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
446 			MV88E6390_PORT_MAC_CTL_ALTSPEED;
447 		break;
448 	case 1000:
449 		ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
450 		break;
451 	case 2500:
452 		ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 |
453 			MV88E6390_PORT_MAC_CTL_ALTSPEED;
454 		break;
455 	case 5000:
456 		ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
457 			MV88E6390_PORT_MAC_CTL_ALTSPEED;
458 		break;
459 	case 10000:
460 	case SPEED_UNFORCED:
461 		ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
462 		break;
463 	default:
464 		return -EOPNOTSUPP;
465 	}
466 
467 	switch (duplex) {
468 	case DUPLEX_HALF:
469 		ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
470 		break;
471 	case DUPLEX_FULL:
472 		ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
473 			MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
474 		break;
475 	case DUPLEX_UNFORCED:
476 		/* normal duplex detection */
477 		break;
478 	default:
479 		return -EOPNOTSUPP;
480 	}
481 
482 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
483 	if (err)
484 		return err;
485 
486 	reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
487 		 MV88E6390_PORT_MAC_CTL_ALTSPEED |
488 		 MV88E6390_PORT_MAC_CTL_FORCE_SPEED);
489 
490 	if (speed != SPEED_UNFORCED)
491 		reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
492 
493 	reg |= ctrl;
494 
495 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
496 	if (err)
497 		return err;
498 
499 	if (speed != SPEED_UNFORCED)
500 		dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
501 	else
502 		dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
503 	dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
504 		reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
505 		reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
506 
507 	return 0;
508 }
509 
510 phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
511 					       int port)
512 {
513 
514 	if (port != 0 && port != 9 && port != 10)
515 		return PHY_INTERFACE_MODE_NA;
516 
517 	if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361)
518 		return PHY_INTERFACE_MODE_2500BASEX;
519 
520 	return PHY_INTERFACE_MODE_10GBASER;
521 }
522 
523 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
524 				    phy_interface_t mode, bool force)
525 {
526 	u16 cmode;
527 	int lane;
528 	u16 reg;
529 	int err;
530 
531 	/* Default to a slow mode, so freeing up SERDES interfaces for
532 	 * other ports which might use them for SFPs.
533 	 */
534 	if (mode == PHY_INTERFACE_MODE_NA)
535 		mode = PHY_INTERFACE_MODE_1000BASEX;
536 
537 	switch (mode) {
538 	case PHY_INTERFACE_MODE_RMII:
539 		cmode = MV88E6XXX_PORT_STS_CMODE_RMII;
540 		break;
541 	case PHY_INTERFACE_MODE_RGMII:
542 	case PHY_INTERFACE_MODE_RGMII_ID:
543 	case PHY_INTERFACE_MODE_RGMII_RXID:
544 	case PHY_INTERFACE_MODE_RGMII_TXID:
545 		cmode = MV88E6XXX_PORT_STS_CMODE_RGMII;
546 		break;
547 	case PHY_INTERFACE_MODE_1000BASEX:
548 		cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX;
549 		break;
550 	case PHY_INTERFACE_MODE_SGMII:
551 		cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
552 		break;
553 	case PHY_INTERFACE_MODE_2500BASEX:
554 		cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
555 		break;
556 	case PHY_INTERFACE_MODE_5GBASER:
557 		cmode = MV88E6393X_PORT_STS_CMODE_5GBASER;
558 		break;
559 	case PHY_INTERFACE_MODE_XGMII:
560 	case PHY_INTERFACE_MODE_XAUI:
561 		cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
562 		break;
563 	case PHY_INTERFACE_MODE_RXAUI:
564 		cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
565 		break;
566 	case PHY_INTERFACE_MODE_10GBASER:
567 		cmode = MV88E6393X_PORT_STS_CMODE_10GBASER;
568 		break;
569 	case PHY_INTERFACE_MODE_USXGMII:
570 		cmode = MV88E6393X_PORT_STS_CMODE_USXGMII;
571 		break;
572 	default:
573 		cmode = 0;
574 	}
575 
576 	/* cmode doesn't change, nothing to do for us unless forced */
577 	if (cmode == chip->ports[port].cmode && !force)
578 		return 0;
579 
580 	lane = mv88e6xxx_serdes_get_lane(chip, port);
581 	if (lane >= 0) {
582 		if (chip->ports[port].serdes_irq) {
583 			err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
584 			if (err)
585 				return err;
586 		}
587 
588 		err = mv88e6xxx_serdes_power_down(chip, port, lane);
589 		if (err)
590 			return err;
591 	}
592 
593 	chip->ports[port].cmode = 0;
594 
595 	if (cmode) {
596 		err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
597 		if (err)
598 			return err;
599 
600 		reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
601 		reg |= cmode;
602 
603 		err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
604 		if (err)
605 			return err;
606 
607 		chip->ports[port].cmode = cmode;
608 
609 		lane = mv88e6xxx_serdes_get_lane(chip, port);
610 		if (lane == -ENODEV)
611 			return 0;
612 		if (lane < 0)
613 			return lane;
614 
615 		err = mv88e6xxx_serdes_power_up(chip, port, lane);
616 		if (err)
617 			return err;
618 
619 		if (chip->ports[port].serdes_irq) {
620 			err = mv88e6xxx_serdes_irq_enable(chip, port, lane);
621 			if (err)
622 				return err;
623 		}
624 	}
625 
626 	return 0;
627 }
628 
629 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
630 			      phy_interface_t mode)
631 {
632 	if (port != 9 && port != 10)
633 		return -EOPNOTSUPP;
634 
635 	return mv88e6xxx_port_set_cmode(chip, port, mode, false);
636 }
637 
638 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
639 			     phy_interface_t mode)
640 {
641 	if (port != 9 && port != 10)
642 		return -EOPNOTSUPP;
643 
644 	switch (mode) {
645 	case PHY_INTERFACE_MODE_NA:
646 		return 0;
647 	case PHY_INTERFACE_MODE_XGMII:
648 	case PHY_INTERFACE_MODE_XAUI:
649 	case PHY_INTERFACE_MODE_RXAUI:
650 		return -EINVAL;
651 	default:
652 		break;
653 	}
654 
655 	return mv88e6xxx_port_set_cmode(chip, port, mode, false);
656 }
657 
658 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
659 			      phy_interface_t mode)
660 {
661 	int err;
662 	u16 reg;
663 
664 	if (port != 0 && port != 9 && port != 10)
665 		return -EOPNOTSUPP;
666 
667 	if (port == 9 || port == 10) {
668 		switch (mode) {
669 		case PHY_INTERFACE_MODE_RMII:
670 		case PHY_INTERFACE_MODE_RGMII:
671 		case PHY_INTERFACE_MODE_RGMII_ID:
672 		case PHY_INTERFACE_MODE_RGMII_RXID:
673 		case PHY_INTERFACE_MODE_RGMII_TXID:
674 			return -EINVAL;
675 		default:
676 			break;
677 		}
678 	}
679 
680 	/* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */
681 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
682 	if (err)
683 		return err;
684 
685 	reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE;
686 	reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE;
687 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
688 	if (err)
689 		return err;
690 
691 	return mv88e6xxx_port_set_cmode(chip, port, mode, false);
692 }
693 
694 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip,
695 					     int port)
696 {
697 	int err, addr;
698 	u16 reg, bits;
699 
700 	if (port != 5)
701 		return -EOPNOTSUPP;
702 
703 	addr = chip->info->port_base_addr + port;
704 
705 	err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, &reg);
706 	if (err)
707 		return err;
708 
709 	bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE |
710 	       MV88E6341_PORT_RESERVED_1A_SGMII_AN;
711 
712 	if ((reg & bits) == bits)
713 		return 0;
714 
715 	reg |= bits;
716 	return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg);
717 }
718 
719 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
720 			     phy_interface_t mode)
721 {
722 	int err;
723 
724 	if (port != 5)
725 		return -EOPNOTSUPP;
726 
727 	switch (mode) {
728 	case PHY_INTERFACE_MODE_NA:
729 		return 0;
730 	case PHY_INTERFACE_MODE_XGMII:
731 	case PHY_INTERFACE_MODE_XAUI:
732 	case PHY_INTERFACE_MODE_RXAUI:
733 		return -EINVAL;
734 	default:
735 		break;
736 	}
737 
738 	err = mv88e6341_port_set_cmode_writable(chip, port);
739 	if (err)
740 		return err;
741 
742 	return mv88e6xxx_port_set_cmode(chip, port, mode, true);
743 }
744 
745 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
746 {
747 	int err;
748 	u16 reg;
749 
750 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
751 	if (err)
752 		return err;
753 
754 	*cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
755 
756 	return 0;
757 }
758 
759 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
760 {
761 	int err;
762 	u16 reg;
763 
764 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
765 	if (err)
766 		return err;
767 
768 	*cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
769 
770 	return 0;
771 }
772 
773 /* Offset 0x02: Jamming Control
774  *
775  * Do not limit the period of time that this port can be paused for by
776  * the remote end or the period of time that this port can pause the
777  * remote end.
778  */
779 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
780 			       u8 out)
781 {
782 	return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
783 				    out << 8 | in);
784 }
785 
786 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
787 			       u8 out)
788 {
789 	int err;
790 
791 	err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
792 				   MV88E6390_PORT_FLOW_CTL_UPDATE |
793 				   MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
794 	if (err)
795 		return err;
796 
797 	return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
798 				    MV88E6390_PORT_FLOW_CTL_UPDATE |
799 				    MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
800 }
801 
802 /* Offset 0x04: Port Control Register */
803 
804 static const char * const mv88e6xxx_port_state_names[] = {
805 	[MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
806 	[MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
807 	[MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
808 	[MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
809 };
810 
811 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
812 {
813 	u16 reg;
814 	int err;
815 
816 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
817 	if (err)
818 		return err;
819 
820 	reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
821 
822 	switch (state) {
823 	case BR_STATE_DISABLED:
824 		state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
825 		break;
826 	case BR_STATE_BLOCKING:
827 	case BR_STATE_LISTENING:
828 		state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
829 		break;
830 	case BR_STATE_LEARNING:
831 		state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
832 		break;
833 	case BR_STATE_FORWARDING:
834 		state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
835 		break;
836 	default:
837 		return -EINVAL;
838 	}
839 
840 	reg |= state;
841 
842 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
843 	if (err)
844 		return err;
845 
846 	dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
847 		mv88e6xxx_port_state_names[state]);
848 
849 	return 0;
850 }
851 
852 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
853 				   enum mv88e6xxx_egress_mode mode)
854 {
855 	int err;
856 	u16 reg;
857 
858 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
859 	if (err)
860 		return err;
861 
862 	reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
863 
864 	switch (mode) {
865 	case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
866 		reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
867 		break;
868 	case MV88E6XXX_EGRESS_MODE_UNTAGGED:
869 		reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
870 		break;
871 	case MV88E6XXX_EGRESS_MODE_TAGGED:
872 		reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
873 		break;
874 	case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
875 		reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
876 		break;
877 	default:
878 		return -EINVAL;
879 	}
880 
881 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
882 }
883 
884 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
885 				  enum mv88e6xxx_frame_mode mode)
886 {
887 	int err;
888 	u16 reg;
889 
890 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
891 	if (err)
892 		return err;
893 
894 	reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
895 
896 	switch (mode) {
897 	case MV88E6XXX_FRAME_MODE_NORMAL:
898 		reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
899 		break;
900 	case MV88E6XXX_FRAME_MODE_DSA:
901 		reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
902 		break;
903 	default:
904 		return -EINVAL;
905 	}
906 
907 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
908 }
909 
910 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
911 				  enum mv88e6xxx_frame_mode mode)
912 {
913 	int err;
914 	u16 reg;
915 
916 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
917 	if (err)
918 		return err;
919 
920 	reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
921 
922 	switch (mode) {
923 	case MV88E6XXX_FRAME_MODE_NORMAL:
924 		reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
925 		break;
926 	case MV88E6XXX_FRAME_MODE_DSA:
927 		reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
928 		break;
929 	case MV88E6XXX_FRAME_MODE_PROVIDER:
930 		reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
931 		break;
932 	case MV88E6XXX_FRAME_MODE_ETHERTYPE:
933 		reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
934 		break;
935 	default:
936 		return -EINVAL;
937 	}
938 
939 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
940 }
941 
942 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
943 				       int port, bool unicast)
944 {
945 	int err;
946 	u16 reg;
947 
948 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
949 	if (err)
950 		return err;
951 
952 	if (unicast)
953 		reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
954 	else
955 		reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
956 
957 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
958 }
959 
960 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
961 				   bool unicast)
962 {
963 	int err;
964 	u16 reg;
965 
966 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
967 	if (err)
968 		return err;
969 
970 	if (unicast)
971 		reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
972 	else
973 		reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC;
974 
975 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
976 }
977 
978 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
979 				   bool multicast)
980 {
981 	int err;
982 	u16 reg;
983 
984 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
985 	if (err)
986 		return err;
987 
988 	if (multicast)
989 		reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
990 	else
991 		reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC;
992 
993 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
994 }
995 
996 /* Offset 0x05: Port Control 1 */
997 
998 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
999 				    bool message_port)
1000 {
1001 	u16 val;
1002 	int err;
1003 
1004 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
1005 	if (err)
1006 		return err;
1007 
1008 	if (message_port)
1009 		val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
1010 	else
1011 		val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
1012 
1013 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
1014 }
1015 
1016 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
1017 			     bool trunk, u8 id)
1018 {
1019 	u16 val;
1020 	int err;
1021 
1022 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
1023 	if (err)
1024 		return err;
1025 
1026 	val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK;
1027 
1028 	if (trunk)
1029 		val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT |
1030 			(id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT);
1031 	else
1032 		val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT;
1033 
1034 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
1035 }
1036 
1037 /* Offset 0x06: Port Based VLAN Map */
1038 
1039 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
1040 {
1041 	const u16 mask = mv88e6xxx_port_mask(chip);
1042 	u16 reg;
1043 	int err;
1044 
1045 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
1046 	if (err)
1047 		return err;
1048 
1049 	reg &= ~mask;
1050 	reg |= map & mask;
1051 
1052 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1053 	if (err)
1054 		return err;
1055 
1056 	dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
1057 
1058 	return 0;
1059 }
1060 
1061 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
1062 {
1063 	const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1064 	u16 reg;
1065 	int err;
1066 
1067 	/* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1068 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
1069 	if (err)
1070 		return err;
1071 
1072 	*fid = (reg & 0xf000) >> 12;
1073 
1074 	/* Port's default FID upper bits are located in reg 0x05, offset 0 */
1075 	if (upper_mask) {
1076 		err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1077 					  &reg);
1078 		if (err)
1079 			return err;
1080 
1081 		*fid |= (reg & upper_mask) << 4;
1082 	}
1083 
1084 	return 0;
1085 }
1086 
1087 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
1088 {
1089 	const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
1090 	u16 reg;
1091 	int err;
1092 
1093 	if (fid >= mv88e6xxx_num_databases(chip))
1094 		return -EINVAL;
1095 
1096 	/* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
1097 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, &reg);
1098 	if (err)
1099 		return err;
1100 
1101 	reg &= 0x0fff;
1102 	reg |= (fid & 0x000f) << 12;
1103 
1104 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
1105 	if (err)
1106 		return err;
1107 
1108 	/* Port's default FID upper bits are located in reg 0x05, offset 0 */
1109 	if (upper_mask) {
1110 		err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
1111 					  &reg);
1112 		if (err)
1113 			return err;
1114 
1115 		reg &= ~upper_mask;
1116 		reg |= (fid >> 4) & upper_mask;
1117 
1118 		err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
1119 					   reg);
1120 		if (err)
1121 			return err;
1122 	}
1123 
1124 	dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
1125 
1126 	return 0;
1127 }
1128 
1129 /* Offset 0x07: Default Port VLAN ID & Priority */
1130 
1131 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
1132 {
1133 	u16 reg;
1134 	int err;
1135 
1136 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1137 				  &reg);
1138 	if (err)
1139 		return err;
1140 
1141 	*pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1142 
1143 	return 0;
1144 }
1145 
1146 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
1147 {
1148 	u16 reg;
1149 	int err;
1150 
1151 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1152 				  &reg);
1153 	if (err)
1154 		return err;
1155 
1156 	reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1157 	reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
1158 
1159 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
1160 				   reg);
1161 	if (err)
1162 		return err;
1163 
1164 	dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
1165 
1166 	return 0;
1167 }
1168 
1169 /* Offset 0x08: Port Control 2 Register */
1170 
1171 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1172 	[MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
1173 	[MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
1174 	[MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
1175 	[MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
1176 };
1177 
1178 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
1179 				       int port, bool multicast)
1180 {
1181 	int err;
1182 	u16 reg;
1183 
1184 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1185 	if (err)
1186 		return err;
1187 
1188 	if (multicast)
1189 		reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1190 	else
1191 		reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
1192 
1193 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1194 }
1195 
1196 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1197 				     int upstream_port)
1198 {
1199 	int err;
1200 	u16 reg;
1201 
1202 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1203 	if (err)
1204 		return err;
1205 
1206 	reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
1207 	reg |= upstream_port;
1208 
1209 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1210 }
1211 
1212 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
1213 			      enum mv88e6xxx_egress_direction direction,
1214 			      bool mirror)
1215 {
1216 	bool *mirror_port;
1217 	u16 reg;
1218 	u16 bit;
1219 	int err;
1220 
1221 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1222 	if (err)
1223 		return err;
1224 
1225 	switch (direction) {
1226 	case MV88E6XXX_EGRESS_DIR_INGRESS:
1227 		bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR;
1228 		mirror_port = &chip->ports[port].mirror_ingress;
1229 		break;
1230 	case MV88E6XXX_EGRESS_DIR_EGRESS:
1231 		bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR;
1232 		mirror_port = &chip->ports[port].mirror_egress;
1233 		break;
1234 	default:
1235 		return -EINVAL;
1236 	}
1237 
1238 	reg &= ~bit;
1239 	if (mirror)
1240 		reg |= bit;
1241 
1242 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1243 	if (!err)
1244 		*mirror_port = mirror;
1245 
1246 	return err;
1247 }
1248 
1249 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port,
1250 			    bool locked)
1251 {
1252 	u16 reg;
1253 	int err;
1254 
1255 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, &reg);
1256 	if (err)
1257 		return err;
1258 
1259 	reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK;
1260 	if (locked)
1261 		reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK;
1262 
1263 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1264 	if (err)
1265 		return err;
1266 
1267 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, &reg);
1268 	if (err)
1269 		return err;
1270 
1271 	reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1272 	if (locked)
1273 		reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT;
1274 
1275 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg);
1276 }
1277 
1278 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
1279 				  u16 mode)
1280 {
1281 	u16 reg;
1282 	int err;
1283 
1284 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1285 	if (err)
1286 		return err;
1287 
1288 	reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1289 	reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
1290 
1291 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1292 	if (err)
1293 		return err;
1294 
1295 	dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
1296 		mv88e6xxx_port_8021q_mode_names[mode]);
1297 
1298 	return 0;
1299 }
1300 
1301 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,
1302 				 bool drop_untagged)
1303 {
1304 	u16 old, new;
1305 	int err;
1306 
1307 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old);
1308 	if (err)
1309 		return err;
1310 
1311 	if (drop_untagged)
1312 		new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;
1313 	else
1314 		new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;
1315 
1316 	if (new == old)
1317 		return 0;
1318 
1319 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new);
1320 }
1321 
1322 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map)
1323 {
1324 	u16 reg;
1325 	int err;
1326 
1327 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1328 	if (err)
1329 		return err;
1330 
1331 	if (map)
1332 		reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
1333 	else
1334 		reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA;
1335 
1336 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1337 }
1338 
1339 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
1340 				  size_t size)
1341 {
1342 	u16 reg;
1343 	int err;
1344 
1345 	size += VLAN_ETH_HLEN + ETH_FCS_LEN;
1346 
1347 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &reg);
1348 	if (err)
1349 		return err;
1350 
1351 	reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
1352 
1353 	if (size <= 1522)
1354 		reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
1355 	else if (size <= 2048)
1356 		reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
1357 	else if (size <= 10240)
1358 		reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
1359 	else
1360 		return -ERANGE;
1361 
1362 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
1363 }
1364 
1365 /* Offset 0x09: Port Rate Control */
1366 
1367 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1368 {
1369 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1370 				    0x0000);
1371 }
1372 
1373 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
1374 {
1375 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
1376 				    0x0001);
1377 }
1378 
1379 /* Offset 0x0B: Port Association Vector */
1380 
1381 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,
1382 				    u16 pav)
1383 {
1384 	u16 reg, mask;
1385 	int err;
1386 
1387 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1388 				  &reg);
1389 	if (err)
1390 		return err;
1391 
1392 	mask = mv88e6xxx_port_mask(chip);
1393 	reg &= ~mask;
1394 	reg |= pav & mask;
1395 
1396 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
1397 				    reg);
1398 }
1399 
1400 /* Offset 0x0C: Port ATU Control */
1401 
1402 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
1403 {
1404 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
1405 }
1406 
1407 /* Offset 0x0D: (Priority) Override Register */
1408 
1409 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
1410 {
1411 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
1412 }
1413 
1414 /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */
1415 
1416 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port,
1417 				       u16 pointer, u8 *data)
1418 {
1419 	u16 reg;
1420 	int err;
1421 
1422 	err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1423 				   pointer);
1424 	if (err)
1425 		return err;
1426 
1427 	err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1428 				  &reg);
1429 	if (err)
1430 		return err;
1431 
1432 	*data = reg;
1433 
1434 	return 0;
1435 }
1436 
1437 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port,
1438 					u16 pointer, u8 data)
1439 {
1440 	u16 reg;
1441 
1442 	reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data;
1443 
1444 	return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL,
1445 				    reg);
1446 }
1447 
1448 static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip,
1449 					    u16 pointer, u8 data)
1450 {
1451 	int err, port;
1452 
1453 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1454 		if (dsa_is_unused_port(chip->ds, port))
1455 			continue;
1456 
1457 		err = mv88e6393x_port_policy_write(chip, port, pointer, data);
1458 		if (err)
1459 			return err;
1460 	}
1461 
1462 	return 0;
1463 }
1464 
1465 int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip,
1466 			       enum mv88e6xxx_egress_direction direction,
1467 			       int port)
1468 {
1469 	u16 ptr;
1470 	int err;
1471 
1472 	switch (direction) {
1473 	case MV88E6XXX_EGRESS_DIR_INGRESS:
1474 		ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST;
1475 		err = mv88e6393x_port_policy_write_all(chip, ptr, port);
1476 		if (err)
1477 			return err;
1478 		break;
1479 	case MV88E6XXX_EGRESS_DIR_EGRESS:
1480 		ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST;
1481 		err = mv88e6xxx_g2_write(chip, ptr, port);
1482 		if (err)
1483 			return err;
1484 		break;
1485 	}
1486 
1487 	return 0;
1488 }
1489 
1490 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
1491 				      int upstream_port)
1492 {
1493 	u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST;
1494 	u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI |
1495 		  upstream_port;
1496 
1497 	return mv88e6393x_port_policy_write(chip, port, ptr, data);
1498 }
1499 
1500 int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
1501 {
1502 	u16 ptr;
1503 	int err;
1504 
1505 	/* Consider the frames with reserved multicast destination
1506 	 * addresses matching 01:80:c2:00:00:00 and
1507 	 * 01:80:c2:00:00:02 as MGMT.
1508 	 */
1509 	ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO;
1510 	err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1511 	if (err)
1512 		return err;
1513 
1514 	ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI;
1515 	err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1516 	if (err)
1517 		return err;
1518 
1519 	ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO;
1520 	err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1521 	if (err)
1522 		return err;
1523 
1524 	ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI;
1525 	err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff);
1526 	if (err)
1527 		return err;
1528 
1529 	return 0;
1530 }
1531 
1532 /* Offset 0x10 & 0x11: EPC */
1533 
1534 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port)
1535 {
1536 	int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY);
1537 
1538 	return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0);
1539 }
1540 
1541 /* Port Ether type for 6393X family */
1542 
1543 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1544 				   u16 etype)
1545 {
1546 	u16 val;
1547 	int err;
1548 
1549 	err = mv88e6393x_port_epc_wait_ready(chip, port);
1550 	if (err)
1551 		return err;
1552 
1553 	err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype);
1554 	if (err)
1555 		return err;
1556 
1557 	val = MV88E6393X_PORT_EPC_CMD_BUSY |
1558 	      MV88E6393X_PORT_EPC_CMD_WRITE |
1559 	      MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE;
1560 
1561 	return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val);
1562 }
1563 
1564 /* Offset 0x0f: Port Ether type */
1565 
1566 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
1567 				  u16 etype)
1568 {
1569 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
1570 }
1571 
1572 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
1573  * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
1574  */
1575 
1576 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1577 {
1578 	int err;
1579 
1580 	/* Use a direct priority mapping for all IEEE tagged frames */
1581 	err = mv88e6xxx_port_write(chip, port,
1582 				   MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
1583 				   0x3210);
1584 	if (err)
1585 		return err;
1586 
1587 	return mv88e6xxx_port_write(chip, port,
1588 				    MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
1589 				    0x7654);
1590 }
1591 
1592 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
1593 					int port, u16 table, u8 ptr, u16 data)
1594 {
1595 	u16 reg;
1596 
1597 	reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
1598 		(ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
1599 		(data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
1600 
1601 	return mv88e6xxx_port_write(chip, port,
1602 				    MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
1603 }
1604 
1605 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
1606 {
1607 	int err, i;
1608 	u16 table;
1609 
1610 	for (i = 0; i <= 7; i++) {
1611 		table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
1612 		err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
1613 						   (i | i << 4));
1614 		if (err)
1615 			return err;
1616 
1617 		table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
1618 		err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1619 		if (err)
1620 			return err;
1621 
1622 		table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
1623 		err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1624 		if (err)
1625 			return err;
1626 
1627 		table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
1628 		err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
1629 		if (err)
1630 			return err;
1631 	}
1632 
1633 	return 0;
1634 }
1635 
1636 /* Offset 0x0E: Policy Control Register */
1637 
1638 static int
1639 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping,
1640 				      enum mv88e6xxx_policy_action action,
1641 				      u16 *mask, u16 *val, int *shift)
1642 {
1643 	switch (mapping) {
1644 	case MV88E6XXX_POLICY_MAPPING_DA:
1645 		*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK);
1646 		*mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK;
1647 		break;
1648 	case MV88E6XXX_POLICY_MAPPING_SA:
1649 		*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK);
1650 		*mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK;
1651 		break;
1652 	case MV88E6XXX_POLICY_MAPPING_VTU:
1653 		*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK);
1654 		*mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK;
1655 		break;
1656 	case MV88E6XXX_POLICY_MAPPING_ETYPE:
1657 		*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK);
1658 		*mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK;
1659 		break;
1660 	case MV88E6XXX_POLICY_MAPPING_PPPOE:
1661 		*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK);
1662 		*mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK;
1663 		break;
1664 	case MV88E6XXX_POLICY_MAPPING_VBAS:
1665 		*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK);
1666 		*mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK;
1667 		break;
1668 	case MV88E6XXX_POLICY_MAPPING_OPT82:
1669 		*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK);
1670 		*mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK;
1671 		break;
1672 	case MV88E6XXX_POLICY_MAPPING_UDP:
1673 		*shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK);
1674 		*mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK;
1675 		break;
1676 	default:
1677 		return -EOPNOTSUPP;
1678 	}
1679 
1680 	switch (action) {
1681 	case MV88E6XXX_POLICY_ACTION_NORMAL:
1682 		*val = MV88E6XXX_PORT_POLICY_CTL_NORMAL;
1683 		break;
1684 	case MV88E6XXX_POLICY_ACTION_MIRROR:
1685 		*val = MV88E6XXX_PORT_POLICY_CTL_MIRROR;
1686 		break;
1687 	case MV88E6XXX_POLICY_ACTION_TRAP:
1688 		*val = MV88E6XXX_PORT_POLICY_CTL_TRAP;
1689 		break;
1690 	case MV88E6XXX_POLICY_ACTION_DISCARD:
1691 		*val = MV88E6XXX_PORT_POLICY_CTL_DISCARD;
1692 		break;
1693 	default:
1694 		return -EOPNOTSUPP;
1695 	}
1696 
1697 	return 0;
1698 }
1699 
1700 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1701 			      enum mv88e6xxx_policy_mapping mapping,
1702 			      enum mv88e6xxx_policy_action action)
1703 {
1704 	u16 reg, mask, val;
1705 	int shift;
1706 	int err;
1707 
1708 	err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
1709 						    &val, &shift);
1710 	if (err)
1711 		return err;
1712 
1713 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, &reg);
1714 	if (err)
1715 		return err;
1716 
1717 	reg &= ~mask;
1718 	reg |= (val << shift) & mask;
1719 
1720 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg);
1721 }
1722 
1723 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
1724 			       enum mv88e6xxx_policy_mapping mapping,
1725 			       enum mv88e6xxx_policy_action action)
1726 {
1727 	u16 mask, val;
1728 	int shift;
1729 	int err;
1730 	u16 ptr;
1731 	u8 reg;
1732 
1733 	err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask,
1734 						    &val, &shift);
1735 	if (err)
1736 		return err;
1737 
1738 	/* The 16-bit Port Policy CTL register from older chips is on 6393x
1739 	 * changed to Port Policy MGMT CTL, which can access more data, but
1740 	 * indirectly. The original 16-bit value is divided into two 8-bit
1741 	 * registers.
1742 	 */
1743 	ptr = shift / 8;
1744 	shift %= 8;
1745 	mask >>= ptr * 8;
1746 
1747 	err = mv88e6393x_port_policy_read(chip, port, ptr, &reg);
1748 	if (err)
1749 		return err;
1750 
1751 	reg &= ~mask;
1752 	reg |= (val << shift) & mask;
1753 
1754 	return mv88e6393x_port_policy_write(chip, port, ptr, reg);
1755 }
1756