1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Port Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/if_bridge.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 16 #include "chip.h" 17 #include "global2.h" 18 #include "port.h" 19 #include "serdes.h" 20 21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 22 u16 *val) 23 { 24 int addr = chip->info->port_base_addr + port; 25 26 return mv88e6xxx_read(chip, addr, reg, val); 27 } 28 29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, 30 int bit, int val) 31 { 32 int addr = chip->info->port_base_addr + port; 33 34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); 35 } 36 37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 38 u16 val) 39 { 40 int addr = chip->info->port_base_addr + port; 41 42 return mv88e6xxx_write(chip, addr, reg, val); 43 } 44 45 /* Offset 0x00: MAC (or PCS or Physical) Status Register 46 * 47 * For most devices, this is read only. However the 6185 has the MyPause 48 * bit read/write. 49 */ 50 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 51 int pause) 52 { 53 u16 reg; 54 int err; 55 56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 57 if (err) 58 return err; 59 60 if (pause) 61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; 62 else 63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; 64 65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 66 } 67 68 /* Offset 0x01: MAC (or PCS or Physical) Control Register 69 * 70 * Link, Duplex and Flow Control have one force bit, one value bit. 71 * 72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. 73 * Alternative values require the 200BASE (or AltSpeed) bit 12 set. 74 * Newer chips need a ForcedSpd bit 13 set to consider the value. 75 */ 76 77 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 78 phy_interface_t mode) 79 { 80 u16 reg; 81 int err; 82 83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 84 if (err) 85 return err; 86 87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 88 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK); 89 90 switch (mode) { 91 case PHY_INTERFACE_MODE_RGMII_RXID: 92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; 93 break; 94 case PHY_INTERFACE_MODE_RGMII_TXID: 95 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 96 break; 97 case PHY_INTERFACE_MODE_RGMII_ID: 98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 99 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 100 break; 101 case PHY_INTERFACE_MODE_RGMII: 102 break; 103 default: 104 return 0; 105 } 106 107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 108 if (err) 109 return err; 110 111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, 112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", 113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); 114 115 return 0; 116 } 117 118 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 119 phy_interface_t mode) 120 { 121 if (port < 5) 122 return -EOPNOTSUPP; 123 124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 125 } 126 127 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 128 phy_interface_t mode) 129 { 130 if (port != 0) 131 return -EOPNOTSUPP; 132 133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 134 } 135 136 int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 137 phy_interface_t mode) 138 { 139 if (port != 2 && port != 5 && port != 6) 140 return -EOPNOTSUPP; 141 142 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 143 } 144 145 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) 146 { 147 u16 reg; 148 int err; 149 150 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 151 if (err) 152 return err; 153 154 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 155 MV88E6XXX_PORT_MAC_CTL_LINK_UP); 156 157 switch (link) { 158 case LINK_FORCED_DOWN: 159 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; 160 break; 161 case LINK_FORCED_UP: 162 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 163 MV88E6XXX_PORT_MAC_CTL_LINK_UP; 164 break; 165 case LINK_UNFORCED: 166 /* normal link detection */ 167 break; 168 default: 169 return -EINVAL; 170 } 171 172 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 173 if (err) 174 return err; 175 176 dev_dbg(chip->dev, "p%d: %s link %s\n", port, 177 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", 178 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); 179 180 return 0; 181 } 182 183 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 184 { 185 const struct mv88e6xxx_ops *ops = chip->info->ops; 186 int err = 0; 187 int link; 188 189 if (isup) 190 link = LINK_FORCED_UP; 191 else 192 link = LINK_FORCED_DOWN; 193 194 if (ops->port_set_link) 195 err = ops->port_set_link(chip, port, link); 196 197 return err; 198 } 199 200 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 201 { 202 const struct mv88e6xxx_ops *ops = chip->info->ops; 203 int err = 0; 204 int link; 205 206 if (mode == MLO_AN_INBAND) 207 link = LINK_UNFORCED; 208 else if (isup) 209 link = LINK_FORCED_UP; 210 else 211 link = LINK_FORCED_DOWN; 212 213 if (ops->port_set_link) 214 err = ops->port_set_link(chip, port, link); 215 216 return err; 217 } 218 219 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip, 220 int port, int speed, bool alt_bit, 221 bool force_bit, int duplex) 222 { 223 u16 reg, ctrl; 224 int err; 225 226 switch (speed) { 227 case 10: 228 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 229 break; 230 case 100: 231 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 232 break; 233 case 200: 234 if (alt_bit) 235 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 236 MV88E6390_PORT_MAC_CTL_ALTSPEED; 237 else 238 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200; 239 break; 240 case 1000: 241 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 242 break; 243 case 2500: 244 if (alt_bit) 245 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 246 MV88E6390_PORT_MAC_CTL_ALTSPEED; 247 else 248 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000; 249 break; 250 case 10000: 251 /* all bits set, fall through... */ 252 case SPEED_UNFORCED: 253 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 254 break; 255 default: 256 return -EOPNOTSUPP; 257 } 258 259 switch (duplex) { 260 case DUPLEX_HALF: 261 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 262 break; 263 case DUPLEX_FULL: 264 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 265 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 266 break; 267 case DUPLEX_UNFORCED: 268 /* normal duplex detection */ 269 break; 270 default: 271 return -EOPNOTSUPP; 272 } 273 274 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 275 if (err) 276 return err; 277 278 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 279 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 280 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); 281 282 if (alt_bit) 283 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; 284 if (force_bit) { 285 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 286 if (speed != SPEED_UNFORCED) 287 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 288 } 289 reg |= ctrl; 290 291 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 292 if (err) 293 return err; 294 295 if (speed != SPEED_UNFORCED) 296 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 297 else 298 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 299 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 300 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 301 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 302 303 return 0; 304 } 305 306 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ 307 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 308 int speed, int duplex) 309 { 310 if (speed == 200 || speed > 1000) 311 return -EOPNOTSUPP; 312 313 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 314 duplex); 315 } 316 317 /* Support 10, 100 Mbps (e.g. 88E6250 family) */ 318 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 319 int speed, int duplex) 320 { 321 if (speed > 100) 322 return -EOPNOTSUPP; 323 324 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 325 duplex); 326 } 327 328 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */ 329 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 330 int speed, int duplex) 331 { 332 if (speed > 2500) 333 return -EOPNOTSUPP; 334 335 if (speed == 200 && port != 0) 336 return -EOPNOTSUPP; 337 338 if (speed == 2500 && port < 5) 339 return -EOPNOTSUPP; 340 341 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true, 342 duplex); 343 } 344 345 phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip, 346 int port) 347 { 348 if (port == 5) 349 return PHY_INTERFACE_MODE_2500BASEX; 350 351 return PHY_INTERFACE_MODE_NA; 352 } 353 354 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ 355 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 356 int speed, int duplex) 357 { 358 if (speed > 1000) 359 return -EOPNOTSUPP; 360 361 if (speed == 200 && port < 5) 362 return -EOPNOTSUPP; 363 364 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false, 365 duplex); 366 } 367 368 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ 369 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 370 int speed, int duplex) 371 { 372 if (speed > 2500) 373 return -EOPNOTSUPP; 374 375 if (speed == 200 && port != 0) 376 return -EOPNOTSUPP; 377 378 if (speed == 2500 && port < 9) 379 return -EOPNOTSUPP; 380 381 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 382 duplex); 383 } 384 385 phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip, 386 int port) 387 { 388 if (port == 9 || port == 10) 389 return PHY_INTERFACE_MODE_2500BASEX; 390 391 return PHY_INTERFACE_MODE_NA; 392 } 393 394 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ 395 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 396 int speed, int duplex) 397 { 398 if (speed == 200 && port != 0) 399 return -EOPNOTSUPP; 400 401 if (speed >= 2500 && port < 9) 402 return -EOPNOTSUPP; 403 404 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 405 duplex); 406 } 407 408 phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip, 409 int port) 410 { 411 if (port == 9 || port == 10) 412 return PHY_INTERFACE_MODE_XAUI; 413 414 return PHY_INTERFACE_MODE_NA; 415 } 416 417 /* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X) 418 * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register 419 * values for speeds 2500 & 5000 conflict. 420 */ 421 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 422 int speed, int duplex) 423 { 424 u16 reg, ctrl; 425 int err; 426 427 if (speed == 200 && port != 0) 428 return -EOPNOTSUPP; 429 430 if (speed >= 2500 && port > 0 && port < 9) 431 return -EOPNOTSUPP; 432 433 switch (speed) { 434 case 10: 435 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 436 break; 437 case 100: 438 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 439 break; 440 case 200: 441 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 442 MV88E6390_PORT_MAC_CTL_ALTSPEED; 443 break; 444 case 1000: 445 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 446 break; 447 case 2500: 448 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 | 449 MV88E6390_PORT_MAC_CTL_ALTSPEED; 450 break; 451 case 5000: 452 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 453 MV88E6390_PORT_MAC_CTL_ALTSPEED; 454 break; 455 case 10000: 456 case SPEED_UNFORCED: 457 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 458 break; 459 default: 460 return -EOPNOTSUPP; 461 } 462 463 switch (duplex) { 464 case DUPLEX_HALF: 465 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 466 break; 467 case DUPLEX_FULL: 468 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 469 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 470 break; 471 case DUPLEX_UNFORCED: 472 /* normal duplex detection */ 473 break; 474 default: 475 return -EOPNOTSUPP; 476 } 477 478 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 479 if (err) 480 return err; 481 482 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 483 MV88E6390_PORT_MAC_CTL_ALTSPEED | 484 MV88E6390_PORT_MAC_CTL_FORCE_SPEED); 485 486 if (speed != SPEED_UNFORCED) 487 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 488 489 reg |= ctrl; 490 491 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 492 if (err) 493 return err; 494 495 if (speed != SPEED_UNFORCED) 496 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 497 else 498 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 499 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 500 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 501 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 502 503 return 0; 504 } 505 506 phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip, 507 int port) 508 { 509 if (port == 0 || port == 9 || port == 10) 510 return PHY_INTERFACE_MODE_10GBASER; 511 512 return PHY_INTERFACE_MODE_NA; 513 } 514 515 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 516 phy_interface_t mode, bool force) 517 { 518 u16 cmode; 519 int lane; 520 u16 reg; 521 int err; 522 523 /* Default to a slow mode, so freeing up SERDES interfaces for 524 * other ports which might use them for SFPs. 525 */ 526 if (mode == PHY_INTERFACE_MODE_NA) 527 mode = PHY_INTERFACE_MODE_1000BASEX; 528 529 switch (mode) { 530 case PHY_INTERFACE_MODE_RMII: 531 cmode = MV88E6XXX_PORT_STS_CMODE_RMII; 532 break; 533 case PHY_INTERFACE_MODE_RGMII: 534 case PHY_INTERFACE_MODE_RGMII_ID: 535 case PHY_INTERFACE_MODE_RGMII_RXID: 536 case PHY_INTERFACE_MODE_RGMII_TXID: 537 cmode = MV88E6XXX_PORT_STS_CMODE_RGMII; 538 break; 539 case PHY_INTERFACE_MODE_1000BASEX: 540 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX; 541 break; 542 case PHY_INTERFACE_MODE_SGMII: 543 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII; 544 break; 545 case PHY_INTERFACE_MODE_2500BASEX: 546 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; 547 break; 548 case PHY_INTERFACE_MODE_5GBASER: 549 cmode = MV88E6393X_PORT_STS_CMODE_5GBASER; 550 break; 551 case PHY_INTERFACE_MODE_XGMII: 552 case PHY_INTERFACE_MODE_XAUI: 553 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; 554 break; 555 case PHY_INTERFACE_MODE_RXAUI: 556 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; 557 break; 558 case PHY_INTERFACE_MODE_10GBASER: 559 cmode = MV88E6393X_PORT_STS_CMODE_10GBASER; 560 break; 561 default: 562 cmode = 0; 563 } 564 565 /* cmode doesn't change, nothing to do for us unless forced */ 566 if (cmode == chip->ports[port].cmode && !force) 567 return 0; 568 569 lane = mv88e6xxx_serdes_get_lane(chip, port); 570 if (lane >= 0) { 571 if (chip->ports[port].serdes_irq) { 572 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 573 if (err) 574 return err; 575 } 576 577 err = mv88e6xxx_serdes_power_down(chip, port, lane); 578 if (err) 579 return err; 580 } 581 582 chip->ports[port].cmode = 0; 583 584 if (cmode) { 585 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 586 if (err) 587 return err; 588 589 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; 590 reg |= cmode; 591 592 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 593 if (err) 594 return err; 595 596 chip->ports[port].cmode = cmode; 597 598 lane = mv88e6xxx_serdes_get_lane(chip, port); 599 if (lane == -ENODEV) 600 return 0; 601 if (lane < 0) 602 return lane; 603 604 err = mv88e6xxx_serdes_power_up(chip, port, lane); 605 if (err) 606 return err; 607 608 if (chip->ports[port].serdes_irq) { 609 err = mv88e6xxx_serdes_irq_enable(chip, port, lane); 610 if (err) 611 return err; 612 } 613 } 614 615 return 0; 616 } 617 618 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 619 phy_interface_t mode) 620 { 621 if (port != 9 && port != 10) 622 return -EOPNOTSUPP; 623 624 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 625 } 626 627 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 628 phy_interface_t mode) 629 { 630 if (port != 9 && port != 10) 631 return -EOPNOTSUPP; 632 633 switch (mode) { 634 case PHY_INTERFACE_MODE_NA: 635 return 0; 636 case PHY_INTERFACE_MODE_XGMII: 637 case PHY_INTERFACE_MODE_XAUI: 638 case PHY_INTERFACE_MODE_RXAUI: 639 return -EINVAL; 640 default: 641 break; 642 } 643 644 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 645 } 646 647 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 648 phy_interface_t mode) 649 { 650 int err; 651 u16 reg; 652 653 if (port != 0 && port != 9 && port != 10) 654 return -EOPNOTSUPP; 655 656 if (port == 9 || port == 10) { 657 switch (mode) { 658 case PHY_INTERFACE_MODE_RMII: 659 case PHY_INTERFACE_MODE_RGMII: 660 case PHY_INTERFACE_MODE_RGMII_ID: 661 case PHY_INTERFACE_MODE_RGMII_RXID: 662 case PHY_INTERFACE_MODE_RGMII_TXID: 663 return -EINVAL; 664 default: 665 break; 666 } 667 } 668 669 /* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */ 670 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 671 if (err) 672 return err; 673 674 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE; 675 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE; 676 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 677 if (err) 678 return err; 679 680 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 681 } 682 683 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip, 684 int port) 685 { 686 int err, addr; 687 u16 reg, bits; 688 689 if (port != 5) 690 return -EOPNOTSUPP; 691 692 addr = chip->info->port_base_addr + port; 693 694 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); 695 if (err) 696 return err; 697 698 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE | 699 MV88E6341_PORT_RESERVED_1A_SGMII_AN; 700 701 if ((reg & bits) == bits) 702 return 0; 703 704 reg |= bits; 705 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); 706 } 707 708 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 709 phy_interface_t mode) 710 { 711 int err; 712 713 if (port != 5) 714 return -EOPNOTSUPP; 715 716 switch (mode) { 717 case PHY_INTERFACE_MODE_NA: 718 return 0; 719 case PHY_INTERFACE_MODE_XGMII: 720 case PHY_INTERFACE_MODE_XAUI: 721 case PHY_INTERFACE_MODE_RXAUI: 722 return -EINVAL; 723 default: 724 break; 725 } 726 727 err = mv88e6341_port_set_cmode_writable(chip, port); 728 if (err) 729 return err; 730 731 return mv88e6xxx_port_set_cmode(chip, port, mode, true); 732 } 733 734 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 735 { 736 int err; 737 u16 reg; 738 739 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 740 if (err) 741 return err; 742 743 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; 744 745 return 0; 746 } 747 748 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 749 { 750 int err; 751 u16 reg; 752 753 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 754 if (err) 755 return err; 756 757 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; 758 759 return 0; 760 } 761 762 /* Offset 0x02: Jamming Control 763 * 764 * Do not limit the period of time that this port can be paused for by 765 * the remote end or the period of time that this port can pause the 766 * remote end. 767 */ 768 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 769 u8 out) 770 { 771 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, 772 out << 8 | in); 773 } 774 775 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 776 u8 out) 777 { 778 int err; 779 780 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 781 MV88E6390_PORT_FLOW_CTL_UPDATE | 782 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in); 783 if (err) 784 return err; 785 786 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 787 MV88E6390_PORT_FLOW_CTL_UPDATE | 788 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out); 789 } 790 791 /* Offset 0x04: Port Control Register */ 792 793 static const char * const mv88e6xxx_port_state_names[] = { 794 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", 795 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", 796 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", 797 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", 798 }; 799 800 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) 801 { 802 u16 reg; 803 int err; 804 805 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 806 if (err) 807 return err; 808 809 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; 810 811 switch (state) { 812 case BR_STATE_DISABLED: 813 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED; 814 break; 815 case BR_STATE_BLOCKING: 816 case BR_STATE_LISTENING: 817 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 818 break; 819 case BR_STATE_LEARNING: 820 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 821 break; 822 case BR_STATE_FORWARDING: 823 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 824 break; 825 default: 826 return -EINVAL; 827 } 828 829 reg |= state; 830 831 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 832 if (err) 833 return err; 834 835 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, 836 mv88e6xxx_port_state_names[state]); 837 838 return 0; 839 } 840 841 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 842 enum mv88e6xxx_egress_mode mode) 843 { 844 int err; 845 u16 reg; 846 847 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 848 if (err) 849 return err; 850 851 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; 852 853 switch (mode) { 854 case MV88E6XXX_EGRESS_MODE_UNMODIFIED: 855 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; 856 break; 857 case MV88E6XXX_EGRESS_MODE_UNTAGGED: 858 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; 859 break; 860 case MV88E6XXX_EGRESS_MODE_TAGGED: 861 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; 862 break; 863 case MV88E6XXX_EGRESS_MODE_ETHERTYPE: 864 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; 865 break; 866 default: 867 return -EINVAL; 868 } 869 870 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 871 } 872 873 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 874 enum mv88e6xxx_frame_mode mode) 875 { 876 int err; 877 u16 reg; 878 879 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 880 if (err) 881 return err; 882 883 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 884 885 switch (mode) { 886 case MV88E6XXX_FRAME_MODE_NORMAL: 887 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 888 break; 889 case MV88E6XXX_FRAME_MODE_DSA: 890 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 891 break; 892 default: 893 return -EINVAL; 894 } 895 896 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 897 } 898 899 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 900 enum mv88e6xxx_frame_mode mode) 901 { 902 int err; 903 u16 reg; 904 905 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 906 if (err) 907 return err; 908 909 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 910 911 switch (mode) { 912 case MV88E6XXX_FRAME_MODE_NORMAL: 913 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 914 break; 915 case MV88E6XXX_FRAME_MODE_DSA: 916 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 917 break; 918 case MV88E6XXX_FRAME_MODE_PROVIDER: 919 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; 920 break; 921 case MV88E6XXX_FRAME_MODE_ETHERTYPE: 922 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; 923 break; 924 default: 925 return -EINVAL; 926 } 927 928 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 929 } 930 931 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 932 int port, bool unicast) 933 { 934 int err; 935 u16 reg; 936 937 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 938 if (err) 939 return err; 940 941 if (unicast) 942 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 943 else 944 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 945 946 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 947 } 948 949 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, 950 bool unicast) 951 { 952 int err; 953 u16 reg; 954 955 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 956 if (err) 957 return err; 958 959 if (unicast) 960 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 961 else 962 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 963 964 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 965 } 966 967 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, 968 bool multicast) 969 { 970 int err; 971 u16 reg; 972 973 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 974 if (err) 975 return err; 976 977 if (multicast) 978 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 979 else 980 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 981 982 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 983 } 984 985 /* Offset 0x05: Port Control 1 */ 986 987 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 988 bool message_port) 989 { 990 u16 val; 991 int err; 992 993 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 994 if (err) 995 return err; 996 997 if (message_port) 998 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 999 else 1000 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 1001 1002 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 1003 } 1004 1005 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, 1006 bool trunk, u8 id) 1007 { 1008 u16 val; 1009 int err; 1010 1011 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 1012 if (err) 1013 return err; 1014 1015 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK; 1016 1017 if (trunk) 1018 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT | 1019 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT); 1020 else 1021 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT; 1022 1023 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 1024 } 1025 1026 /* Offset 0x06: Port Based VLAN Map */ 1027 1028 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) 1029 { 1030 const u16 mask = mv88e6xxx_port_mask(chip); 1031 u16 reg; 1032 int err; 1033 1034 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1035 if (err) 1036 return err; 1037 1038 reg &= ~mask; 1039 reg |= map & mask; 1040 1041 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1042 if (err) 1043 return err; 1044 1045 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); 1046 1047 return 0; 1048 } 1049 1050 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) 1051 { 1052 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1053 u16 reg; 1054 int err; 1055 1056 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1057 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1058 if (err) 1059 return err; 1060 1061 *fid = (reg & 0xf000) >> 12; 1062 1063 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1064 if (upper_mask) { 1065 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1066 ®); 1067 if (err) 1068 return err; 1069 1070 *fid |= (reg & upper_mask) << 4; 1071 } 1072 1073 return 0; 1074 } 1075 1076 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) 1077 { 1078 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1079 u16 reg; 1080 int err; 1081 1082 if (fid >= mv88e6xxx_num_databases(chip)) 1083 return -EINVAL; 1084 1085 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1086 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1087 if (err) 1088 return err; 1089 1090 reg &= 0x0fff; 1091 reg |= (fid & 0x000f) << 12; 1092 1093 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1094 if (err) 1095 return err; 1096 1097 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1098 if (upper_mask) { 1099 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1100 ®); 1101 if (err) 1102 return err; 1103 1104 reg &= ~upper_mask; 1105 reg |= (fid >> 4) & upper_mask; 1106 1107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, 1108 reg); 1109 if (err) 1110 return err; 1111 } 1112 1113 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); 1114 1115 return 0; 1116 } 1117 1118 /* Offset 0x07: Default Port VLAN ID & Priority */ 1119 1120 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) 1121 { 1122 u16 reg; 1123 int err; 1124 1125 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1126 ®); 1127 if (err) 1128 return err; 1129 1130 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1131 1132 return 0; 1133 } 1134 1135 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) 1136 { 1137 u16 reg; 1138 int err; 1139 1140 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1141 ®); 1142 if (err) 1143 return err; 1144 1145 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1146 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1147 1148 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1149 reg); 1150 if (err) 1151 return err; 1152 1153 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); 1154 1155 return 0; 1156 } 1157 1158 /* Offset 0x08: Port Control 2 Register */ 1159 1160 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 1161 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", 1162 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", 1163 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", 1164 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", 1165 }; 1166 1167 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 1168 int port, bool multicast) 1169 { 1170 int err; 1171 u16 reg; 1172 1173 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1174 if (err) 1175 return err; 1176 1177 if (multicast) 1178 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1179 else 1180 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1181 1182 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1183 } 1184 1185 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1186 int upstream_port) 1187 { 1188 int err; 1189 u16 reg; 1190 1191 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1192 if (err) 1193 return err; 1194 1195 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; 1196 reg |= upstream_port; 1197 1198 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1199 } 1200 1201 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 1202 enum mv88e6xxx_egress_direction direction, 1203 bool mirror) 1204 { 1205 bool *mirror_port; 1206 u16 reg; 1207 u16 bit; 1208 int err; 1209 1210 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1211 if (err) 1212 return err; 1213 1214 switch (direction) { 1215 case MV88E6XXX_EGRESS_DIR_INGRESS: 1216 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR; 1217 mirror_port = &chip->ports[port].mirror_ingress; 1218 break; 1219 case MV88E6XXX_EGRESS_DIR_EGRESS: 1220 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR; 1221 mirror_port = &chip->ports[port].mirror_egress; 1222 break; 1223 default: 1224 return -EINVAL; 1225 } 1226 1227 reg &= ~bit; 1228 if (mirror) 1229 reg |= bit; 1230 1231 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1232 if (!err) 1233 *mirror_port = mirror; 1234 1235 return err; 1236 } 1237 1238 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, 1239 bool locked) 1240 { 1241 u16 reg; 1242 int err; 1243 1244 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 1245 if (err) 1246 return err; 1247 1248 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK; 1249 if (locked) 1250 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK; 1251 1252 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1253 if (err) 1254 return err; 1255 1256 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®); 1257 if (err) 1258 return err; 1259 1260 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1261 if (locked) 1262 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1263 1264 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg); 1265 } 1266 1267 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 1268 u16 mode) 1269 { 1270 u16 reg; 1271 int err; 1272 1273 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1274 if (err) 1275 return err; 1276 1277 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1278 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1279 1280 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1281 if (err) 1282 return err; 1283 1284 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, 1285 mv88e6xxx_port_8021q_mode_names[mode]); 1286 1287 return 0; 1288 } 1289 1290 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, 1291 bool drop_untagged) 1292 { 1293 u16 old, new; 1294 int err; 1295 1296 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old); 1297 if (err) 1298 return err; 1299 1300 if (drop_untagged) 1301 new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1302 else 1303 new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1304 1305 if (new == old) 1306 return 0; 1307 1308 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new); 1309 } 1310 1311 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map) 1312 { 1313 u16 reg; 1314 int err; 1315 1316 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1317 if (err) 1318 return err; 1319 1320 if (map) 1321 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; 1322 else 1323 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA; 1324 1325 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1326 } 1327 1328 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 1329 size_t size) 1330 { 1331 u16 reg; 1332 int err; 1333 1334 size += VLAN_ETH_HLEN + ETH_FCS_LEN; 1335 1336 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1337 if (err) 1338 return err; 1339 1340 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; 1341 1342 if (size <= 1522) 1343 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; 1344 else if (size <= 2048) 1345 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; 1346 else if (size <= 10240) 1347 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; 1348 else 1349 return -ERANGE; 1350 1351 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1352 } 1353 1354 /* Offset 0x09: Port Rate Control */ 1355 1356 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1357 { 1358 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1359 0x0000); 1360 } 1361 1362 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1363 { 1364 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1365 0x0001); 1366 } 1367 1368 /* Offset 0x0B: Port Association Vector */ 1369 1370 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, 1371 u16 pav) 1372 { 1373 u16 reg, mask; 1374 int err; 1375 1376 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1377 ®); 1378 if (err) 1379 return err; 1380 1381 mask = mv88e6xxx_port_mask(chip); 1382 reg &= ~mask; 1383 reg |= pav & mask; 1384 1385 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1386 reg); 1387 } 1388 1389 /* Offset 0x0C: Port ATU Control */ 1390 1391 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) 1392 { 1393 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); 1394 } 1395 1396 /* Offset 0x0D: (Priority) Override Register */ 1397 1398 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) 1399 { 1400 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); 1401 } 1402 1403 /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */ 1404 1405 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port, 1406 u16 pointer, u8 *data) 1407 { 1408 u16 reg; 1409 int err; 1410 1411 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1412 pointer); 1413 if (err) 1414 return err; 1415 1416 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1417 ®); 1418 if (err) 1419 return err; 1420 1421 *data = reg; 1422 1423 return 0; 1424 } 1425 1426 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port, 1427 u16 pointer, u8 data) 1428 { 1429 u16 reg; 1430 1431 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data; 1432 1433 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1434 reg); 1435 } 1436 1437 static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip, 1438 u16 pointer, u8 data) 1439 { 1440 int err, port; 1441 1442 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1443 if (dsa_is_unused_port(chip->ds, port)) 1444 continue; 1445 1446 err = mv88e6393x_port_policy_write(chip, port, pointer, data); 1447 if (err) 1448 return err; 1449 } 1450 1451 return 0; 1452 } 1453 1454 int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, 1455 enum mv88e6xxx_egress_direction direction, 1456 int port) 1457 { 1458 u16 ptr; 1459 int err; 1460 1461 switch (direction) { 1462 case MV88E6XXX_EGRESS_DIR_INGRESS: 1463 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST; 1464 err = mv88e6393x_port_policy_write_all(chip, ptr, port); 1465 if (err) 1466 return err; 1467 break; 1468 case MV88E6XXX_EGRESS_DIR_EGRESS: 1469 ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST; 1470 err = mv88e6xxx_g2_write(chip, ptr, port); 1471 if (err) 1472 return err; 1473 break; 1474 } 1475 1476 return 0; 1477 } 1478 1479 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1480 int upstream_port) 1481 { 1482 u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST; 1483 u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI | 1484 upstream_port; 1485 1486 return mv88e6393x_port_policy_write(chip, port, ptr, data); 1487 } 1488 1489 int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 1490 { 1491 u16 ptr; 1492 int err; 1493 1494 /* Consider the frames with reserved multicast destination 1495 * addresses matching 01:80:c2:00:00:00 and 1496 * 01:80:c2:00:00:02 as MGMT. 1497 */ 1498 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO; 1499 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1500 if (err) 1501 return err; 1502 1503 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI; 1504 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1505 if (err) 1506 return err; 1507 1508 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO; 1509 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1510 if (err) 1511 return err; 1512 1513 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI; 1514 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1515 if (err) 1516 return err; 1517 1518 return 0; 1519 } 1520 1521 /* Offset 0x10 & 0x11: EPC */ 1522 1523 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) 1524 { 1525 int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY); 1526 1527 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); 1528 } 1529 1530 /* Port Ether type for 6393X family */ 1531 1532 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1533 u16 etype) 1534 { 1535 u16 val; 1536 int err; 1537 1538 err = mv88e6393x_port_epc_wait_ready(chip, port); 1539 if (err) 1540 return err; 1541 1542 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype); 1543 if (err) 1544 return err; 1545 1546 val = MV88E6393X_PORT_EPC_CMD_BUSY | 1547 MV88E6393X_PORT_EPC_CMD_WRITE | 1548 MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE; 1549 1550 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val); 1551 } 1552 1553 /* Offset 0x0f: Port Ether type */ 1554 1555 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1556 u16 etype) 1557 { 1558 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); 1559 } 1560 1561 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] 1562 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] 1563 */ 1564 1565 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1566 { 1567 int err; 1568 1569 /* Use a direct priority mapping for all IEEE tagged frames */ 1570 err = mv88e6xxx_port_write(chip, port, 1571 MV88E6095_PORT_IEEE_PRIO_REMAP_0123, 1572 0x3210); 1573 if (err) 1574 return err; 1575 1576 return mv88e6xxx_port_write(chip, port, 1577 MV88E6095_PORT_IEEE_PRIO_REMAP_4567, 1578 0x7654); 1579 } 1580 1581 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, 1582 int port, u16 table, u8 ptr, u16 data) 1583 { 1584 u16 reg; 1585 1586 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | 1587 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | 1588 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK); 1589 1590 return mv88e6xxx_port_write(chip, port, 1591 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); 1592 } 1593 1594 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1595 { 1596 int err, i; 1597 u16 table; 1598 1599 for (i = 0; i <= 7; i++) { 1600 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; 1601 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, 1602 (i | i << 4)); 1603 if (err) 1604 return err; 1605 1606 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP; 1607 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1608 if (err) 1609 return err; 1610 1611 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP; 1612 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1613 if (err) 1614 return err; 1615 1616 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP; 1617 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1618 if (err) 1619 return err; 1620 } 1621 1622 return 0; 1623 } 1624 1625 /* Offset 0x0E: Policy Control Register */ 1626 1627 static int 1628 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping, 1629 enum mv88e6xxx_policy_action action, 1630 u16 *mask, u16 *val, int *shift) 1631 { 1632 switch (mapping) { 1633 case MV88E6XXX_POLICY_MAPPING_DA: 1634 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK); 1635 *mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK; 1636 break; 1637 case MV88E6XXX_POLICY_MAPPING_SA: 1638 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK); 1639 *mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK; 1640 break; 1641 case MV88E6XXX_POLICY_MAPPING_VTU: 1642 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK); 1643 *mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK; 1644 break; 1645 case MV88E6XXX_POLICY_MAPPING_ETYPE: 1646 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK); 1647 *mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK; 1648 break; 1649 case MV88E6XXX_POLICY_MAPPING_PPPOE: 1650 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK); 1651 *mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK; 1652 break; 1653 case MV88E6XXX_POLICY_MAPPING_VBAS: 1654 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK); 1655 *mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK; 1656 break; 1657 case MV88E6XXX_POLICY_MAPPING_OPT82: 1658 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK); 1659 *mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK; 1660 break; 1661 case MV88E6XXX_POLICY_MAPPING_UDP: 1662 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK); 1663 *mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK; 1664 break; 1665 default: 1666 return -EOPNOTSUPP; 1667 } 1668 1669 switch (action) { 1670 case MV88E6XXX_POLICY_ACTION_NORMAL: 1671 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL; 1672 break; 1673 case MV88E6XXX_POLICY_ACTION_MIRROR: 1674 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR; 1675 break; 1676 case MV88E6XXX_POLICY_ACTION_TRAP: 1677 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP; 1678 break; 1679 case MV88E6XXX_POLICY_ACTION_DISCARD: 1680 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD; 1681 break; 1682 default: 1683 return -EOPNOTSUPP; 1684 } 1685 1686 return 0; 1687 } 1688 1689 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1690 enum mv88e6xxx_policy_mapping mapping, 1691 enum mv88e6xxx_policy_action action) 1692 { 1693 u16 reg, mask, val; 1694 int shift; 1695 int err; 1696 1697 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1698 &val, &shift); 1699 if (err) 1700 return err; 1701 1702 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); 1703 if (err) 1704 return err; 1705 1706 reg &= ~mask; 1707 reg |= (val << shift) & mask; 1708 1709 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); 1710 } 1711 1712 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1713 enum mv88e6xxx_policy_mapping mapping, 1714 enum mv88e6xxx_policy_action action) 1715 { 1716 u16 mask, val; 1717 int shift; 1718 int err; 1719 u16 ptr; 1720 u8 reg; 1721 1722 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1723 &val, &shift); 1724 if (err) 1725 return err; 1726 1727 /* The 16-bit Port Policy CTL register from older chips is on 6393x 1728 * changed to Port Policy MGMT CTL, which can access more data, but 1729 * indirectly. The original 16-bit value is divided into two 8-bit 1730 * registers. 1731 */ 1732 ptr = shift / 8; 1733 shift %= 8; 1734 mask >>= ptr * 8; 1735 1736 err = mv88e6393x_port_policy_read(chip, port, ptr, ®); 1737 if (err) 1738 return err; 1739 1740 reg &= ~mask; 1741 reg |= (val << shift) & mask; 1742 1743 return mv88e6393x_port_policy_write(chip, port, ptr, reg); 1744 } 1745