1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Port Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/if_bridge.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 16 #include "chip.h" 17 #include "global2.h" 18 #include "port.h" 19 #include "serdes.h" 20 21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 22 u16 *val) 23 { 24 int addr = chip->info->port_base_addr + port; 25 26 return mv88e6xxx_read(chip, addr, reg, val); 27 } 28 29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, 30 int bit, int val) 31 { 32 int addr = chip->info->port_base_addr + port; 33 34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); 35 } 36 37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 38 u16 val) 39 { 40 int addr = chip->info->port_base_addr + port; 41 42 return mv88e6xxx_write(chip, addr, reg, val); 43 } 44 45 /* Offset 0x00: MAC (or PCS or Physical) Status Register 46 * 47 * For most devices, this is read only. However the 6185 has the MyPause 48 * bit read/write. 49 */ 50 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 51 int pause) 52 { 53 u16 reg; 54 int err; 55 56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 57 if (err) 58 return err; 59 60 if (pause) 61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; 62 else 63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; 64 65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 66 } 67 68 /* Offset 0x01: MAC (or PCS or Physical) Control Register 69 * 70 * Link, Duplex and Flow Control have one force bit, one value bit. 71 * 72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. 73 * Alternative values require the 200BASE (or AltSpeed) bit 12 set. 74 * Newer chips need a ForcedSpd bit 13 set to consider the value. 75 */ 76 77 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 78 phy_interface_t mode) 79 { 80 u16 reg; 81 int err; 82 83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 84 if (err) 85 return err; 86 87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 88 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK); 89 90 switch (mode) { 91 case PHY_INTERFACE_MODE_RGMII_RXID: 92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; 93 break; 94 case PHY_INTERFACE_MODE_RGMII_TXID: 95 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 96 break; 97 case PHY_INTERFACE_MODE_RGMII_ID: 98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 99 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 100 break; 101 case PHY_INTERFACE_MODE_RGMII: 102 break; 103 default: 104 return 0; 105 } 106 107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 108 if (err) 109 return err; 110 111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, 112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", 113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); 114 115 return 0; 116 } 117 118 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 119 phy_interface_t mode) 120 { 121 if (port < 5) 122 return -EOPNOTSUPP; 123 124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 125 } 126 127 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 128 phy_interface_t mode) 129 { 130 if (port != 0) 131 return -EOPNOTSUPP; 132 133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 134 } 135 136 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) 137 { 138 u16 reg; 139 int err; 140 141 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 142 if (err) 143 return err; 144 145 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 146 MV88E6XXX_PORT_MAC_CTL_LINK_UP); 147 148 switch (link) { 149 case LINK_FORCED_DOWN: 150 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; 151 break; 152 case LINK_FORCED_UP: 153 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 154 MV88E6XXX_PORT_MAC_CTL_LINK_UP; 155 break; 156 case LINK_UNFORCED: 157 /* normal link detection */ 158 break; 159 default: 160 return -EINVAL; 161 } 162 163 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 164 if (err) 165 return err; 166 167 dev_dbg(chip->dev, "p%d: %s link %s\n", port, 168 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", 169 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); 170 171 return 0; 172 } 173 174 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 175 { 176 const struct mv88e6xxx_ops *ops = chip->info->ops; 177 int err = 0; 178 int link; 179 180 if (isup) 181 link = LINK_FORCED_UP; 182 else 183 link = LINK_FORCED_DOWN; 184 185 if (ops->port_set_link) 186 err = ops->port_set_link(chip, port, link); 187 188 return err; 189 } 190 191 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 192 { 193 const struct mv88e6xxx_ops *ops = chip->info->ops; 194 int err = 0; 195 int link; 196 197 if (mode == MLO_AN_INBAND) 198 link = LINK_UNFORCED; 199 else if (isup) 200 link = LINK_FORCED_UP; 201 else 202 link = LINK_FORCED_DOWN; 203 204 if (ops->port_set_link) 205 err = ops->port_set_link(chip, port, link); 206 207 return err; 208 } 209 210 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip, 211 int port, int speed, bool alt_bit, 212 bool force_bit, int duplex) 213 { 214 u16 reg, ctrl; 215 int err; 216 217 switch (speed) { 218 case 10: 219 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 220 break; 221 case 100: 222 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 223 break; 224 case 200: 225 if (alt_bit) 226 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 227 MV88E6390_PORT_MAC_CTL_ALTSPEED; 228 else 229 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200; 230 break; 231 case 1000: 232 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 233 break; 234 case 2500: 235 if (alt_bit) 236 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 237 MV88E6390_PORT_MAC_CTL_ALTSPEED; 238 else 239 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000; 240 break; 241 case 10000: 242 /* all bits set, fall through... */ 243 case SPEED_UNFORCED: 244 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 245 break; 246 default: 247 return -EOPNOTSUPP; 248 } 249 250 switch (duplex) { 251 case DUPLEX_HALF: 252 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 253 break; 254 case DUPLEX_FULL: 255 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 256 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 257 break; 258 case DUPLEX_UNFORCED: 259 /* normal duplex detection */ 260 break; 261 default: 262 return -EOPNOTSUPP; 263 } 264 265 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 266 if (err) 267 return err; 268 269 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 270 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 271 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); 272 273 if (alt_bit) 274 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; 275 if (force_bit) { 276 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 277 if (speed != SPEED_UNFORCED) 278 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 279 } 280 reg |= ctrl; 281 282 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 283 if (err) 284 return err; 285 286 if (speed != SPEED_UNFORCED) 287 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 288 else 289 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 290 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 291 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 292 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 293 294 return 0; 295 } 296 297 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */ 298 int mv88e6065_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 299 int speed, int duplex) 300 { 301 if (speed == SPEED_MAX) 302 speed = 200; 303 304 if (speed > 200) 305 return -EOPNOTSUPP; 306 307 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */ 308 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 309 duplex); 310 } 311 312 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ 313 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 314 int speed, int duplex) 315 { 316 if (speed == SPEED_MAX) 317 speed = 1000; 318 319 if (speed == 200 || speed > 1000) 320 return -EOPNOTSUPP; 321 322 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 323 duplex); 324 } 325 326 /* Support 10, 100 Mbps (e.g. 88E6250 family) */ 327 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 328 int speed, int duplex) 329 { 330 if (speed == SPEED_MAX) 331 speed = 100; 332 333 if (speed > 100) 334 return -EOPNOTSUPP; 335 336 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 337 duplex); 338 } 339 340 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */ 341 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 342 int speed, int duplex) 343 { 344 if (speed == SPEED_MAX) 345 speed = port < 5 ? 1000 : 2500; 346 347 if (speed > 2500) 348 return -EOPNOTSUPP; 349 350 if (speed == 200 && port != 0) 351 return -EOPNOTSUPP; 352 353 if (speed == 2500 && port < 5) 354 return -EOPNOTSUPP; 355 356 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true, 357 duplex); 358 } 359 360 phy_interface_t mv88e6341_port_max_speed_mode(int port) 361 { 362 if (port == 5) 363 return PHY_INTERFACE_MODE_2500BASEX; 364 365 return PHY_INTERFACE_MODE_NA; 366 } 367 368 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ 369 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 370 int speed, int duplex) 371 { 372 if (speed == SPEED_MAX) 373 speed = 1000; 374 375 if (speed > 1000) 376 return -EOPNOTSUPP; 377 378 if (speed == 200 && port < 5) 379 return -EOPNOTSUPP; 380 381 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false, 382 duplex); 383 } 384 385 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ 386 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 387 int speed, int duplex) 388 { 389 if (speed == SPEED_MAX) 390 speed = port < 9 ? 1000 : 2500; 391 392 if (speed > 2500) 393 return -EOPNOTSUPP; 394 395 if (speed == 200 && port != 0) 396 return -EOPNOTSUPP; 397 398 if (speed == 2500 && port < 9) 399 return -EOPNOTSUPP; 400 401 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 402 duplex); 403 } 404 405 phy_interface_t mv88e6390_port_max_speed_mode(int port) 406 { 407 if (port == 9 || port == 10) 408 return PHY_INTERFACE_MODE_2500BASEX; 409 410 return PHY_INTERFACE_MODE_NA; 411 } 412 413 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ 414 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 415 int speed, int duplex) 416 { 417 if (speed == SPEED_MAX) 418 speed = port < 9 ? 1000 : 10000; 419 420 if (speed == 200 && port != 0) 421 return -EOPNOTSUPP; 422 423 if (speed >= 2500 && port < 9) 424 return -EOPNOTSUPP; 425 426 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 427 duplex); 428 } 429 430 phy_interface_t mv88e6390x_port_max_speed_mode(int port) 431 { 432 if (port == 9 || port == 10) 433 return PHY_INTERFACE_MODE_XAUI; 434 435 return PHY_INTERFACE_MODE_NA; 436 } 437 438 /* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X) 439 * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register 440 * values for speeds 2500 & 5000 conflict. 441 */ 442 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 443 int speed, int duplex) 444 { 445 u16 reg, ctrl; 446 int err; 447 448 if (speed == SPEED_MAX) 449 speed = (port > 0 && port < 9) ? 1000 : 10000; 450 451 if (speed == 200 && port != 0) 452 return -EOPNOTSUPP; 453 454 if (speed >= 2500 && port > 0 && port < 9) 455 return -EOPNOTSUPP; 456 457 switch (speed) { 458 case 10: 459 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 460 break; 461 case 100: 462 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 463 break; 464 case 200: 465 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 466 MV88E6390_PORT_MAC_CTL_ALTSPEED; 467 break; 468 case 1000: 469 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 470 break; 471 case 2500: 472 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 | 473 MV88E6390_PORT_MAC_CTL_ALTSPEED; 474 break; 475 case 5000: 476 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 477 MV88E6390_PORT_MAC_CTL_ALTSPEED; 478 break; 479 case 10000: 480 case SPEED_UNFORCED: 481 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 482 break; 483 default: 484 return -EOPNOTSUPP; 485 } 486 487 switch (duplex) { 488 case DUPLEX_HALF: 489 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 490 break; 491 case DUPLEX_FULL: 492 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 493 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 494 break; 495 case DUPLEX_UNFORCED: 496 /* normal duplex detection */ 497 break; 498 default: 499 return -EOPNOTSUPP; 500 } 501 502 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 503 if (err) 504 return err; 505 506 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 507 MV88E6390_PORT_MAC_CTL_ALTSPEED | 508 MV88E6390_PORT_MAC_CTL_FORCE_SPEED); 509 510 if (speed != SPEED_UNFORCED) 511 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 512 513 reg |= ctrl; 514 515 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 516 if (err) 517 return err; 518 519 if (speed != SPEED_UNFORCED) 520 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 521 else 522 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 523 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 524 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 525 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 526 527 return 0; 528 } 529 530 phy_interface_t mv88e6393x_port_max_speed_mode(int port) 531 { 532 if (port == 0 || port == 9 || port == 10) 533 return PHY_INTERFACE_MODE_10GBASER; 534 535 return PHY_INTERFACE_MODE_NA; 536 } 537 538 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 539 phy_interface_t mode, bool force) 540 { 541 u16 cmode; 542 int lane; 543 u16 reg; 544 int err; 545 546 /* Default to a slow mode, so freeing up SERDES interfaces for 547 * other ports which might use them for SFPs. 548 */ 549 if (mode == PHY_INTERFACE_MODE_NA) 550 mode = PHY_INTERFACE_MODE_1000BASEX; 551 552 switch (mode) { 553 case PHY_INTERFACE_MODE_1000BASEX: 554 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX; 555 break; 556 case PHY_INTERFACE_MODE_SGMII: 557 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII; 558 break; 559 case PHY_INTERFACE_MODE_2500BASEX: 560 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; 561 break; 562 case PHY_INTERFACE_MODE_5GBASER: 563 cmode = MV88E6393X_PORT_STS_CMODE_5GBASER; 564 break; 565 case PHY_INTERFACE_MODE_XGMII: 566 case PHY_INTERFACE_MODE_XAUI: 567 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; 568 break; 569 case PHY_INTERFACE_MODE_RXAUI: 570 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; 571 break; 572 case PHY_INTERFACE_MODE_10GBASER: 573 cmode = MV88E6393X_PORT_STS_CMODE_10GBASER; 574 break; 575 default: 576 cmode = 0; 577 } 578 579 /* cmode doesn't change, nothing to do for us unless forced */ 580 if (cmode == chip->ports[port].cmode && !force) 581 return 0; 582 583 lane = mv88e6xxx_serdes_get_lane(chip, port); 584 if (lane >= 0) { 585 if (chip->ports[port].serdes_irq) { 586 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 587 if (err) 588 return err; 589 } 590 591 err = mv88e6xxx_serdes_power_down(chip, port, lane); 592 if (err) 593 return err; 594 } 595 596 chip->ports[port].cmode = 0; 597 598 if (cmode) { 599 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 600 if (err) 601 return err; 602 603 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; 604 reg |= cmode; 605 606 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 607 if (err) 608 return err; 609 610 chip->ports[port].cmode = cmode; 611 612 lane = mv88e6xxx_serdes_get_lane(chip, port); 613 if (lane == -ENODEV) 614 return 0; 615 if (lane < 0) 616 return lane; 617 618 err = mv88e6xxx_serdes_power_up(chip, port, lane); 619 if (err) 620 return err; 621 622 if (chip->ports[port].serdes_irq) { 623 err = mv88e6xxx_serdes_irq_enable(chip, port, lane); 624 if (err) 625 return err; 626 } 627 } 628 629 return 0; 630 } 631 632 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 633 phy_interface_t mode) 634 { 635 if (port != 9 && port != 10) 636 return -EOPNOTSUPP; 637 638 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 639 } 640 641 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 642 phy_interface_t mode) 643 { 644 if (port != 9 && port != 10) 645 return -EOPNOTSUPP; 646 647 switch (mode) { 648 case PHY_INTERFACE_MODE_NA: 649 return 0; 650 case PHY_INTERFACE_MODE_XGMII: 651 case PHY_INTERFACE_MODE_XAUI: 652 case PHY_INTERFACE_MODE_RXAUI: 653 return -EINVAL; 654 default: 655 break; 656 } 657 658 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 659 } 660 661 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 662 phy_interface_t mode) 663 { 664 int err; 665 u16 reg; 666 667 if (port != 0 && port != 9 && port != 10) 668 return -EOPNOTSUPP; 669 670 /* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */ 671 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 672 if (err) 673 return err; 674 675 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE; 676 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE; 677 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 678 if (err) 679 return err; 680 681 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 682 } 683 684 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip, 685 int port) 686 { 687 int err, addr; 688 u16 reg, bits; 689 690 if (port != 5) 691 return -EOPNOTSUPP; 692 693 addr = chip->info->port_base_addr + port; 694 695 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); 696 if (err) 697 return err; 698 699 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE | 700 MV88E6341_PORT_RESERVED_1A_SGMII_AN; 701 702 if ((reg & bits) == bits) 703 return 0; 704 705 reg |= bits; 706 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); 707 } 708 709 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 710 phy_interface_t mode) 711 { 712 int err; 713 714 if (port != 5) 715 return -EOPNOTSUPP; 716 717 switch (mode) { 718 case PHY_INTERFACE_MODE_NA: 719 return 0; 720 case PHY_INTERFACE_MODE_XGMII: 721 case PHY_INTERFACE_MODE_XAUI: 722 case PHY_INTERFACE_MODE_RXAUI: 723 return -EINVAL; 724 default: 725 break; 726 } 727 728 err = mv88e6341_port_set_cmode_writable(chip, port); 729 if (err) 730 return err; 731 732 return mv88e6xxx_port_set_cmode(chip, port, mode, true); 733 } 734 735 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 736 { 737 int err; 738 u16 reg; 739 740 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 741 if (err) 742 return err; 743 744 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; 745 746 return 0; 747 } 748 749 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 750 { 751 int err; 752 u16 reg; 753 754 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 755 if (err) 756 return err; 757 758 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; 759 760 return 0; 761 } 762 763 /* Offset 0x02: Jamming Control 764 * 765 * Do not limit the period of time that this port can be paused for by 766 * the remote end or the period of time that this port can pause the 767 * remote end. 768 */ 769 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 770 u8 out) 771 { 772 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, 773 out << 8 | in); 774 } 775 776 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 777 u8 out) 778 { 779 int err; 780 781 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 782 MV88E6390_PORT_FLOW_CTL_UPDATE | 783 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in); 784 if (err) 785 return err; 786 787 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 788 MV88E6390_PORT_FLOW_CTL_UPDATE | 789 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out); 790 } 791 792 /* Offset 0x04: Port Control Register */ 793 794 static const char * const mv88e6xxx_port_state_names[] = { 795 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", 796 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", 797 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", 798 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", 799 }; 800 801 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) 802 { 803 u16 reg; 804 int err; 805 806 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 807 if (err) 808 return err; 809 810 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; 811 812 switch (state) { 813 case BR_STATE_DISABLED: 814 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED; 815 break; 816 case BR_STATE_BLOCKING: 817 case BR_STATE_LISTENING: 818 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 819 break; 820 case BR_STATE_LEARNING: 821 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 822 break; 823 case BR_STATE_FORWARDING: 824 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 825 break; 826 default: 827 return -EINVAL; 828 } 829 830 reg |= state; 831 832 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 833 if (err) 834 return err; 835 836 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, 837 mv88e6xxx_port_state_names[state]); 838 839 return 0; 840 } 841 842 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 843 enum mv88e6xxx_egress_mode mode) 844 { 845 int err; 846 u16 reg; 847 848 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 849 if (err) 850 return err; 851 852 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; 853 854 switch (mode) { 855 case MV88E6XXX_EGRESS_MODE_UNMODIFIED: 856 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; 857 break; 858 case MV88E6XXX_EGRESS_MODE_UNTAGGED: 859 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; 860 break; 861 case MV88E6XXX_EGRESS_MODE_TAGGED: 862 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; 863 break; 864 case MV88E6XXX_EGRESS_MODE_ETHERTYPE: 865 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; 866 break; 867 default: 868 return -EINVAL; 869 } 870 871 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 872 } 873 874 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 875 enum mv88e6xxx_frame_mode mode) 876 { 877 int err; 878 u16 reg; 879 880 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 881 if (err) 882 return err; 883 884 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 885 886 switch (mode) { 887 case MV88E6XXX_FRAME_MODE_NORMAL: 888 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 889 break; 890 case MV88E6XXX_FRAME_MODE_DSA: 891 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 892 break; 893 default: 894 return -EINVAL; 895 } 896 897 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 898 } 899 900 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 901 enum mv88e6xxx_frame_mode mode) 902 { 903 int err; 904 u16 reg; 905 906 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 907 if (err) 908 return err; 909 910 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 911 912 switch (mode) { 913 case MV88E6XXX_FRAME_MODE_NORMAL: 914 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 915 break; 916 case MV88E6XXX_FRAME_MODE_DSA: 917 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 918 break; 919 case MV88E6XXX_FRAME_MODE_PROVIDER: 920 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; 921 break; 922 case MV88E6XXX_FRAME_MODE_ETHERTYPE: 923 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; 924 break; 925 default: 926 return -EINVAL; 927 } 928 929 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 930 } 931 932 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 933 int port, bool unicast) 934 { 935 int err; 936 u16 reg; 937 938 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 939 if (err) 940 return err; 941 942 if (unicast) 943 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 944 else 945 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 946 947 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 948 } 949 950 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, 951 bool unicast) 952 { 953 int err; 954 u16 reg; 955 956 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 957 if (err) 958 return err; 959 960 if (unicast) 961 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 962 else 963 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 964 965 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 966 } 967 968 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, 969 bool multicast) 970 { 971 int err; 972 u16 reg; 973 974 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 975 if (err) 976 return err; 977 978 if (multicast) 979 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 980 else 981 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 982 983 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 984 } 985 986 /* Offset 0x05: Port Control 1 */ 987 988 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 989 bool message_port) 990 { 991 u16 val; 992 int err; 993 994 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 995 if (err) 996 return err; 997 998 if (message_port) 999 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 1000 else 1001 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 1002 1003 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 1004 } 1005 1006 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, 1007 bool trunk, u8 id) 1008 { 1009 u16 val; 1010 int err; 1011 1012 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 1013 if (err) 1014 return err; 1015 1016 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK; 1017 1018 if (trunk) 1019 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT | 1020 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT); 1021 else 1022 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT; 1023 1024 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 1025 } 1026 1027 /* Offset 0x06: Port Based VLAN Map */ 1028 1029 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) 1030 { 1031 const u16 mask = mv88e6xxx_port_mask(chip); 1032 u16 reg; 1033 int err; 1034 1035 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1036 if (err) 1037 return err; 1038 1039 reg &= ~mask; 1040 reg |= map & mask; 1041 1042 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1043 if (err) 1044 return err; 1045 1046 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); 1047 1048 return 0; 1049 } 1050 1051 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) 1052 { 1053 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1054 u16 reg; 1055 int err; 1056 1057 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1058 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1059 if (err) 1060 return err; 1061 1062 *fid = (reg & 0xf000) >> 12; 1063 1064 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1065 if (upper_mask) { 1066 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1067 ®); 1068 if (err) 1069 return err; 1070 1071 *fid |= (reg & upper_mask) << 4; 1072 } 1073 1074 return 0; 1075 } 1076 1077 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) 1078 { 1079 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1080 u16 reg; 1081 int err; 1082 1083 if (fid >= mv88e6xxx_num_databases(chip)) 1084 return -EINVAL; 1085 1086 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1087 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1088 if (err) 1089 return err; 1090 1091 reg &= 0x0fff; 1092 reg |= (fid & 0x000f) << 12; 1093 1094 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1095 if (err) 1096 return err; 1097 1098 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1099 if (upper_mask) { 1100 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1101 ®); 1102 if (err) 1103 return err; 1104 1105 reg &= ~upper_mask; 1106 reg |= (fid >> 4) & upper_mask; 1107 1108 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, 1109 reg); 1110 if (err) 1111 return err; 1112 } 1113 1114 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); 1115 1116 return 0; 1117 } 1118 1119 /* Offset 0x07: Default Port VLAN ID & Priority */ 1120 1121 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) 1122 { 1123 u16 reg; 1124 int err; 1125 1126 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1127 ®); 1128 if (err) 1129 return err; 1130 1131 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1132 1133 return 0; 1134 } 1135 1136 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) 1137 { 1138 u16 reg; 1139 int err; 1140 1141 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1142 ®); 1143 if (err) 1144 return err; 1145 1146 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1147 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1148 1149 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1150 reg); 1151 if (err) 1152 return err; 1153 1154 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); 1155 1156 return 0; 1157 } 1158 1159 /* Offset 0x08: Port Control 2 Register */ 1160 1161 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 1162 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", 1163 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", 1164 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", 1165 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", 1166 }; 1167 1168 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 1169 int port, bool multicast) 1170 { 1171 int err; 1172 u16 reg; 1173 1174 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1175 if (err) 1176 return err; 1177 1178 if (multicast) 1179 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1180 else 1181 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1182 1183 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1184 } 1185 1186 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1187 int upstream_port) 1188 { 1189 int err; 1190 u16 reg; 1191 1192 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1193 if (err) 1194 return err; 1195 1196 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; 1197 reg |= upstream_port; 1198 1199 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1200 } 1201 1202 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 1203 enum mv88e6xxx_egress_direction direction, 1204 bool mirror) 1205 { 1206 bool *mirror_port; 1207 u16 reg; 1208 u16 bit; 1209 int err; 1210 1211 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1212 if (err) 1213 return err; 1214 1215 switch (direction) { 1216 case MV88E6XXX_EGRESS_DIR_INGRESS: 1217 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR; 1218 mirror_port = &chip->ports[port].mirror_ingress; 1219 break; 1220 case MV88E6XXX_EGRESS_DIR_EGRESS: 1221 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR; 1222 mirror_port = &chip->ports[port].mirror_egress; 1223 break; 1224 default: 1225 return -EINVAL; 1226 } 1227 1228 reg &= ~bit; 1229 if (mirror) 1230 reg |= bit; 1231 1232 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1233 if (!err) 1234 *mirror_port = mirror; 1235 1236 return err; 1237 } 1238 1239 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, 1240 bool locked) 1241 { 1242 u16 reg; 1243 int err; 1244 1245 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 1246 if (err) 1247 return err; 1248 1249 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK; 1250 if (locked) 1251 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK; 1252 1253 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1254 if (err) 1255 return err; 1256 1257 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®); 1258 if (err) 1259 return err; 1260 1261 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1262 if (locked) 1263 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1264 1265 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg); 1266 } 1267 1268 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 1269 u16 mode) 1270 { 1271 u16 reg; 1272 int err; 1273 1274 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1275 if (err) 1276 return err; 1277 1278 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1279 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1280 1281 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1282 if (err) 1283 return err; 1284 1285 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, 1286 mv88e6xxx_port_8021q_mode_names[mode]); 1287 1288 return 0; 1289 } 1290 1291 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, 1292 bool drop_untagged) 1293 { 1294 u16 old, new; 1295 int err; 1296 1297 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old); 1298 if (err) 1299 return err; 1300 1301 if (drop_untagged) 1302 new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1303 else 1304 new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1305 1306 if (new == old) 1307 return 0; 1308 1309 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new); 1310 } 1311 1312 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map) 1313 { 1314 u16 reg; 1315 int err; 1316 1317 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1318 if (err) 1319 return err; 1320 1321 if (map) 1322 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; 1323 else 1324 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA; 1325 1326 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1327 } 1328 1329 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 1330 size_t size) 1331 { 1332 u16 reg; 1333 int err; 1334 1335 size += VLAN_ETH_HLEN + ETH_FCS_LEN; 1336 1337 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1338 if (err) 1339 return err; 1340 1341 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; 1342 1343 if (size <= 1522) 1344 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; 1345 else if (size <= 2048) 1346 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; 1347 else if (size <= 10240) 1348 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; 1349 else 1350 return -ERANGE; 1351 1352 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1353 } 1354 1355 /* Offset 0x09: Port Rate Control */ 1356 1357 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1358 { 1359 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1360 0x0000); 1361 } 1362 1363 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1364 { 1365 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1366 0x0001); 1367 } 1368 1369 /* Offset 0x0B: Port Association Vector */ 1370 1371 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, 1372 u16 pav) 1373 { 1374 u16 reg, mask; 1375 int err; 1376 1377 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1378 ®); 1379 if (err) 1380 return err; 1381 1382 mask = mv88e6xxx_port_mask(chip); 1383 reg &= ~mask; 1384 reg |= pav & mask; 1385 1386 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1387 reg); 1388 } 1389 1390 /* Offset 0x0C: Port ATU Control */ 1391 1392 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) 1393 { 1394 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); 1395 } 1396 1397 /* Offset 0x0D: (Priority) Override Register */ 1398 1399 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) 1400 { 1401 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); 1402 } 1403 1404 /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */ 1405 1406 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port, 1407 u16 pointer, u8 *data) 1408 { 1409 u16 reg; 1410 int err; 1411 1412 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1413 pointer); 1414 if (err) 1415 return err; 1416 1417 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1418 ®); 1419 if (err) 1420 return err; 1421 1422 *data = reg; 1423 1424 return 0; 1425 } 1426 1427 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port, 1428 u16 pointer, u8 data) 1429 { 1430 u16 reg; 1431 1432 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data; 1433 1434 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1435 reg); 1436 } 1437 1438 static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip, 1439 u16 pointer, u8 data) 1440 { 1441 int err, port; 1442 1443 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1444 if (dsa_is_unused_port(chip->ds, port)) 1445 continue; 1446 1447 err = mv88e6393x_port_policy_write(chip, port, pointer, data); 1448 if (err) 1449 return err; 1450 } 1451 1452 return 0; 1453 } 1454 1455 int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, 1456 enum mv88e6xxx_egress_direction direction, 1457 int port) 1458 { 1459 u16 ptr; 1460 int err; 1461 1462 switch (direction) { 1463 case MV88E6XXX_EGRESS_DIR_INGRESS: 1464 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST; 1465 err = mv88e6393x_port_policy_write_all(chip, ptr, port); 1466 if (err) 1467 return err; 1468 break; 1469 case MV88E6XXX_EGRESS_DIR_EGRESS: 1470 ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST; 1471 err = mv88e6xxx_g2_write(chip, ptr, port); 1472 if (err) 1473 return err; 1474 break; 1475 } 1476 1477 return 0; 1478 } 1479 1480 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1481 int upstream_port) 1482 { 1483 u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST; 1484 u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI | 1485 upstream_port; 1486 1487 return mv88e6393x_port_policy_write(chip, port, ptr, data); 1488 } 1489 1490 int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 1491 { 1492 u16 ptr; 1493 int err; 1494 1495 /* Consider the frames with reserved multicast destination 1496 * addresses matching 01:80:c2:00:00:00 and 1497 * 01:80:c2:00:00:02 as MGMT. 1498 */ 1499 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO; 1500 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1501 if (err) 1502 return err; 1503 1504 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI; 1505 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1506 if (err) 1507 return err; 1508 1509 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO; 1510 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1511 if (err) 1512 return err; 1513 1514 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI; 1515 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1516 if (err) 1517 return err; 1518 1519 return 0; 1520 } 1521 1522 /* Offset 0x10 & 0x11: EPC */ 1523 1524 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) 1525 { 1526 int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY); 1527 1528 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); 1529 } 1530 1531 /* Port Ether type for 6393X family */ 1532 1533 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1534 u16 etype) 1535 { 1536 u16 val; 1537 int err; 1538 1539 err = mv88e6393x_port_epc_wait_ready(chip, port); 1540 if (err) 1541 return err; 1542 1543 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype); 1544 if (err) 1545 return err; 1546 1547 val = MV88E6393X_PORT_EPC_CMD_BUSY | 1548 MV88E6393X_PORT_EPC_CMD_WRITE | 1549 MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE; 1550 1551 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val); 1552 } 1553 1554 /* Offset 0x0f: Port Ether type */ 1555 1556 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1557 u16 etype) 1558 { 1559 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); 1560 } 1561 1562 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] 1563 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] 1564 */ 1565 1566 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1567 { 1568 int err; 1569 1570 /* Use a direct priority mapping for all IEEE tagged frames */ 1571 err = mv88e6xxx_port_write(chip, port, 1572 MV88E6095_PORT_IEEE_PRIO_REMAP_0123, 1573 0x3210); 1574 if (err) 1575 return err; 1576 1577 return mv88e6xxx_port_write(chip, port, 1578 MV88E6095_PORT_IEEE_PRIO_REMAP_4567, 1579 0x7654); 1580 } 1581 1582 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, 1583 int port, u16 table, u8 ptr, u16 data) 1584 { 1585 u16 reg; 1586 1587 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | 1588 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | 1589 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK); 1590 1591 return mv88e6xxx_port_write(chip, port, 1592 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); 1593 } 1594 1595 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1596 { 1597 int err, i; 1598 u16 table; 1599 1600 for (i = 0; i <= 7; i++) { 1601 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; 1602 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, 1603 (i | i << 4)); 1604 if (err) 1605 return err; 1606 1607 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP; 1608 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1609 if (err) 1610 return err; 1611 1612 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP; 1613 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1614 if (err) 1615 return err; 1616 1617 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP; 1618 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1619 if (err) 1620 return err; 1621 } 1622 1623 return 0; 1624 } 1625 1626 /* Offset 0x0E: Policy Control Register */ 1627 1628 static int 1629 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping, 1630 enum mv88e6xxx_policy_action action, 1631 u16 *mask, u16 *val, int *shift) 1632 { 1633 switch (mapping) { 1634 case MV88E6XXX_POLICY_MAPPING_DA: 1635 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK); 1636 *mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK; 1637 break; 1638 case MV88E6XXX_POLICY_MAPPING_SA: 1639 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK); 1640 *mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK; 1641 break; 1642 case MV88E6XXX_POLICY_MAPPING_VTU: 1643 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK); 1644 *mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK; 1645 break; 1646 case MV88E6XXX_POLICY_MAPPING_ETYPE: 1647 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK); 1648 *mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK; 1649 break; 1650 case MV88E6XXX_POLICY_MAPPING_PPPOE: 1651 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK); 1652 *mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK; 1653 break; 1654 case MV88E6XXX_POLICY_MAPPING_VBAS: 1655 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK); 1656 *mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK; 1657 break; 1658 case MV88E6XXX_POLICY_MAPPING_OPT82: 1659 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK); 1660 *mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK; 1661 break; 1662 case MV88E6XXX_POLICY_MAPPING_UDP: 1663 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK); 1664 *mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK; 1665 break; 1666 default: 1667 return -EOPNOTSUPP; 1668 } 1669 1670 switch (action) { 1671 case MV88E6XXX_POLICY_ACTION_NORMAL: 1672 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL; 1673 break; 1674 case MV88E6XXX_POLICY_ACTION_MIRROR: 1675 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR; 1676 break; 1677 case MV88E6XXX_POLICY_ACTION_TRAP: 1678 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP; 1679 break; 1680 case MV88E6XXX_POLICY_ACTION_DISCARD: 1681 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD; 1682 break; 1683 default: 1684 return -EOPNOTSUPP; 1685 } 1686 1687 return 0; 1688 } 1689 1690 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1691 enum mv88e6xxx_policy_mapping mapping, 1692 enum mv88e6xxx_policy_action action) 1693 { 1694 u16 reg, mask, val; 1695 int shift; 1696 int err; 1697 1698 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1699 &val, &shift); 1700 if (err) 1701 return err; 1702 1703 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); 1704 if (err) 1705 return err; 1706 1707 reg &= ~mask; 1708 reg |= (val << shift) & mask; 1709 1710 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); 1711 } 1712 1713 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1714 enum mv88e6xxx_policy_mapping mapping, 1715 enum mv88e6xxx_policy_action action) 1716 { 1717 u16 mask, val; 1718 int shift; 1719 int err; 1720 u16 ptr; 1721 u8 reg; 1722 1723 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1724 &val, &shift); 1725 if (err) 1726 return err; 1727 1728 /* The 16-bit Port Policy CTL register from older chips is on 6393x 1729 * changed to Port Policy MGMT CTL, which can access more data, but 1730 * indirectly. The original 16-bit value is divided into two 8-bit 1731 * registers. 1732 */ 1733 ptr = shift / 8; 1734 shift %= 8; 1735 mask >>= ptr * 8; 1736 1737 err = mv88e6393x_port_policy_read(chip, port, ptr, ®); 1738 if (err) 1739 return err; 1740 1741 reg &= ~mask; 1742 reg |= (val << shift) & mask; 1743 1744 return mv88e6393x_port_policy_write(chip, port, ptr, reg); 1745 } 1746