1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Port Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/if_bridge.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 16 #include "chip.h" 17 #include "global2.h" 18 #include "port.h" 19 #include "serdes.h" 20 21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 22 u16 *val) 23 { 24 int addr = chip->info->port_base_addr + port; 25 26 return mv88e6xxx_read(chip, addr, reg, val); 27 } 28 29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, 30 int bit, int val) 31 { 32 int addr = chip->info->port_base_addr + port; 33 34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); 35 } 36 37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 38 u16 val) 39 { 40 int addr = chip->info->port_base_addr + port; 41 42 return mv88e6xxx_write(chip, addr, reg, val); 43 } 44 45 /* Offset 0x00: MAC (or PCS or Physical) Status Register 46 * 47 * For most devices, this is read only. However the 6185 has the MyPause 48 * bit read/write. 49 */ 50 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 51 int pause) 52 { 53 u16 reg; 54 int err; 55 56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 57 if (err) 58 return err; 59 60 if (pause) 61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; 62 else 63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; 64 65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 66 } 67 68 /* Offset 0x01: MAC (or PCS or Physical) Control Register 69 * 70 * Link, Duplex and Flow Control have one force bit, one value bit. 71 * 72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. 73 * Alternative values require the 200BASE (or AltSpeed) bit 12 set. 74 * Newer chips need a ForcedSpd bit 13 set to consider the value. 75 */ 76 77 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 78 phy_interface_t mode) 79 { 80 u16 reg; 81 int err; 82 83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 84 if (err) 85 return err; 86 87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 88 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK); 89 90 switch (mode) { 91 case PHY_INTERFACE_MODE_RGMII_RXID: 92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; 93 break; 94 case PHY_INTERFACE_MODE_RGMII_TXID: 95 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 96 break; 97 case PHY_INTERFACE_MODE_RGMII_ID: 98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 99 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 100 break; 101 case PHY_INTERFACE_MODE_RGMII: 102 break; 103 default: 104 return 0; 105 } 106 107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 108 if (err) 109 return err; 110 111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, 112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", 113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); 114 115 return 0; 116 } 117 118 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 119 phy_interface_t mode) 120 { 121 if (port < 5) 122 return -EOPNOTSUPP; 123 124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 125 } 126 127 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 128 phy_interface_t mode) 129 { 130 if (port != 0) 131 return -EOPNOTSUPP; 132 133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 134 } 135 136 int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 137 phy_interface_t mode) 138 { 139 if (port != 2 && port != 5 && port != 6) 140 return -EOPNOTSUPP; 141 142 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 143 } 144 145 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) 146 { 147 u16 reg; 148 int err; 149 150 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 151 if (err) 152 return err; 153 154 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 155 MV88E6XXX_PORT_MAC_CTL_LINK_UP); 156 157 switch (link) { 158 case LINK_FORCED_DOWN: 159 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; 160 break; 161 case LINK_FORCED_UP: 162 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 163 MV88E6XXX_PORT_MAC_CTL_LINK_UP; 164 break; 165 case LINK_UNFORCED: 166 /* normal link detection */ 167 break; 168 default: 169 return -EINVAL; 170 } 171 172 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 173 if (err) 174 return err; 175 176 dev_dbg(chip->dev, "p%d: %s link %s\n", port, 177 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", 178 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); 179 180 return 0; 181 } 182 183 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 184 { 185 const struct mv88e6xxx_ops *ops = chip->info->ops; 186 int err = 0; 187 int link; 188 189 if (isup) 190 link = LINK_FORCED_UP; 191 else 192 link = LINK_FORCED_DOWN; 193 194 if (ops->port_set_link) 195 err = ops->port_set_link(chip, port, link); 196 197 return err; 198 } 199 200 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 201 { 202 const struct mv88e6xxx_ops *ops = chip->info->ops; 203 int err = 0; 204 int link; 205 206 if (mode == MLO_AN_INBAND) 207 link = LINK_UNFORCED; 208 else if (isup) 209 link = LINK_FORCED_UP; 210 else 211 link = LINK_FORCED_DOWN; 212 213 if (ops->port_set_link) 214 err = ops->port_set_link(chip, port, link); 215 216 return err; 217 } 218 219 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip, 220 int port, int speed, bool alt_bit, 221 bool force_bit, int duplex) 222 { 223 u16 reg, ctrl; 224 int err; 225 226 switch (speed) { 227 case 10: 228 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 229 break; 230 case 100: 231 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 232 break; 233 case 200: 234 if (alt_bit) 235 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 236 MV88E6390_PORT_MAC_CTL_ALTSPEED; 237 else 238 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200; 239 break; 240 case 1000: 241 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 242 break; 243 case 2500: 244 if (alt_bit) 245 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 246 MV88E6390_PORT_MAC_CTL_ALTSPEED; 247 else 248 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000; 249 break; 250 case 10000: 251 /* all bits set, fall through... */ 252 case SPEED_UNFORCED: 253 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 254 break; 255 default: 256 return -EOPNOTSUPP; 257 } 258 259 switch (duplex) { 260 case DUPLEX_HALF: 261 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 262 break; 263 case DUPLEX_FULL: 264 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 265 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 266 break; 267 case DUPLEX_UNFORCED: 268 /* normal duplex detection */ 269 break; 270 default: 271 return -EOPNOTSUPP; 272 } 273 274 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 275 if (err) 276 return err; 277 278 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 279 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 280 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); 281 282 if (alt_bit) 283 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; 284 if (force_bit) { 285 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 286 if (speed != SPEED_UNFORCED) 287 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 288 } 289 reg |= ctrl; 290 291 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 292 if (err) 293 return err; 294 295 if (speed != SPEED_UNFORCED) 296 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 297 else 298 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 299 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 300 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 301 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 302 303 return 0; 304 } 305 306 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ 307 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 308 int speed, int duplex) 309 { 310 if (speed == 200 || speed > 1000) 311 return -EOPNOTSUPP; 312 313 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 314 duplex); 315 } 316 317 /* Support 10, 100 Mbps (e.g. 88E6250 family) */ 318 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 319 int speed, int duplex) 320 { 321 if (speed > 100) 322 return -EOPNOTSUPP; 323 324 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 325 duplex); 326 } 327 328 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */ 329 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 330 int speed, int duplex) 331 { 332 if (speed > 2500) 333 return -EOPNOTSUPP; 334 335 if (speed == 200 && port != 0) 336 return -EOPNOTSUPP; 337 338 if (speed == 2500 && port < 5) 339 return -EOPNOTSUPP; 340 341 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true, 342 duplex); 343 } 344 345 phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip, 346 int port) 347 { 348 if (port == 5) 349 return PHY_INTERFACE_MODE_2500BASEX; 350 351 return PHY_INTERFACE_MODE_NA; 352 } 353 354 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ 355 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 356 int speed, int duplex) 357 { 358 if (speed > 1000) 359 return -EOPNOTSUPP; 360 361 if (speed == 200 && port < 5) 362 return -EOPNOTSUPP; 363 364 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false, 365 duplex); 366 } 367 368 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ 369 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 370 int speed, int duplex) 371 { 372 if (speed > 2500) 373 return -EOPNOTSUPP; 374 375 if (speed == 200 && port != 0) 376 return -EOPNOTSUPP; 377 378 if (speed == 2500 && port < 9) 379 return -EOPNOTSUPP; 380 381 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 382 duplex); 383 } 384 385 phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip, 386 int port) 387 { 388 if (port == 9 || port == 10) 389 return PHY_INTERFACE_MODE_2500BASEX; 390 391 return PHY_INTERFACE_MODE_NA; 392 } 393 394 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ 395 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 396 int speed, int duplex) 397 { 398 if (speed == 200 && port != 0) 399 return -EOPNOTSUPP; 400 401 if (speed >= 2500 && port < 9) 402 return -EOPNOTSUPP; 403 404 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 405 duplex); 406 } 407 408 phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip, 409 int port) 410 { 411 if (port == 9 || port == 10) 412 return PHY_INTERFACE_MODE_XAUI; 413 414 return PHY_INTERFACE_MODE_NA; 415 } 416 417 /* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X) 418 * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register 419 * values for speeds 2500 & 5000 conflict. 420 */ 421 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 422 int speed, int duplex) 423 { 424 u16 reg, ctrl; 425 int err; 426 427 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 && 428 speed > 2500) 429 return -EOPNOTSUPP; 430 431 if (speed == 200 && port != 0) 432 return -EOPNOTSUPP; 433 434 if (speed >= 2500 && port > 0 && port < 9) 435 return -EOPNOTSUPP; 436 437 switch (speed) { 438 case 10: 439 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 440 break; 441 case 100: 442 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 443 break; 444 case 200: 445 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 446 MV88E6390_PORT_MAC_CTL_ALTSPEED; 447 break; 448 case 1000: 449 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 450 break; 451 case 2500: 452 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 | 453 MV88E6390_PORT_MAC_CTL_ALTSPEED; 454 break; 455 case 5000: 456 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 457 MV88E6390_PORT_MAC_CTL_ALTSPEED; 458 break; 459 case 10000: 460 case SPEED_UNFORCED: 461 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 462 break; 463 default: 464 return -EOPNOTSUPP; 465 } 466 467 switch (duplex) { 468 case DUPLEX_HALF: 469 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 470 break; 471 case DUPLEX_FULL: 472 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 473 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 474 break; 475 case DUPLEX_UNFORCED: 476 /* normal duplex detection */ 477 break; 478 default: 479 return -EOPNOTSUPP; 480 } 481 482 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 483 if (err) 484 return err; 485 486 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 487 MV88E6390_PORT_MAC_CTL_ALTSPEED | 488 MV88E6390_PORT_MAC_CTL_FORCE_SPEED); 489 490 if (speed != SPEED_UNFORCED) 491 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 492 493 reg |= ctrl; 494 495 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 496 if (err) 497 return err; 498 499 if (speed != SPEED_UNFORCED) 500 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 501 else 502 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 503 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 504 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 505 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 506 507 return 0; 508 } 509 510 phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip, 511 int port) 512 { 513 514 if (port != 0 && port != 9 && port != 10) 515 return PHY_INTERFACE_MODE_NA; 516 517 if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361) 518 return PHY_INTERFACE_MODE_2500BASEX; 519 520 return PHY_INTERFACE_MODE_10GBASER; 521 } 522 523 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 524 phy_interface_t mode, bool force) 525 { 526 u16 cmode; 527 int lane; 528 u16 reg; 529 int err; 530 531 /* Default to a slow mode, so freeing up SERDES interfaces for 532 * other ports which might use them for SFPs. 533 */ 534 if (mode == PHY_INTERFACE_MODE_NA) 535 mode = PHY_INTERFACE_MODE_1000BASEX; 536 537 switch (mode) { 538 case PHY_INTERFACE_MODE_RMII: 539 cmode = MV88E6XXX_PORT_STS_CMODE_RMII; 540 break; 541 case PHY_INTERFACE_MODE_RGMII: 542 case PHY_INTERFACE_MODE_RGMII_ID: 543 case PHY_INTERFACE_MODE_RGMII_RXID: 544 case PHY_INTERFACE_MODE_RGMII_TXID: 545 cmode = MV88E6XXX_PORT_STS_CMODE_RGMII; 546 break; 547 case PHY_INTERFACE_MODE_1000BASEX: 548 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX; 549 break; 550 case PHY_INTERFACE_MODE_SGMII: 551 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII; 552 break; 553 case PHY_INTERFACE_MODE_2500BASEX: 554 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; 555 break; 556 case PHY_INTERFACE_MODE_5GBASER: 557 cmode = MV88E6393X_PORT_STS_CMODE_5GBASER; 558 break; 559 case PHY_INTERFACE_MODE_XGMII: 560 case PHY_INTERFACE_MODE_XAUI: 561 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; 562 break; 563 case PHY_INTERFACE_MODE_RXAUI: 564 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; 565 break; 566 case PHY_INTERFACE_MODE_10GBASER: 567 cmode = MV88E6393X_PORT_STS_CMODE_10GBASER; 568 break; 569 default: 570 cmode = 0; 571 } 572 573 /* cmode doesn't change, nothing to do for us unless forced */ 574 if (cmode == chip->ports[port].cmode && !force) 575 return 0; 576 577 lane = mv88e6xxx_serdes_get_lane(chip, port); 578 if (lane >= 0) { 579 if (chip->ports[port].serdes_irq) { 580 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 581 if (err) 582 return err; 583 } 584 585 err = mv88e6xxx_serdes_power_down(chip, port, lane); 586 if (err) 587 return err; 588 } 589 590 chip->ports[port].cmode = 0; 591 592 if (cmode) { 593 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 594 if (err) 595 return err; 596 597 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; 598 reg |= cmode; 599 600 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 601 if (err) 602 return err; 603 604 chip->ports[port].cmode = cmode; 605 606 lane = mv88e6xxx_serdes_get_lane(chip, port); 607 if (lane == -ENODEV) 608 return 0; 609 if (lane < 0) 610 return lane; 611 612 err = mv88e6xxx_serdes_power_up(chip, port, lane); 613 if (err) 614 return err; 615 616 if (chip->ports[port].serdes_irq) { 617 err = mv88e6xxx_serdes_irq_enable(chip, port, lane); 618 if (err) 619 return err; 620 } 621 } 622 623 return 0; 624 } 625 626 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 627 phy_interface_t mode) 628 { 629 if (port != 9 && port != 10) 630 return -EOPNOTSUPP; 631 632 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 633 } 634 635 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 636 phy_interface_t mode) 637 { 638 if (port != 9 && port != 10) 639 return -EOPNOTSUPP; 640 641 switch (mode) { 642 case PHY_INTERFACE_MODE_NA: 643 return 0; 644 case PHY_INTERFACE_MODE_XGMII: 645 case PHY_INTERFACE_MODE_XAUI: 646 case PHY_INTERFACE_MODE_RXAUI: 647 return -EINVAL; 648 default: 649 break; 650 } 651 652 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 653 } 654 655 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 656 phy_interface_t mode) 657 { 658 int err; 659 u16 reg; 660 661 if (port != 0 && port != 9 && port != 10) 662 return -EOPNOTSUPP; 663 664 if (port == 9 || port == 10) { 665 switch (mode) { 666 case PHY_INTERFACE_MODE_RMII: 667 case PHY_INTERFACE_MODE_RGMII: 668 case PHY_INTERFACE_MODE_RGMII_ID: 669 case PHY_INTERFACE_MODE_RGMII_RXID: 670 case PHY_INTERFACE_MODE_RGMII_TXID: 671 return -EINVAL; 672 default: 673 break; 674 } 675 } 676 677 /* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */ 678 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 679 if (err) 680 return err; 681 682 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE; 683 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE; 684 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 685 if (err) 686 return err; 687 688 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 689 } 690 691 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip, 692 int port) 693 { 694 int err, addr; 695 u16 reg, bits; 696 697 if (port != 5) 698 return -EOPNOTSUPP; 699 700 addr = chip->info->port_base_addr + port; 701 702 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); 703 if (err) 704 return err; 705 706 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE | 707 MV88E6341_PORT_RESERVED_1A_SGMII_AN; 708 709 if ((reg & bits) == bits) 710 return 0; 711 712 reg |= bits; 713 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); 714 } 715 716 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 717 phy_interface_t mode) 718 { 719 int err; 720 721 if (port != 5) 722 return -EOPNOTSUPP; 723 724 switch (mode) { 725 case PHY_INTERFACE_MODE_NA: 726 return 0; 727 case PHY_INTERFACE_MODE_XGMII: 728 case PHY_INTERFACE_MODE_XAUI: 729 case PHY_INTERFACE_MODE_RXAUI: 730 return -EINVAL; 731 default: 732 break; 733 } 734 735 err = mv88e6341_port_set_cmode_writable(chip, port); 736 if (err) 737 return err; 738 739 return mv88e6xxx_port_set_cmode(chip, port, mode, true); 740 } 741 742 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 743 { 744 int err; 745 u16 reg; 746 747 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 748 if (err) 749 return err; 750 751 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; 752 753 return 0; 754 } 755 756 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 757 { 758 int err; 759 u16 reg; 760 761 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 762 if (err) 763 return err; 764 765 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; 766 767 return 0; 768 } 769 770 /* Offset 0x02: Jamming Control 771 * 772 * Do not limit the period of time that this port can be paused for by 773 * the remote end or the period of time that this port can pause the 774 * remote end. 775 */ 776 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 777 u8 out) 778 { 779 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, 780 out << 8 | in); 781 } 782 783 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 784 u8 out) 785 { 786 int err; 787 788 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 789 MV88E6390_PORT_FLOW_CTL_UPDATE | 790 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in); 791 if (err) 792 return err; 793 794 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 795 MV88E6390_PORT_FLOW_CTL_UPDATE | 796 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out); 797 } 798 799 /* Offset 0x04: Port Control Register */ 800 801 static const char * const mv88e6xxx_port_state_names[] = { 802 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", 803 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", 804 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", 805 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", 806 }; 807 808 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) 809 { 810 u16 reg; 811 int err; 812 813 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 814 if (err) 815 return err; 816 817 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; 818 819 switch (state) { 820 case BR_STATE_DISABLED: 821 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED; 822 break; 823 case BR_STATE_BLOCKING: 824 case BR_STATE_LISTENING: 825 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 826 break; 827 case BR_STATE_LEARNING: 828 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 829 break; 830 case BR_STATE_FORWARDING: 831 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 832 break; 833 default: 834 return -EINVAL; 835 } 836 837 reg |= state; 838 839 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 840 if (err) 841 return err; 842 843 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, 844 mv88e6xxx_port_state_names[state]); 845 846 return 0; 847 } 848 849 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 850 enum mv88e6xxx_egress_mode mode) 851 { 852 int err; 853 u16 reg; 854 855 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 856 if (err) 857 return err; 858 859 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; 860 861 switch (mode) { 862 case MV88E6XXX_EGRESS_MODE_UNMODIFIED: 863 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; 864 break; 865 case MV88E6XXX_EGRESS_MODE_UNTAGGED: 866 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; 867 break; 868 case MV88E6XXX_EGRESS_MODE_TAGGED: 869 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; 870 break; 871 case MV88E6XXX_EGRESS_MODE_ETHERTYPE: 872 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; 873 break; 874 default: 875 return -EINVAL; 876 } 877 878 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 879 } 880 881 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 882 enum mv88e6xxx_frame_mode mode) 883 { 884 int err; 885 u16 reg; 886 887 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 888 if (err) 889 return err; 890 891 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 892 893 switch (mode) { 894 case MV88E6XXX_FRAME_MODE_NORMAL: 895 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 896 break; 897 case MV88E6XXX_FRAME_MODE_DSA: 898 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 899 break; 900 default: 901 return -EINVAL; 902 } 903 904 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 905 } 906 907 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 908 enum mv88e6xxx_frame_mode mode) 909 { 910 int err; 911 u16 reg; 912 913 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 914 if (err) 915 return err; 916 917 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 918 919 switch (mode) { 920 case MV88E6XXX_FRAME_MODE_NORMAL: 921 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 922 break; 923 case MV88E6XXX_FRAME_MODE_DSA: 924 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 925 break; 926 case MV88E6XXX_FRAME_MODE_PROVIDER: 927 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; 928 break; 929 case MV88E6XXX_FRAME_MODE_ETHERTYPE: 930 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; 931 break; 932 default: 933 return -EINVAL; 934 } 935 936 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 937 } 938 939 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 940 int port, bool unicast) 941 { 942 int err; 943 u16 reg; 944 945 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 946 if (err) 947 return err; 948 949 if (unicast) 950 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 951 else 952 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 953 954 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 955 } 956 957 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, 958 bool unicast) 959 { 960 int err; 961 u16 reg; 962 963 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 964 if (err) 965 return err; 966 967 if (unicast) 968 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 969 else 970 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 971 972 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 973 } 974 975 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, 976 bool multicast) 977 { 978 int err; 979 u16 reg; 980 981 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 982 if (err) 983 return err; 984 985 if (multicast) 986 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 987 else 988 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 989 990 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 991 } 992 993 /* Offset 0x05: Port Control 1 */ 994 995 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 996 bool message_port) 997 { 998 u16 val; 999 int err; 1000 1001 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 1002 if (err) 1003 return err; 1004 1005 if (message_port) 1006 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 1007 else 1008 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 1009 1010 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 1011 } 1012 1013 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, 1014 bool trunk, u8 id) 1015 { 1016 u16 val; 1017 int err; 1018 1019 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 1020 if (err) 1021 return err; 1022 1023 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK; 1024 1025 if (trunk) 1026 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT | 1027 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT); 1028 else 1029 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT; 1030 1031 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 1032 } 1033 1034 /* Offset 0x06: Port Based VLAN Map */ 1035 1036 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) 1037 { 1038 const u16 mask = mv88e6xxx_port_mask(chip); 1039 u16 reg; 1040 int err; 1041 1042 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1043 if (err) 1044 return err; 1045 1046 reg &= ~mask; 1047 reg |= map & mask; 1048 1049 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1050 if (err) 1051 return err; 1052 1053 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); 1054 1055 return 0; 1056 } 1057 1058 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) 1059 { 1060 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1061 u16 reg; 1062 int err; 1063 1064 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1065 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1066 if (err) 1067 return err; 1068 1069 *fid = (reg & 0xf000) >> 12; 1070 1071 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1072 if (upper_mask) { 1073 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1074 ®); 1075 if (err) 1076 return err; 1077 1078 *fid |= (reg & upper_mask) << 4; 1079 } 1080 1081 return 0; 1082 } 1083 1084 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) 1085 { 1086 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1087 u16 reg; 1088 int err; 1089 1090 if (fid >= mv88e6xxx_num_databases(chip)) 1091 return -EINVAL; 1092 1093 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1094 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1095 if (err) 1096 return err; 1097 1098 reg &= 0x0fff; 1099 reg |= (fid & 0x000f) << 12; 1100 1101 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1102 if (err) 1103 return err; 1104 1105 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1106 if (upper_mask) { 1107 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1108 ®); 1109 if (err) 1110 return err; 1111 1112 reg &= ~upper_mask; 1113 reg |= (fid >> 4) & upper_mask; 1114 1115 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, 1116 reg); 1117 if (err) 1118 return err; 1119 } 1120 1121 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); 1122 1123 return 0; 1124 } 1125 1126 /* Offset 0x07: Default Port VLAN ID & Priority */ 1127 1128 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) 1129 { 1130 u16 reg; 1131 int err; 1132 1133 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1134 ®); 1135 if (err) 1136 return err; 1137 1138 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1139 1140 return 0; 1141 } 1142 1143 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) 1144 { 1145 u16 reg; 1146 int err; 1147 1148 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1149 ®); 1150 if (err) 1151 return err; 1152 1153 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1154 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1155 1156 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1157 reg); 1158 if (err) 1159 return err; 1160 1161 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); 1162 1163 return 0; 1164 } 1165 1166 /* Offset 0x08: Port Control 2 Register */ 1167 1168 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 1169 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", 1170 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", 1171 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", 1172 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", 1173 }; 1174 1175 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 1176 int port, bool multicast) 1177 { 1178 int err; 1179 u16 reg; 1180 1181 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1182 if (err) 1183 return err; 1184 1185 if (multicast) 1186 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1187 else 1188 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1189 1190 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1191 } 1192 1193 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1194 int upstream_port) 1195 { 1196 int err; 1197 u16 reg; 1198 1199 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1200 if (err) 1201 return err; 1202 1203 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; 1204 reg |= upstream_port; 1205 1206 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1207 } 1208 1209 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 1210 enum mv88e6xxx_egress_direction direction, 1211 bool mirror) 1212 { 1213 bool *mirror_port; 1214 u16 reg; 1215 u16 bit; 1216 int err; 1217 1218 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1219 if (err) 1220 return err; 1221 1222 switch (direction) { 1223 case MV88E6XXX_EGRESS_DIR_INGRESS: 1224 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR; 1225 mirror_port = &chip->ports[port].mirror_ingress; 1226 break; 1227 case MV88E6XXX_EGRESS_DIR_EGRESS: 1228 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR; 1229 mirror_port = &chip->ports[port].mirror_egress; 1230 break; 1231 default: 1232 return -EINVAL; 1233 } 1234 1235 reg &= ~bit; 1236 if (mirror) 1237 reg |= bit; 1238 1239 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1240 if (!err) 1241 *mirror_port = mirror; 1242 1243 return err; 1244 } 1245 1246 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, 1247 bool locked) 1248 { 1249 u16 reg; 1250 int err; 1251 1252 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 1253 if (err) 1254 return err; 1255 1256 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK; 1257 if (locked) 1258 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK; 1259 1260 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1261 if (err) 1262 return err; 1263 1264 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®); 1265 if (err) 1266 return err; 1267 1268 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1269 if (locked) 1270 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1271 1272 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg); 1273 } 1274 1275 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 1276 u16 mode) 1277 { 1278 u16 reg; 1279 int err; 1280 1281 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1282 if (err) 1283 return err; 1284 1285 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1286 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1287 1288 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1289 if (err) 1290 return err; 1291 1292 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, 1293 mv88e6xxx_port_8021q_mode_names[mode]); 1294 1295 return 0; 1296 } 1297 1298 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, 1299 bool drop_untagged) 1300 { 1301 u16 old, new; 1302 int err; 1303 1304 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old); 1305 if (err) 1306 return err; 1307 1308 if (drop_untagged) 1309 new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1310 else 1311 new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1312 1313 if (new == old) 1314 return 0; 1315 1316 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new); 1317 } 1318 1319 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map) 1320 { 1321 u16 reg; 1322 int err; 1323 1324 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1325 if (err) 1326 return err; 1327 1328 if (map) 1329 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; 1330 else 1331 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA; 1332 1333 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1334 } 1335 1336 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 1337 size_t size) 1338 { 1339 u16 reg; 1340 int err; 1341 1342 size += VLAN_ETH_HLEN + ETH_FCS_LEN; 1343 1344 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1345 if (err) 1346 return err; 1347 1348 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; 1349 1350 if (size <= 1522) 1351 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; 1352 else if (size <= 2048) 1353 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; 1354 else if (size <= 10240) 1355 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; 1356 else 1357 return -ERANGE; 1358 1359 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1360 } 1361 1362 /* Offset 0x09: Port Rate Control */ 1363 1364 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1365 { 1366 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1367 0x0000); 1368 } 1369 1370 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1371 { 1372 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1373 0x0001); 1374 } 1375 1376 /* Offset 0x0B: Port Association Vector */ 1377 1378 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, 1379 u16 pav) 1380 { 1381 u16 reg, mask; 1382 int err; 1383 1384 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1385 ®); 1386 if (err) 1387 return err; 1388 1389 mask = mv88e6xxx_port_mask(chip); 1390 reg &= ~mask; 1391 reg |= pav & mask; 1392 1393 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1394 reg); 1395 } 1396 1397 /* Offset 0x0C: Port ATU Control */ 1398 1399 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) 1400 { 1401 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); 1402 } 1403 1404 /* Offset 0x0D: (Priority) Override Register */ 1405 1406 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) 1407 { 1408 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); 1409 } 1410 1411 /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */ 1412 1413 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port, 1414 u16 pointer, u8 *data) 1415 { 1416 u16 reg; 1417 int err; 1418 1419 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1420 pointer); 1421 if (err) 1422 return err; 1423 1424 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1425 ®); 1426 if (err) 1427 return err; 1428 1429 *data = reg; 1430 1431 return 0; 1432 } 1433 1434 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port, 1435 u16 pointer, u8 data) 1436 { 1437 u16 reg; 1438 1439 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data; 1440 1441 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1442 reg); 1443 } 1444 1445 static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip, 1446 u16 pointer, u8 data) 1447 { 1448 int err, port; 1449 1450 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1451 if (dsa_is_unused_port(chip->ds, port)) 1452 continue; 1453 1454 err = mv88e6393x_port_policy_write(chip, port, pointer, data); 1455 if (err) 1456 return err; 1457 } 1458 1459 return 0; 1460 } 1461 1462 int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, 1463 enum mv88e6xxx_egress_direction direction, 1464 int port) 1465 { 1466 u16 ptr; 1467 int err; 1468 1469 switch (direction) { 1470 case MV88E6XXX_EGRESS_DIR_INGRESS: 1471 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST; 1472 err = mv88e6393x_port_policy_write_all(chip, ptr, port); 1473 if (err) 1474 return err; 1475 break; 1476 case MV88E6XXX_EGRESS_DIR_EGRESS: 1477 ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST; 1478 err = mv88e6xxx_g2_write(chip, ptr, port); 1479 if (err) 1480 return err; 1481 break; 1482 } 1483 1484 return 0; 1485 } 1486 1487 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1488 int upstream_port) 1489 { 1490 u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST; 1491 u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI | 1492 upstream_port; 1493 1494 return mv88e6393x_port_policy_write(chip, port, ptr, data); 1495 } 1496 1497 int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 1498 { 1499 u16 ptr; 1500 int err; 1501 1502 /* Consider the frames with reserved multicast destination 1503 * addresses matching 01:80:c2:00:00:00 and 1504 * 01:80:c2:00:00:02 as MGMT. 1505 */ 1506 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO; 1507 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1508 if (err) 1509 return err; 1510 1511 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI; 1512 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1513 if (err) 1514 return err; 1515 1516 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO; 1517 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1518 if (err) 1519 return err; 1520 1521 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI; 1522 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1523 if (err) 1524 return err; 1525 1526 return 0; 1527 } 1528 1529 /* Offset 0x10 & 0x11: EPC */ 1530 1531 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) 1532 { 1533 int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY); 1534 1535 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); 1536 } 1537 1538 /* Port Ether type for 6393X family */ 1539 1540 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1541 u16 etype) 1542 { 1543 u16 val; 1544 int err; 1545 1546 err = mv88e6393x_port_epc_wait_ready(chip, port); 1547 if (err) 1548 return err; 1549 1550 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype); 1551 if (err) 1552 return err; 1553 1554 val = MV88E6393X_PORT_EPC_CMD_BUSY | 1555 MV88E6393X_PORT_EPC_CMD_WRITE | 1556 MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE; 1557 1558 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val); 1559 } 1560 1561 /* Offset 0x0f: Port Ether type */ 1562 1563 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1564 u16 etype) 1565 { 1566 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); 1567 } 1568 1569 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] 1570 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] 1571 */ 1572 1573 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1574 { 1575 int err; 1576 1577 /* Use a direct priority mapping for all IEEE tagged frames */ 1578 err = mv88e6xxx_port_write(chip, port, 1579 MV88E6095_PORT_IEEE_PRIO_REMAP_0123, 1580 0x3210); 1581 if (err) 1582 return err; 1583 1584 return mv88e6xxx_port_write(chip, port, 1585 MV88E6095_PORT_IEEE_PRIO_REMAP_4567, 1586 0x7654); 1587 } 1588 1589 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, 1590 int port, u16 table, u8 ptr, u16 data) 1591 { 1592 u16 reg; 1593 1594 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | 1595 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | 1596 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK); 1597 1598 return mv88e6xxx_port_write(chip, port, 1599 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); 1600 } 1601 1602 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1603 { 1604 int err, i; 1605 u16 table; 1606 1607 for (i = 0; i <= 7; i++) { 1608 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; 1609 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, 1610 (i | i << 4)); 1611 if (err) 1612 return err; 1613 1614 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP; 1615 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1616 if (err) 1617 return err; 1618 1619 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP; 1620 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1621 if (err) 1622 return err; 1623 1624 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP; 1625 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1626 if (err) 1627 return err; 1628 } 1629 1630 return 0; 1631 } 1632 1633 /* Offset 0x0E: Policy Control Register */ 1634 1635 static int 1636 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping, 1637 enum mv88e6xxx_policy_action action, 1638 u16 *mask, u16 *val, int *shift) 1639 { 1640 switch (mapping) { 1641 case MV88E6XXX_POLICY_MAPPING_DA: 1642 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK); 1643 *mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK; 1644 break; 1645 case MV88E6XXX_POLICY_MAPPING_SA: 1646 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK); 1647 *mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK; 1648 break; 1649 case MV88E6XXX_POLICY_MAPPING_VTU: 1650 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK); 1651 *mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK; 1652 break; 1653 case MV88E6XXX_POLICY_MAPPING_ETYPE: 1654 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK); 1655 *mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK; 1656 break; 1657 case MV88E6XXX_POLICY_MAPPING_PPPOE: 1658 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK); 1659 *mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK; 1660 break; 1661 case MV88E6XXX_POLICY_MAPPING_VBAS: 1662 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK); 1663 *mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK; 1664 break; 1665 case MV88E6XXX_POLICY_MAPPING_OPT82: 1666 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK); 1667 *mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK; 1668 break; 1669 case MV88E6XXX_POLICY_MAPPING_UDP: 1670 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK); 1671 *mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK; 1672 break; 1673 default: 1674 return -EOPNOTSUPP; 1675 } 1676 1677 switch (action) { 1678 case MV88E6XXX_POLICY_ACTION_NORMAL: 1679 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL; 1680 break; 1681 case MV88E6XXX_POLICY_ACTION_MIRROR: 1682 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR; 1683 break; 1684 case MV88E6XXX_POLICY_ACTION_TRAP: 1685 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP; 1686 break; 1687 case MV88E6XXX_POLICY_ACTION_DISCARD: 1688 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD; 1689 break; 1690 default: 1691 return -EOPNOTSUPP; 1692 } 1693 1694 return 0; 1695 } 1696 1697 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1698 enum mv88e6xxx_policy_mapping mapping, 1699 enum mv88e6xxx_policy_action action) 1700 { 1701 u16 reg, mask, val; 1702 int shift; 1703 int err; 1704 1705 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1706 &val, &shift); 1707 if (err) 1708 return err; 1709 1710 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); 1711 if (err) 1712 return err; 1713 1714 reg &= ~mask; 1715 reg |= (val << shift) & mask; 1716 1717 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); 1718 } 1719 1720 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1721 enum mv88e6xxx_policy_mapping mapping, 1722 enum mv88e6xxx_policy_action action) 1723 { 1724 u16 mask, val; 1725 int shift; 1726 int err; 1727 u16 ptr; 1728 u8 reg; 1729 1730 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1731 &val, &shift); 1732 if (err) 1733 return err; 1734 1735 /* The 16-bit Port Policy CTL register from older chips is on 6393x 1736 * changed to Port Policy MGMT CTL, which can access more data, but 1737 * indirectly. The original 16-bit value is divided into two 8-bit 1738 * registers. 1739 */ 1740 ptr = shift / 8; 1741 shift %= 8; 1742 mask >>= ptr * 8; 1743 1744 err = mv88e6393x_port_policy_read(chip, port, ptr, ®); 1745 if (err) 1746 return err; 1747 1748 reg &= ~mask; 1749 reg |= (val << shift) & mask; 1750 1751 return mv88e6393x_port_policy_write(chip, port, ptr, reg); 1752 } 1753