12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 210fa5bfcSAndrew Lunn /* 310fa5bfcSAndrew Lunn * Marvell 88E6xxx PHY access 410fa5bfcSAndrew Lunn * 510fa5bfcSAndrew Lunn * Copyright (c) 2008 Marvell Semiconductor 610fa5bfcSAndrew Lunn * 710fa5bfcSAndrew Lunn * Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch> 810fa5bfcSAndrew Lunn */ 910fa5bfcSAndrew Lunn 1010fa5bfcSAndrew Lunn #ifndef _MV88E6XXX_PHY_H 1110fa5bfcSAndrew Lunn #define _MV88E6XXX_PHY_H 1210fa5bfcSAndrew Lunn 13bec90b6dSVivien Didelot #define MV88E6XXX_PHY_PAGE 0x16 14bec90b6dSVivien Didelot #define MV88E6XXX_PHY_PAGE_COPPER 0x00 15c4530ee1SVivien Didelot 167e20cfb5SVivien Didelot /* PHY Registers accesses implementations */ 1710fa5bfcSAndrew Lunn int mv88e6165_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus, 1810fa5bfcSAndrew Lunn int addr, int reg, u16 *val); 1910fa5bfcSAndrew Lunn int mv88e6165_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus, 2010fa5bfcSAndrew Lunn int addr, int reg, u16 val); 217e20cfb5SVivien Didelot int mv88e6185_phy_ppu_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus, 227e20cfb5SVivien Didelot int addr, int reg, u16 *val); 237e20cfb5SVivien Didelot int mv88e6185_phy_ppu_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus, 247e20cfb5SVivien Didelot int addr, int reg, u16 val); 257e20cfb5SVivien Didelot 267e20cfb5SVivien Didelot /* Generic PHY operations */ 2710fa5bfcSAndrew Lunn int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, 2810fa5bfcSAndrew Lunn int reg, u16 *val); 2910fa5bfcSAndrew Lunn int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, 3010fa5bfcSAndrew Lunn int reg, u16 val); 31*743a19e3SAndrew Lunn int mv88e6xxx_phy_read_c45(struct mv88e6xxx_chip *chip, int phy, int devad, 32*743a19e3SAndrew Lunn int reg, u16 *val); 33*743a19e3SAndrew Lunn int mv88e6xxx_phy_write_c45(struct mv88e6xxx_chip *chip, int phy, int devad, 34*743a19e3SAndrew Lunn int reg, u16 val); 3510fa5bfcSAndrew Lunn int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, 3610fa5bfcSAndrew Lunn u8 page, int reg, u16 *val); 3710fa5bfcSAndrew Lunn int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, 3810fa5bfcSAndrew Lunn u8 page, int reg, u16 val); 3910fa5bfcSAndrew Lunn void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip); 4010fa5bfcSAndrew Lunn void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip); 411b17aedfSVivien Didelot int mv88e6xxx_phy_setup(struct mv88e6xxx_chip *chip); 4210fa5bfcSAndrew Lunn 4310fa5bfcSAndrew Lunn #endif /*_MV88E6XXX_PHY_H */ 44