1 /* 2 * Marvell 88E6xxx Switch hardware timestamping support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2017 National Instruments 7 * Erik Hons <erik.hons@ni.com> 8 * Brandon Streiff <brandon.streiff@ni.com> 9 * Dane Wagner <dane.wagner@ni.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #ifndef _MV88E6XXX_HWTSTAMP_H 18 #define _MV88E6XXX_HWTSTAMP_H 19 20 #include "chip.h" 21 22 /* Global 6352 PTP registers */ 23 /* Offset 0x00: PTP EtherType */ 24 #define MV88E6XXX_PTP_ETHERTYPE 0x00 25 26 /* Offset 0x01: Message Type Timestamp Enables */ 27 #define MV88E6XXX_PTP_MSGTYPE 0x01 28 #define MV88E6XXX_PTP_MSGTYPE_SYNC 0x0001 29 #define MV88E6XXX_PTP_MSGTYPE_DELAY_REQ 0x0002 30 #define MV88E6XXX_PTP_MSGTYPE_PDLAY_REQ 0x0004 31 #define MV88E6XXX_PTP_MSGTYPE_PDLAY_RES 0x0008 32 #define MV88E6XXX_PTP_MSGTYPE_ALL_EVENT 0x000f 33 34 /* Offset 0x02: Timestamp Arrival Capture Pointers */ 35 #define MV88E6XXX_PTP_TS_ARRIVAL_PTR 0x02 36 37 /* Offset 0x05: PTP Global Configuration */ 38 #define MV88E6165_PTP_CFG 0x05 39 #define MV88E6165_PTP_CFG_TSPEC_MASK 0xf000 40 #define MV88E6165_PTP_CFG_DISABLE_TS_OVERWRITE BIT(1) 41 #define MV88E6165_PTP_CFG_DISABLE_PTP BIT(0) 42 43 /* Offset 0x07: PTP Global Configuration */ 44 #define MV88E6341_PTP_CFG 0x07 45 #define MV88E6341_PTP_CFG_UPDATE 0x8000 46 #define MV88E6341_PTP_CFG_IDX_MASK 0x7f00 47 #define MV88E6341_PTP_CFG_DATA_MASK 0x00ff 48 #define MV88E6341_PTP_CFG_MODE_IDX 0x0 49 #define MV88E6341_PTP_CFG_MODE_TS_AT_PHY 0x00 50 #define MV88E6341_PTP_CFG_MODE_TS_AT_MAC 0x80 51 52 /* Offset 0x08: PTP Interrupt Status */ 53 #define MV88E6XXX_PTP_IRQ_STATUS 0x08 54 55 /* Per-Port 6352 PTP Registers */ 56 /* Offset 0x00: PTP Configuration 0 */ 57 #define MV88E6XXX_PORT_PTP_CFG0 0x00 58 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_SHIFT 12 59 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_MASK 0xf000 60 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_1588 0x0000 61 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_8021AS 0x1000 62 #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_TSPEC_MATCH 0x0800 63 #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_OVERWRITE 0x0002 64 #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_PTP 0x0001 65 66 /* Offset 0x01: PTP Configuration 1 */ 67 #define MV88E6XXX_PORT_PTP_CFG1 0x01 68 69 /* Offset 0x02: PTP Configuration 2 */ 70 #define MV88E6XXX_PORT_PTP_CFG2 0x02 71 #define MV88E6XXX_PORT_PTP_CFG2_EMBED_ARRIVAL 0x1000 72 #define MV88E6XXX_PORT_PTP_CFG2_DEP_IRQ_EN 0x0002 73 #define MV88E6XXX_PORT_PTP_CFG2_ARR_IRQ_EN 0x0001 74 75 /* Offset 0x03: PTP LED Configuration */ 76 #define MV88E6XXX_PORT_PTP_LED_CFG 0x03 77 78 /* Offset 0x08: PTP Arrival 0 Status */ 79 #define MV88E6XXX_PORT_PTP_ARR0_STS 0x08 80 81 /* Offset 0x09/0x0A: PTP Arrival 0 Time */ 82 #define MV88E6XXX_PORT_PTP_ARR0_TIME_LO 0x09 83 #define MV88E6XXX_PORT_PTP_ARR0_TIME_HI 0x0a 84 85 /* Offset 0x0B: PTP Arrival 0 Sequence ID */ 86 #define MV88E6XXX_PORT_PTP_ARR0_SEQID 0x0b 87 88 /* Offset 0x0C: PTP Arrival 1 Status */ 89 #define MV88E6XXX_PORT_PTP_ARR1_STS 0x0c 90 91 /* Offset 0x0D/0x0E: PTP Arrival 1 Time */ 92 #define MV88E6XXX_PORT_PTP_ARR1_TIME_LO 0x0d 93 #define MV88E6XXX_PORT_PTP_ARR1_TIME_HI 0x0e 94 95 /* Offset 0x0F: PTP Arrival 1 Sequence ID */ 96 #define MV88E6XXX_PORT_PTP_ARR1_SEQID 0x0f 97 98 /* Offset 0x10: PTP Departure Status */ 99 #define MV88E6XXX_PORT_PTP_DEP_STS 0x10 100 101 /* Offset 0x11/0x12: PTP Deperture Time */ 102 #define MV88E6XXX_PORT_PTP_DEP_TIME_LO 0x11 103 #define MV88E6XXX_PORT_PTP_DEP_TIME_HI 0x12 104 105 /* Offset 0x13: PTP Departure Sequence ID */ 106 #define MV88E6XXX_PORT_PTP_DEP_SEQID 0x13 107 108 /* Status fields for arrival and depature timestamp status registers */ 109 #define MV88E6XXX_PTP_TS_STATUS_MASK 0x0006 110 #define MV88E6XXX_PTP_TS_STATUS_NORMAL 0x0000 111 #define MV88E6XXX_PTP_TS_STATUS_OVERWITTEN 0x0002 112 #define MV88E6XXX_PTP_TS_STATUS_DISCARDED 0x0004 113 #define MV88E6XXX_PTP_TS_VALID 0x0001 114 115 #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP 116 117 int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds, int port, 118 struct ifreq *ifr); 119 int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds, int port, 120 struct ifreq *ifr); 121 122 bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port, 123 struct sk_buff *clone, unsigned int type); 124 bool mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port, 125 struct sk_buff *clone, unsigned int type); 126 127 int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port, 128 struct ethtool_ts_info *info); 129 130 int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip); 131 void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip); 132 int mv88e6352_hwtstamp_port_enable(struct mv88e6xxx_chip *chip, int port); 133 int mv88e6352_hwtstamp_port_disable(struct mv88e6xxx_chip *chip, int port); 134 int mv88e6165_global_enable(struct mv88e6xxx_chip *chip); 135 int mv88e6165_global_disable(struct mv88e6xxx_chip *chip); 136 137 #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */ 138 139 static inline int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds, 140 int port, struct ifreq *ifr) 141 { 142 return -EOPNOTSUPP; 143 } 144 145 static inline int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds, 146 int port, struct ifreq *ifr) 147 { 148 return -EOPNOTSUPP; 149 } 150 151 static inline bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port, 152 struct sk_buff *clone, 153 unsigned int type) 154 { 155 return false; 156 } 157 158 static inline bool mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port, 159 struct sk_buff *clone, 160 unsigned int type) 161 { 162 return false; 163 } 164 165 static inline int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port, 166 struct ethtool_ts_info *info) 167 { 168 return -EOPNOTSUPP; 169 } 170 171 static inline int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip) 172 { 173 return 0; 174 } 175 176 static inline void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip) 177 { 178 } 179 180 #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */ 181 182 #endif /* _MV88E6XXX_HWTSTAMP_H */ 183