1 /* 2 * Marvell 88E6xxx Switch hardware timestamping support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2017 National Instruments 7 * Erik Hons <erik.hons@ni.com> 8 * Brandon Streiff <brandon.streiff@ni.com> 9 * Dane Wagner <dane.wagner@ni.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #ifndef _MV88E6XXX_HWTSTAMP_H 18 #define _MV88E6XXX_HWTSTAMP_H 19 20 #include "chip.h" 21 22 /* Global PTP registers */ 23 /* Offset 0x00: PTP EtherType */ 24 #define MV88E6XXX_PTP_ETHERTYPE 0x00 25 26 /* Offset 0x01: Message Type Timestamp Enables */ 27 #define MV88E6XXX_PTP_MSGTYPE 0x01 28 #define MV88E6XXX_PTP_MSGTYPE_SYNC 0x0001 29 #define MV88E6XXX_PTP_MSGTYPE_DELAY_REQ 0x0002 30 #define MV88E6XXX_PTP_MSGTYPE_PDLAY_REQ 0x0004 31 #define MV88E6XXX_PTP_MSGTYPE_PDLAY_RES 0x0008 32 #define MV88E6XXX_PTP_MSGTYPE_ALL_EVENT 0x000f 33 34 /* Offset 0x02: Timestamp Arrival Capture Pointers */ 35 #define MV88E6XXX_PTP_TS_ARRIVAL_PTR 0x02 36 37 /* Offset 0x07: PTP Global Configuration */ 38 #define MV88E6341_PTP_CFG 0x07 39 #define MV88E6341_PTP_CFG_UPDATE 0x8000 40 #define MV88E6341_PTP_CFG_IDX_MASK 0x7f00 41 #define MV88E6341_PTP_CFG_DATA_MASK 0x00ff 42 #define MV88E6341_PTP_CFG_MODE_IDX 0x0 43 #define MV88E6341_PTP_CFG_MODE_TS_AT_PHY 0x00 44 #define MV88E6341_PTP_CFG_MODE_TS_AT_MAC 0x80 45 46 /* Offset 0x08: PTP Interrupt Status */ 47 #define MV88E6XXX_PTP_IRQ_STATUS 0x08 48 49 /* Per-Port PTP Registers */ 50 /* Offset 0x00: PTP Configuration 0 */ 51 #define MV88E6XXX_PORT_PTP_CFG0 0x00 52 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_SHIFT 12 53 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_MASK 0xf000 54 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_1588 0x0000 55 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_8021AS 0x1000 56 #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_TSPEC_MATCH 0x0800 57 #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_OVERWRITE 0x0002 58 #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_PTP 0x0001 59 60 /* Offset 0x01: PTP Configuration 1 */ 61 #define MV88E6XXX_PORT_PTP_CFG1 0x01 62 63 /* Offset 0x02: PTP Configuration 2 */ 64 #define MV88E6XXX_PORT_PTP_CFG2 0x02 65 #define MV88E6XXX_PORT_PTP_CFG2_EMBED_ARRIVAL 0x1000 66 #define MV88E6XXX_PORT_PTP_CFG2_DEP_IRQ_EN 0x0002 67 #define MV88E6XXX_PORT_PTP_CFG2_ARR_IRQ_EN 0x0001 68 69 /* Offset 0x03: PTP LED Configuration */ 70 #define MV88E6XXX_PORT_PTP_LED_CFG 0x03 71 72 /* Offset 0x08: PTP Arrival 0 Status */ 73 #define MV88E6XXX_PORT_PTP_ARR0_STS 0x08 74 75 /* Offset 0x09/0x0A: PTP Arrival 0 Time */ 76 #define MV88E6XXX_PORT_PTP_ARR0_TIME_LO 0x09 77 #define MV88E6XXX_PORT_PTP_ARR0_TIME_HI 0x0a 78 79 /* Offset 0x0B: PTP Arrival 0 Sequence ID */ 80 #define MV88E6XXX_PORT_PTP_ARR0_SEQID 0x0b 81 82 /* Offset 0x0C: PTP Arrival 1 Status */ 83 #define MV88E6XXX_PORT_PTP_ARR1_STS 0x0c 84 85 /* Offset 0x0D/0x0E: PTP Arrival 1 Time */ 86 #define MV88E6XXX_PORT_PTP_ARR1_TIME_LO 0x0d 87 #define MV88E6XXX_PORT_PTP_ARR1_TIME_HI 0x0e 88 89 /* Offset 0x0F: PTP Arrival 1 Sequence ID */ 90 #define MV88E6XXX_PORT_PTP_ARR1_SEQID 0x0f 91 92 /* Offset 0x10: PTP Departure Status */ 93 #define MV88E6XXX_PORT_PTP_DEP_STS 0x10 94 95 /* Offset 0x11/0x12: PTP Deperture Time */ 96 #define MV88E6XXX_PORT_PTP_DEP_TIME_LO 0x11 97 #define MV88E6XXX_PORT_PTP_DEP_TIME_HI 0x12 98 99 /* Offset 0x13: PTP Departure Sequence ID */ 100 #define MV88E6XXX_PORT_PTP_DEP_SEQID 0x13 101 102 /* Status fields for arrival and depature timestamp status registers */ 103 #define MV88E6XXX_PTP_TS_STATUS_MASK 0x0006 104 #define MV88E6XXX_PTP_TS_STATUS_NORMAL 0x0000 105 #define MV88E6XXX_PTP_TS_STATUS_OVERWITTEN 0x0002 106 #define MV88E6XXX_PTP_TS_STATUS_DISCARDED 0x0004 107 #define MV88E6XXX_PTP_TS_VALID 0x0001 108 109 #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP 110 111 int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds, int port, 112 struct ifreq *ifr); 113 int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds, int port, 114 struct ifreq *ifr); 115 116 bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port, 117 struct sk_buff *clone, unsigned int type); 118 bool mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port, 119 struct sk_buff *clone, unsigned int type); 120 121 int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port, 122 struct ethtool_ts_info *info); 123 124 int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip); 125 void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip); 126 127 #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */ 128 129 static inline int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds, 130 int port, struct ifreq *ifr) 131 { 132 return -EOPNOTSUPP; 133 } 134 135 static inline int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds, 136 int port, struct ifreq *ifr) 137 { 138 return -EOPNOTSUPP; 139 } 140 141 static inline bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port, 142 struct sk_buff *clone, 143 unsigned int type) 144 { 145 return false; 146 } 147 148 static inline bool mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port, 149 struct sk_buff *clone, 150 unsigned int type) 151 { 152 return false; 153 } 154 155 static inline int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port, 156 struct ethtool_ts_info *info) 157 { 158 return -EOPNOTSUPP; 159 } 160 161 static inline int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip) 162 { 163 return 0; 164 } 165 166 static inline void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip) 167 { 168 } 169 170 #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */ 171 172 #endif /* _MV88E6XXX_HWTSTAMP_H */ 173